1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
12
13#ifndef ASIC_REG_TPC1_CMDQ_REGS_H_
14#define ASIC_REG_TPC1_CMDQ_REGS_H_
15
16/*
17 *****************************************
18 * TPC1_CMDQ (Prototype: CMDQ)
19 *****************************************
20 */
21
22#define mmTPC1_CMDQ_GLBL_CFG0 0xE49000
23
24#define mmTPC1_CMDQ_GLBL_CFG1 0xE49004
25
26#define mmTPC1_CMDQ_GLBL_PROT 0xE49008
27
28#define mmTPC1_CMDQ_GLBL_ERR_CFG 0xE4900C
29
30#define mmTPC1_CMDQ_GLBL_ERR_ADDR_LO 0xE49010
31
32#define mmTPC1_CMDQ_GLBL_ERR_ADDR_HI 0xE49014
33
34#define mmTPC1_CMDQ_GLBL_ERR_WDATA 0xE49018
35
36#define mmTPC1_CMDQ_GLBL_SECURE_PROPS 0xE4901C
37
38#define mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS 0xE49020
39
40#define mmTPC1_CMDQ_GLBL_STS0 0xE49024
41
42#define mmTPC1_CMDQ_GLBL_STS1 0xE49028
43
44#define mmTPC1_CMDQ_CQ_CFG0 0xE490B0
45
46#define mmTPC1_CMDQ_CQ_CFG1 0xE490B4
47
48#define mmTPC1_CMDQ_CQ_ARUSER 0xE490B8
49
50#define mmTPC1_CMDQ_CQ_PTR_LO 0xE490C0
51
52#define mmTPC1_CMDQ_CQ_PTR_HI 0xE490C4
53
54#define mmTPC1_CMDQ_CQ_TSIZE 0xE490C8
55
56#define mmTPC1_CMDQ_CQ_CTL 0xE490CC
57
58#define mmTPC1_CMDQ_CQ_PTR_LO_STS 0xE490D4
59
60#define mmTPC1_CMDQ_CQ_PTR_HI_STS 0xE490D8
61
62#define mmTPC1_CMDQ_CQ_TSIZE_STS 0xE490DC
63
64#define mmTPC1_CMDQ_CQ_CTL_STS 0xE490E0
65
66#define mmTPC1_CMDQ_CQ_STS0 0xE490E4
67
68#define mmTPC1_CMDQ_CQ_STS1 0xE490E8
69
70#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_EN 0xE490F0
71
72#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE490F4
73
74#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_SAT 0xE490F8
75
76#define mmTPC1_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE490FC
77
78#define mmTPC1_CMDQ_CQ_IFIFO_CNT 0xE49108
79
80#define mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE49120
81
82#define mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE49124
83
84#define mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE49128
85
86#define mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE4912C
87
88#define mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE49130
89
90#define mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE49134
91
92#define mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE49138
93
94#define mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE4913C
95
96#define mmTPC1_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE49140
97
98#define mmTPC1_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE49144
99
100#define mmTPC1_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE49148
101
102#define mmTPC1_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE4914C
103
104#define mmTPC1_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE49150
105
106#define mmTPC1_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE49154
107
108#define mmTPC1_CMDQ_CP_FENCE0_RDATA 0xE49158
109
110#define mmTPC1_CMDQ_CP_FENCE1_RDATA 0xE4915C
111
112#define mmTPC1_CMDQ_CP_FENCE2_RDATA 0xE49160
113
114#define mmTPC1_CMDQ_CP_FENCE3_RDATA 0xE49164
115
116#define mmTPC1_CMDQ_CP_FENCE0_CNT 0xE49168
117
118#define mmTPC1_CMDQ_CP_FENCE1_CNT 0xE4916C
119
120#define mmTPC1_CMDQ_CP_FENCE2_CNT 0xE49170
121
122#define mmTPC1_CMDQ_CP_FENCE3_CNT 0xE49174
123
124#define mmTPC1_CMDQ_CP_STS 0xE49178
125
126#define mmTPC1_CMDQ_CP_CURRENT_INST_LO 0xE4917C
127
128#define mmTPC1_CMDQ_CP_CURRENT_INST_HI 0xE49180
129
130#define mmTPC1_CMDQ_CP_BARRIER_CFG 0xE49184
131
132#define mmTPC1_CMDQ_CP_DBG_0 0xE49188
133
134#define mmTPC1_CMDQ_CQ_BUF_ADDR 0xE49308
135
136#define mmTPC1_CMDQ_CQ_BUF_RDATA 0xE4930C
137
138#endif /* ASIC_REG_TPC1_CMDQ_REGS_H_ */
139

source code of linux/drivers/accel/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h