| 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright 2016-2018 HabanaLabs, Ltd. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | /************************************ |
| 9 | ** This is an auto-generated file ** |
| 10 | ** DO NOT EDIT BELOW ** |
| 11 | ************************************/ |
| 12 | |
| 13 | #ifndef ASIC_REG_TPC4_CFG_REGS_H_ |
| 14 | #define ASIC_REG_TPC4_CFG_REGS_H_ |
| 15 | |
| 16 | /* |
| 17 | ***************************************** |
| 18 | * TPC4_CFG (Prototype: TPC) |
| 19 | ***************************************** |
| 20 | */ |
| 21 | |
| 22 | #define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF06400 |
| 23 | |
| 24 | #define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF06404 |
| 25 | |
| 26 | #define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF06408 |
| 27 | |
| 28 | #define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C |
| 29 | |
| 30 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF06410 |
| 31 | |
| 32 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF06414 |
| 33 | |
| 34 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF06418 |
| 35 | |
| 36 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF0641C |
| 37 | |
| 38 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF06420 |
| 39 | |
| 40 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF06424 |
| 41 | |
| 42 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF06428 |
| 43 | |
| 44 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF0642C |
| 45 | |
| 46 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF06430 |
| 47 | |
| 48 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF06434 |
| 49 | |
| 50 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF06438 |
| 51 | |
| 52 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF0643C |
| 53 | |
| 54 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF06440 |
| 55 | |
| 56 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF06444 |
| 57 | |
| 58 | #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF06448 |
| 59 | |
| 60 | #define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF0644C |
| 61 | |
| 62 | #define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF06450 |
| 63 | |
| 64 | #define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF06454 |
| 65 | |
| 66 | #define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF06458 |
| 67 | |
| 68 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF0645C |
| 69 | |
| 70 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF06460 |
| 71 | |
| 72 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF06464 |
| 73 | |
| 74 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF06468 |
| 75 | |
| 76 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF0646C |
| 77 | |
| 78 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF06470 |
| 79 | |
| 80 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF06474 |
| 81 | |
| 82 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF06478 |
| 83 | |
| 84 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF0647C |
| 85 | |
| 86 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF06480 |
| 87 | |
| 88 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF06484 |
| 89 | |
| 90 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF06488 |
| 91 | |
| 92 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF0648C |
| 93 | |
| 94 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF06490 |
| 95 | |
| 96 | #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF06494 |
| 97 | |
| 98 | #define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF06498 |
| 99 | |
| 100 | #define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF0649C |
| 101 | |
| 102 | #define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF064A0 |
| 103 | |
| 104 | #define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF064A4 |
| 105 | |
| 106 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF064A8 |
| 107 | |
| 108 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF064AC |
| 109 | |
| 110 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF064B0 |
| 111 | |
| 112 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF064B4 |
| 113 | |
| 114 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF064B8 |
| 115 | |
| 116 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF064BC |
| 117 | |
| 118 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF064C0 |
| 119 | |
| 120 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF064C4 |
| 121 | |
| 122 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF064C8 |
| 123 | |
| 124 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF064CC |
| 125 | |
| 126 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF064D0 |
| 127 | |
| 128 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF064D4 |
| 129 | |
| 130 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064D8 |
| 131 | |
| 132 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064DC |
| 133 | |
| 134 | #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF064E0 |
| 135 | |
| 136 | #define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064E4 |
| 137 | |
| 138 | #define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064E8 |
| 139 | |
| 140 | #define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064EC |
| 141 | |
| 142 | #define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064F0 |
| 143 | |
| 144 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064F4 |
| 145 | |
| 146 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064F8 |
| 147 | |
| 148 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF064FC |
| 149 | |
| 150 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF06500 |
| 151 | |
| 152 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF06504 |
| 153 | |
| 154 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF06508 |
| 155 | |
| 156 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF0650C |
| 157 | |
| 158 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF06510 |
| 159 | |
| 160 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF06514 |
| 161 | |
| 162 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF06518 |
| 163 | |
| 164 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF0651C |
| 165 | |
| 166 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF06520 |
| 167 | |
| 168 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF06524 |
| 169 | |
| 170 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF06528 |
| 171 | |
| 172 | #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF0652C |
| 173 | |
| 174 | #define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF06530 |
| 175 | |
| 176 | #define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF06534 |
| 177 | |
| 178 | #define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF06538 |
| 179 | |
| 180 | #define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF0653C |
| 181 | |
| 182 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF06540 |
| 183 | |
| 184 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF06544 |
| 185 | |
| 186 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF06548 |
| 187 | |
| 188 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF0654C |
| 189 | |
| 190 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF06550 |
| 191 | |
| 192 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF06554 |
| 193 | |
| 194 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06558 |
| 195 | |
| 196 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF0655C |
| 197 | |
| 198 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF06560 |
| 199 | |
| 200 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06564 |
| 201 | |
| 202 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF06568 |
| 203 | |
| 204 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF0656C |
| 205 | |
| 206 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06570 |
| 207 | |
| 208 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06574 |
| 209 | |
| 210 | #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF06578 |
| 211 | |
| 212 | #define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF0657C |
| 213 | |
| 214 | #define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF06580 |
| 215 | |
| 216 | #define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06584 |
| 217 | |
| 218 | #define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06588 |
| 219 | |
| 220 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF0658C |
| 221 | |
| 222 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF06590 |
| 223 | |
| 224 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF06594 |
| 225 | |
| 226 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06598 |
| 227 | |
| 228 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF0659C |
| 229 | |
| 230 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF065A0 |
| 231 | |
| 232 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF065A4 |
| 233 | |
| 234 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF065A8 |
| 235 | |
| 236 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF065AC |
| 237 | |
| 238 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF065B0 |
| 239 | |
| 240 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF065B4 |
| 241 | |
| 242 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF065B8 |
| 243 | |
| 244 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF065BC |
| 245 | |
| 246 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF065C0 |
| 247 | |
| 248 | #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF065C4 |
| 249 | |
| 250 | #define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF065C8 |
| 251 | |
| 252 | #define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF065CC |
| 253 | |
| 254 | #define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF065D0 |
| 255 | |
| 256 | #define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF065D4 |
| 257 | |
| 258 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF065D8 |
| 259 | |
| 260 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF065DC |
| 261 | |
| 262 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF065E0 |
| 263 | |
| 264 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF065E4 |
| 265 | |
| 266 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF065E8 |
| 267 | |
| 268 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF065EC |
| 269 | |
| 270 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF065F0 |
| 271 | |
| 272 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF065F4 |
| 273 | |
| 274 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF065F8 |
| 275 | |
| 276 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF065FC |
| 277 | |
| 278 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF06600 |
| 279 | |
| 280 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF06604 |
| 281 | |
| 282 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06608 |
| 283 | |
| 284 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF0660C |
| 285 | |
| 286 | #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF06610 |
| 287 | |
| 288 | #define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06614 |
| 289 | |
| 290 | #define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF06618 |
| 291 | |
| 292 | #define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF0661C |
| 293 | |
| 294 | #define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06620 |
| 295 | |
| 296 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06624 |
| 297 | |
| 298 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF06628 |
| 299 | |
| 300 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF0662C |
| 301 | |
| 302 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF06630 |
| 303 | |
| 304 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF06634 |
| 305 | |
| 306 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF06638 |
| 307 | |
| 308 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF0663C |
| 309 | |
| 310 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF06640 |
| 311 | |
| 312 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF06644 |
| 313 | |
| 314 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF06648 |
| 315 | |
| 316 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF0664C |
| 317 | |
| 318 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF06650 |
| 319 | |
| 320 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF06654 |
| 321 | |
| 322 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF06658 |
| 323 | |
| 324 | #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF0665C |
| 325 | |
| 326 | #define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06660 |
| 327 | |
| 328 | #define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF06664 |
| 329 | |
| 330 | #define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06668 |
| 331 | |
| 332 | #define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF0666C |
| 333 | |
| 334 | #define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06670 |
| 335 | |
| 336 | #define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF06674 |
| 337 | |
| 338 | #define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF06678 |
| 339 | |
| 340 | #define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF0667C |
| 341 | |
| 342 | #define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF06680 |
| 343 | |
| 344 | #define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF06684 |
| 345 | |
| 346 | #define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF06688 |
| 347 | |
| 348 | #define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF0668C |
| 349 | |
| 350 | #define mmTPC4_CFG_KERNEL_SRF_0 0xF06690 |
| 351 | |
| 352 | #define mmTPC4_CFG_KERNEL_SRF_1 0xF06694 |
| 353 | |
| 354 | #define mmTPC4_CFG_KERNEL_SRF_2 0xF06698 |
| 355 | |
| 356 | #define mmTPC4_CFG_KERNEL_SRF_3 0xF0669C |
| 357 | |
| 358 | #define mmTPC4_CFG_KERNEL_SRF_4 0xF066A0 |
| 359 | |
| 360 | #define mmTPC4_CFG_KERNEL_SRF_5 0xF066A4 |
| 361 | |
| 362 | #define mmTPC4_CFG_KERNEL_SRF_6 0xF066A8 |
| 363 | |
| 364 | #define mmTPC4_CFG_KERNEL_SRF_7 0xF066AC |
| 365 | |
| 366 | #define mmTPC4_CFG_KERNEL_SRF_8 0xF066B0 |
| 367 | |
| 368 | #define mmTPC4_CFG_KERNEL_SRF_9 0xF066B4 |
| 369 | |
| 370 | #define mmTPC4_CFG_KERNEL_SRF_10 0xF066B8 |
| 371 | |
| 372 | #define mmTPC4_CFG_KERNEL_SRF_11 0xF066BC |
| 373 | |
| 374 | #define mmTPC4_CFG_KERNEL_SRF_12 0xF066C0 |
| 375 | |
| 376 | #define mmTPC4_CFG_KERNEL_SRF_13 0xF066C4 |
| 377 | |
| 378 | #define mmTPC4_CFG_KERNEL_SRF_14 0xF066C8 |
| 379 | |
| 380 | #define mmTPC4_CFG_KERNEL_SRF_15 0xF066CC |
| 381 | |
| 382 | #define mmTPC4_CFG_KERNEL_SRF_16 0xF066D0 |
| 383 | |
| 384 | #define mmTPC4_CFG_KERNEL_SRF_17 0xF066D4 |
| 385 | |
| 386 | #define mmTPC4_CFG_KERNEL_SRF_18 0xF066D8 |
| 387 | |
| 388 | #define mmTPC4_CFG_KERNEL_SRF_19 0xF066DC |
| 389 | |
| 390 | #define mmTPC4_CFG_KERNEL_SRF_20 0xF066E0 |
| 391 | |
| 392 | #define mmTPC4_CFG_KERNEL_SRF_21 0xF066E4 |
| 393 | |
| 394 | #define mmTPC4_CFG_KERNEL_SRF_22 0xF066E8 |
| 395 | |
| 396 | #define mmTPC4_CFG_KERNEL_SRF_23 0xF066EC |
| 397 | |
| 398 | #define mmTPC4_CFG_KERNEL_SRF_24 0xF066F0 |
| 399 | |
| 400 | #define mmTPC4_CFG_KERNEL_SRF_25 0xF066F4 |
| 401 | |
| 402 | #define mmTPC4_CFG_KERNEL_SRF_26 0xF066F8 |
| 403 | |
| 404 | #define mmTPC4_CFG_KERNEL_SRF_27 0xF066FC |
| 405 | |
| 406 | #define mmTPC4_CFG_KERNEL_SRF_28 0xF06700 |
| 407 | |
| 408 | #define mmTPC4_CFG_KERNEL_SRF_29 0xF06704 |
| 409 | |
| 410 | #define mmTPC4_CFG_KERNEL_SRF_30 0xF06708 |
| 411 | |
| 412 | #define mmTPC4_CFG_KERNEL_SRF_31 0xF0670C |
| 413 | |
| 414 | #define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF06710 |
| 415 | |
| 416 | #define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06714 |
| 417 | |
| 418 | #define mmTPC4_CFG_RESERVED_DESC_END 0xF06738 |
| 419 | |
| 420 | #define mmTPC4_CFG_ROUND_CSR 0xF067FC |
| 421 | |
| 422 | #define mmTPC4_CFG_TBUF_BASE_ADDR_LOW 0xF06800 |
| 423 | |
| 424 | #define mmTPC4_CFG_TBUF_BASE_ADDR_HIGH 0xF06804 |
| 425 | |
| 426 | #define mmTPC4_CFG_SEMAPHORE 0xF06808 |
| 427 | |
| 428 | #define mmTPC4_CFG_VFLAGS 0xF0680C |
| 429 | |
| 430 | #define mmTPC4_CFG_SFLAGS 0xF06810 |
| 431 | |
| 432 | #define mmTPC4_CFG_LFSR_POLYNOM 0xF06818 |
| 433 | |
| 434 | #define mmTPC4_CFG_STATUS 0xF0681C |
| 435 | |
| 436 | #define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06820 |
| 437 | |
| 438 | #define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06824 |
| 439 | |
| 440 | #define mmTPC4_CFG_SM_BASE_ADDRESS_LOW 0xF06828 |
| 441 | |
| 442 | #define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0682C |
| 443 | |
| 444 | #define mmTPC4_CFG_TPC_CMD 0xF06830 |
| 445 | |
| 446 | #define mmTPC4_CFG_TPC_EXECUTE 0xF06838 |
| 447 | |
| 448 | #define mmTPC4_CFG_TPC_STALL 0xF0683C |
| 449 | |
| 450 | #define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06840 |
| 451 | |
| 452 | #define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06844 |
| 453 | |
| 454 | #define mmTPC4_CFG_MSS_CONFIG 0xF06854 |
| 455 | |
| 456 | #define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06858 |
| 457 | |
| 458 | #define mmTPC4_CFG_TPC_INTR_MASK 0xF0685C |
| 459 | |
| 460 | #define mmTPC4_CFG_TSB_CONFIG 0xF06860 |
| 461 | |
| 462 | #define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00 |
| 463 | |
| 464 | #define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04 |
| 465 | |
| 466 | #define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08 |
| 467 | |
| 468 | #define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C |
| 469 | |
| 470 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10 |
| 471 | |
| 472 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14 |
| 473 | |
| 474 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF06A18 |
| 475 | |
| 476 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A1C |
| 477 | |
| 478 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A20 |
| 479 | |
| 480 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF06A24 |
| 481 | |
| 482 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A28 |
| 483 | |
| 484 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A2C |
| 485 | |
| 486 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF06A30 |
| 487 | |
| 488 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A34 |
| 489 | |
| 490 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A38 |
| 491 | |
| 492 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF06A3C |
| 493 | |
| 494 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A40 |
| 495 | |
| 496 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A44 |
| 497 | |
| 498 | #define mmTPC4_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF06A48 |
| 499 | |
| 500 | #define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A4C |
| 501 | |
| 502 | #define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A50 |
| 503 | |
| 504 | #define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A54 |
| 505 | |
| 506 | #define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A58 |
| 507 | |
| 508 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A5C |
| 509 | |
| 510 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A60 |
| 511 | |
| 512 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF06A64 |
| 513 | |
| 514 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A68 |
| 515 | |
| 516 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A6C |
| 517 | |
| 518 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF06A70 |
| 519 | |
| 520 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A74 |
| 521 | |
| 522 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A78 |
| 523 | |
| 524 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF06A7C |
| 525 | |
| 526 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A80 |
| 527 | |
| 528 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A84 |
| 529 | |
| 530 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF06A88 |
| 531 | |
| 532 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A8C |
| 533 | |
| 534 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A90 |
| 535 | |
| 536 | #define mmTPC4_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF06A94 |
| 537 | |
| 538 | #define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A98 |
| 539 | |
| 540 | #define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A9C |
| 541 | |
| 542 | #define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06AA0 |
| 543 | |
| 544 | #define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06AA4 |
| 545 | |
| 546 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06AA8 |
| 547 | |
| 548 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06AAC |
| 549 | |
| 550 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF06AB0 |
| 551 | |
| 552 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06AB4 |
| 553 | |
| 554 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06AB8 |
| 555 | |
| 556 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF06ABC |
| 557 | |
| 558 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06AC0 |
| 559 | |
| 560 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06AC4 |
| 561 | |
| 562 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF06AC8 |
| 563 | |
| 564 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06ACC |
| 565 | |
| 566 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06AD0 |
| 567 | |
| 568 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF06AD4 |
| 569 | |
| 570 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AD8 |
| 571 | |
| 572 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06ADC |
| 573 | |
| 574 | #define mmTPC4_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF06AE0 |
| 575 | |
| 576 | #define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AE4 |
| 577 | |
| 578 | #define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AE8 |
| 579 | |
| 580 | #define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AEC |
| 581 | |
| 582 | #define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AF0 |
| 583 | |
| 584 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AF4 |
| 585 | |
| 586 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06AF8 |
| 587 | |
| 588 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF06AFC |
| 589 | |
| 590 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06B00 |
| 591 | |
| 592 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06B04 |
| 593 | |
| 594 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF06B08 |
| 595 | |
| 596 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06B0C |
| 597 | |
| 598 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06B10 |
| 599 | |
| 600 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF06B14 |
| 601 | |
| 602 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06B18 |
| 603 | |
| 604 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06B1C |
| 605 | |
| 606 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF06B20 |
| 607 | |
| 608 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06B24 |
| 609 | |
| 610 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06B28 |
| 611 | |
| 612 | #define mmTPC4_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF06B2C |
| 613 | |
| 614 | #define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06B30 |
| 615 | |
| 616 | #define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06B34 |
| 617 | |
| 618 | #define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06B38 |
| 619 | |
| 620 | #define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06B3C |
| 621 | |
| 622 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06B40 |
| 623 | |
| 624 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06B44 |
| 625 | |
| 626 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF06B48 |
| 627 | |
| 628 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06B4C |
| 629 | |
| 630 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06B50 |
| 631 | |
| 632 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF06B54 |
| 633 | |
| 634 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B58 |
| 635 | |
| 636 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B5C |
| 637 | |
| 638 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF06B60 |
| 639 | |
| 640 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B64 |
| 641 | |
| 642 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B68 |
| 643 | |
| 644 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF06B6C |
| 645 | |
| 646 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B70 |
| 647 | |
| 648 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B74 |
| 649 | |
| 650 | #define mmTPC4_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF06B78 |
| 651 | |
| 652 | #define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B7C |
| 653 | |
| 654 | #define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B80 |
| 655 | |
| 656 | #define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B84 |
| 657 | |
| 658 | #define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B88 |
| 659 | |
| 660 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B8C |
| 661 | |
| 662 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B90 |
| 663 | |
| 664 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF06B94 |
| 665 | |
| 666 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B98 |
| 667 | |
| 668 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B9C |
| 669 | |
| 670 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF06BA0 |
| 671 | |
| 672 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06BA4 |
| 673 | |
| 674 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06BA8 |
| 675 | |
| 676 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF06BAC |
| 677 | |
| 678 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06BB0 |
| 679 | |
| 680 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06BB4 |
| 681 | |
| 682 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF06BB8 |
| 683 | |
| 684 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06BBC |
| 685 | |
| 686 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06BC0 |
| 687 | |
| 688 | #define mmTPC4_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF06BC4 |
| 689 | |
| 690 | #define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06BC8 |
| 691 | |
| 692 | #define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06BCC |
| 693 | |
| 694 | #define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06BD0 |
| 695 | |
| 696 | #define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06BD4 |
| 697 | |
| 698 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06BD8 |
| 699 | |
| 700 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06BDC |
| 701 | |
| 702 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF06BE0 |
| 703 | |
| 704 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06BE4 |
| 705 | |
| 706 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06BE8 |
| 707 | |
| 708 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF06BEC |
| 709 | |
| 710 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06BF0 |
| 711 | |
| 712 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06BF4 |
| 713 | |
| 714 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF06BF8 |
| 715 | |
| 716 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06BFC |
| 717 | |
| 718 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06C00 |
| 719 | |
| 720 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF06C04 |
| 721 | |
| 722 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06C08 |
| 723 | |
| 724 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06C0C |
| 725 | |
| 726 | #define mmTPC4_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF06C10 |
| 727 | |
| 728 | #define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06C14 |
| 729 | |
| 730 | #define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06C18 |
| 731 | |
| 732 | #define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06C1C |
| 733 | |
| 734 | #define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06C20 |
| 735 | |
| 736 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06C24 |
| 737 | |
| 738 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06C28 |
| 739 | |
| 740 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF06C2C |
| 741 | |
| 742 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06C30 |
| 743 | |
| 744 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06C34 |
| 745 | |
| 746 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF06C38 |
| 747 | |
| 748 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06C3C |
| 749 | |
| 750 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06C40 |
| 751 | |
| 752 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF06C44 |
| 753 | |
| 754 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06C48 |
| 755 | |
| 756 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06C4C |
| 757 | |
| 758 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF06C50 |
| 759 | |
| 760 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06C54 |
| 761 | |
| 762 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06C58 |
| 763 | |
| 764 | #define mmTPC4_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF06C5C |
| 765 | |
| 766 | #define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06C60 |
| 767 | |
| 768 | #define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06C64 |
| 769 | |
| 770 | #define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06C68 |
| 771 | |
| 772 | #define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06C6C |
| 773 | |
| 774 | #define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06C70 |
| 775 | |
| 776 | #define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06C74 |
| 777 | |
| 778 | #define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06C78 |
| 779 | |
| 780 | #define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06C7C |
| 781 | |
| 782 | #define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06C80 |
| 783 | |
| 784 | #define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06C84 |
| 785 | |
| 786 | #define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06C88 |
| 787 | |
| 788 | #define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06C8C |
| 789 | |
| 790 | #define mmTPC4_CFG_QM_SRF_0 0xF06C90 |
| 791 | |
| 792 | #define mmTPC4_CFG_QM_SRF_1 0xF06C94 |
| 793 | |
| 794 | #define mmTPC4_CFG_QM_SRF_2 0xF06C98 |
| 795 | |
| 796 | #define mmTPC4_CFG_QM_SRF_3 0xF06C9C |
| 797 | |
| 798 | #define mmTPC4_CFG_QM_SRF_4 0xF06CA0 |
| 799 | |
| 800 | #define mmTPC4_CFG_QM_SRF_5 0xF06CA4 |
| 801 | |
| 802 | #define mmTPC4_CFG_QM_SRF_6 0xF06CA8 |
| 803 | |
| 804 | #define mmTPC4_CFG_QM_SRF_7 0xF06CAC |
| 805 | |
| 806 | #define mmTPC4_CFG_QM_SRF_8 0xF06CB0 |
| 807 | |
| 808 | #define mmTPC4_CFG_QM_SRF_9 0xF06CB4 |
| 809 | |
| 810 | #define mmTPC4_CFG_QM_SRF_10 0xF06CB8 |
| 811 | |
| 812 | #define mmTPC4_CFG_QM_SRF_11 0xF06CBC |
| 813 | |
| 814 | #define mmTPC4_CFG_QM_SRF_12 0xF06CC0 |
| 815 | |
| 816 | #define mmTPC4_CFG_QM_SRF_13 0xF06CC4 |
| 817 | |
| 818 | #define mmTPC4_CFG_QM_SRF_14 0xF06CC8 |
| 819 | |
| 820 | #define mmTPC4_CFG_QM_SRF_15 0xF06CCC |
| 821 | |
| 822 | #define mmTPC4_CFG_QM_SRF_16 0xF06CD0 |
| 823 | |
| 824 | #define mmTPC4_CFG_QM_SRF_17 0xF06CD4 |
| 825 | |
| 826 | #define mmTPC4_CFG_QM_SRF_18 0xF06CD8 |
| 827 | |
| 828 | #define mmTPC4_CFG_QM_SRF_19 0xF06CDC |
| 829 | |
| 830 | #define mmTPC4_CFG_QM_SRF_20 0xF06CE0 |
| 831 | |
| 832 | #define mmTPC4_CFG_QM_SRF_21 0xF06CE4 |
| 833 | |
| 834 | #define mmTPC4_CFG_QM_SRF_22 0xF06CE8 |
| 835 | |
| 836 | #define mmTPC4_CFG_QM_SRF_23 0xF06CEC |
| 837 | |
| 838 | #define mmTPC4_CFG_QM_SRF_24 0xF06CF0 |
| 839 | |
| 840 | #define mmTPC4_CFG_QM_SRF_25 0xF06CF4 |
| 841 | |
| 842 | #define mmTPC4_CFG_QM_SRF_26 0xF06CF8 |
| 843 | |
| 844 | #define mmTPC4_CFG_QM_SRF_27 0xF06CFC |
| 845 | |
| 846 | #define mmTPC4_CFG_QM_SRF_28 0xF06D00 |
| 847 | |
| 848 | #define mmTPC4_CFG_QM_SRF_29 0xF06D04 |
| 849 | |
| 850 | #define mmTPC4_CFG_QM_SRF_30 0xF06D08 |
| 851 | |
| 852 | #define mmTPC4_CFG_QM_SRF_31 0xF06D0C |
| 853 | |
| 854 | #define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06D10 |
| 855 | |
| 856 | #define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D14 |
| 857 | |
| 858 | #define mmTPC4_CFG_ARUSER 0xF06D18 |
| 859 | |
| 860 | #define mmTPC4_CFG_AWUSER 0xF06D1C |
| 861 | |
| 862 | #define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF06E00 |
| 863 | |
| 864 | #define mmTPC4_CFG_FUNC_MBIST_PAT 0xF06E04 |
| 865 | |
| 866 | #define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF06E08 |
| 867 | |
| 868 | #define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF06E0C |
| 869 | |
| 870 | #define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF06E10 |
| 871 | |
| 872 | #define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF06E14 |
| 873 | |
| 874 | #define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF06E18 |
| 875 | |
| 876 | #define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF06E1C |
| 877 | |
| 878 | #define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF06E20 |
| 879 | |
| 880 | #define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF06E24 |
| 881 | |
| 882 | #define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF06E28 |
| 883 | |
| 884 | #define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF06E2C |
| 885 | |
| 886 | #endif /* ASIC_REG_TPC4_CFG_REGS_H_ */ |
| 887 | |