1/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2/* Copyright(c) 2015 - 2021 Intel Corporation */
3#ifndef ADF_PFVF_MSG_H
4#define ADF_PFVF_MSG_H
5
6#include <linux/bits.h>
7
8/*
9 * PF<->VF Gen2 Messaging format
10 *
11 * The PF has an array of 32-bit PF2VF registers, one for each VF. The
12 * PF can access all these registers while each VF can access only the one
13 * register associated with that particular VF.
14 *
15 * The register functionally is split into two parts:
16 * The bottom half is for PF->VF messages. In particular when the first
17 * bit of this register (bit 0) gets set an interrupt will be triggered
18 * in the respective VF.
19 * The top half is for VF->PF messages. In particular when the first bit
20 * of this half of register (bit 16) gets set an interrupt will be triggered
21 * in the PF.
22 *
23 * The remaining bits within this register are available to encode messages.
24 * and implement a collision control mechanism to prevent concurrent use of
25 * the PF2VF register by both the PF and VF.
26 *
27 * 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
28 * _______________________________________________
29 * | | | | | | | | | | | | | | | | |
30 * +-----------------------------------------------+
31 * \___________________________/ \_________/ ^ ^
32 * ^ ^ | |
33 * | | | VF2PF Int
34 * | | Message Origin
35 * | Message Type
36 * Message-specific Data/Reserved
37 *
38 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
39 * _______________________________________________
40 * | | | | | | | | | | | | | | | | |
41 * +-----------------------------------------------+
42 * \___________________________/ \_________/ ^ ^
43 * ^ ^ | |
44 * | | | PF2VF Int
45 * | | Message Origin
46 * | Message Type
47 * Message-specific Data/Reserved
48 *
49 * Message Origin (Should always be 1)
50 * A legacy out-of-tree QAT driver allowed for a set of messages not supported
51 * by this driver; these had a Msg Origin of 0 and are ignored by this driver.
52 *
53 * When a PF or VF attempts to send a message in the lower or upper 16 bits,
54 * respectively, the other 16 bits are written to first with a defined
55 * IN_USE_BY pattern as part of a collision control scheme (see function
56 * adf_gen2_pfvf_send() in adf_pf2vf_msg.c).
57 *
58 *
59 * PF<->VF Gen4 Messaging format
60 *
61 * Similarly to the gen2 messaging format, 32-bit long registers are used for
62 * communication between PF and VFs. However, each VF and PF share a pair of
63 * 32-bits register to avoid collisions: one for PV to VF messages and one
64 * for VF to PF messages.
65 *
66 * Both the Interrupt bit and the Message Origin bit retain the same position
67 * and meaning, although non-system messages are now deprecated and not
68 * expected.
69 *
70 * 31 30 9 8 7 6 5 4 3 2 1 0
71 * _______________________________________________
72 * | | | . . . | | | | | | | | | | |
73 * +-----------------------------------------------+
74 * \_____________________/ \_______________/ ^ ^
75 * ^ ^ | |
76 * | | | PF/VF Int
77 * | | Message Origin
78 * | Message Type
79 * Message-specific Data/Reserved
80 *
81 * For both formats, the message reception is acknowledged by lowering the
82 * interrupt bit on the register where the message was sent.
83 */
84
85/* PFVF message common bits */
86#define ADF_PFVF_INT BIT(0)
87#define ADF_PFVF_MSGORIGIN_SYSTEM BIT(1)
88
89/* Different generations have different CSR layouts, use this struct
90 * to abstract these differences away
91 */
92struct pfvf_message {
93 u8 type;
94 u32 data;
95};
96
97/* PF->VF messages */
98enum pf2vf_msgtype {
99 ADF_PF2VF_MSGTYPE_RESTARTING = 0x01,
100 ADF_PF2VF_MSGTYPE_VERSION_RESP = 0x02,
101 ADF_PF2VF_MSGTYPE_BLKMSG_RESP = 0x03,
102 ADF_PF2VF_MSGTYPE_FATAL_ERROR = 0x04,
103 ADF_PF2VF_MSGTYPE_RESTARTED = 0x05,
104/* Values from 0x10 are Gen4 specific, message type is only 4 bits in Gen2 devices. */
105 ADF_PF2VF_MSGTYPE_RP_RESET_RESP = 0x10,
106};
107
108/* VF->PF messages */
109enum vf2pf_msgtype {
110 ADF_VF2PF_MSGTYPE_INIT = 0x03,
111 ADF_VF2PF_MSGTYPE_SHUTDOWN = 0x04,
112 ADF_VF2PF_MSGTYPE_VERSION_REQ = 0x05,
113 ADF_VF2PF_MSGTYPE_COMPAT_VER_REQ = 0x06,
114 ADF_VF2PF_MSGTYPE_LARGE_BLOCK_REQ = 0x07,
115 ADF_VF2PF_MSGTYPE_MEDIUM_BLOCK_REQ = 0x08,
116 ADF_VF2PF_MSGTYPE_SMALL_BLOCK_REQ = 0x09,
117 ADF_VF2PF_MSGTYPE_RESTARTING_COMPLETE = 0x0a,
118/* Values from 0x10 are Gen4 specific, message type is only 4 bits in Gen2 devices. */
119 ADF_VF2PF_MSGTYPE_RP_RESET = 0x10,
120};
121
122/* VF/PF compatibility version. */
123enum pfvf_compatibility_version {
124 /* Support for extended capabilities */
125 ADF_PFVF_COMPAT_CAPABILITIES = 0x02,
126 /* In-use pattern cleared by receiver */
127 ADF_PFVF_COMPAT_FAST_ACK = 0x03,
128 /* Ring to service mapping support for non-standard mappings */
129 ADF_PFVF_COMPAT_RING_TO_SVC_MAP = 0x04,
130 /* Fallback compat */
131 ADF_PFVF_COMPAT_FALLBACK = 0x05,
132 /* Reference to the latest version */
133 ADF_PFVF_COMPAT_THIS_VERSION = 0x05,
134};
135
136/* PF->VF Version Response */
137#define ADF_PF2VF_VERSION_RESP_VERS_MASK GENMASK(7, 0)
138#define ADF_PF2VF_VERSION_RESP_RESULT_MASK GENMASK(9, 8)
139
140enum pf2vf_compat_response {
141 ADF_PF2VF_VF_COMPATIBLE = 0x01,
142 ADF_PF2VF_VF_INCOMPATIBLE = 0x02,
143 ADF_PF2VF_VF_COMPAT_UNKNOWN = 0x03,
144};
145
146enum ring_reset_result {
147 RPRESET_SUCCESS = 0x00,
148 RPRESET_NOT_SUPPORTED = 0x01,
149 RPRESET_INVAL_BANK = 0x02,
150 RPRESET_TIMEOUT = 0x03,
151};
152
153#define ADF_VF2PF_RNG_RESET_RP_MASK GENMASK(1, 0)
154#define ADF_VF2PF_RNG_RESET_RSVD_MASK GENMASK(25, 2)
155
156/* PF->VF Block Responses */
157#define ADF_PF2VF_BLKMSG_RESP_TYPE_MASK GENMASK(1, 0)
158#define ADF_PF2VF_BLKMSG_RESP_DATA_MASK GENMASK(9, 2)
159
160enum pf2vf_blkmsg_resp_type {
161 ADF_PF2VF_BLKMSG_RESP_TYPE_DATA = 0x00,
162 ADF_PF2VF_BLKMSG_RESP_TYPE_CRC = 0x01,
163 ADF_PF2VF_BLKMSG_RESP_TYPE_ERROR = 0x02,
164};
165
166/* PF->VF Block Error Code */
167enum pf2vf_blkmsg_error {
168 ADF_PF2VF_INVALID_BLOCK_TYPE = 0x00,
169 ADF_PF2VF_INVALID_BYTE_NUM_REQ = 0x01,
170 ADF_PF2VF_PAYLOAD_TRUNCATED = 0x02,
171 ADF_PF2VF_UNSPECIFIED_ERROR = 0x03,
172};
173
174/* VF->PF Block Requests */
175#define ADF_VF2PF_LARGE_BLOCK_TYPE_MASK GENMASK(1, 0)
176#define ADF_VF2PF_LARGE_BLOCK_BYTE_MASK GENMASK(8, 2)
177#define ADF_VF2PF_MEDIUM_BLOCK_TYPE_MASK GENMASK(2, 0)
178#define ADF_VF2PF_MEDIUM_BLOCK_BYTE_MASK GENMASK(8, 3)
179#define ADF_VF2PF_SMALL_BLOCK_TYPE_MASK GENMASK(3, 0)
180#define ADF_VF2PF_SMALL_BLOCK_BYTE_MASK GENMASK(8, 4)
181#define ADF_VF2PF_BLOCK_CRC_REQ_MASK BIT(9)
182
183/* PF->VF Block Request Types
184 * 0..15 - 32 byte message
185 * 16..23 - 64 byte message
186 * 24..27 - 128 byte message
187 */
188enum vf2pf_blkmsg_req_type {
189 ADF_VF2PF_BLKMSG_REQ_CAP_SUMMARY = 0x02,
190 ADF_VF2PF_BLKMSG_REQ_RING_SVC_MAP = 0x03,
191};
192
193#define ADF_VF2PF_SMALL_BLOCK_TYPE_MAX \
194 (FIELD_MAX(ADF_VF2PF_SMALL_BLOCK_TYPE_MASK))
195
196#define ADF_VF2PF_MEDIUM_BLOCK_TYPE_MAX \
197 (FIELD_MAX(ADF_VF2PF_MEDIUM_BLOCK_TYPE_MASK) + \
198 ADF_VF2PF_SMALL_BLOCK_TYPE_MAX + 1)
199
200#define ADF_VF2PF_LARGE_BLOCK_TYPE_MAX \
201 (FIELD_MAX(ADF_VF2PF_LARGE_BLOCK_TYPE_MASK) + \
202 ADF_VF2PF_MEDIUM_BLOCK_TYPE_MAX)
203
204#define ADF_VF2PF_SMALL_BLOCK_BYTE_MAX \
205 FIELD_MAX(ADF_VF2PF_SMALL_BLOCK_BYTE_MASK)
206
207#define ADF_VF2PF_MEDIUM_BLOCK_BYTE_MAX \
208 FIELD_MAX(ADF_VF2PF_MEDIUM_BLOCK_BYTE_MASK)
209
210#define ADF_VF2PF_LARGE_BLOCK_BYTE_MAX \
211 FIELD_MAX(ADF_VF2PF_LARGE_BLOCK_BYTE_MASK)
212
213struct pfvf_blkmsg_header {
214 u8 version;
215 u8 payload_size;
216} __packed;
217
218#define ADF_PFVF_BLKMSG_HEADER_SIZE (sizeof(struct pfvf_blkmsg_header))
219#define ADF_PFVF_BLKMSG_PAYLOAD_SIZE(blkmsg) (sizeof(blkmsg) - \
220 ADF_PFVF_BLKMSG_HEADER_SIZE)
221#define ADF_PFVF_BLKMSG_MSG_SIZE(blkmsg) (ADF_PFVF_BLKMSG_HEADER_SIZE + \
222 (blkmsg)->hdr.payload_size)
223#define ADF_PFVF_BLKMSG_MSG_MAX_SIZE 128
224
225/* PF->VF Block message header bytes */
226#define ADF_PFVF_BLKMSG_VER_BYTE 0
227#define ADF_PFVF_BLKMSG_LEN_BYTE 1
228
229/* PF/VF Capabilities message values */
230enum blkmsg_capabilities_versions {
231 ADF_PFVF_CAPABILITIES_V1_VERSION = 0x01,
232 ADF_PFVF_CAPABILITIES_V2_VERSION = 0x02,
233 ADF_PFVF_CAPABILITIES_V3_VERSION = 0x03,
234};
235
236struct capabilities_v1 {
237 struct pfvf_blkmsg_header hdr;
238 u32 ext_dc_caps;
239} __packed;
240
241struct capabilities_v2 {
242 struct pfvf_blkmsg_header hdr;
243 u32 ext_dc_caps;
244 u32 capabilities;
245} __packed;
246
247struct capabilities_v3 {
248 struct pfvf_blkmsg_header hdr;
249 u32 ext_dc_caps;
250 u32 capabilities;
251 u32 frequency;
252} __packed;
253
254/* PF/VF Ring to service mapping values */
255enum blkmsg_ring_to_svc_versions {
256 ADF_PFVF_RING_TO_SVC_VERSION = 0x01,
257};
258
259struct ring_to_svc_map_v1 {
260 struct pfvf_blkmsg_header hdr;
261 u16 map;
262} __packed;
263
264#endif /* ADF_PFVF_MSG_H */
265

source code of linux/drivers/crypto/intel/qat/qat_common/adf_pfvf_msg.h