1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #ifndef __AMDGPU_ATOMBIOS_H__ |
25 | #define __AMDGPU_ATOMBIOS_H__ |
26 | |
27 | struct atom_clock_dividers { |
28 | u32 post_div; |
29 | union { |
30 | struct { |
31 | #ifdef __BIG_ENDIAN |
32 | u32 reserved : 6; |
33 | u32 whole_fb_div : 12; |
34 | u32 frac_fb_div : 14; |
35 | #else |
36 | u32 frac_fb_div : 14; |
37 | u32 whole_fb_div : 12; |
38 | u32 reserved : 6; |
39 | #endif |
40 | }; |
41 | u32 fb_div; |
42 | }; |
43 | u32 ref_div; |
44 | bool enable_post_div; |
45 | bool enable_dithen; |
46 | u32 vco_mode; |
47 | u32 real_clock; |
48 | /* added for CI */ |
49 | u32 post_divider; |
50 | u32 flags; |
51 | }; |
52 | |
53 | struct atom_mpll_param { |
54 | union { |
55 | struct { |
56 | #ifdef __BIG_ENDIAN |
57 | u32 reserved : 8; |
58 | u32 clkfrac : 12; |
59 | u32 clkf : 12; |
60 | #else |
61 | u32 clkf : 12; |
62 | u32 clkfrac : 12; |
63 | u32 reserved : 8; |
64 | #endif |
65 | }; |
66 | u32 fb_div; |
67 | }; |
68 | u32 post_div; |
69 | u32 bwcntl; |
70 | u32 dll_speed; |
71 | u32 vco_mode; |
72 | u32 yclk_sel; |
73 | u32 qdr; |
74 | u32 half_rate; |
75 | }; |
76 | |
77 | #define MEM_TYPE_GDDR5 0x50 |
78 | #define MEM_TYPE_GDDR4 0x40 |
79 | #define MEM_TYPE_GDDR3 0x30 |
80 | #define MEM_TYPE_DDR2 0x20 |
81 | #define MEM_TYPE_GDDR1 0x10 |
82 | #define MEM_TYPE_DDR3 0xb0 |
83 | #define MEM_TYPE_MASK 0xf0 |
84 | |
85 | struct atom_memory_info { |
86 | u8 mem_vendor; |
87 | u8 mem_type; |
88 | }; |
89 | |
90 | #define MAX_AC_TIMING_ENTRIES 16 |
91 | |
92 | struct atom_memory_clock_range_table { |
93 | u8 num_entries; |
94 | u8 rsv[3]; |
95 | u32 mclk[MAX_AC_TIMING_ENTRIES]; |
96 | }; |
97 | |
98 | #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 |
99 | #define VBIOS_MAX_AC_TIMING_ENTRIES 20 |
100 | |
101 | struct atom_mc_reg_entry { |
102 | u32 mclk_max; |
103 | u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
104 | }; |
105 | |
106 | struct atom_mc_register_address { |
107 | u16 s1; |
108 | u8 pre_reg_data; |
109 | }; |
110 | |
111 | struct atom_mc_reg_table { |
112 | u8 last; |
113 | u8 num_entries; |
114 | struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; |
115 | struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
116 | }; |
117 | |
118 | #define MAX_VOLTAGE_ENTRIES 32 |
119 | |
120 | struct atom_voltage_table_entry { |
121 | u16 value; |
122 | u32 smio_low; |
123 | }; |
124 | |
125 | struct atom_voltage_table { |
126 | u32 count; |
127 | u32 mask_low; |
128 | u32 phase_delay; |
129 | struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; |
130 | }; |
131 | |
132 | struct amdgpu_gpio_rec |
133 | amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev, |
134 | u8 id); |
135 | |
136 | struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev, |
137 | uint8_t id); |
138 | void amdgpu_atombios_i2c_init(struct amdgpu_device *adev); |
139 | |
140 | bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev); |
141 | |
142 | bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev); |
143 | |
144 | int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev); |
145 | |
146 | int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev); |
147 | |
148 | int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev); |
149 | |
150 | bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, |
151 | struct amdgpu_atom_ss *ss, |
152 | int id, u32 clock); |
153 | |
154 | int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, |
155 | u8 clock_type, |
156 | u32 clock, |
157 | bool strobe_mode, |
158 | struct atom_clock_dividers *dividers); |
159 | |
160 | #ifdef CONFIG_DRM_AMDGPU_SI |
161 | int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, |
162 | u32 clock, |
163 | bool strobe_mode, |
164 | struct atom_mpll_param *mpll_param); |
165 | |
166 | void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, |
167 | u32 eng_clock, u32 mem_clock); |
168 | |
169 | bool |
170 | amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, |
171 | u8 voltage_type, u8 voltage_mode); |
172 | |
173 | int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, |
174 | u8 voltage_type, u8 voltage_mode, |
175 | struct atom_voltage_table *voltage_table); |
176 | |
177 | int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, |
178 | u8 module_index, |
179 | struct atom_mc_reg_table *reg_table); |
180 | int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type, |
181 | u16 voltage_id, u16 *voltage); |
182 | int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev, |
183 | u16 *voltage, |
184 | u16 leakage_idx); |
185 | void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev, |
186 | u16 *vddc, u16 *vddci, u16 *mvdd); |
187 | int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev, |
188 | u8 voltage_type, |
189 | u8 *svd_gpio_id, u8 *svc_gpio_id); |
190 | #endif |
191 | |
192 | bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev); |
193 | |
194 | void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock); |
195 | void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev, |
196 | bool hung); |
197 | void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device *adev, |
198 | u32 backlight_level); |
199 | bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev); |
200 | |
201 | void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); |
202 | int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, |
203 | u8 clock_type, |
204 | u32 clock, |
205 | bool strobe_mode, |
206 | struct atom_clock_dividers *dividers); |
207 | |
208 | int amdgpu_atombios_get_data_table(struct amdgpu_device *adev, |
209 | uint32_t table, |
210 | uint16_t *size, |
211 | uint8_t *frev, |
212 | uint8_t *crev, |
213 | uint8_t **addr); |
214 | |
215 | void amdgpu_atombios_fini(struct amdgpu_device *adev); |
216 | int amdgpu_atombios_init(struct amdgpu_device *adev); |
217 | int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev); |
218 | |
219 | #endif |
220 | |