1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
25 | */ |
26 | |
27 | #include <linux/export.h> |
28 | #include <linux/pci.h> |
29 | |
30 | #include <drm/drm_edid.h> |
31 | #include <drm/amdgpu_drm.h> |
32 | #include "amdgpu.h" |
33 | #include "amdgpu_i2c.h" |
34 | #include "amdgpu_atombios.h" |
35 | #include "atom.h" |
36 | #include "atombios_dp.h" |
37 | #include "atombios_i2c.h" |
38 | |
39 | /* bit banging i2c */ |
40 | static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap) |
41 | { |
42 | struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(adap: i2c_adap); |
43 | struct amdgpu_device *adev = drm_to_adev(ddev: i2c->dev); |
44 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; |
45 | uint32_t temp; |
46 | |
47 | mutex_lock(&i2c->mutex); |
48 | |
49 | /* switch the pads to ddc mode */ |
50 | if (rec->hw_capable) { |
51 | temp = RREG32(rec->mask_clk_reg); |
52 | temp &= ~(1 << 16); |
53 | WREG32(rec->mask_clk_reg, temp); |
54 | } |
55 | |
56 | /* clear the output pin values */ |
57 | temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; |
58 | WREG32(rec->a_clk_reg, temp); |
59 | |
60 | temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; |
61 | WREG32(rec->a_data_reg, temp); |
62 | |
63 | /* set the pins to input */ |
64 | temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; |
65 | WREG32(rec->en_clk_reg, temp); |
66 | |
67 | temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; |
68 | WREG32(rec->en_data_reg, temp); |
69 | |
70 | /* mask the gpio pins for software use */ |
71 | temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; |
72 | WREG32(rec->mask_clk_reg, temp); |
73 | temp = RREG32(rec->mask_clk_reg); |
74 | |
75 | temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; |
76 | WREG32(rec->mask_data_reg, temp); |
77 | temp = RREG32(rec->mask_data_reg); |
78 | |
79 | return 0; |
80 | } |
81 | |
82 | static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap) |
83 | { |
84 | struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(adap: i2c_adap); |
85 | struct amdgpu_device *adev = drm_to_adev(ddev: i2c->dev); |
86 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; |
87 | uint32_t temp; |
88 | |
89 | /* unmask the gpio pins for software use */ |
90 | temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; |
91 | WREG32(rec->mask_clk_reg, temp); |
92 | temp = RREG32(rec->mask_clk_reg); |
93 | |
94 | temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; |
95 | WREG32(rec->mask_data_reg, temp); |
96 | temp = RREG32(rec->mask_data_reg); |
97 | |
98 | mutex_unlock(lock: &i2c->mutex); |
99 | } |
100 | |
101 | static int amdgpu_i2c_get_clock(void *i2c_priv) |
102 | { |
103 | struct amdgpu_i2c_chan *i2c = i2c_priv; |
104 | struct amdgpu_device *adev = drm_to_adev(ddev: i2c->dev); |
105 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; |
106 | uint32_t val; |
107 | |
108 | /* read the value off the pin */ |
109 | val = RREG32(rec->y_clk_reg); |
110 | val &= rec->y_clk_mask; |
111 | |
112 | return (val != 0); |
113 | } |
114 | |
115 | |
116 | static int amdgpu_i2c_get_data(void *i2c_priv) |
117 | { |
118 | struct amdgpu_i2c_chan *i2c = i2c_priv; |
119 | struct amdgpu_device *adev = drm_to_adev(ddev: i2c->dev); |
120 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; |
121 | uint32_t val; |
122 | |
123 | /* read the value off the pin */ |
124 | val = RREG32(rec->y_data_reg); |
125 | val &= rec->y_data_mask; |
126 | |
127 | return (val != 0); |
128 | } |
129 | |
130 | static void amdgpu_i2c_set_clock(void *i2c_priv, int clock) |
131 | { |
132 | struct amdgpu_i2c_chan *i2c = i2c_priv; |
133 | struct amdgpu_device *adev = drm_to_adev(ddev: i2c->dev); |
134 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; |
135 | uint32_t val; |
136 | |
137 | /* set pin direction */ |
138 | val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; |
139 | val |= clock ? 0 : rec->en_clk_mask; |
140 | WREG32(rec->en_clk_reg, val); |
141 | } |
142 | |
143 | static void amdgpu_i2c_set_data(void *i2c_priv, int data) |
144 | { |
145 | struct amdgpu_i2c_chan *i2c = i2c_priv; |
146 | struct amdgpu_device *adev = drm_to_adev(ddev: i2c->dev); |
147 | struct amdgpu_i2c_bus_rec *rec = &i2c->rec; |
148 | uint32_t val; |
149 | |
150 | /* set pin direction */ |
151 | val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; |
152 | val |= data ? 0 : rec->en_data_mask; |
153 | WREG32(rec->en_data_reg, val); |
154 | } |
155 | |
156 | static const struct i2c_algorithm amdgpu_atombios_i2c_algo = { |
157 | .master_xfer = amdgpu_atombios_i2c_xfer, |
158 | .functionality = amdgpu_atombios_i2c_func, |
159 | }; |
160 | |
161 | struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, |
162 | const struct amdgpu_i2c_bus_rec *rec, |
163 | const char *name) |
164 | { |
165 | struct amdgpu_i2c_chan *i2c; |
166 | int ret; |
167 | |
168 | /* don't add the mm_i2c bus unless hw_i2c is enabled */ |
169 | if (rec->mm_i2c && (amdgpu_hw_i2c == 0)) |
170 | return NULL; |
171 | |
172 | i2c = kzalloc(size: sizeof(struct amdgpu_i2c_chan), GFP_KERNEL); |
173 | if (i2c == NULL) |
174 | return NULL; |
175 | |
176 | i2c->rec = *rec; |
177 | i2c->adapter.owner = THIS_MODULE; |
178 | i2c->adapter.class = I2C_CLASS_DDC; |
179 | i2c->adapter.dev.parent = dev->dev; |
180 | i2c->dev = dev; |
181 | i2c_set_adapdata(adap: &i2c->adapter, data: i2c); |
182 | mutex_init(&i2c->mutex); |
183 | if (rec->hw_capable && |
184 | amdgpu_hw_i2c) { |
185 | /* hw i2c using atom */ |
186 | snprintf(buf: i2c->adapter.name, size: sizeof(i2c->adapter.name), |
187 | fmt: "AMDGPU i2c hw bus %s" , name); |
188 | i2c->adapter.algo = &amdgpu_atombios_i2c_algo; |
189 | ret = i2c_add_adapter(adap: &i2c->adapter); |
190 | if (ret) |
191 | goto out_free; |
192 | } else { |
193 | /* set the amdgpu bit adapter */ |
194 | snprintf(buf: i2c->adapter.name, size: sizeof(i2c->adapter.name), |
195 | fmt: "AMDGPU i2c bit bus %s" , name); |
196 | i2c->adapter.algo_data = &i2c->bit; |
197 | i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer; |
198 | i2c->bit.post_xfer = amdgpu_i2c_post_xfer; |
199 | i2c->bit.setsda = amdgpu_i2c_set_data; |
200 | i2c->bit.setscl = amdgpu_i2c_set_clock; |
201 | i2c->bit.getsda = amdgpu_i2c_get_data; |
202 | i2c->bit.getscl = amdgpu_i2c_get_clock; |
203 | i2c->bit.udelay = 10; |
204 | i2c->bit.timeout = usecs_to_jiffies(u: 2200); /* from VESA */ |
205 | i2c->bit.data = i2c; |
206 | ret = i2c_bit_add_bus(&i2c->adapter); |
207 | if (ret) { |
208 | DRM_ERROR("Failed to register bit i2c %s\n" , name); |
209 | goto out_free; |
210 | } |
211 | } |
212 | |
213 | return i2c; |
214 | out_free: |
215 | kfree(objp: i2c); |
216 | return NULL; |
217 | |
218 | } |
219 | |
220 | void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c) |
221 | { |
222 | if (!i2c) |
223 | return; |
224 | WARN_ON(i2c->has_aux); |
225 | i2c_del_adapter(adap: &i2c->adapter); |
226 | kfree(objp: i2c); |
227 | } |
228 | |
229 | /* Add the default buses */ |
230 | void amdgpu_i2c_init(struct amdgpu_device *adev) |
231 | { |
232 | if (amdgpu_hw_i2c) |
233 | DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n" ); |
234 | |
235 | amdgpu_atombios_i2c_init(adev); |
236 | } |
237 | |
238 | /* remove all the buses */ |
239 | void amdgpu_i2c_fini(struct amdgpu_device *adev) |
240 | { |
241 | int i; |
242 | |
243 | for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { |
244 | if (adev->i2c_bus[i]) { |
245 | amdgpu_i2c_destroy(i2c: adev->i2c_bus[i]); |
246 | adev->i2c_bus[i] = NULL; |
247 | } |
248 | } |
249 | } |
250 | |
251 | /* Add additional buses */ |
252 | void amdgpu_i2c_add(struct amdgpu_device *adev, |
253 | const struct amdgpu_i2c_bus_rec *rec, |
254 | const char *name) |
255 | { |
256 | struct drm_device *dev = adev_to_drm(adev); |
257 | int i; |
258 | |
259 | for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { |
260 | if (!adev->i2c_bus[i]) { |
261 | adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name); |
262 | return; |
263 | } |
264 | } |
265 | } |
266 | |
267 | /* looks up bus based on id */ |
268 | struct amdgpu_i2c_chan * |
269 | amdgpu_i2c_lookup(struct amdgpu_device *adev, |
270 | const struct amdgpu_i2c_bus_rec *i2c_bus) |
271 | { |
272 | int i; |
273 | |
274 | for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { |
275 | if (adev->i2c_bus[i] && |
276 | (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { |
277 | return adev->i2c_bus[i]; |
278 | } |
279 | } |
280 | return NULL; |
281 | } |
282 | |
283 | static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus, |
284 | u8 slave_addr, |
285 | u8 addr, |
286 | u8 *val) |
287 | { |
288 | u8 out_buf[2]; |
289 | u8 in_buf[2]; |
290 | struct i2c_msg msgs[] = { |
291 | { |
292 | .addr = slave_addr, |
293 | .flags = 0, |
294 | .len = 1, |
295 | .buf = out_buf, |
296 | }, |
297 | { |
298 | .addr = slave_addr, |
299 | .flags = I2C_M_RD, |
300 | .len = 1, |
301 | .buf = in_buf, |
302 | } |
303 | }; |
304 | |
305 | out_buf[0] = addr; |
306 | out_buf[1] = 0; |
307 | |
308 | if (i2c_transfer(adap: &i2c_bus->adapter, msgs, num: 2) == 2) { |
309 | *val = in_buf[0]; |
310 | DRM_DEBUG("val = 0x%02x\n" , *val); |
311 | } else { |
312 | DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n" , |
313 | addr, *val); |
314 | } |
315 | } |
316 | |
317 | static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus, |
318 | u8 slave_addr, |
319 | u8 addr, |
320 | u8 val) |
321 | { |
322 | uint8_t out_buf[2]; |
323 | struct i2c_msg msg = { |
324 | .addr = slave_addr, |
325 | .flags = 0, |
326 | .len = 2, |
327 | .buf = out_buf, |
328 | }; |
329 | |
330 | out_buf[0] = addr; |
331 | out_buf[1] = val; |
332 | |
333 | if (i2c_transfer(adap: &i2c_bus->adapter, msgs: &msg, num: 1) != 1) |
334 | DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n" , |
335 | addr, val); |
336 | } |
337 | |
338 | /* ddc router switching */ |
339 | void |
340 | amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector) |
341 | { |
342 | u8 val = 0; |
343 | |
344 | if (!amdgpu_connector->router.ddc_valid) |
345 | return; |
346 | |
347 | if (!amdgpu_connector->router_bus) |
348 | return; |
349 | |
350 | amdgpu_i2c_get_byte(i2c_bus: amdgpu_connector->router_bus, |
351 | slave_addr: amdgpu_connector->router.i2c_addr, |
352 | addr: 0x3, val: &val); |
353 | val &= ~amdgpu_connector->router.ddc_mux_control_pin; |
354 | amdgpu_i2c_put_byte(i2c_bus: amdgpu_connector->router_bus, |
355 | slave_addr: amdgpu_connector->router.i2c_addr, |
356 | addr: 0x3, val); |
357 | amdgpu_i2c_get_byte(i2c_bus: amdgpu_connector->router_bus, |
358 | slave_addr: amdgpu_connector->router.i2c_addr, |
359 | addr: 0x1, val: &val); |
360 | val &= ~amdgpu_connector->router.ddc_mux_control_pin; |
361 | val |= amdgpu_connector->router.ddc_mux_state; |
362 | amdgpu_i2c_put_byte(i2c_bus: amdgpu_connector->router_bus, |
363 | slave_addr: amdgpu_connector->router.i2c_addr, |
364 | addr: 0x1, val); |
365 | } |
366 | |
367 | /* clock/data router switching */ |
368 | void |
369 | amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector) |
370 | { |
371 | u8 val; |
372 | |
373 | if (!amdgpu_connector->router.cd_valid) |
374 | return; |
375 | |
376 | if (!amdgpu_connector->router_bus) |
377 | return; |
378 | |
379 | amdgpu_i2c_get_byte(i2c_bus: amdgpu_connector->router_bus, |
380 | slave_addr: amdgpu_connector->router.i2c_addr, |
381 | addr: 0x3, val: &val); |
382 | val &= ~amdgpu_connector->router.cd_mux_control_pin; |
383 | amdgpu_i2c_put_byte(i2c_bus: amdgpu_connector->router_bus, |
384 | slave_addr: amdgpu_connector->router.i2c_addr, |
385 | addr: 0x3, val); |
386 | amdgpu_i2c_get_byte(i2c_bus: amdgpu_connector->router_bus, |
387 | slave_addr: amdgpu_connector->router.i2c_addr, |
388 | addr: 0x1, val: &val); |
389 | val &= ~amdgpu_connector->router.cd_mux_control_pin; |
390 | val |= amdgpu_connector->router.cd_mux_state; |
391 | amdgpu_i2c_put_byte(i2c_bus: amdgpu_connector->router_bus, |
392 | slave_addr: amdgpu_connector->router.i2c_addr, |
393 | addr: 0x1, val); |
394 | } |
395 | |