1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef __AMDGPU_UCODE_H__ |
24 | #define __AMDGPU_UCODE_H__ |
25 | |
26 | #include "amdgpu_socbb.h" |
27 | |
28 | struct { |
29 | uint32_t ; /* size of the entire header+image(s) in bytes */ |
30 | uint32_t ; /* size of just the header in bytes */ |
31 | uint16_t ; /* header version */ |
32 | uint16_t ; /* header version */ |
33 | uint16_t ; /* IP version */ |
34 | uint16_t ; /* IP version */ |
35 | uint32_t ; |
36 | uint32_t ; /* size of ucode in bytes */ |
37 | uint32_t ; /* payload offset from the start of the header */ |
38 | uint32_t ; /* crc32 checksum of the payload */ |
39 | }; |
40 | |
41 | /* version_major=1, version_minor=0 */ |
42 | struct { |
43 | struct common_firmware_header ; |
44 | uint32_t ; /* size of debug array in dwords */ |
45 | uint32_t ; /* payload offset from the start of the header */ |
46 | }; |
47 | |
48 | /* version_major=1, version_minor=0 */ |
49 | struct { |
50 | struct common_firmware_header ; |
51 | uint32_t ; |
52 | }; |
53 | |
54 | /* version_major=2, version_minor=0 */ |
55 | struct { |
56 | struct smc_firmware_header_v1_0 ; |
57 | uint32_t ; /* soft pptable offset */ |
58 | uint32_t ; /* soft pptable size */ |
59 | }; |
60 | |
61 | struct smc_soft_pptable_entry { |
62 | uint32_t id; |
63 | uint32_t ppt_offset_bytes; |
64 | uint32_t ppt_size_bytes; |
65 | }; |
66 | |
67 | /* version_major=2, version_minor=1 */ |
68 | struct { |
69 | struct smc_firmware_header_v1_0 ; |
70 | uint32_t ; |
71 | uint32_t ; |
72 | }; |
73 | |
74 | struct psp_fw_legacy_bin_desc { |
75 | uint32_t fw_version; |
76 | uint32_t offset_bytes; |
77 | uint32_t size_bytes; |
78 | }; |
79 | |
80 | /* version_major=1, version_minor=0 */ |
81 | struct { |
82 | struct common_firmware_header ; |
83 | struct psp_fw_legacy_bin_desc ; |
84 | }; |
85 | |
86 | /* version_major=1, version_minor=1 */ |
87 | struct { |
88 | struct psp_firmware_header_v1_0 ; |
89 | struct psp_fw_legacy_bin_desc ; |
90 | struct psp_fw_legacy_bin_desc ; |
91 | }; |
92 | |
93 | /* version_major=1, version_minor=2 */ |
94 | struct { |
95 | struct psp_firmware_header_v1_0 ; |
96 | struct psp_fw_legacy_bin_desc ; |
97 | struct psp_fw_legacy_bin_desc ; |
98 | }; |
99 | |
100 | /* version_major=1, version_minor=3 */ |
101 | struct { |
102 | struct psp_firmware_header_v1_1 ; |
103 | struct psp_fw_legacy_bin_desc ; |
104 | struct psp_fw_legacy_bin_desc ; |
105 | struct psp_fw_legacy_bin_desc ; |
106 | struct psp_fw_legacy_bin_desc ; |
107 | }; |
108 | |
109 | struct psp_fw_bin_desc { |
110 | uint32_t fw_type; |
111 | uint32_t fw_version; |
112 | uint32_t offset_bytes; |
113 | uint32_t size_bytes; |
114 | }; |
115 | |
116 | enum psp_fw_type { |
117 | PSP_FW_TYPE_UNKOWN, |
118 | PSP_FW_TYPE_PSP_SOS, |
119 | PSP_FW_TYPE_PSP_SYS_DRV, |
120 | PSP_FW_TYPE_PSP_KDB, |
121 | PSP_FW_TYPE_PSP_TOC, |
122 | PSP_FW_TYPE_PSP_SPL, |
123 | PSP_FW_TYPE_PSP_RL, |
124 | PSP_FW_TYPE_PSP_SOC_DRV, |
125 | PSP_FW_TYPE_PSP_INTF_DRV, |
126 | PSP_FW_TYPE_PSP_DBG_DRV, |
127 | PSP_FW_TYPE_PSP_RAS_DRV, |
128 | PSP_FW_TYPE_MAX_INDEX, |
129 | }; |
130 | |
131 | /* version_major=2, version_minor=0 */ |
132 | struct { |
133 | struct common_firmware_header ; |
134 | uint32_t ; |
135 | struct psp_fw_bin_desc []; |
136 | }; |
137 | |
138 | /* version_major=1, version_minor=0 */ |
139 | struct { |
140 | struct common_firmware_header ; |
141 | struct psp_fw_legacy_bin_desc ; |
142 | struct psp_fw_legacy_bin_desc ; |
143 | struct psp_fw_legacy_bin_desc ; |
144 | struct psp_fw_legacy_bin_desc ; |
145 | struct psp_fw_legacy_bin_desc ; |
146 | }; |
147 | |
148 | enum ta_fw_type { |
149 | TA_FW_TYPE_UNKOWN, |
150 | TA_FW_TYPE_PSP_ASD, |
151 | TA_FW_TYPE_PSP_XGMI, |
152 | TA_FW_TYPE_PSP_RAS, |
153 | TA_FW_TYPE_PSP_HDCP, |
154 | TA_FW_TYPE_PSP_DTM, |
155 | TA_FW_TYPE_PSP_RAP, |
156 | TA_FW_TYPE_PSP_SECUREDISPLAY, |
157 | TA_FW_TYPE_MAX_INDEX, |
158 | }; |
159 | |
160 | /* version_major=2, version_minor=0 */ |
161 | struct { |
162 | struct common_firmware_header ; |
163 | uint32_t ; |
164 | struct psp_fw_bin_desc []; |
165 | }; |
166 | |
167 | /* version_major=1, version_minor=0 */ |
168 | struct { |
169 | struct common_firmware_header ; |
170 | uint32_t ; |
171 | uint32_t ; /* jt location */ |
172 | uint32_t ; /* size of jt */ |
173 | }; |
174 | |
175 | /* version_major=2, version_minor=0 */ |
176 | struct { |
177 | struct common_firmware_header ; |
178 | uint32_t ; |
179 | uint32_t ; |
180 | uint32_t ; |
181 | uint32_t ; |
182 | uint32_t ; |
183 | uint32_t ; |
184 | uint32_t ; |
185 | }; |
186 | |
187 | /* version_major=1, version_minor=0 */ |
188 | struct { |
189 | struct common_firmware_header ; |
190 | uint32_t ; |
191 | uint32_t ; |
192 | uint32_t ; |
193 | uint32_t ; |
194 | uint32_t ; |
195 | uint32_t ; |
196 | uint32_t ; |
197 | uint32_t ; |
198 | uint32_t ; |
199 | uint32_t ; |
200 | }; |
201 | |
202 | /* version_major=1, version_minor=0 */ |
203 | struct { |
204 | struct common_firmware_header ; |
205 | uint32_t ; |
206 | uint32_t save_and_restore_offset; |
207 | uint32_t ; |
208 | uint32_t ; |
209 | uint32_t ; |
210 | }; |
211 | |
212 | /* version_major=2, version_minor=0 */ |
213 | struct { |
214 | struct common_firmware_header ; |
215 | uint32_t ; |
216 | uint32_t ; /* jt location */ |
217 | uint32_t ; /* size of jt */ |
218 | uint32_t save_and_restore_offset; |
219 | uint32_t ; |
220 | uint32_t ; |
221 | uint32_t ; |
222 | uint32_t ; |
223 | uint32_t ; |
224 | uint32_t ; |
225 | uint32_t ; /* size of reg list format array in bytes */ |
226 | uint32_t ; /* payload offset from the start of the header */ |
227 | uint32_t ; /* size of reg list array in bytes */ |
228 | uint32_t ; /* payload offset from the start of the header */ |
229 | uint32_t ; /* size of reg list format array in bytes */ |
230 | uint32_t ; /* payload offset from the start of the header */ |
231 | uint32_t ; /* size of reg list array in bytes */ |
232 | uint32_t ; /* payload offset from the start of the header */ |
233 | }; |
234 | |
235 | /* version_major=2, version_minor=1 */ |
236 | struct { |
237 | struct rlc_firmware_header_v2_0 ; |
238 | uint32_t ; /* length of direct reg list format array */ |
239 | uint32_t ; |
240 | uint32_t ; |
241 | uint32_t ; |
242 | uint32_t ; |
243 | uint32_t ; |
244 | uint32_t ; |
245 | uint32_t ; |
246 | uint32_t ; |
247 | uint32_t ; |
248 | uint32_t ; |
249 | uint32_t ; |
250 | uint32_t ; |
251 | }; |
252 | |
253 | /* version_major=2, version_minor=2 */ |
254 | struct { |
255 | struct rlc_firmware_header_v2_1 ; |
256 | uint32_t ; |
257 | uint32_t ; |
258 | uint32_t ; |
259 | uint32_t ; |
260 | }; |
261 | |
262 | /* version_major=2, version_minor=3 */ |
263 | struct { |
264 | struct rlc_firmware_header_v2_2 ; |
265 | uint32_t ; |
266 | uint32_t ; |
267 | uint32_t ; |
268 | uint32_t ; |
269 | uint32_t ; |
270 | uint32_t ; |
271 | uint32_t ; |
272 | uint32_t ; |
273 | }; |
274 | |
275 | /* version_major=2, version_minor=4 */ |
276 | struct { |
277 | struct rlc_firmware_header_v2_3 ; |
278 | uint32_t ; |
279 | uint32_t ; |
280 | uint32_t ; |
281 | uint32_t ; |
282 | uint32_t ; |
283 | uint32_t ; |
284 | uint32_t ; |
285 | uint32_t ; |
286 | uint32_t ; |
287 | uint32_t ; |
288 | }; |
289 | |
290 | /* version_major=1, version_minor=0 */ |
291 | struct { |
292 | struct common_firmware_header ; |
293 | uint32_t ; |
294 | uint32_t ; |
295 | uint32_t ; /* jt location */ |
296 | uint32_t ; /* size of jt */ |
297 | }; |
298 | |
299 | /* version_major=1, version_minor=1 */ |
300 | struct { |
301 | struct sdma_firmware_header_v1_0 ; |
302 | uint32_t ; |
303 | }; |
304 | |
305 | /* version_major=2, version_minor=0 */ |
306 | struct { |
307 | struct common_firmware_header ; |
308 | uint32_t ; |
309 | uint32_t ; /* context thread ucode size */ |
310 | uint32_t ; /* context thread jt location */ |
311 | uint32_t ; /* context thread size of jt */ |
312 | uint32_t ; |
313 | uint32_t ; /* control thread ucode size */ |
314 | uint32_t ; /* control thread jt location */ |
315 | uint32_t ; /* control thread size of jt */ |
316 | }; |
317 | |
318 | /* version_major=1, version_minor=0 */ |
319 | struct { |
320 | struct common_firmware_header ; |
321 | uint32_t ; |
322 | uint32_t ; /* context thread ucode size */ |
323 | uint32_t ; /* context thread jt location */ |
324 | uint32_t ; /* context thread size of jt */ |
325 | uint32_t ; |
326 | uint32_t ; /* control thread ucode size */ |
327 | uint32_t ; /* control thread jt location */ |
328 | uint32_t ; /* control thread size of jt */ |
329 | }; |
330 | |
331 | /* version_major=1, version_minor=0 */ |
332 | struct { |
333 | struct common_firmware_header ; |
334 | uint32_t ; |
335 | uint32_t ; |
336 | uint32_t ; |
337 | uint32_t ; |
338 | uint32_t ; |
339 | uint32_t ; |
340 | uint32_t ; |
341 | uint32_t ; |
342 | uint32_t ; |
343 | uint32_t ; |
344 | uint32_t ; |
345 | uint32_t ; |
346 | }; |
347 | |
348 | /* gpu info payload */ |
349 | struct gpu_info_firmware_v1_0 { |
350 | uint32_t gc_num_se; |
351 | uint32_t gc_num_cu_per_sh; |
352 | uint32_t gc_num_sh_per_se; |
353 | uint32_t gc_num_rb_per_se; |
354 | uint32_t gc_num_tccs; |
355 | uint32_t gc_num_gprs; |
356 | uint32_t gc_num_max_gs_thds; |
357 | uint32_t gc_gs_table_depth; |
358 | uint32_t gc_gsprim_buff_depth; |
359 | uint32_t gc_parameter_cache_depth; |
360 | uint32_t gc_double_offchip_lds_buffer; |
361 | uint32_t gc_wave_size; |
362 | uint32_t gc_max_waves_per_simd; |
363 | uint32_t gc_max_scratch_slots_per_cu; |
364 | uint32_t gc_lds_size; |
365 | }; |
366 | |
367 | struct gpu_info_firmware_v1_1 { |
368 | struct gpu_info_firmware_v1_0 v1_0; |
369 | uint32_t num_sc_per_sh; |
370 | uint32_t num_packer_per_sc; |
371 | }; |
372 | |
373 | /* gpu info payload |
374 | * version_major=1, version_minor=1 */ |
375 | struct gpu_info_firmware_v1_2 { |
376 | struct gpu_info_firmware_v1_1 v1_1; |
377 | struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; |
378 | }; |
379 | |
380 | /* version_major=1, version_minor=0 */ |
381 | struct { |
382 | struct common_firmware_header ; |
383 | uint16_t ; /* version */ |
384 | uint16_t ; /* version */ |
385 | }; |
386 | |
387 | /* version_major=1, version_minor=0 */ |
388 | struct { |
389 | struct common_firmware_header ; |
390 | uint32_t ; /* interrupt vectors offset from end of header, in bytes */ |
391 | uint32_t ; /* size of interrupt vectors, in bytes */ |
392 | }; |
393 | |
394 | /* version_major=1, version_minor=0 */ |
395 | struct { |
396 | struct common_firmware_header ; |
397 | uint32_t ; /* size of instruction region, in bytes */ |
398 | uint32_t ; /* size of bss/data region, in bytes */ |
399 | }; |
400 | |
401 | /* version_major=1, version_minor=0 */ |
402 | struct { |
403 | struct common_firmware_header ; |
404 | uint32_t ; |
405 | uint32_t ; |
406 | uint32_t ; |
407 | uint32_t ; |
408 | }; |
409 | |
410 | /* header is fixed size */ |
411 | union { |
412 | struct common_firmware_header ; |
413 | struct mc_firmware_header_v1_0 ; |
414 | struct smc_firmware_header_v1_0 ; |
415 | struct smc_firmware_header_v2_0 ; |
416 | struct psp_firmware_header_v1_0 ; |
417 | struct psp_firmware_header_v1_1 ; |
418 | struct psp_firmware_header_v1_3 ; |
419 | struct psp_firmware_header_v2_0 ; |
420 | struct ta_firmware_header_v1_0 ; |
421 | struct ta_firmware_header_v2_0 ; |
422 | struct gfx_firmware_header_v1_0 ; |
423 | struct gfx_firmware_header_v2_0 ; |
424 | struct rlc_firmware_header_v1_0 ; |
425 | struct rlc_firmware_header_v2_0 ; |
426 | struct rlc_firmware_header_v2_1 ; |
427 | struct rlc_firmware_header_v2_2 ; |
428 | struct rlc_firmware_header_v2_3 ; |
429 | struct rlc_firmware_header_v2_4 ; |
430 | struct sdma_firmware_header_v1_0 ; |
431 | struct sdma_firmware_header_v1_1 ; |
432 | struct sdma_firmware_header_v2_0 ; |
433 | struct gpu_info_firmware_header_v1_0 ; |
434 | struct dmcu_firmware_header_v1_0 ; |
435 | struct dmcub_firmware_header_v1_0 ; |
436 | struct imu_firmware_header_v1_0 ; |
437 | uint8_t [0x100]; |
438 | }; |
439 | |
440 | #define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) |
441 | |
442 | /* |
443 | * fw loading support |
444 | */ |
445 | enum AMDGPU_UCODE_ID { |
446 | AMDGPU_UCODE_ID_CAP = 0, |
447 | AMDGPU_UCODE_ID_SDMA0, |
448 | AMDGPU_UCODE_ID_SDMA1, |
449 | AMDGPU_UCODE_ID_SDMA2, |
450 | AMDGPU_UCODE_ID_SDMA3, |
451 | AMDGPU_UCODE_ID_SDMA4, |
452 | AMDGPU_UCODE_ID_SDMA5, |
453 | AMDGPU_UCODE_ID_SDMA6, |
454 | AMDGPU_UCODE_ID_SDMA7, |
455 | AMDGPU_UCODE_ID_SDMA_UCODE_TH0, |
456 | AMDGPU_UCODE_ID_SDMA_UCODE_TH1, |
457 | AMDGPU_UCODE_ID_CP_CE, |
458 | AMDGPU_UCODE_ID_CP_PFP, |
459 | AMDGPU_UCODE_ID_CP_ME, |
460 | AMDGPU_UCODE_ID_CP_RS64_PFP, |
461 | AMDGPU_UCODE_ID_CP_RS64_ME, |
462 | AMDGPU_UCODE_ID_CP_RS64_MEC, |
463 | AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK, |
464 | AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK, |
465 | AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK, |
466 | AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK, |
467 | AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK, |
468 | AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK, |
469 | AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK, |
470 | AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK, |
471 | AMDGPU_UCODE_ID_CP_MEC1, |
472 | AMDGPU_UCODE_ID_CP_MEC1_JT, |
473 | AMDGPU_UCODE_ID_CP_MEC2, |
474 | AMDGPU_UCODE_ID_CP_MEC2_JT, |
475 | AMDGPU_UCODE_ID_CP_MES, |
476 | AMDGPU_UCODE_ID_CP_MES_DATA, |
477 | AMDGPU_UCODE_ID_CP_MES1, |
478 | AMDGPU_UCODE_ID_CP_MES1_DATA, |
479 | AMDGPU_UCODE_ID_IMU_I, |
480 | AMDGPU_UCODE_ID_IMU_D, |
481 | AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS, |
482 | AMDGPU_UCODE_ID_SE0_TAP_DELAYS, |
483 | AMDGPU_UCODE_ID_SE1_TAP_DELAYS, |
484 | AMDGPU_UCODE_ID_SE2_TAP_DELAYS, |
485 | AMDGPU_UCODE_ID_SE3_TAP_DELAYS, |
486 | AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, |
487 | AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, |
488 | AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, |
489 | AMDGPU_UCODE_ID_RLC_IRAM, |
490 | AMDGPU_UCODE_ID_RLC_DRAM, |
491 | AMDGPU_UCODE_ID_RLC_P, |
492 | AMDGPU_UCODE_ID_RLC_V, |
493 | AMDGPU_UCODE_ID_RLC_G, |
494 | AMDGPU_UCODE_ID_STORAGE, |
495 | AMDGPU_UCODE_ID_SMC, |
496 | AMDGPU_UCODE_ID_PPTABLE, |
497 | AMDGPU_UCODE_ID_UVD, |
498 | AMDGPU_UCODE_ID_UVD1, |
499 | AMDGPU_UCODE_ID_VCE, |
500 | AMDGPU_UCODE_ID_VCN, |
501 | AMDGPU_UCODE_ID_VCN1, |
502 | AMDGPU_UCODE_ID_DMCU_ERAM, |
503 | AMDGPU_UCODE_ID_DMCU_INTV, |
504 | AMDGPU_UCODE_ID_VCN0_RAM, |
505 | AMDGPU_UCODE_ID_VCN1_RAM, |
506 | AMDGPU_UCODE_ID_DMCUB, |
507 | AMDGPU_UCODE_ID_VPE_CTX, |
508 | AMDGPU_UCODE_ID_VPE_CTL, |
509 | AMDGPU_UCODE_ID_VPE, |
510 | AMDGPU_UCODE_ID_UMSCH_MM_UCODE, |
511 | AMDGPU_UCODE_ID_UMSCH_MM_DATA, |
512 | AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER, |
513 | AMDGPU_UCODE_ID_P2S_TABLE, |
514 | AMDGPU_UCODE_ID_MAXIMUM, |
515 | }; |
516 | |
517 | /* engine firmware status */ |
518 | enum AMDGPU_UCODE_STATUS { |
519 | AMDGPU_UCODE_STATUS_INVALID, |
520 | AMDGPU_UCODE_STATUS_NOT_LOADED, |
521 | AMDGPU_UCODE_STATUS_LOADED, |
522 | }; |
523 | |
524 | enum amdgpu_firmware_load_type { |
525 | AMDGPU_FW_LOAD_DIRECT = 0, |
526 | AMDGPU_FW_LOAD_PSP, |
527 | AMDGPU_FW_LOAD_SMU, |
528 | AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, |
529 | }; |
530 | |
531 | /* conform to smu_ucode_xfer_cz.h */ |
532 | #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 |
533 | #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 |
534 | #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 |
535 | #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 |
536 | #define AMDGPU_CPME_UCODE_LOADED 0x00000010 |
537 | #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 |
538 | #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 |
539 | #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 |
540 | |
541 | /* amdgpu firmware info */ |
542 | struct amdgpu_firmware_info { |
543 | /* ucode ID */ |
544 | enum AMDGPU_UCODE_ID ucode_id; |
545 | /* request_firmware */ |
546 | const struct firmware *fw; |
547 | /* starting mc address */ |
548 | uint64_t mc_addr; |
549 | /* kernel linear address */ |
550 | void *kaddr; |
551 | /* ucode_size_bytes */ |
552 | uint32_t ucode_size; |
553 | /* starting tmr mc address */ |
554 | uint32_t tmr_mc_addr_lo; |
555 | uint32_t tmr_mc_addr_hi; |
556 | }; |
557 | |
558 | struct amdgpu_firmware { |
559 | struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; |
560 | enum amdgpu_firmware_load_type load_type; |
561 | struct amdgpu_bo *fw_buf; |
562 | unsigned int fw_size; |
563 | unsigned int max_ucodes; |
564 | /* firmwares are loaded by psp instead of smu from vega10 */ |
565 | const struct amdgpu_psp_funcs *funcs; |
566 | struct amdgpu_bo *rbuf; |
567 | struct mutex mutex; |
568 | |
569 | /* gpu info firmware data pointer */ |
570 | const struct firmware *gpu_info_fw; |
571 | |
572 | void *fw_buf_ptr; |
573 | uint64_t fw_buf_mc; |
574 | }; |
575 | |
576 | void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); |
577 | void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); |
578 | void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr); |
579 | void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); |
580 | void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); |
581 | void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); |
582 | void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); |
583 | void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); |
584 | int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, |
585 | const char *fw_name); |
586 | void amdgpu_ucode_release(const struct firmware **fw); |
587 | bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, |
588 | uint16_t hdr_major, uint16_t hdr_minor); |
589 | |
590 | int amdgpu_ucode_init_bo(struct amdgpu_device *adev); |
591 | int amdgpu_ucode_create_bo(struct amdgpu_device *adev); |
592 | int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); |
593 | void amdgpu_ucode_free_bo(struct amdgpu_device *adev); |
594 | void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); |
595 | |
596 | enum amdgpu_firmware_load_type |
597 | amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); |
598 | |
599 | const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); |
600 | |
601 | void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len); |
602 | |
603 | #endif |
604 | |