1 | /* |
2 | * Copyright (c) 2018-2021 Advanced Micro Devices, Inc. All rights reserved. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
5 | * of this software and associated documentation files (the "Software"), to deal |
6 | * in the Software without restriction, including without limitation the rights |
7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
8 | * copies of the Software, and to permit persons to whom the Software is |
9 | * furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
17 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
20 | * THE SOFTWARE. |
21 | */ |
22 | |
23 | #ifndef AMDGV_SRIOV_MSG__H_ |
24 | #define AMDGV_SRIOV_MSG__H_ |
25 | |
26 | /* unit in kilobytes */ |
27 | #define AMD_SRIOV_MSG_VBIOS_OFFSET 0 |
28 | #define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64 |
29 | #define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB |
30 | #define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4 |
31 | |
32 | /* |
33 | * layout |
34 | * 0 64KB 65KB 66KB |
35 | * | VBIOS | PF2VF | VF2PF | Bad Page | ... |
36 | * | 64KB | 1KB | 1KB | |
37 | */ |
38 | #define AMD_SRIOV_MSG_SIZE_KB 1 |
39 | #define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB |
40 | #define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) |
41 | #define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) |
42 | |
43 | /* |
44 | * PF2VF history log: |
45 | * v1 defined in amdgim |
46 | * v2 current |
47 | * |
48 | * VF2PF history log: |
49 | * v1 defined in amdgim |
50 | * v2 defined in amdgim |
51 | * v3 current |
52 | */ |
53 | #define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2 |
54 | #define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3 |
55 | |
56 | #define AMD_SRIOV_MSG_RESERVE_UCODE 24 |
57 | |
58 | #define AMD_SRIOV_MSG_RESERVE_VCN_INST 4 |
59 | |
60 | enum amd_sriov_ucode_engine_id { |
61 | AMD_SRIOV_UCODE_ID_VCE = 0, |
62 | AMD_SRIOV_UCODE_ID_UVD, |
63 | AMD_SRIOV_UCODE_ID_MC, |
64 | AMD_SRIOV_UCODE_ID_ME, |
65 | AMD_SRIOV_UCODE_ID_PFP, |
66 | AMD_SRIOV_UCODE_ID_CE, |
67 | AMD_SRIOV_UCODE_ID_RLC, |
68 | AMD_SRIOV_UCODE_ID_RLC_SRLC, |
69 | AMD_SRIOV_UCODE_ID_RLC_SRLG, |
70 | AMD_SRIOV_UCODE_ID_RLC_SRLS, |
71 | AMD_SRIOV_UCODE_ID_MEC, |
72 | AMD_SRIOV_UCODE_ID_MEC2, |
73 | AMD_SRIOV_UCODE_ID_SOS, |
74 | AMD_SRIOV_UCODE_ID_ASD, |
75 | AMD_SRIOV_UCODE_ID_TA_RAS, |
76 | AMD_SRIOV_UCODE_ID_TA_XGMI, |
77 | AMD_SRIOV_UCODE_ID_SMC, |
78 | AMD_SRIOV_UCODE_ID_SDMA, |
79 | AMD_SRIOV_UCODE_ID_SDMA2, |
80 | AMD_SRIOV_UCODE_ID_VCN, |
81 | AMD_SRIOV_UCODE_ID_DMCU, |
82 | AMD_SRIOV_UCODE_ID__MAX |
83 | }; |
84 | |
85 | #pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed |
86 | |
87 | union amd_sriov_msg_feature_flags { |
88 | struct { |
89 | uint32_t error_log_collect : 1; |
90 | uint32_t host_load_ucodes : 1; |
91 | uint32_t host_flr_vramlost : 1; |
92 | uint32_t mm_bw_management : 1; |
93 | uint32_t pp_one_vf_mode : 1; |
94 | uint32_t reg_indirect_acc : 1; |
95 | uint32_t av1_support : 1; |
96 | uint32_t vcn_rb_decouple : 1; |
97 | uint32_t reserved : 24; |
98 | } flags; |
99 | uint32_t all; |
100 | }; |
101 | |
102 | union amd_sriov_reg_access_flags { |
103 | struct { |
104 | uint32_t vf_reg_access_ih : 1; |
105 | uint32_t vf_reg_access_mmhub : 1; |
106 | uint32_t vf_reg_access_gc : 1; |
107 | uint32_t reserved : 29; |
108 | } flags; |
109 | uint32_t all; |
110 | }; |
111 | |
112 | union amd_sriov_msg_os_info { |
113 | struct { |
114 | uint32_t windows : 1; |
115 | uint32_t reserved : 31; |
116 | } info; |
117 | uint32_t all; |
118 | }; |
119 | |
120 | struct amd_sriov_msg_uuid_info { |
121 | union { |
122 | struct { |
123 | uint32_t did : 16; |
124 | uint32_t fcn : 8; |
125 | uint32_t asic_7 : 8; |
126 | }; |
127 | uint32_t time_low; |
128 | }; |
129 | |
130 | struct { |
131 | uint32_t time_mid : 16; |
132 | uint32_t time_high : 12; |
133 | uint32_t version : 4; |
134 | }; |
135 | |
136 | struct { |
137 | struct { |
138 | uint8_t clk_seq_hi : 6; |
139 | uint8_t variant : 2; |
140 | }; |
141 | union { |
142 | uint8_t clk_seq_low; |
143 | uint8_t asic_6; |
144 | }; |
145 | uint16_t asic_4; |
146 | }; |
147 | |
148 | uint32_t asic_0; |
149 | }; |
150 | |
151 | struct { |
152 | /* the total structure size in byte */ |
153 | uint32_t ; |
154 | /* version of this structure, written by the HOST */ |
155 | uint32_t ; |
156 | /* reserved */ |
157 | uint32_t [2]; |
158 | }; |
159 | |
160 | #define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (48) |
161 | struct amd_sriov_msg_pf2vf_info { |
162 | /* header contains size and version */ |
163 | struct amd_sriov_msg_pf2vf_info_header ; |
164 | /* use private key from mailbox 2 to create checksum */ |
165 | uint32_t checksum; |
166 | /* The features flags of the HOST driver supports */ |
167 | union amd_sriov_msg_feature_flags feature_flags; |
168 | /* (max_width * max_height * fps) / (16 * 16) */ |
169 | uint32_t hevc_enc_max_mb_per_second; |
170 | /* (max_width * max_height) / (16 * 16) */ |
171 | uint32_t hevc_enc_max_mb_per_frame; |
172 | /* (max_width * max_height * fps) / (16 * 16) */ |
173 | uint32_t avc_enc_max_mb_per_second; |
174 | /* (max_width * max_height) / (16 * 16) */ |
175 | uint32_t avc_enc_max_mb_per_frame; |
176 | /* MEC FW position in BYTE from the start of VF visible frame buffer */ |
177 | uint64_t mecfw_offset; |
178 | /* MEC FW size in BYTE */ |
179 | uint32_t mecfw_size; |
180 | /* UVD FW position in BYTE from the start of VF visible frame buffer */ |
181 | uint64_t uvdfw_offset; |
182 | /* UVD FW size in BYTE */ |
183 | uint32_t uvdfw_size; |
184 | /* VCE FW position in BYTE from the start of VF visible frame buffer */ |
185 | uint64_t vcefw_offset; |
186 | /* VCE FW size in BYTE */ |
187 | uint32_t vcefw_size; |
188 | /* Bad pages block position in BYTE */ |
189 | uint32_t bp_block_offset_low; |
190 | uint32_t bp_block_offset_high; |
191 | /* Bad pages block size in BYTE */ |
192 | uint32_t bp_block_size; |
193 | /* frequency for VF to update the VF2PF area in msec, 0 = manual */ |
194 | uint32_t vf2pf_update_interval_ms; |
195 | /* identification in ROCm SMI */ |
196 | uint64_t uuid; |
197 | uint32_t fcn_idx; |
198 | /* flags to indicate which register access method VF should use */ |
199 | union amd_sriov_reg_access_flags reg_access_flags; |
200 | /* MM BW management */ |
201 | struct { |
202 | uint32_t decode_max_dimension_pixels; |
203 | uint32_t decode_max_frame_pixels; |
204 | uint32_t encode_max_dimension_pixels; |
205 | uint32_t encode_max_frame_pixels; |
206 | } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST]; |
207 | /* UUID info */ |
208 | struct amd_sriov_msg_uuid_info uuid_info; |
209 | /* PCIE atomic ops support flag */ |
210 | uint32_t pcie_atomic_ops_support_flags; |
211 | /* reserved */ |
212 | uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE]; |
213 | }; |
214 | |
215 | struct { |
216 | /* the total structure size in byte */ |
217 | uint32_t ; |
218 | /* version of this structure, written by the guest */ |
219 | uint32_t ; |
220 | /* reserved */ |
221 | uint32_t [2]; |
222 | }; |
223 | |
224 | #define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (70) |
225 | struct amd_sriov_msg_vf2pf_info { |
226 | /* header contains size and version */ |
227 | struct amd_sriov_msg_vf2pf_info_header ; |
228 | uint32_t checksum; |
229 | /* driver version */ |
230 | uint8_t driver_version[64]; |
231 | /* driver certification, 1=WHQL, 0=None */ |
232 | uint32_t driver_cert; |
233 | /* guest OS type and version */ |
234 | union amd_sriov_msg_os_info os_info; |
235 | /* guest fb information in the unit of MB */ |
236 | uint32_t fb_usage; |
237 | /* guest gfx engine usage percentage */ |
238 | uint32_t gfx_usage; |
239 | /* guest gfx engine health percentage */ |
240 | uint32_t gfx_health; |
241 | /* guest compute engine usage percentage */ |
242 | uint32_t compute_usage; |
243 | /* guest compute engine health percentage */ |
244 | uint32_t compute_health; |
245 | /* guest avc engine usage percentage. 0xffff means N/A */ |
246 | uint32_t avc_enc_usage; |
247 | /* guest avc engine health percentage. 0xffff means N/A */ |
248 | uint32_t avc_enc_health; |
249 | /* guest hevc engine usage percentage. 0xffff means N/A */ |
250 | uint32_t hevc_enc_usage; |
251 | /* guest hevc engine usage percentage. 0xffff means N/A */ |
252 | uint32_t hevc_enc_health; |
253 | /* combined encode/decode usage */ |
254 | uint32_t encode_usage; |
255 | uint32_t decode_usage; |
256 | /* Version of PF2VF that VF understands */ |
257 | uint32_t pf2vf_version_required; |
258 | /* additional FB usage */ |
259 | uint32_t fb_vis_usage; |
260 | uint32_t fb_vis_size; |
261 | uint32_t fb_size; |
262 | /* guest ucode data, each one is 1.25 Dword */ |
263 | struct { |
264 | uint8_t id; |
265 | uint32_t version; |
266 | } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE]; |
267 | uint64_t dummy_page_addr; |
268 | |
269 | /* reserved */ |
270 | uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE]; |
271 | }; |
272 | |
273 | /* mailbox message send from guest to host */ |
274 | enum amd_sriov_mailbox_request_message { |
275 | MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1, |
276 | MB_REQ_MSG_REL_GPU_INIT_ACCESS, |
277 | MB_REQ_MSG_REQ_GPU_FINI_ACCESS, |
278 | MB_REQ_MSG_REL_GPU_FINI_ACCESS, |
279 | MB_REQ_MSG_REQ_GPU_RESET_ACCESS, |
280 | MB_REQ_MSG_REQ_GPU_INIT_DATA, |
281 | |
282 | MB_REQ_MSG_LOG_VF_ERROR = 200, |
283 | }; |
284 | |
285 | /* mailbox message send from host to guest */ |
286 | enum amd_sriov_mailbox_response_message { |
287 | MB_RES_MSG_CLR_MSG_BUF = 0, |
288 | MB_RES_MSG_READY_TO_ACCESS_GPU = 1, |
289 | MB_RES_MSG_FLR_NOTIFICATION, |
290 | MB_RES_MSG_FLR_NOTIFICATION_COMPLETION, |
291 | MB_RES_MSG_SUCCESS, |
292 | MB_RES_MSG_FAIL, |
293 | MB_RES_MSG_QUERY_ALIVE, |
294 | MB_RES_MSG_GPU_INIT_DATA_READY, |
295 | |
296 | MB_RES_MSG_TEXT_MESSAGE = 255 |
297 | }; |
298 | |
299 | /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */ |
300 | enum amd_sriov_gpu_init_data_version { |
301 | GPU_INIT_DATA_READY_V1 = 1, |
302 | }; |
303 | |
304 | #pragma pack(pop) // Restore previous packing option |
305 | |
306 | /* checksum function between host and guest */ |
307 | unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key, |
308 | unsigned int checksum); |
309 | |
310 | /* assertion at compile time */ |
311 | #ifdef __linux__ |
312 | #define stringification(s) _stringification(s) |
313 | #define _stringification(s) #s |
314 | |
315 | _Static_assert( |
316 | sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10, |
317 | "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB" ); |
318 | |
319 | _Static_assert( |
320 | sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10, |
321 | "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB" ); |
322 | |
323 | _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0, |
324 | "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4" ); |
325 | |
326 | _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX, |
327 | "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX" ); |
328 | |
329 | #undef _stringification |
330 | #undef stringification |
331 | #endif |
332 | |
333 | #endif /* AMDGV_SRIOV_MSG__H_ */ |
334 | |