1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29
30#include "amdgpu.h"
31#include "amdgpu_gfx.h"
32#include "amdgpu_ring.h"
33#include "vi.h"
34#include "vi_structs.h"
35#include "vid.h"
36#include "amdgpu_ucode.h"
37#include "amdgpu_atombios.h"
38#include "atombios_i2c.h"
39#include "clearstate_vi.h"
40
41#include "gmc/gmc_8_2_d.h"
42#include "gmc/gmc_8_2_sh_mask.h"
43
44#include "oss/oss_3_0_d.h"
45#include "oss/oss_3_0_sh_mask.h"
46
47#include "bif/bif_5_0_d.h"
48#include "bif/bif_5_0_sh_mask.h"
49#include "gca/gfx_8_0_d.h"
50#include "gca/gfx_8_0_enum.h"
51#include "gca/gfx_8_0_sh_mask.h"
52
53#include "dce/dce_10_0_d.h"
54#include "dce/dce_10_0_sh_mask.h"
55
56#include "smu/smu_7_1_3_d.h"
57
58#include "ivsrcid/ivsrcid_vislands30.h"
59
60#define GFX8_NUM_GFX_RINGS 1
61#define GFX8_MEC_HPD_SIZE 4096
62
63#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
64#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
65#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
66#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
67
68#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
69#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
70#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
71#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
72#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
73#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
74#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
75#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
76#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
77
78#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
79#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
80#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
81#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
82#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
83#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
84
85/* BPM SERDES CMD */
86#define SET_BPM_SERDES_CMD 1
87#define CLE_BPM_SERDES_CMD 0
88
89/* BPM Register Address*/
90enum {
91 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
92 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
93 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
94 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
95 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
96 BPM_REG_FGCG_MAX
97};
98
99#define RLC_FormatDirectRegListLength 14
100
101MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
102MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
103MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
104MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
105MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
106MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
107
108MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
109MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
110MODULE_FIRMWARE("amdgpu/stoney_me.bin");
111MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
112MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
113
114MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
115MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
116MODULE_FIRMWARE("amdgpu/tonga_me.bin");
117MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
118MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
119MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
120
121MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
122MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
123MODULE_FIRMWARE("amdgpu/topaz_me.bin");
124MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
125MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
126
127MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
128MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
129MODULE_FIRMWARE("amdgpu/fiji_me.bin");
130MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
131MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
132MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
133
134MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
135MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
136MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
137MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
138MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
139MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
140MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
141MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
142MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
143MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
144MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
145
146MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
147MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
148MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
149MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
150MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
151MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
152MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
153MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
154MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
155MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
156MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
157
158MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
159MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
160MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
161MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
162MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
163MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
164MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
165MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
166MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
167MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
168MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
169
170MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
171MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
172MODULE_FIRMWARE("amdgpu/vegam_me.bin");
173MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
174MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
175MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
176
177static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
178{
179 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
180 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
181 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
182 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
183 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
184 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
185 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
186 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
187 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
188 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
189 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
190 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
191 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
192 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
193 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
194 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
195};
196
197static const u32 golden_settings_tonga_a11[] =
198{
199 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
200 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
201 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
202 mmGB_GPU_ID, 0x0000000f, 0x00000000,
203 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
204 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
205 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
206 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
207 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
208 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
209 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
210 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
211 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
212 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
213 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
214 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
215};
216
217static const u32 tonga_golden_common_all[] =
218{
219 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
220 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
221 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
222 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
223 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
224 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
225 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
226 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
227};
228
229static const u32 tonga_mgcg_cgcg_init[] =
230{
231 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
232 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
233 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
234 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
235 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
236 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
237 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
238 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
239 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
240 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
241 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
242 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
243 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
244 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
245 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
246 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
247 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
248 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
249 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
250 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
251 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
252 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
253 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
254 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
255 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
256 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
257 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
258 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
259 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
260 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
261 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
262 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
263 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
264 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
265 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
266 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
267 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
268 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
269 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
270 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
271 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
272 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
273 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
274 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
275 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
276 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
277 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
278 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
279 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
280 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
281 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
282 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
283 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
284 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
285 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
286 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
287 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
288 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
289 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
290 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
291 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
292 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
293 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
294 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
295 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
296 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
297 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
298 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
299 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
300 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
301 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
302 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
303 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
304 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
305 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
306};
307
308static const u32 golden_settings_vegam_a11[] =
309{
310 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
311 mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
312 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
313 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
314 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
315 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
316 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
317 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
318 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
319 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
320 mmSQ_CONFIG, 0x07f80000, 0x01180000,
321 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
322 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
323 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
324 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
325 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
326 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
327};
328
329static const u32 vegam_golden_common_all[] =
330{
331 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
332 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
333 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
334 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
335 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
336 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
337};
338
339static const u32 golden_settings_polaris11_a11[] =
340{
341 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
342 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
343 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
344 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
345 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
346 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
347 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
348 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
349 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
350 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
351 mmSQ_CONFIG, 0x07f80000, 0x01180000,
352 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
353 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
354 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
355 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
356 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
357 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
358};
359
360static const u32 polaris11_golden_common_all[] =
361{
362 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
363 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
364 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
365 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
366 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
367 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
368};
369
370static const u32 golden_settings_polaris10_a11[] =
371{
372 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
373 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
374 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
375 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
376 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
377 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
378 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
379 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
380 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
381 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
382 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
383 mmSQ_CONFIG, 0x07f80000, 0x07180000,
384 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
385 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
386 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
387 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
388 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
389};
390
391static const u32 polaris10_golden_common_all[] =
392{
393 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
394 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
395 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
396 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
397 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
398 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
399 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
400 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
401};
402
403static const u32 fiji_golden_common_all[] =
404{
405 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
406 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
407 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
408 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
409 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
410 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
411 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
412 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
413 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
414 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
415};
416
417static const u32 golden_settings_fiji_a10[] =
418{
419 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
420 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
421 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
422 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
423 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
424 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
425 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
426 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
427 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
428 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
429 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
430};
431
432static const u32 fiji_mgcg_cgcg_init[] =
433{
434 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
435 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
436 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
437 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
438 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
439 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
440 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
441 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
443 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
444 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
445 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
446 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
447 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
448 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
449 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
450 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
451 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
452 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
453 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
454 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
455 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
456 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
457 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
458 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
459 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
460 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
461 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
462 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
463 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
464 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
465 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
466 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
467 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
468 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
469};
470
471static const u32 golden_settings_iceland_a11[] =
472{
473 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
474 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
475 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
476 mmGB_GPU_ID, 0x0000000f, 0x00000000,
477 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
478 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
479 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
480 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
481 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
482 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
483 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
484 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
485 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
486 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
487 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
488 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
489};
490
491static const u32 iceland_golden_common_all[] =
492{
493 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
494 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
495 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
496 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
497 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
498 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
499 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
500 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
501};
502
503static const u32 iceland_mgcg_cgcg_init[] =
504{
505 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
506 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
507 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
508 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
509 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
510 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
511 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
512 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
513 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
514 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
515 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
516 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
517 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
518 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
519 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
520 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
521 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
522 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
523 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
524 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
525 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
526 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
527 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
528 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
529 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
530 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
531 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
532 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
533 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
534 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
535 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
536 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
537 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
538 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
539 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
540 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
541 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
542 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
543 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
544 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
545 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
546 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
547 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
548 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
549 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
550 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
551 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
552 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
553 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
554 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
555 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
556 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
557 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
558 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
559 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
560 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
561 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
562 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
563 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
564 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
565 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
566 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
567 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
568 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
569};
570
571static const u32 cz_golden_settings_a11[] =
572{
573 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
574 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
575 mmGB_GPU_ID, 0x0000000f, 0x00000000,
576 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
577 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
578 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
579 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
580 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
581 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
582 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
583 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
584 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
585};
586
587static const u32 cz_golden_common_all[] =
588{
589 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
590 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
591 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
592 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
593 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
594 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
595 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
596 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
597};
598
599static const u32 cz_mgcg_cgcg_init[] =
600{
601 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
602 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
603 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
604 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
605 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
606 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
607 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
608 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
609 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
610 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
611 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
612 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
613 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
614 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
615 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
616 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
617 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
618 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
619 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
620 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
621 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
622 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
623 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
624 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
625 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
626 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
627 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
628 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
629 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
630 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
631 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
632 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
633 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
634 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
635 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
636 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
637 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
638 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
639 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
640 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
641 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
642 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
643 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
644 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
645 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
646 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
647 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
648 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
649 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
650 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
651 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
652 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
653 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
654 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
655 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
656 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
657 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
658 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
659 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
660 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
661 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
662 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
663 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
664 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
665 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
666 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
667 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
668 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
669 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
670 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
671 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
672 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
673 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
674 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
675 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
676};
677
678static const u32 stoney_golden_settings_a11[] =
679{
680 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
681 mmGB_GPU_ID, 0x0000000f, 0x00000000,
682 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
683 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
684 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
685 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
686 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
687 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
688 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
689 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
690};
691
692static const u32 stoney_golden_common_all[] =
693{
694 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
695 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
696 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
697 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
698 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
699 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
700 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
701 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
702};
703
704static const u32 stoney_mgcg_cgcg_init[] =
705{
706 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
707 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
708 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
709 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
710 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
711};
712
713
714static const char * const sq_edc_source_names[] = {
715 "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
716 "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
717 "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
718 "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
719 "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
720 "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
721 "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
722};
723
724static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
725static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
726static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
727static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
728static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
729static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
730static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
731static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
732
733#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x0000007fL
734#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x00000000L
735
736static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
737{
738 uint32_t data;
739
740 switch (adev->asic_type) {
741 case CHIP_TOPAZ:
742 amdgpu_device_program_register_sequence(adev,
743 iceland_mgcg_cgcg_init,
744 ARRAY_SIZE(iceland_mgcg_cgcg_init));
745 amdgpu_device_program_register_sequence(adev,
746 golden_settings_iceland_a11,
747 ARRAY_SIZE(golden_settings_iceland_a11));
748 amdgpu_device_program_register_sequence(adev,
749 iceland_golden_common_all,
750 ARRAY_SIZE(iceland_golden_common_all));
751 break;
752 case CHIP_FIJI:
753 amdgpu_device_program_register_sequence(adev,
754 fiji_mgcg_cgcg_init,
755 ARRAY_SIZE(fiji_mgcg_cgcg_init));
756 amdgpu_device_program_register_sequence(adev,
757 golden_settings_fiji_a10,
758 ARRAY_SIZE(golden_settings_fiji_a10));
759 amdgpu_device_program_register_sequence(adev,
760 fiji_golden_common_all,
761 ARRAY_SIZE(fiji_golden_common_all));
762 break;
763
764 case CHIP_TONGA:
765 amdgpu_device_program_register_sequence(adev,
766 tonga_mgcg_cgcg_init,
767 ARRAY_SIZE(tonga_mgcg_cgcg_init));
768 amdgpu_device_program_register_sequence(adev,
769 golden_settings_tonga_a11,
770 ARRAY_SIZE(golden_settings_tonga_a11));
771 amdgpu_device_program_register_sequence(adev,
772 tonga_golden_common_all,
773 ARRAY_SIZE(tonga_golden_common_all));
774 break;
775 case CHIP_VEGAM:
776 amdgpu_device_program_register_sequence(adev,
777 golden_settings_vegam_a11,
778 ARRAY_SIZE(golden_settings_vegam_a11));
779 amdgpu_device_program_register_sequence(adev,
780 vegam_golden_common_all,
781 ARRAY_SIZE(vegam_golden_common_all));
782 break;
783 case CHIP_POLARIS11:
784 case CHIP_POLARIS12:
785 amdgpu_device_program_register_sequence(adev,
786 golden_settings_polaris11_a11,
787 ARRAY_SIZE(golden_settings_polaris11_a11));
788 amdgpu_device_program_register_sequence(adev,
789 polaris11_golden_common_all,
790 ARRAY_SIZE(polaris11_golden_common_all));
791 break;
792 case CHIP_POLARIS10:
793 amdgpu_device_program_register_sequence(adev,
794 golden_settings_polaris10_a11,
795 ARRAY_SIZE(golden_settings_polaris10_a11));
796 amdgpu_device_program_register_sequence(adev,
797 polaris10_golden_common_all,
798 ARRAY_SIZE(polaris10_golden_common_all));
799 data = RREG32_SMC(ixCG_ACLK_CNTL);
800 data &= ~CG_ACLK_CNTL__ACLK_DIVIDER_MASK;
801 data |= 0x18 << CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT;
802 WREG32_SMC(ixCG_ACLK_CNTL, data);
803 if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) &&
804 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
805 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
806 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) {
807 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
808 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
809 }
810 break;
811 case CHIP_CARRIZO:
812 amdgpu_device_program_register_sequence(adev,
813 cz_mgcg_cgcg_init,
814 ARRAY_SIZE(cz_mgcg_cgcg_init));
815 amdgpu_device_program_register_sequence(adev,
816 cz_golden_settings_a11,
817 ARRAY_SIZE(cz_golden_settings_a11));
818 amdgpu_device_program_register_sequence(adev,
819 cz_golden_common_all,
820 ARRAY_SIZE(cz_golden_common_all));
821 break;
822 case CHIP_STONEY:
823 amdgpu_device_program_register_sequence(adev,
824 stoney_mgcg_cgcg_init,
825 ARRAY_SIZE(stoney_mgcg_cgcg_init));
826 amdgpu_device_program_register_sequence(adev,
827 stoney_golden_settings_a11,
828 ARRAY_SIZE(stoney_golden_settings_a11));
829 amdgpu_device_program_register_sequence(adev,
830 stoney_golden_common_all,
831 ARRAY_SIZE(stoney_golden_common_all));
832 break;
833 default:
834 break;
835 }
836}
837
838static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
839{
840 struct amdgpu_device *adev = ring->adev;
841 uint32_t tmp = 0;
842 unsigned i;
843 int r;
844
845 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
846 r = amdgpu_ring_alloc(ring, 3);
847 if (r)
848 return r;
849
850 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
852 amdgpu_ring_write(ring, 0xDEADBEEF);
853 amdgpu_ring_commit(ring);
854
855 for (i = 0; i < adev->usec_timeout; i++) {
856 tmp = RREG32(mmSCRATCH_REG0);
857 if (tmp == 0xDEADBEEF)
858 break;
859 udelay(1);
860 }
861
862 if (i >= adev->usec_timeout)
863 r = -ETIMEDOUT;
864
865 return r;
866}
867
868static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
869{
870 struct amdgpu_device *adev = ring->adev;
871 struct amdgpu_ib ib;
872 struct dma_fence *f = NULL;
873
874 unsigned int index;
875 uint64_t gpu_addr;
876 uint32_t tmp;
877 long r;
878
879 r = amdgpu_device_wb_get(adev, &index);
880 if (r)
881 return r;
882
883 gpu_addr = adev->wb.gpu_addr + (index * 4);
884 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
885 memset(&ib, 0, sizeof(ib));
886 r = amdgpu_ib_get(adev, NULL, 16,
887 AMDGPU_IB_POOL_DIRECT, &ib);
888 if (r)
889 goto err1;
890
891 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
893 ib.ptr[2] = lower_32_bits(gpu_addr);
894 ib.ptr[3] = upper_32_bits(gpu_addr);
895 ib.ptr[4] = 0xDEADBEEF;
896 ib.length_dw = 5;
897
898 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
899 if (r)
900 goto err2;
901
902 r = dma_fence_wait_timeout(f, false, timeout);
903 if (r == 0) {
904 r = -ETIMEDOUT;
905 goto err2;
906 } else if (r < 0) {
907 goto err2;
908 }
909
910 tmp = adev->wb.wb[index];
911 if (tmp == 0xDEADBEEF)
912 r = 0;
913 else
914 r = -EINVAL;
915
916err2:
917 amdgpu_ib_free(adev, &ib, NULL);
918 dma_fence_put(f);
919err1:
920 amdgpu_device_wb_free(adev, index);
921 return r;
922}
923
924
925static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
926{
927 release_firmware(adev->gfx.pfp_fw);
928 adev->gfx.pfp_fw = NULL;
929 release_firmware(adev->gfx.me_fw);
930 adev->gfx.me_fw = NULL;
931 release_firmware(adev->gfx.ce_fw);
932 adev->gfx.ce_fw = NULL;
933 release_firmware(adev->gfx.rlc_fw);
934 adev->gfx.rlc_fw = NULL;
935 release_firmware(adev->gfx.mec_fw);
936 adev->gfx.mec_fw = NULL;
937 if ((adev->asic_type != CHIP_STONEY) &&
938 (adev->asic_type != CHIP_TOPAZ))
939 release_firmware(adev->gfx.mec2_fw);
940 adev->gfx.mec2_fw = NULL;
941
942 kfree(adev->gfx.rlc.register_list_format);
943}
944
945static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
946{
947 const char *chip_name;
948 char fw_name[30];
949 int err;
950 struct amdgpu_firmware_info *info = NULL;
951 const struct common_firmware_header *header = NULL;
952 const struct gfx_firmware_header_v1_0 *cp_hdr;
953 const struct rlc_firmware_header_v2_0 *rlc_hdr;
954 unsigned int *tmp = NULL, i;
955
956 DRM_DEBUG("\n");
957
958 switch (adev->asic_type) {
959 case CHIP_TOPAZ:
960 chip_name = "topaz";
961 break;
962 case CHIP_TONGA:
963 chip_name = "tonga";
964 break;
965 case CHIP_CARRIZO:
966 chip_name = "carrizo";
967 break;
968 case CHIP_FIJI:
969 chip_name = "fiji";
970 break;
971 case CHIP_STONEY:
972 chip_name = "stoney";
973 break;
974 case CHIP_POLARIS10:
975 chip_name = "polaris10";
976 break;
977 case CHIP_POLARIS11:
978 chip_name = "polaris11";
979 break;
980 case CHIP_POLARIS12:
981 chip_name = "polaris12";
982 break;
983 case CHIP_VEGAM:
984 chip_name = "vegam";
985 break;
986 default:
987 BUG();
988 }
989
990 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
991 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
992 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
993 if (err == -ENOENT) {
994 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
995 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
996 }
997 } else {
998 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
999 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1000 }
1001 if (err)
1002 goto out;
1003 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
1004 if (err)
1005 goto out;
1006 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1007 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1008 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1009
1010 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1011 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
1012 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1013 if (err == -ENOENT) {
1014 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1015 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1016 }
1017 } else {
1018 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1019 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1020 }
1021 if (err)
1022 goto out;
1023 err = amdgpu_ucode_validate(adev->gfx.me_fw);
1024 if (err)
1025 goto out;
1026 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1027 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1028
1029 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1030
1031 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1032 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
1033 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1034 if (err == -ENOENT) {
1035 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1036 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1037 }
1038 } else {
1039 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1040 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1041 }
1042 if (err)
1043 goto out;
1044 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
1045 if (err)
1046 goto out;
1047 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1048 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1049 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1050
1051 /*
1052 * Support for MCBP/Virtualization in combination with chained IBs is
1053 * formal released on feature version #46
1054 */
1055 if (adev->gfx.ce_feature_version >= 46 &&
1056 adev->gfx.pfp_feature_version >= 46) {
1057 adev->virt.chained_ib_support = true;
1058 DRM_INFO("Chained IB support enabled!\n");
1059 } else
1060 adev->virt.chained_ib_support = false;
1061
1062 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1063 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1064 if (err)
1065 goto out;
1066 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1067 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1068 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1069 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1070
1071 adev->gfx.rlc.save_and_restore_offset =
1072 le32_to_cpu(rlc_hdr->save_and_restore_offset);
1073 adev->gfx.rlc.clear_state_descriptor_offset =
1074 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1075 adev->gfx.rlc.avail_scratch_ram_locations =
1076 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1077 adev->gfx.rlc.reg_restore_list_size =
1078 le32_to_cpu(rlc_hdr->reg_restore_list_size);
1079 adev->gfx.rlc.reg_list_format_start =
1080 le32_to_cpu(rlc_hdr->reg_list_format_start);
1081 adev->gfx.rlc.reg_list_format_separate_start =
1082 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1083 adev->gfx.rlc.starting_offsets_start =
1084 le32_to_cpu(rlc_hdr->starting_offsets_start);
1085 adev->gfx.rlc.reg_list_format_size_bytes =
1086 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1087 adev->gfx.rlc.reg_list_size_bytes =
1088 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1089
1090 adev->gfx.rlc.register_list_format =
1091 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1092 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1093
1094 if (!adev->gfx.rlc.register_list_format) {
1095 err = -ENOMEM;
1096 goto out;
1097 }
1098
1099 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1100 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1101 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1102 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1103
1104 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1105
1106 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1107 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1108 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1109 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1110
1111 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1112 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
1113 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1114 if (err == -ENOENT) {
1115 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1116 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1117 }
1118 } else {
1119 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1120 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1121 }
1122 if (err)
1123 goto out;
1124 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1125 if (err)
1126 goto out;
1127 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1128 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1129 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1130
1131 if ((adev->asic_type != CHIP_STONEY) &&
1132 (adev->asic_type != CHIP_TOPAZ)) {
1133 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1134 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
1135 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1136 if (err == -ENOENT) {
1137 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1138 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1139 }
1140 } else {
1141 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1142 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1143 }
1144 if (!err) {
1145 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1146 if (err)
1147 goto out;
1148 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1149 adev->gfx.mec2_fw->data;
1150 adev->gfx.mec2_fw_version =
1151 le32_to_cpu(cp_hdr->header.ucode_version);
1152 adev->gfx.mec2_feature_version =
1153 le32_to_cpu(cp_hdr->ucode_feature_version);
1154 } else {
1155 err = 0;
1156 adev->gfx.mec2_fw = NULL;
1157 }
1158 }
1159
1160 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1161 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1162 info->fw = adev->gfx.pfp_fw;
1163 header = (const struct common_firmware_header *)info->fw->data;
1164 adev->firmware.fw_size +=
1165 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1166
1167 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1168 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1169 info->fw = adev->gfx.me_fw;
1170 header = (const struct common_firmware_header *)info->fw->data;
1171 adev->firmware.fw_size +=
1172 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1173
1174 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1175 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1176 info->fw = adev->gfx.ce_fw;
1177 header = (const struct common_firmware_header *)info->fw->data;
1178 adev->firmware.fw_size +=
1179 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1180
1181 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1182 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1183 info->fw = adev->gfx.rlc_fw;
1184 header = (const struct common_firmware_header *)info->fw->data;
1185 adev->firmware.fw_size +=
1186 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1187
1188 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1189 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1190 info->fw = adev->gfx.mec_fw;
1191 header = (const struct common_firmware_header *)info->fw->data;
1192 adev->firmware.fw_size +=
1193 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1194
1195 /* we need account JT in */
1196 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1197 adev->firmware.fw_size +=
1198 ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1199
1200 if (amdgpu_sriov_vf(adev)) {
1201 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1202 info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1203 info->fw = adev->gfx.mec_fw;
1204 adev->firmware.fw_size +=
1205 ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1206 }
1207
1208 if (adev->gfx.mec2_fw) {
1209 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1210 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1211 info->fw = adev->gfx.mec2_fw;
1212 header = (const struct common_firmware_header *)info->fw->data;
1213 adev->firmware.fw_size +=
1214 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1215 }
1216
1217out:
1218 if (err) {
1219 dev_err(adev->dev,
1220 "gfx8: Failed to load firmware \"%s\"\n",
1221 fw_name);
1222 release_firmware(adev->gfx.pfp_fw);
1223 adev->gfx.pfp_fw = NULL;
1224 release_firmware(adev->gfx.me_fw);
1225 adev->gfx.me_fw = NULL;
1226 release_firmware(adev->gfx.ce_fw);
1227 adev->gfx.ce_fw = NULL;
1228 release_firmware(adev->gfx.rlc_fw);
1229 adev->gfx.rlc_fw = NULL;
1230 release_firmware(adev->gfx.mec_fw);
1231 adev->gfx.mec_fw = NULL;
1232 release_firmware(adev->gfx.mec2_fw);
1233 adev->gfx.mec2_fw = NULL;
1234 }
1235 return err;
1236}
1237
1238static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1239 volatile u32 *buffer)
1240{
1241 u32 count = 0, i;
1242 const struct cs_section_def *sect = NULL;
1243 const struct cs_extent_def *ext = NULL;
1244
1245 if (adev->gfx.rlc.cs_data == NULL)
1246 return;
1247 if (buffer == NULL)
1248 return;
1249
1250 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1251 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1252
1253 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1254 buffer[count++] = cpu_to_le32(0x80000000);
1255 buffer[count++] = cpu_to_le32(0x80000000);
1256
1257 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1258 for (ext = sect->section; ext->extent != NULL; ++ext) {
1259 if (sect->id == SECT_CONTEXT) {
1260 buffer[count++] =
1261 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1262 buffer[count++] = cpu_to_le32(ext->reg_index -
1263 PACKET3_SET_CONTEXT_REG_START);
1264 for (i = 0; i < ext->reg_count; i++)
1265 buffer[count++] = cpu_to_le32(ext->extent[i]);
1266 } else {
1267 return;
1268 }
1269 }
1270 }
1271
1272 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1273 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1274 PACKET3_SET_CONTEXT_REG_START);
1275 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1276 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
1277
1278 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1279 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1280
1281 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1282 buffer[count++] = cpu_to_le32(0);
1283}
1284
1285static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)
1286{
1287 if (adev->asic_type == CHIP_CARRIZO)
1288 return 5;
1289 else
1290 return 4;
1291}
1292
1293static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1294{
1295 const struct cs_section_def *cs_data;
1296 int r;
1297
1298 adev->gfx.rlc.cs_data = vi_cs_data;
1299
1300 cs_data = adev->gfx.rlc.cs_data;
1301
1302 if (cs_data) {
1303 /* init clear state block */
1304 r = amdgpu_gfx_rlc_init_csb(adev);
1305 if (r)
1306 return r;
1307 }
1308
1309 if ((adev->asic_type == CHIP_CARRIZO) ||
1310 (adev->asic_type == CHIP_STONEY)) {
1311 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1312 r = amdgpu_gfx_rlc_init_cpt(adev);
1313 if (r)
1314 return r;
1315 }
1316
1317 /* init spm vmid with 0xf */
1318 if (adev->gfx.rlc.funcs->update_spm_vmid)
1319 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1320
1321 return 0;
1322}
1323
1324static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1325{
1326 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1327}
1328
1329static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1330{
1331 int r;
1332 u32 *hpd;
1333 size_t mec_hpd_size;
1334
1335 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1336
1337 /* take ownership of the relevant compute queues */
1338 amdgpu_gfx_compute_queue_acquire(adev);
1339
1340 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1341 if (mec_hpd_size) {
1342 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1343 AMDGPU_GEM_DOMAIN_VRAM,
1344 &adev->gfx.mec.hpd_eop_obj,
1345 &adev->gfx.mec.hpd_eop_gpu_addr,
1346 (void **)&hpd);
1347 if (r) {
1348 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1349 return r;
1350 }
1351
1352 memset(hpd, 0, mec_hpd_size);
1353
1354 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1355 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1356 }
1357
1358 return 0;
1359}
1360
1361static const u32 vgpr_init_compute_shader[] =
1362{
1363 0x7e000209, 0x7e020208,
1364 0x7e040207, 0x7e060206,
1365 0x7e080205, 0x7e0a0204,
1366 0x7e0c0203, 0x7e0e0202,
1367 0x7e100201, 0x7e120200,
1368 0x7e140209, 0x7e160208,
1369 0x7e180207, 0x7e1a0206,
1370 0x7e1c0205, 0x7e1e0204,
1371 0x7e200203, 0x7e220202,
1372 0x7e240201, 0x7e260200,
1373 0x7e280209, 0x7e2a0208,
1374 0x7e2c0207, 0x7e2e0206,
1375 0x7e300205, 0x7e320204,
1376 0x7e340203, 0x7e360202,
1377 0x7e380201, 0x7e3a0200,
1378 0x7e3c0209, 0x7e3e0208,
1379 0x7e400207, 0x7e420206,
1380 0x7e440205, 0x7e460204,
1381 0x7e480203, 0x7e4a0202,
1382 0x7e4c0201, 0x7e4e0200,
1383 0x7e500209, 0x7e520208,
1384 0x7e540207, 0x7e560206,
1385 0x7e580205, 0x7e5a0204,
1386 0x7e5c0203, 0x7e5e0202,
1387 0x7e600201, 0x7e620200,
1388 0x7e640209, 0x7e660208,
1389 0x7e680207, 0x7e6a0206,
1390 0x7e6c0205, 0x7e6e0204,
1391 0x7e700203, 0x7e720202,
1392 0x7e740201, 0x7e760200,
1393 0x7e780209, 0x7e7a0208,
1394 0x7e7c0207, 0x7e7e0206,
1395 0xbf8a0000, 0xbf810000,
1396};
1397
1398static const u32 sgpr_init_compute_shader[] =
1399{
1400 0xbe8a0100, 0xbe8c0102,
1401 0xbe8e0104, 0xbe900106,
1402 0xbe920108, 0xbe940100,
1403 0xbe960102, 0xbe980104,
1404 0xbe9a0106, 0xbe9c0108,
1405 0xbe9e0100, 0xbea00102,
1406 0xbea20104, 0xbea40106,
1407 0xbea60108, 0xbea80100,
1408 0xbeaa0102, 0xbeac0104,
1409 0xbeae0106, 0xbeb00108,
1410 0xbeb20100, 0xbeb40102,
1411 0xbeb60104, 0xbeb80106,
1412 0xbeba0108, 0xbebc0100,
1413 0xbebe0102, 0xbec00104,
1414 0xbec20106, 0xbec40108,
1415 0xbec60100, 0xbec80102,
1416 0xbee60004, 0xbee70005,
1417 0xbeea0006, 0xbeeb0007,
1418 0xbee80008, 0xbee90009,
1419 0xbefc0000, 0xbf8a0000,
1420 0xbf810000, 0x00000000,
1421};
1422
1423static const u32 vgpr_init_regs[] =
1424{
1425 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1426 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1427 mmCOMPUTE_NUM_THREAD_X, 256*4,
1428 mmCOMPUTE_NUM_THREAD_Y, 1,
1429 mmCOMPUTE_NUM_THREAD_Z, 1,
1430 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1431 mmCOMPUTE_PGM_RSRC2, 20,
1432 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1433 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1434 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1435 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1436 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1437 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1438 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1439 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1440 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1441 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1442};
1443
1444static const u32 sgpr1_init_regs[] =
1445{
1446 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1447 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1448 mmCOMPUTE_NUM_THREAD_X, 256*5,
1449 mmCOMPUTE_NUM_THREAD_Y, 1,
1450 mmCOMPUTE_NUM_THREAD_Z, 1,
1451 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1452 mmCOMPUTE_PGM_RSRC2, 20,
1453 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1454 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1455 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1456 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1457 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1458 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1459 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1460 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1461 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1462 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1463};
1464
1465static const u32 sgpr2_init_regs[] =
1466{
1467 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1468 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1469 mmCOMPUTE_NUM_THREAD_X, 256*5,
1470 mmCOMPUTE_NUM_THREAD_Y, 1,
1471 mmCOMPUTE_NUM_THREAD_Z, 1,
1472 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1473 mmCOMPUTE_PGM_RSRC2, 20,
1474 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1475 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1476 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1477 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1478 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1479 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1480 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1481 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1482 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1483 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1484};
1485
1486static const u32 sec_ded_counter_registers[] =
1487{
1488 mmCPC_EDC_ATC_CNT,
1489 mmCPC_EDC_SCRATCH_CNT,
1490 mmCPC_EDC_UCODE_CNT,
1491 mmCPF_EDC_ATC_CNT,
1492 mmCPF_EDC_ROQ_CNT,
1493 mmCPF_EDC_TAG_CNT,
1494 mmCPG_EDC_ATC_CNT,
1495 mmCPG_EDC_DMA_CNT,
1496 mmCPG_EDC_TAG_CNT,
1497 mmDC_EDC_CSINVOC_CNT,
1498 mmDC_EDC_RESTORE_CNT,
1499 mmDC_EDC_STATE_CNT,
1500 mmGDS_EDC_CNT,
1501 mmGDS_EDC_GRBM_CNT,
1502 mmGDS_EDC_OA_DED,
1503 mmSPI_EDC_CNT,
1504 mmSQC_ATC_EDC_GATCL1_CNT,
1505 mmSQC_EDC_CNT,
1506 mmSQ_EDC_DED_CNT,
1507 mmSQ_EDC_INFO,
1508 mmSQ_EDC_SEC_CNT,
1509 mmTCC_EDC_CNT,
1510 mmTCP_ATC_EDC_GATCL1_CNT,
1511 mmTCP_EDC_CNT,
1512 mmTD_EDC_CNT
1513};
1514
1515static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1516{
1517 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1518 struct amdgpu_ib ib;
1519 struct dma_fence *f = NULL;
1520 int r, i;
1521 u32 tmp;
1522 unsigned total_size, vgpr_offset, sgpr_offset;
1523 u64 gpu_addr;
1524
1525 /* only supported on CZ */
1526 if (adev->asic_type != CHIP_CARRIZO)
1527 return 0;
1528
1529 /* bail if the compute ring is not ready */
1530 if (!ring->sched.ready)
1531 return 0;
1532
1533 tmp = RREG32(mmGB_EDC_MODE);
1534 WREG32(mmGB_EDC_MODE, 0);
1535
1536 total_size =
1537 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1538 total_size +=
1539 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1540 total_size +=
1541 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1542 total_size = ALIGN(total_size, 256);
1543 vgpr_offset = total_size;
1544 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1545 sgpr_offset = total_size;
1546 total_size += sizeof(sgpr_init_compute_shader);
1547
1548 /* allocate an indirect buffer to put the commands in */
1549 memset(&ib, 0, sizeof(ib));
1550 r = amdgpu_ib_get(adev, NULL, total_size,
1551 AMDGPU_IB_POOL_DIRECT, &ib);
1552 if (r) {
1553 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1554 return r;
1555 }
1556
1557 /* load the compute shaders */
1558 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1559 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1560
1561 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1562 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1563
1564 /* init the ib length to 0 */
1565 ib.length_dw = 0;
1566
1567 /* VGPR */
1568 /* write the register state for the compute dispatch */
1569 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1570 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1571 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1572 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1573 }
1574 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1575 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1576 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1577 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1578 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1579 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1580
1581 /* write dispatch packet */
1582 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1583 ib.ptr[ib.length_dw++] = 8; /* x */
1584 ib.ptr[ib.length_dw++] = 1; /* y */
1585 ib.ptr[ib.length_dw++] = 1; /* z */
1586 ib.ptr[ib.length_dw++] =
1587 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1588
1589 /* write CS partial flush packet */
1590 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1591 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1592
1593 /* SGPR1 */
1594 /* write the register state for the compute dispatch */
1595 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1596 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1597 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1598 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1599 }
1600 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1601 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1602 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1603 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1604 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1605 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1606
1607 /* write dispatch packet */
1608 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1609 ib.ptr[ib.length_dw++] = 8; /* x */
1610 ib.ptr[ib.length_dw++] = 1; /* y */
1611 ib.ptr[ib.length_dw++] = 1; /* z */
1612 ib.ptr[ib.length_dw++] =
1613 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1614
1615 /* write CS partial flush packet */
1616 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1617 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1618
1619 /* SGPR2 */
1620 /* write the register state for the compute dispatch */
1621 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1622 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1623 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1624 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1625 }
1626 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1627 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1628 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1629 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1630 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1631 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1632
1633 /* write dispatch packet */
1634 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1635 ib.ptr[ib.length_dw++] = 8; /* x */
1636 ib.ptr[ib.length_dw++] = 1; /* y */
1637 ib.ptr[ib.length_dw++] = 1; /* z */
1638 ib.ptr[ib.length_dw++] =
1639 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1640
1641 /* write CS partial flush packet */
1642 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1643 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1644
1645 /* shedule the ib on the ring */
1646 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1647 if (r) {
1648 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1649 goto fail;
1650 }
1651
1652 /* wait for the GPU to finish processing the IB */
1653 r = dma_fence_wait(f, false);
1654 if (r) {
1655 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1656 goto fail;
1657 }
1658
1659 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1660 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1661 WREG32(mmGB_EDC_MODE, tmp);
1662
1663 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1664 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1665 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1666
1667
1668 /* read back registers to clear the counters */
1669 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1670 RREG32(sec_ded_counter_registers[i]);
1671
1672fail:
1673 amdgpu_ib_free(adev, &ib, NULL);
1674 dma_fence_put(f);
1675
1676 return r;
1677}
1678
1679static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1680{
1681 u32 gb_addr_config;
1682 u32 mc_arb_ramcfg;
1683 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1684 u32 tmp;
1685 int ret;
1686
1687 switch (adev->asic_type) {
1688 case CHIP_TOPAZ:
1689 adev->gfx.config.max_shader_engines = 1;
1690 adev->gfx.config.max_tile_pipes = 2;
1691 adev->gfx.config.max_cu_per_sh = 6;
1692 adev->gfx.config.max_sh_per_se = 1;
1693 adev->gfx.config.max_backends_per_se = 2;
1694 adev->gfx.config.max_texture_channel_caches = 2;
1695 adev->gfx.config.max_gprs = 256;
1696 adev->gfx.config.max_gs_threads = 32;
1697 adev->gfx.config.max_hw_contexts = 8;
1698
1699 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1700 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1701 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1702 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1703 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1704 break;
1705 case CHIP_FIJI:
1706 adev->gfx.config.max_shader_engines = 4;
1707 adev->gfx.config.max_tile_pipes = 16;
1708 adev->gfx.config.max_cu_per_sh = 16;
1709 adev->gfx.config.max_sh_per_se = 1;
1710 adev->gfx.config.max_backends_per_se = 4;
1711 adev->gfx.config.max_texture_channel_caches = 16;
1712 adev->gfx.config.max_gprs = 256;
1713 adev->gfx.config.max_gs_threads = 32;
1714 adev->gfx.config.max_hw_contexts = 8;
1715
1716 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1717 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1718 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1719 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1720 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1721 break;
1722 case CHIP_POLARIS11:
1723 case CHIP_POLARIS12:
1724 ret = amdgpu_atombios_get_gfx_info(adev);
1725 if (ret)
1726 return ret;
1727 adev->gfx.config.max_gprs = 256;
1728 adev->gfx.config.max_gs_threads = 32;
1729 adev->gfx.config.max_hw_contexts = 8;
1730
1731 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1732 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1733 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1734 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1735 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
1736 break;
1737 case CHIP_POLARIS10:
1738 case CHIP_VEGAM:
1739 ret = amdgpu_atombios_get_gfx_info(adev);
1740 if (ret)
1741 return ret;
1742 adev->gfx.config.max_gprs = 256;
1743 adev->gfx.config.max_gs_threads = 32;
1744 adev->gfx.config.max_hw_contexts = 8;
1745
1746 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1747 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1748 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1749 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1750 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1751 break;
1752 case CHIP_TONGA:
1753 adev->gfx.config.max_shader_engines = 4;
1754 adev->gfx.config.max_tile_pipes = 8;
1755 adev->gfx.config.max_cu_per_sh = 8;
1756 adev->gfx.config.max_sh_per_se = 1;
1757 adev->gfx.config.max_backends_per_se = 2;
1758 adev->gfx.config.max_texture_channel_caches = 8;
1759 adev->gfx.config.max_gprs = 256;
1760 adev->gfx.config.max_gs_threads = 32;
1761 adev->gfx.config.max_hw_contexts = 8;
1762
1763 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1764 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1765 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1766 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1767 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1768 break;
1769 case CHIP_CARRIZO:
1770 adev->gfx.config.max_shader_engines = 1;
1771 adev->gfx.config.max_tile_pipes = 2;
1772 adev->gfx.config.max_sh_per_se = 1;
1773 adev->gfx.config.max_backends_per_se = 2;
1774 adev->gfx.config.max_cu_per_sh = 8;
1775 adev->gfx.config.max_texture_channel_caches = 2;
1776 adev->gfx.config.max_gprs = 256;
1777 adev->gfx.config.max_gs_threads = 32;
1778 adev->gfx.config.max_hw_contexts = 8;
1779
1780 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1781 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1782 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1783 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1784 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1785 break;
1786 case CHIP_STONEY:
1787 adev->gfx.config.max_shader_engines = 1;
1788 adev->gfx.config.max_tile_pipes = 2;
1789 adev->gfx.config.max_sh_per_se = 1;
1790 adev->gfx.config.max_backends_per_se = 1;
1791 adev->gfx.config.max_cu_per_sh = 3;
1792 adev->gfx.config.max_texture_channel_caches = 2;
1793 adev->gfx.config.max_gprs = 256;
1794 adev->gfx.config.max_gs_threads = 16;
1795 adev->gfx.config.max_hw_contexts = 8;
1796
1797 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1798 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1799 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1800 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1801 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1802 break;
1803 default:
1804 adev->gfx.config.max_shader_engines = 2;
1805 adev->gfx.config.max_tile_pipes = 4;
1806 adev->gfx.config.max_cu_per_sh = 2;
1807 adev->gfx.config.max_sh_per_se = 1;
1808 adev->gfx.config.max_backends_per_se = 2;
1809 adev->gfx.config.max_texture_channel_caches = 4;
1810 adev->gfx.config.max_gprs = 256;
1811 adev->gfx.config.max_gs_threads = 32;
1812 adev->gfx.config.max_hw_contexts = 8;
1813
1814 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1815 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1816 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1817 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1818 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1819 break;
1820 }
1821
1822 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1823 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1824
1825 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,
1826 MC_ARB_RAMCFG, NOOFBANK);
1827 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,
1828 MC_ARB_RAMCFG, NOOFRANKS);
1829
1830 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1831 adev->gfx.config.mem_max_burst_length_bytes = 256;
1832 if (adev->flags & AMD_IS_APU) {
1833 /* Get memory bank mapping mode. */
1834 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1835 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1836 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1837
1838 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1839 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1840 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1841
1842 /* Validate settings in case only one DIMM installed. */
1843 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1844 dimm00_addr_map = 0;
1845 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1846 dimm01_addr_map = 0;
1847 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1848 dimm10_addr_map = 0;
1849 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1850 dimm11_addr_map = 0;
1851
1852 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1853 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1854 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1855 adev->gfx.config.mem_row_size_in_kb = 2;
1856 else
1857 adev->gfx.config.mem_row_size_in_kb = 1;
1858 } else {
1859 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1860 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1861 if (adev->gfx.config.mem_row_size_in_kb > 4)
1862 adev->gfx.config.mem_row_size_in_kb = 4;
1863 }
1864
1865 adev->gfx.config.shader_engine_tile_size = 32;
1866 adev->gfx.config.num_gpus = 1;
1867 adev->gfx.config.multi_gpu_tile_size = 64;
1868
1869 /* fix up row size */
1870 switch (adev->gfx.config.mem_row_size_in_kb) {
1871 case 1:
1872 default:
1873 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1874 break;
1875 case 2:
1876 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1877 break;
1878 case 4:
1879 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1880 break;
1881 }
1882 adev->gfx.config.gb_addr_config = gb_addr_config;
1883
1884 return 0;
1885}
1886
1887static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1888 int mec, int pipe, int queue)
1889{
1890 int r;
1891 unsigned irq_type;
1892 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1893 unsigned int hw_prio;
1894
1895 ring = &adev->gfx.compute_ring[ring_id];
1896
1897 /* mec0 is me1 */
1898 ring->me = mec + 1;
1899 ring->pipe = pipe;
1900 ring->queue = queue;
1901
1902 ring->ring_obj = NULL;
1903 ring->use_doorbell = true;
1904 ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
1905 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1906 + (ring_id * GFX8_MEC_HPD_SIZE);
1907 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1908
1909 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1910 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1911 + ring->pipe;
1912
1913 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
1914 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
1915 /* type-2 packets are deprecated on MEC, use type-3 instead */
1916 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1917 hw_prio, NULL);
1918 if (r)
1919 return r;
1920
1921
1922 return 0;
1923}
1924
1925static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
1926
1927static int gfx_v8_0_sw_init(void *handle)
1928{
1929 int i, j, k, r, ring_id;
1930 struct amdgpu_ring *ring;
1931 struct amdgpu_kiq *kiq;
1932 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1933
1934 switch (adev->asic_type) {
1935 case CHIP_TONGA:
1936 case CHIP_CARRIZO:
1937 case CHIP_FIJI:
1938 case CHIP_POLARIS10:
1939 case CHIP_POLARIS11:
1940 case CHIP_POLARIS12:
1941 case CHIP_VEGAM:
1942 adev->gfx.mec.num_mec = 2;
1943 break;
1944 case CHIP_TOPAZ:
1945 case CHIP_STONEY:
1946 default:
1947 adev->gfx.mec.num_mec = 1;
1948 break;
1949 }
1950
1951 adev->gfx.mec.num_pipe_per_mec = 4;
1952 adev->gfx.mec.num_queue_per_pipe = 8;
1953
1954 /* EOP Event */
1955 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
1956 if (r)
1957 return r;
1958
1959 /* Privileged reg */
1960 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
1961 &adev->gfx.priv_reg_irq);
1962 if (r)
1963 return r;
1964
1965 /* Privileged inst */
1966 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
1967 &adev->gfx.priv_inst_irq);
1968 if (r)
1969 return r;
1970
1971 /* Add CP EDC/ECC irq */
1972 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
1973 &adev->gfx.cp_ecc_error_irq);
1974 if (r)
1975 return r;
1976
1977 /* SQ interrupts. */
1978 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
1979 &adev->gfx.sq_irq);
1980 if (r) {
1981 DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
1982 return r;
1983 }
1984
1985 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
1986
1987 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1988
1989 r = gfx_v8_0_init_microcode(adev);
1990 if (r) {
1991 DRM_ERROR("Failed to load gfx firmware!\n");
1992 return r;
1993 }
1994
1995 r = adev->gfx.rlc.funcs->init(adev);
1996 if (r) {
1997 DRM_ERROR("Failed to init rlc BOs!\n");
1998 return r;
1999 }
2000
2001 r = gfx_v8_0_mec_init(adev);
2002 if (r) {
2003 DRM_ERROR("Failed to init MEC BOs!\n");
2004 return r;
2005 }
2006
2007 /* set up the gfx ring */
2008 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2009 ring = &adev->gfx.gfx_ring[i];
2010 ring->ring_obj = NULL;
2011 sprintf(ring->name, "gfx");
2012 /* no gfx doorbells on iceland */
2013 if (adev->asic_type != CHIP_TOPAZ) {
2014 ring->use_doorbell = true;
2015 ring->doorbell_index = adev->doorbell_index.gfx_ring0;
2016 }
2017
2018 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2019 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
2020 AMDGPU_RING_PRIO_DEFAULT, NULL);
2021 if (r)
2022 return r;
2023 }
2024
2025
2026 /* set up the compute queues - allocate horizontally across pipes */
2027 ring_id = 0;
2028 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2029 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2030 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2031 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2032 continue;
2033
2034 r = gfx_v8_0_compute_ring_init(adev,
2035 ring_id,
2036 i, k, j);
2037 if (r)
2038 return r;
2039
2040 ring_id++;
2041 }
2042 }
2043 }
2044
2045 r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE);
2046 if (r) {
2047 DRM_ERROR("Failed to init KIQ BOs!\n");
2048 return r;
2049 }
2050
2051 kiq = &adev->gfx.kiq;
2052 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2053 if (r)
2054 return r;
2055
2056 /* create MQD for all compute queues as well as KIQ for SRIOV case */
2057 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation));
2058 if (r)
2059 return r;
2060
2061 adev->gfx.ce_ram_size = 0x8000;
2062
2063 r = gfx_v8_0_gpu_early_init(adev);
2064 if (r)
2065 return r;
2066
2067 return 0;
2068}
2069
2070static int gfx_v8_0_sw_fini(void *handle)
2071{
2072 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2073 int i;
2074
2075 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2076 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2077 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2078 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2079
2080 amdgpu_gfx_mqd_sw_fini(adev);
2081 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
2082 amdgpu_gfx_kiq_fini(adev);
2083
2084 gfx_v8_0_mec_fini(adev);
2085 amdgpu_gfx_rlc_fini(adev);
2086 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2087 &adev->gfx.rlc.clear_state_gpu_addr,
2088 (void **)&adev->gfx.rlc.cs_ptr);
2089 if ((adev->asic_type == CHIP_CARRIZO) ||
2090 (adev->asic_type == CHIP_STONEY)) {
2091 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2092 &adev->gfx.rlc.cp_table_gpu_addr,
2093 (void **)&adev->gfx.rlc.cp_table_ptr);
2094 }
2095 gfx_v8_0_free_microcode(adev);
2096
2097 return 0;
2098}
2099
2100static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2101{
2102 uint32_t *modearray, *mod2array;
2103 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2104 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2105 u32 reg_offset;
2106
2107 modearray = adev->gfx.config.tile_mode_array;
2108 mod2array = adev->gfx.config.macrotile_mode_array;
2109
2110 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2111 modearray[reg_offset] = 0;
2112
2113 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2114 mod2array[reg_offset] = 0;
2115
2116 switch (adev->asic_type) {
2117 case CHIP_TOPAZ:
2118 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2119 PIPE_CONFIG(ADDR_SURF_P2) |
2120 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2121 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2122 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2123 PIPE_CONFIG(ADDR_SURF_P2) |
2124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2125 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2126 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2127 PIPE_CONFIG(ADDR_SURF_P2) |
2128 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2129 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2130 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2131 PIPE_CONFIG(ADDR_SURF_P2) |
2132 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2133 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2134 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2135 PIPE_CONFIG(ADDR_SURF_P2) |
2136 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2137 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2138 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2139 PIPE_CONFIG(ADDR_SURF_P2) |
2140 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2141 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2142 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2143 PIPE_CONFIG(ADDR_SURF_P2) |
2144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2145 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2146 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2147 PIPE_CONFIG(ADDR_SURF_P2));
2148 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2149 PIPE_CONFIG(ADDR_SURF_P2) |
2150 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2151 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2152 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2153 PIPE_CONFIG(ADDR_SURF_P2) |
2154 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2155 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2156 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2157 PIPE_CONFIG(ADDR_SURF_P2) |
2158 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2159 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2160 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2161 PIPE_CONFIG(ADDR_SURF_P2) |
2162 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2163 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2164 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2165 PIPE_CONFIG(ADDR_SURF_P2) |
2166 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2167 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2168 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2169 PIPE_CONFIG(ADDR_SURF_P2) |
2170 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2171 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2172 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2173 PIPE_CONFIG(ADDR_SURF_P2) |
2174 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2175 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2176 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2177 PIPE_CONFIG(ADDR_SURF_P2) |
2178 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2179 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2180 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2181 PIPE_CONFIG(ADDR_SURF_P2) |
2182 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2183 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2184 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2185 PIPE_CONFIG(ADDR_SURF_P2) |
2186 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2187 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2188 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2189 PIPE_CONFIG(ADDR_SURF_P2) |
2190 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2191 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2192 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2193 PIPE_CONFIG(ADDR_SURF_P2) |
2194 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2195 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2196 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2197 PIPE_CONFIG(ADDR_SURF_P2) |
2198 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2199 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2200 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2201 PIPE_CONFIG(ADDR_SURF_P2) |
2202 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2203 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2204 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2205 PIPE_CONFIG(ADDR_SURF_P2) |
2206 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2207 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2208 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2209 PIPE_CONFIG(ADDR_SURF_P2) |
2210 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2211 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2212 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2213 PIPE_CONFIG(ADDR_SURF_P2) |
2214 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2215 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2216 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2217 PIPE_CONFIG(ADDR_SURF_P2) |
2218 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2219 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2220
2221 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2222 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2223 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2224 NUM_BANKS(ADDR_SURF_8_BANK));
2225 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2226 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2227 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2228 NUM_BANKS(ADDR_SURF_8_BANK));
2229 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2232 NUM_BANKS(ADDR_SURF_8_BANK));
2233 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2234 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2235 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2236 NUM_BANKS(ADDR_SURF_8_BANK));
2237 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2240 NUM_BANKS(ADDR_SURF_8_BANK));
2241 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2242 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2243 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2244 NUM_BANKS(ADDR_SURF_8_BANK));
2245 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2246 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2247 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2248 NUM_BANKS(ADDR_SURF_8_BANK));
2249 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2250 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2251 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2252 NUM_BANKS(ADDR_SURF_16_BANK));
2253 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2256 NUM_BANKS(ADDR_SURF_16_BANK));
2257 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2258 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2259 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2260 NUM_BANKS(ADDR_SURF_16_BANK));
2261 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2262 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2263 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2264 NUM_BANKS(ADDR_SURF_16_BANK));
2265 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2266 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2267 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2268 NUM_BANKS(ADDR_SURF_16_BANK));
2269 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2272 NUM_BANKS(ADDR_SURF_16_BANK));
2273 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2274 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2275 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2276 NUM_BANKS(ADDR_SURF_8_BANK));
2277
2278 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2279 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2280 reg_offset != 23)
2281 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2282
2283 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2284 if (reg_offset != 7)
2285 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2286
2287 break;
2288 case CHIP_FIJI:
2289 case CHIP_VEGAM:
2290 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2291 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2292 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2293 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2294 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2295 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2296 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2297 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2298 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2299 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2300 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2301 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2302 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2303 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2304 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2305 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2306 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2307 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2308 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2309 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2310 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2312 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2313 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2314 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2316 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2317 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2318 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2319 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2320 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2321 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2322 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2323 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2324 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2325 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2326 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2327 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2328 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2329 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2330 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2331 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2332 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2333 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2334 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2335 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2336 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2337 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2338 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2339 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2340 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2341 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2342 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2343 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2344 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2345 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2346 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2347 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2348 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2349 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2350 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2351 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2352 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2353 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2354 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2355 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2356 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2357 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2358 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2359 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2360 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2361 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2362 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2363 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2364 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2365 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2366 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2367 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2368 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2369 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2370 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2371 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2372 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2373 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2374 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2375 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2376 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2377 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2378 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2379 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2380 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2381 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2382 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2383 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2384 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2385 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2386 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2387 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2388 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2389 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2390 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2391 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2392 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2393 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2394 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2395 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2396 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2397 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2398 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2399 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2400 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2401 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2402 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2403 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2404 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2405 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2406 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2407 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2408 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2409 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2410 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2411 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2412
2413 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2414 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2415 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2416 NUM_BANKS(ADDR_SURF_8_BANK));
2417 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2418 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2419 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2420 NUM_BANKS(ADDR_SURF_8_BANK));
2421 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2424 NUM_BANKS(ADDR_SURF_8_BANK));
2425 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2426 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2427 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2428 NUM_BANKS(ADDR_SURF_8_BANK));
2429 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2430 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2431 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2432 NUM_BANKS(ADDR_SURF_8_BANK));
2433 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2434 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2435 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2436 NUM_BANKS(ADDR_SURF_8_BANK));
2437 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2440 NUM_BANKS(ADDR_SURF_8_BANK));
2441 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2442 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2443 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2444 NUM_BANKS(ADDR_SURF_8_BANK));
2445 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2446 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2447 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2448 NUM_BANKS(ADDR_SURF_8_BANK));
2449 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2451 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2452 NUM_BANKS(ADDR_SURF_8_BANK));
2453 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2456 NUM_BANKS(ADDR_SURF_8_BANK));
2457 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2458 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2459 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2460 NUM_BANKS(ADDR_SURF_8_BANK));
2461 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2463 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2464 NUM_BANKS(ADDR_SURF_8_BANK));
2465 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2468 NUM_BANKS(ADDR_SURF_4_BANK));
2469
2470 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2471 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2472
2473 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2474 if (reg_offset != 7)
2475 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2476
2477 break;
2478 case CHIP_TONGA:
2479 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2480 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2481 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2482 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2483 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2484 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2485 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2486 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2487 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2488 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2489 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2490 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2491 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2492 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2493 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2494 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2495 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2496 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2497 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2498 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2499 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2500 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2501 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2502 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2503 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2504 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2505 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2506 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2507 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2508 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2510 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2511 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2512 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2513 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2514 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2515 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2516 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2517 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2518 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2519 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2520 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2521 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2522 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2523 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2524 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2525 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2526 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2527 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2528 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2529 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2530 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2531 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2532 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2533 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2534 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2535 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2536 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2537 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2538 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2539 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2540 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2541 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2542 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2543 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2544 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2545 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2546 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2547 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2548 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2549 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2550 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2551 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2552 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2553 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2554 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2555 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2556 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2557 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2558 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2559 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2560 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2561 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2562 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2563 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2564 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2565 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2566 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2567 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2568 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2569 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2570 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2571 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2572 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2573 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2574 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2575 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2576 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2577 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2578 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2579 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2580 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2581 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2582 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2583 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2584 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2585 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2586 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2587 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2588 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2589 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2590 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2591 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2592 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2593 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2594 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2595 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2596 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2597 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2598 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2599 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2600 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2601
2602 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2603 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2604 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2605 NUM_BANKS(ADDR_SURF_16_BANK));
2606 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2607 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2608 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2609 NUM_BANKS(ADDR_SURF_16_BANK));
2610 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2611 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2612 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2613 NUM_BANKS(ADDR_SURF_16_BANK));
2614 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2615 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2616 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2617 NUM_BANKS(ADDR_SURF_16_BANK));
2618 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2621 NUM_BANKS(ADDR_SURF_16_BANK));
2622 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2623 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2624 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2625 NUM_BANKS(ADDR_SURF_16_BANK));
2626 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2629 NUM_BANKS(ADDR_SURF_16_BANK));
2630 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2631 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2632 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2633 NUM_BANKS(ADDR_SURF_16_BANK));
2634 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2637 NUM_BANKS(ADDR_SURF_16_BANK));
2638 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2640 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2641 NUM_BANKS(ADDR_SURF_16_BANK));
2642 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2643 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2644 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2645 NUM_BANKS(ADDR_SURF_16_BANK));
2646 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2649 NUM_BANKS(ADDR_SURF_8_BANK));
2650 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2653 NUM_BANKS(ADDR_SURF_4_BANK));
2654 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2657 NUM_BANKS(ADDR_SURF_4_BANK));
2658
2659 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2660 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2661
2662 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2663 if (reg_offset != 7)
2664 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2665
2666 break;
2667 case CHIP_POLARIS11:
2668 case CHIP_POLARIS12:
2669 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2670 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2671 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2672 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2673 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2674 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2675 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2676 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2677 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2678 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2679 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2680 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2681 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2682 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2683 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2684 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2685 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2686 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2687 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2688 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2689 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2690 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2691 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2692 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2693 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2694 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2695 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2696 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2697 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2698 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2699 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2700 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2701 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2702 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2703 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2704 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2705 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2706 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2707 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2708 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2709 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2710 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2711 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2712 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2713 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2714 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2715 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2716 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2717 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2718 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2719 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2720 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2721 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2722 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2723 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2724 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2725 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2726 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2727 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2728 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2729 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2730 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2731 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2732 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2733 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2734 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2735 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2736 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2737 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2738 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2739 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2740 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2741 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2742 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2743 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2744 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2745 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2746 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2747 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2748 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2749 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2750 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2751 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2752 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2753 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2754 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2755 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2756 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2757 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2758 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2759 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2760 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2761 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2762 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2763 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2764 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2765 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2766 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2767 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2768 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2769 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2770 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2771 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2772 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2773 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2774 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2775 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2776 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2777 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2778 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2779 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2780 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2781 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2782 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2783 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2784 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2785 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2786 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2787 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2788 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2789 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2790 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2791
2792 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2793 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2794 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2795 NUM_BANKS(ADDR_SURF_16_BANK));
2796
2797 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2800 NUM_BANKS(ADDR_SURF_16_BANK));
2801
2802 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2803 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2804 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2805 NUM_BANKS(ADDR_SURF_16_BANK));
2806
2807 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2808 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2809 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2810 NUM_BANKS(ADDR_SURF_16_BANK));
2811
2812 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2813 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2814 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2815 NUM_BANKS(ADDR_SURF_16_BANK));
2816
2817 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2820 NUM_BANKS(ADDR_SURF_16_BANK));
2821
2822 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2823 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2824 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2825 NUM_BANKS(ADDR_SURF_16_BANK));
2826
2827 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2828 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2829 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2830 NUM_BANKS(ADDR_SURF_16_BANK));
2831
2832 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2835 NUM_BANKS(ADDR_SURF_16_BANK));
2836
2837 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2838 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2839 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2840 NUM_BANKS(ADDR_SURF_16_BANK));
2841
2842 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2843 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2844 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2845 NUM_BANKS(ADDR_SURF_16_BANK));
2846
2847 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2848 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2849 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2850 NUM_BANKS(ADDR_SURF_16_BANK));
2851
2852 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2853 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2854 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2855 NUM_BANKS(ADDR_SURF_8_BANK));
2856
2857 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2858 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2859 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2860 NUM_BANKS(ADDR_SURF_4_BANK));
2861
2862 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2863 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2864
2865 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2866 if (reg_offset != 7)
2867 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2868
2869 break;
2870 case CHIP_POLARIS10:
2871 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2872 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2873 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2874 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2875 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2876 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2877 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2878 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2879 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2880 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2881 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2882 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2883 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2884 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2885 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2886 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2887 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2888 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2889 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2890 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2891 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2892 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2893 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2894 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2895 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2896 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2897 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2898 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2899 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2900 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2901 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2902 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2903 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2904 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2905 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2906 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2907 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2908 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2909 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2910 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2911 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2912 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2913 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2914 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2915 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2916 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2917 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2918 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2919 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2920 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2921 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2922 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2923 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2924 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2925 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2926 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2927 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2928 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2929 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2930 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2931 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2932 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2933 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2934 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2935 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2936 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2937 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2938 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2939 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2940 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2941 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2942 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2943 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2944 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2945 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2946 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2947 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2948 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2949 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2950 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2951 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2952 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2953 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2954 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2955 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2956 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2957 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2958 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2959 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2960 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2961 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2962 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2963 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2964 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2965 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2966 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2967 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2968 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2969 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2970 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2971 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2972 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2973 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2974 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2975 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2976 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2977 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2978 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2979 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2980 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2981 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2982 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2983 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2984 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2985 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2986 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2987 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2988 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2989 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2990 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2991 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2992 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2993
2994 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2995 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2996 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2997 NUM_BANKS(ADDR_SURF_16_BANK));
2998
2999 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3000 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3001 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3002 NUM_BANKS(ADDR_SURF_16_BANK));
3003
3004 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3005 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3006 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3007 NUM_BANKS(ADDR_SURF_16_BANK));
3008
3009 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3010 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3011 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3012 NUM_BANKS(ADDR_SURF_16_BANK));
3013
3014 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3015 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3016 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3017 NUM_BANKS(ADDR_SURF_16_BANK));
3018
3019 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3020 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3021 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3022 NUM_BANKS(ADDR_SURF_16_BANK));
3023
3024 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3025 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3026 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3027 NUM_BANKS(ADDR_SURF_16_BANK));
3028
3029 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3030 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3031 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3032 NUM_BANKS(ADDR_SURF_16_BANK));
3033
3034 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3035 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3036 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3037 NUM_BANKS(ADDR_SURF_16_BANK));
3038
3039 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3040 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3041 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3042 NUM_BANKS(ADDR_SURF_16_BANK));
3043
3044 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3045 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3046 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3047 NUM_BANKS(ADDR_SURF_16_BANK));
3048
3049 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3050 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3051 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3052 NUM_BANKS(ADDR_SURF_8_BANK));
3053
3054 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3055 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3056 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3057 NUM_BANKS(ADDR_SURF_4_BANK));
3058
3059 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3060 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3061 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3062 NUM_BANKS(ADDR_SURF_4_BANK));
3063
3064 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3065 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3066
3067 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3068 if (reg_offset != 7)
3069 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3070
3071 break;
3072 case CHIP_STONEY:
3073 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3074 PIPE_CONFIG(ADDR_SURF_P2) |
3075 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3076 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3077 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3078 PIPE_CONFIG(ADDR_SURF_P2) |
3079 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3080 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3081 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3082 PIPE_CONFIG(ADDR_SURF_P2) |
3083 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3084 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3085 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3086 PIPE_CONFIG(ADDR_SURF_P2) |
3087 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3088 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3089 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3090 PIPE_CONFIG(ADDR_SURF_P2) |
3091 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3092 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3093 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3094 PIPE_CONFIG(ADDR_SURF_P2) |
3095 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3096 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3097 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3098 PIPE_CONFIG(ADDR_SURF_P2) |
3099 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3100 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3101 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3102 PIPE_CONFIG(ADDR_SURF_P2));
3103 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3104 PIPE_CONFIG(ADDR_SURF_P2) |
3105 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3106 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3107 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3108 PIPE_CONFIG(ADDR_SURF_P2) |
3109 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3110 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3111 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3112 PIPE_CONFIG(ADDR_SURF_P2) |
3113 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3114 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3115 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3116 PIPE_CONFIG(ADDR_SURF_P2) |
3117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3118 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3119 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3120 PIPE_CONFIG(ADDR_SURF_P2) |
3121 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3122 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3123 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3124 PIPE_CONFIG(ADDR_SURF_P2) |
3125 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3126 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3127 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3128 PIPE_CONFIG(ADDR_SURF_P2) |
3129 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3130 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3131 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3132 PIPE_CONFIG(ADDR_SURF_P2) |
3133 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3135 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3136 PIPE_CONFIG(ADDR_SURF_P2) |
3137 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3139 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3140 PIPE_CONFIG(ADDR_SURF_P2) |
3141 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3143 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3144 PIPE_CONFIG(ADDR_SURF_P2) |
3145 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3146 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3147 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3148 PIPE_CONFIG(ADDR_SURF_P2) |
3149 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3150 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3151 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3152 PIPE_CONFIG(ADDR_SURF_P2) |
3153 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3154 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3155 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3156 PIPE_CONFIG(ADDR_SURF_P2) |
3157 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3158 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3159 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3160 PIPE_CONFIG(ADDR_SURF_P2) |
3161 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3162 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3163 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3164 PIPE_CONFIG(ADDR_SURF_P2) |
3165 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3166 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3167 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3168 PIPE_CONFIG(ADDR_SURF_P2) |
3169 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3170 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3171 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3172 PIPE_CONFIG(ADDR_SURF_P2) |
3173 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3174 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3175
3176 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3179 NUM_BANKS(ADDR_SURF_8_BANK));
3180 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3183 NUM_BANKS(ADDR_SURF_8_BANK));
3184 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3187 NUM_BANKS(ADDR_SURF_8_BANK));
3188 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3191 NUM_BANKS(ADDR_SURF_8_BANK));
3192 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3195 NUM_BANKS(ADDR_SURF_8_BANK));
3196 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3199 NUM_BANKS(ADDR_SURF_8_BANK));
3200 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3203 NUM_BANKS(ADDR_SURF_8_BANK));
3204 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3207 NUM_BANKS(ADDR_SURF_16_BANK));
3208 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3211 NUM_BANKS(ADDR_SURF_16_BANK));
3212 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3213 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3214 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3215 NUM_BANKS(ADDR_SURF_16_BANK));
3216 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3217 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3218 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3219 NUM_BANKS(ADDR_SURF_16_BANK));
3220 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3223 NUM_BANKS(ADDR_SURF_16_BANK));
3224 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3225 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3226 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3227 NUM_BANKS(ADDR_SURF_16_BANK));
3228 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3229 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3231 NUM_BANKS(ADDR_SURF_8_BANK));
3232
3233 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3234 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3235 reg_offset != 23)
3236 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3237
3238 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3239 if (reg_offset != 7)
3240 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3241
3242 break;
3243 default:
3244 dev_warn(adev->dev,
3245 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3246 adev->asic_type);
3247 fallthrough;
3248
3249 case CHIP_CARRIZO:
3250 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3251 PIPE_CONFIG(ADDR_SURF_P2) |
3252 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3253 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3254 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3255 PIPE_CONFIG(ADDR_SURF_P2) |
3256 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3257 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3258 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3259 PIPE_CONFIG(ADDR_SURF_P2) |
3260 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3261 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3262 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3263 PIPE_CONFIG(ADDR_SURF_P2) |
3264 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3265 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3266 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3267 PIPE_CONFIG(ADDR_SURF_P2) |
3268 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3269 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3270 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3271 PIPE_CONFIG(ADDR_SURF_P2) |
3272 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3273 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3274 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3275 PIPE_CONFIG(ADDR_SURF_P2) |
3276 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3277 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3278 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3279 PIPE_CONFIG(ADDR_SURF_P2));
3280 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3281 PIPE_CONFIG(ADDR_SURF_P2) |
3282 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3284 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3285 PIPE_CONFIG(ADDR_SURF_P2) |
3286 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3288 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3289 PIPE_CONFIG(ADDR_SURF_P2) |
3290 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3291 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3292 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3293 PIPE_CONFIG(ADDR_SURF_P2) |
3294 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3295 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3296 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3297 PIPE_CONFIG(ADDR_SURF_P2) |
3298 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3299 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3300 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3301 PIPE_CONFIG(ADDR_SURF_P2) |
3302 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3303 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3304 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3305 PIPE_CONFIG(ADDR_SURF_P2) |
3306 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3307 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3308 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3309 PIPE_CONFIG(ADDR_SURF_P2) |
3310 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3311 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3312 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3313 PIPE_CONFIG(ADDR_SURF_P2) |
3314 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3315 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3316 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3317 PIPE_CONFIG(ADDR_SURF_P2) |
3318 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3319 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3320 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3321 PIPE_CONFIG(ADDR_SURF_P2) |
3322 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3323 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3324 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3325 PIPE_CONFIG(ADDR_SURF_P2) |
3326 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3327 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3328 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3329 PIPE_CONFIG(ADDR_SURF_P2) |
3330 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3331 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3332 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3333 PIPE_CONFIG(ADDR_SURF_P2) |
3334 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3335 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3336 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3337 PIPE_CONFIG(ADDR_SURF_P2) |
3338 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3339 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3340 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3341 PIPE_CONFIG(ADDR_SURF_P2) |
3342 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3343 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3344 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3345 PIPE_CONFIG(ADDR_SURF_P2) |
3346 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3347 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3348 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3349 PIPE_CONFIG(ADDR_SURF_P2) |
3350 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3351 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3352
3353 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3354 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3355 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3356 NUM_BANKS(ADDR_SURF_8_BANK));
3357 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3358 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3359 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3360 NUM_BANKS(ADDR_SURF_8_BANK));
3361 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3362 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3363 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3364 NUM_BANKS(ADDR_SURF_8_BANK));
3365 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3366 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3367 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3368 NUM_BANKS(ADDR_SURF_8_BANK));
3369 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3370 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3371 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3372 NUM_BANKS(ADDR_SURF_8_BANK));
3373 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3374 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3375 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3376 NUM_BANKS(ADDR_SURF_8_BANK));
3377 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3378 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3379 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3380 NUM_BANKS(ADDR_SURF_8_BANK));
3381 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3382 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3383 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3384 NUM_BANKS(ADDR_SURF_16_BANK));
3385 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3386 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3387 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3388 NUM_BANKS(ADDR_SURF_16_BANK));
3389 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3390 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3391 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3392 NUM_BANKS(ADDR_SURF_16_BANK));
3393 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3394 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3395 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3396 NUM_BANKS(ADDR_SURF_16_BANK));
3397 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3398 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3399 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3400 NUM_BANKS(ADDR_SURF_16_BANK));
3401 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3402 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3403 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3404 NUM_BANKS(ADDR_SURF_16_BANK));
3405 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3406 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3407 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3408 NUM_BANKS(ADDR_SURF_8_BANK));
3409
3410 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3411 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3412 reg_offset != 23)
3413 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3414
3415 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3416 if (reg_offset != 7)
3417 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3418
3419 break;
3420 }
3421}
3422
3423static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
3424 u32 se_num, u32 sh_num, u32 instance)
3425{
3426 u32 data;
3427
3428 if (instance == 0xffffffff)
3429 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3430 else
3431 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
3432
3433 if (se_num == 0xffffffff)
3434 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3435 else
3436 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3437
3438 if (sh_num == 0xffffffff)
3439 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3440 else
3441 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3442
3443 WREG32(mmGRBM_GFX_INDEX, data);
3444}
3445
3446static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
3447 u32 me, u32 pipe, u32 q, u32 vm)
3448{
3449 vi_srbm_select(adev, me, pipe, q, vm);
3450}
3451
3452static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
3453{
3454 u32 data, mask;
3455
3456 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
3457 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3458
3459 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
3460
3461 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
3462 adev->gfx.config.max_sh_per_se);
3463
3464 return (~data) & mask;
3465}
3466
3467static void
3468gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
3469{
3470 switch (adev->asic_type) {
3471 case CHIP_FIJI:
3472 case CHIP_VEGAM:
3473 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
3474 RB_XSEL2(1) | PKR_MAP(2) |
3475 PKR_XSEL(1) | PKR_YSEL(1) |
3476 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3);
3477 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
3478 SE_PAIR_YSEL(2);
3479 break;
3480 case CHIP_TONGA:
3481 case CHIP_POLARIS10:
3482 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3483 SE_XSEL(1) | SE_YSEL(1);
3484 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) |
3485 SE_PAIR_YSEL(2);
3486 break;
3487 case CHIP_TOPAZ:
3488 case CHIP_CARRIZO:
3489 *rconf |= RB_MAP_PKR0(2);
3490 *rconf1 |= 0x0;
3491 break;
3492 case CHIP_POLARIS11:
3493 case CHIP_POLARIS12:
3494 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3495 SE_XSEL(1) | SE_YSEL(1);
3496 *rconf1 |= 0x0;
3497 break;
3498 case CHIP_STONEY:
3499 *rconf |= 0x0;
3500 *rconf1 |= 0x0;
3501 break;
3502 default:
3503 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
3504 break;
3505 }
3506}
3507
3508static void
3509gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev,
3510 u32 raster_config, u32 raster_config_1,
3511 unsigned rb_mask, unsigned num_rb)
3512{
3513 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
3514 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
3515 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
3516 unsigned rb_per_se = num_rb / num_se;
3517 unsigned se_mask[4];
3518 unsigned se;
3519
3520 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3521 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3522 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3523 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3524
3525 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
3526 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
3527 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
3528
3529 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3530 (!se_mask[2] && !se_mask[3]))) {
3531 raster_config_1 &= ~SE_PAIR_MAP_MASK;
3532
3533 if (!se_mask[0] && !se_mask[1]) {
3534 raster_config_1 |=
3535 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
3536 } else {
3537 raster_config_1 |=
3538 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
3539 }
3540 }
3541
3542 for (se = 0; se < num_se; se++) {
3543 unsigned raster_config_se = raster_config;
3544 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3545 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3546 int idx = (se / 2) * 2;
3547
3548 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3549 raster_config_se &= ~SE_MAP_MASK;
3550
3551 if (!se_mask[idx]) {
3552 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
3553 } else {
3554 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
3555 }
3556 }
3557
3558 pkr0_mask &= rb_mask;
3559 pkr1_mask &= rb_mask;
3560 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3561 raster_config_se &= ~PKR_MAP_MASK;
3562
3563 if (!pkr0_mask) {
3564 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
3565 } else {
3566 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
3567 }
3568 }
3569
3570 if (rb_per_se >= 2) {
3571 unsigned rb0_mask = 1 << (se * rb_per_se);
3572 unsigned rb1_mask = rb0_mask << 1;
3573
3574 rb0_mask &= rb_mask;
3575 rb1_mask &= rb_mask;
3576 if (!rb0_mask || !rb1_mask) {
3577 raster_config_se &= ~RB_MAP_PKR0_MASK;
3578
3579 if (!rb0_mask) {
3580 raster_config_se |=
3581 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
3582 } else {
3583 raster_config_se |=
3584 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
3585 }
3586 }
3587
3588 if (rb_per_se > 2) {
3589 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3590 rb1_mask = rb0_mask << 1;
3591 rb0_mask &= rb_mask;
3592 rb1_mask &= rb_mask;
3593 if (!rb0_mask || !rb1_mask) {
3594 raster_config_se &= ~RB_MAP_PKR1_MASK;
3595
3596 if (!rb0_mask) {
3597 raster_config_se |=
3598 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
3599 } else {
3600 raster_config_se |=
3601 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
3602 }
3603 }
3604 }
3605 }
3606
3607 /* GRBM_GFX_INDEX has a different offset on VI */
3608 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
3609 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
3610 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3611 }
3612
3613 /* GRBM_GFX_INDEX has a different offset on VI */
3614 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3615}
3616
3617static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
3618{
3619 int i, j;
3620 u32 data;
3621 u32 raster_config = 0, raster_config_1 = 0;
3622 u32 active_rbs = 0;
3623 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3624 adev->gfx.config.max_sh_per_se;
3625 unsigned num_rb_pipes;
3626
3627 mutex_lock(&adev->grbm_idx_mutex);
3628 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3629 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3630 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3631 data = gfx_v8_0_get_rb_active_bitmap(adev);
3632 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
3633 rb_bitmap_width_per_sh);
3634 }
3635 }
3636 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3637
3638 adev->gfx.config.backend_enable_mask = active_rbs;
3639 adev->gfx.config.num_rbs = hweight32(active_rbs);
3640
3641 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
3642 adev->gfx.config.max_shader_engines, 16);
3643
3644 gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1);
3645
3646 if (!adev->gfx.config.backend_enable_mask ||
3647 adev->gfx.config.num_rbs >= num_rb_pipes) {
3648 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
3649 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3650 } else {
3651 gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
3652 adev->gfx.config.backend_enable_mask,
3653 num_rb_pipes);
3654 }
3655
3656 /* cache the values for userspace */
3657 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3658 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3659 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3660 adev->gfx.config.rb_config[i][j].rb_backend_disable =
3661 RREG32(mmCC_RB_BACKEND_DISABLE);
3662 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
3663 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3664 adev->gfx.config.rb_config[i][j].raster_config =
3665 RREG32(mmPA_SC_RASTER_CONFIG);
3666 adev->gfx.config.rb_config[i][j].raster_config_1 =
3667 RREG32(mmPA_SC_RASTER_CONFIG_1);
3668 }
3669 }
3670 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3671 mutex_unlock(&adev->grbm_idx_mutex);
3672}
3673
3674#define DEFAULT_SH_MEM_BASES (0x6000)
3675/**
3676 * gfx_v8_0_init_compute_vmid - gart enable
3677 *
3678 * @adev: amdgpu_device pointer
3679 *
3680 * Initialize compute vmid sh_mem registers
3681 *
3682 */
3683static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
3684{
3685 int i;
3686 uint32_t sh_mem_config;
3687 uint32_t sh_mem_bases;
3688
3689 /*
3690 * Configure apertures:
3691 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3692 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3693 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3694 */
3695 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3696
3697 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3698 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3699 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3700 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3701 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3702 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3703
3704 mutex_lock(&adev->srbm_mutex);
3705 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
3706 vi_srbm_select(adev, 0, 0, 0, i);
3707 /* CP and shaders */
3708 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3709 WREG32(mmSH_MEM_APE1_BASE, 1);
3710 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3711 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3712 }
3713 vi_srbm_select(adev, 0, 0, 0, 0);
3714 mutex_unlock(&adev->srbm_mutex);
3715
3716 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
3717 access. These should be enabled by FW for target VMIDs. */
3718 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
3719 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
3720 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
3721 WREG32(amdgpu_gds_reg_offset[i].gws, 0);
3722 WREG32(amdgpu_gds_reg_offset[i].oa, 0);
3723 }
3724}
3725
3726static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
3727{
3728 int vmid;
3729
3730 /*
3731 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
3732 * access. Compute VMIDs should be enabled by FW for target VMIDs,
3733 * the driver can enable them for graphics. VMID0 should maintain
3734 * access so that HWS firmware can save/restore entries.
3735 */
3736 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
3737 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
3738 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
3739 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
3740 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
3741 }
3742}
3743
3744static void gfx_v8_0_config_init(struct amdgpu_device *adev)
3745{
3746 switch (adev->asic_type) {
3747 default:
3748 adev->gfx.config.double_offchip_lds_buf = 1;
3749 break;
3750 case CHIP_CARRIZO:
3751 case CHIP_STONEY:
3752 adev->gfx.config.double_offchip_lds_buf = 0;
3753 break;
3754 }
3755}
3756
3757static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
3758{
3759 u32 tmp, sh_static_mem_cfg;
3760 int i;
3761
3762 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
3763 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3764 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3765 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
3766
3767 gfx_v8_0_tiling_mode_table_init(adev);
3768 gfx_v8_0_setup_rb(adev);
3769 gfx_v8_0_get_cu_info(adev);
3770 gfx_v8_0_config_init(adev);
3771
3772 /* XXX SH_MEM regs */
3773 /* where to put LDS, scratch, GPUVM in FSA64 space */
3774 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
3775 SWIZZLE_ENABLE, 1);
3776 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3777 ELEMENT_SIZE, 1);
3778 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3779 INDEX_STRIDE, 3);
3780 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
3781
3782 mutex_lock(&adev->srbm_mutex);
3783 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
3784 vi_srbm_select(adev, 0, 0, 0, i);
3785 /* CP and shaders */
3786 if (i == 0) {
3787 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3788 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3789 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3790 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3791 WREG32(mmSH_MEM_CONFIG, tmp);
3792 WREG32(mmSH_MEM_BASES, 0);
3793 } else {
3794 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3795 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3796 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3797 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3798 WREG32(mmSH_MEM_CONFIG, tmp);
3799 tmp = adev->gmc.shared_aperture_start >> 48;
3800 WREG32(mmSH_MEM_BASES, tmp);
3801 }
3802
3803 WREG32(mmSH_MEM_APE1_BASE, 1);
3804 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3805 }
3806 vi_srbm_select(adev, 0, 0, 0, 0);
3807 mutex_unlock(&adev->srbm_mutex);
3808
3809 gfx_v8_0_init_compute_vmid(adev);
3810 gfx_v8_0_init_gds_vmid(adev);
3811
3812 mutex_lock(&adev->grbm_idx_mutex);
3813 /*
3814 * making sure that the following register writes will be broadcasted
3815 * to all the shaders
3816 */
3817 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3818
3819 WREG32(mmPA_SC_FIFO_SIZE,
3820 (adev->gfx.config.sc_prim_fifo_size_frontend <<
3821 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3822 (adev->gfx.config.sc_prim_fifo_size_backend <<
3823 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3824 (adev->gfx.config.sc_hiz_tile_fifo_size <<
3825 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3826 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3827 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3828
3829 tmp = RREG32(mmSPI_ARB_PRIORITY);
3830 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
3831 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
3832 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
3833 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
3834 WREG32(mmSPI_ARB_PRIORITY, tmp);
3835
3836 mutex_unlock(&adev->grbm_idx_mutex);
3837
3838}
3839
3840static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3841{
3842 u32 i, j, k;
3843 u32 mask;
3844
3845 mutex_lock(&adev->grbm_idx_mutex);
3846 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3847 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3848 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3849 for (k = 0; k < adev->usec_timeout; k++) {
3850 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3851 break;
3852 udelay(1);
3853 }
3854 if (k == adev->usec_timeout) {
3855 gfx_v8_0_select_se_sh(adev, 0xffffffff,
3856 0xffffffff, 0xffffffff);
3857 mutex_unlock(&adev->grbm_idx_mutex);
3858 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
3859 i, j);
3860 return;
3861 }
3862 }
3863 }
3864 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3865 mutex_unlock(&adev->grbm_idx_mutex);
3866
3867 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3868 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3869 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3870 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3871 for (k = 0; k < adev->usec_timeout; k++) {
3872 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3873 break;
3874 udelay(1);
3875 }
3876}
3877
3878static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3879 bool enable)
3880{
3881 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3882
3883 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3884 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3885 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3886 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3887
3888 WREG32(mmCP_INT_CNTL_RING0, tmp);
3889}
3890
3891static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3892{
3893 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
3894 /* csib */
3895 WREG32(mmRLC_CSIB_ADDR_HI,
3896 adev->gfx.rlc.clear_state_gpu_addr >> 32);
3897 WREG32(mmRLC_CSIB_ADDR_LO,
3898 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3899 WREG32(mmRLC_CSIB_LENGTH,
3900 adev->gfx.rlc.clear_state_size);
3901}
3902
3903static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3904 int ind_offset,
3905 int list_size,
3906 int *unique_indices,
3907 int *indices_count,
3908 int max_indices,
3909 int *ind_start_offsets,
3910 int *offset_count,
3911 int max_offset)
3912{
3913 int indices;
3914 bool new_entry = true;
3915
3916 for (; ind_offset < list_size; ind_offset++) {
3917
3918 if (new_entry) {
3919 new_entry = false;
3920 ind_start_offsets[*offset_count] = ind_offset;
3921 *offset_count = *offset_count + 1;
3922 BUG_ON(*offset_count >= max_offset);
3923 }
3924
3925 if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3926 new_entry = true;
3927 continue;
3928 }
3929
3930 ind_offset += 2;
3931
3932 /* look for the matching indice */
3933 for (indices = 0;
3934 indices < *indices_count;
3935 indices++) {
3936 if (unique_indices[indices] ==
3937 register_list_format[ind_offset])
3938 break;
3939 }
3940
3941 if (indices >= *indices_count) {
3942 unique_indices[*indices_count] =
3943 register_list_format[ind_offset];
3944 indices = *indices_count;
3945 *indices_count = *indices_count + 1;
3946 BUG_ON(*indices_count >= max_indices);
3947 }
3948
3949 register_list_format[ind_offset] = indices;
3950 }
3951}
3952
3953static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3954{
3955 int i, temp, data;
3956 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3957 int indices_count = 0;
3958 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3959 int offset_count = 0;
3960
3961 int list_size;
3962 unsigned int *register_list_format =
3963 kmemdup(adev->gfx.rlc.register_list_format,
3964 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3965 if (!register_list_format)
3966 return -ENOMEM;
3967
3968 gfx_v8_0_parse_ind_reg_list(register_list_format,
3969 RLC_FormatDirectRegListLength,
3970 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3971 unique_indices,
3972 &indices_count,
3973 ARRAY_SIZE(unique_indices),
3974 indirect_start_offsets,
3975 &offset_count,
3976 ARRAY_SIZE(indirect_start_offsets));
3977
3978 /* save and restore list */
3979 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
3980
3981 WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3982 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3983 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
3984
3985 /* indirect list */
3986 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
3987 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
3988 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3989
3990 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
3991 list_size = list_size >> 1;
3992 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
3993 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
3994
3995 /* starting offsets starts */
3996 WREG32(mmRLC_GPM_SCRATCH_ADDR,
3997 adev->gfx.rlc.starting_offsets_start);
3998 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
3999 WREG32(