1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König <christian.koenig@amd.com>
23 */
24
25#include <linux/delay.h>
26#include <linux/firmware.h>
27
28#include "amdgpu.h"
29#include "amdgpu_uvd.h"
30#include "vid.h"
31#include "uvd/uvd_5_0_d.h"
32#include "uvd/uvd_5_0_sh_mask.h"
33#include "oss/oss_2_0_d.h"
34#include "oss/oss_2_0_sh_mask.h"
35#include "bif/bif_5_0_d.h"
36#include "vi.h"
37#include "smu/smu_7_1_2_d.h"
38#include "smu/smu_7_1_2_sh_mask.h"
39#include "ivsrcid/ivsrcid_vislands30.h"
40
41static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
42static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
43static int uvd_v5_0_start(struct amdgpu_device *adev);
44static void uvd_v5_0_stop(struct amdgpu_device *adev);
45static int uvd_v5_0_set_clockgating_state(void *handle,
46 enum amd_clockgating_state state);
47static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
48 bool enable);
49/**
50 * uvd_v5_0_ring_get_rptr - get read pointer
51 *
52 * @ring: amdgpu_ring pointer
53 *
54 * Returns the current hardware read pointer
55 */
56static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
57{
58 struct amdgpu_device *adev = ring->adev;
59
60 return RREG32(mmUVD_RBC_RB_RPTR);
61}
62
63/**
64 * uvd_v5_0_ring_get_wptr - get write pointer
65 *
66 * @ring: amdgpu_ring pointer
67 *
68 * Returns the current hardware write pointer
69 */
70static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
71{
72 struct amdgpu_device *adev = ring->adev;
73
74 return RREG32(mmUVD_RBC_RB_WPTR);
75}
76
77/**
78 * uvd_v5_0_ring_set_wptr - set write pointer
79 *
80 * @ring: amdgpu_ring pointer
81 *
82 * Commits the write pointer to the hardware
83 */
84static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
85{
86 struct amdgpu_device *adev = ring->adev;
87
88 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
89}
90
91static int uvd_v5_0_early_init(void *handle)
92{
93 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
94 adev->uvd.num_uvd_inst = 1;
95
96 uvd_v5_0_set_ring_funcs(adev);
97 uvd_v5_0_set_irq_funcs(adev);
98
99 return 0;
100}
101
102static int uvd_v5_0_sw_init(void *handle)
103{
104 struct amdgpu_ring *ring;
105 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
106 int r;
107
108 /* UVD TRAP */
109 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, source: &adev->uvd.inst->irq);
110 if (r)
111 return r;
112
113 r = amdgpu_uvd_sw_init(adev);
114 if (r)
115 return r;
116
117 ring = &adev->uvd.inst->ring;
118 sprintf(buf: ring->name, fmt: "uvd");
119 r = amdgpu_ring_init(adev, ring, max_dw: 512, irq_src: &adev->uvd.inst->irq, irq_type: 0,
120 hw_prio: AMDGPU_RING_PRIO_DEFAULT, NULL);
121 if (r)
122 return r;
123
124 r = amdgpu_uvd_resume(adev);
125 if (r)
126 return r;
127
128 r = amdgpu_uvd_entity_init(adev);
129
130 return r;
131}
132
133static int uvd_v5_0_sw_fini(void *handle)
134{
135 int r;
136 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
137
138 r = amdgpu_uvd_suspend(adev);
139 if (r)
140 return r;
141
142 return amdgpu_uvd_sw_fini(adev);
143}
144
145/**
146 * uvd_v5_0_hw_init - start and test UVD block
147 *
148 * @handle: handle used to pass amdgpu_device pointer
149 *
150 * Initialize the hardware, boot up the VCPU and do some testing
151 */
152static int uvd_v5_0_hw_init(void *handle)
153{
154 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
155 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
156 uint32_t tmp;
157 int r;
158
159 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
160 uvd_v5_0_set_clockgating_state(handle: adev, state: AMD_CG_STATE_UNGATE);
161 uvd_v5_0_enable_mgcg(adev, enable: true);
162
163 r = amdgpu_ring_test_helper(ring);
164 if (r)
165 goto done;
166
167 r = amdgpu_ring_alloc(ring, ndw: 10);
168 if (r) {
169 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
170 goto done;
171 }
172
173 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
174 amdgpu_ring_write(ring, v: tmp);
175 amdgpu_ring_write(ring, v: 0xFFFFF);
176
177 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
178 amdgpu_ring_write(ring, v: tmp);
179 amdgpu_ring_write(ring, v: 0xFFFFF);
180
181 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
182 amdgpu_ring_write(ring, v: tmp);
183 amdgpu_ring_write(ring, v: 0xFFFFF);
184
185 /* Clear timeout status bits */
186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
187 amdgpu_ring_write(ring, v: 0x8);
188
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
190 amdgpu_ring_write(ring, v: 3);
191
192 amdgpu_ring_commit(ring);
193
194done:
195 if (!r)
196 DRM_INFO("UVD initialized successfully.\n");
197
198 return r;
199
200}
201
202/**
203 * uvd_v5_0_hw_fini - stop the hardware block
204 *
205 * @handle: handle used to pass amdgpu_device pointer
206 *
207 * Stop the UVD block, mark ring as not ready any more
208 */
209static int uvd_v5_0_hw_fini(void *handle)
210{
211 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
212
213 cancel_delayed_work_sync(dwork: &adev->uvd.idle_work);
214
215 if (RREG32(mmUVD_STATUS) != 0)
216 uvd_v5_0_stop(adev);
217
218 return 0;
219}
220
221static int uvd_v5_0_prepare_suspend(void *handle)
222{
223 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
224
225 return amdgpu_uvd_prepare_suspend(adev);
226}
227
228static int uvd_v5_0_suspend(void *handle)
229{
230 int r;
231 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
232
233 /*
234 * Proper cleanups before halting the HW engine:
235 * - cancel the delayed idle work
236 * - enable powergating
237 * - enable clockgating
238 * - disable dpm
239 *
240 * TODO: to align with the VCN implementation, move the
241 * jobs for clockgating/powergating/dpm setting to
242 * ->set_powergating_state().
243 */
244 cancel_delayed_work_sync(dwork: &adev->uvd.idle_work);
245
246 if (adev->pm.dpm_enabled) {
247 amdgpu_dpm_enable_uvd(adev, enable: false);
248 } else {
249 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
250 /* shutdown the UVD block */
251 amdgpu_device_ip_set_powergating_state(dev: adev, block_type: AMD_IP_BLOCK_TYPE_UVD,
252 state: AMD_PG_STATE_GATE);
253 amdgpu_device_ip_set_clockgating_state(dev: adev, block_type: AMD_IP_BLOCK_TYPE_UVD,
254 state: AMD_CG_STATE_GATE);
255 }
256
257 r = uvd_v5_0_hw_fini(handle: adev);
258 if (r)
259 return r;
260
261 return amdgpu_uvd_suspend(adev);
262}
263
264static int uvd_v5_0_resume(void *handle)
265{
266 int r;
267 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
268
269 r = amdgpu_uvd_resume(adev);
270 if (r)
271 return r;
272
273 return uvd_v5_0_hw_init(handle: adev);
274}
275
276/**
277 * uvd_v5_0_mc_resume - memory controller programming
278 *
279 * @adev: amdgpu_device pointer
280 *
281 * Let the UVD memory controller know it's offsets
282 */
283static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
284{
285 uint64_t offset;
286 uint32_t size;
287
288 /* program memory controller bits 0-27 */
289 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
290 lower_32_bits(adev->uvd.inst->gpu_addr));
291 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
292 upper_32_bits(adev->uvd.inst->gpu_addr));
293
294 offset = AMDGPU_UVD_FIRMWARE_OFFSET;
295 size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
296 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
297 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
298
299 offset += size;
300 size = AMDGPU_UVD_HEAP_SIZE;
301 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
302 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
303
304 offset += size;
305 size = AMDGPU_UVD_STACK_SIZE +
306 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
307 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
308 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
309
310 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
311 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
312 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
313}
314
315/**
316 * uvd_v5_0_start - start UVD block
317 *
318 * @adev: amdgpu_device pointer
319 *
320 * Setup and start the UVD block
321 */
322static int uvd_v5_0_start(struct amdgpu_device *adev)
323{
324 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
325 uint32_t rb_bufsz, tmp;
326 uint32_t lmi_swap_cntl;
327 uint32_t mp_swap_cntl;
328 int i, j, r;
329
330 /*disable DPG */
331 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
332
333 /* disable byte swapping */
334 lmi_swap_cntl = 0;
335 mp_swap_cntl = 0;
336
337 uvd_v5_0_mc_resume(adev);
338
339 /* disable interupt */
340 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
341
342 /* stall UMC and register bus before resetting VCPU */
343 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
344 mdelay(1);
345
346 /* put LMI, VCPU, RBC etc... into reset */
347 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
348 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
349 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
350 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
351 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
352 mdelay(5);
353
354 /* take UVD block out of reset */
355 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
356 mdelay(5);
357
358 /* initialize UVD memory controller */
359 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
360 (1 << 21) | (1 << 9) | (1 << 20));
361
362#ifdef __BIG_ENDIAN
363 /* swap (8 in 32) RB and IB */
364 lmi_swap_cntl = 0xa;
365 mp_swap_cntl = 0;
366#endif
367 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
368 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
369
370 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
371 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
372 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
373 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
374 WREG32(mmUVD_MPC_SET_ALU, 0);
375 WREG32(mmUVD_MPC_SET_MUX, 0x88);
376
377 /* take all subblocks out of reset, except VCPU */
378 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
379 mdelay(5);
380
381 /* enable VCPU clock */
382 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
383
384 /* enable UMC */
385 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
386
387 /* boot up the VCPU */
388 WREG32(mmUVD_SOFT_RESET, 0);
389 mdelay(10);
390
391 for (i = 0; i < 10; ++i) {
392 uint32_t status;
393 for (j = 0; j < 100; ++j) {
394 status = RREG32(mmUVD_STATUS);
395 if (status & 2)
396 break;
397 mdelay(10);
398 }
399 r = 0;
400 if (status & 2)
401 break;
402
403 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
404 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
405 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
406 mdelay(10);
407 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
408 mdelay(10);
409 r = -1;
410 }
411
412 if (r) {
413 DRM_ERROR("UVD not responding, giving up!!!\n");
414 return r;
415 }
416 /* enable master interrupt */
417 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
418
419 /* clear the bit 4 of UVD_STATUS */
420 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
421
422 rb_bufsz = order_base_2(ring->ring_size);
423 tmp = 0;
424 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
425 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
426 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
427 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
428 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
429 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
430 /* force RBC into idle state */
431 WREG32(mmUVD_RBC_RB_CNTL, tmp);
432
433 /* set the write pointer delay */
434 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
435
436 /* set the wb address */
437 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
438
439 /* program the RB_BASE for ring buffer */
440 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
441 lower_32_bits(ring->gpu_addr));
442 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
443 upper_32_bits(ring->gpu_addr));
444
445 /* Initialize the ring buffer's read and write pointers */
446 WREG32(mmUVD_RBC_RB_RPTR, 0);
447
448 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
449 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
450
451 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
452
453 return 0;
454}
455
456/**
457 * uvd_v5_0_stop - stop UVD block
458 *
459 * @adev: amdgpu_device pointer
460 *
461 * stop the UVD block
462 */
463static void uvd_v5_0_stop(struct amdgpu_device *adev)
464{
465 /* force RBC into idle state */
466 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
467
468 /* Stall UMC and register bus before resetting VCPU */
469 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
470 mdelay(1);
471
472 /* put VCPU into reset */
473 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
474 mdelay(5);
475
476 /* disable VCPU clock */
477 WREG32(mmUVD_VCPU_CNTL, 0x0);
478
479 /* Unstall UMC and register bus */
480 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
481
482 WREG32(mmUVD_STATUS, 0);
483}
484
485/**
486 * uvd_v5_0_ring_emit_fence - emit an fence & trap command
487 *
488 * @ring: amdgpu_ring pointer
489 * @addr: address
490 * @seq: sequence number
491 * @flags: fence related flags
492 *
493 * Write a fence and a trap command to the ring.
494 */
495static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
496 unsigned flags)
497{
498 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
499
500 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
501 amdgpu_ring_write(ring, v: seq);
502 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
503 amdgpu_ring_write(ring, v: addr & 0xffffffff);
504 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
505 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
506 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
507 amdgpu_ring_write(ring, v: 0);
508
509 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
510 amdgpu_ring_write(ring, v: 0);
511 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
512 amdgpu_ring_write(ring, v: 0);
513 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
514 amdgpu_ring_write(ring, v: 2);
515}
516
517/**
518 * uvd_v5_0_ring_test_ring - register write test
519 *
520 * @ring: amdgpu_ring pointer
521 *
522 * Test if we can successfully write to the context register
523 */
524static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
525{
526 struct amdgpu_device *adev = ring->adev;
527 uint32_t tmp = 0;
528 unsigned i;
529 int r;
530
531 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
532 r = amdgpu_ring_alloc(ring, ndw: 3);
533 if (r)
534 return r;
535 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
536 amdgpu_ring_write(ring, v: 0xDEADBEEF);
537 amdgpu_ring_commit(ring);
538 for (i = 0; i < adev->usec_timeout; i++) {
539 tmp = RREG32(mmUVD_CONTEXT_ID);
540 if (tmp == 0xDEADBEEF)
541 break;
542 udelay(1);
543 }
544
545 if (i >= adev->usec_timeout)
546 r = -ETIMEDOUT;
547
548 return r;
549}
550
551/**
552 * uvd_v5_0_ring_emit_ib - execute indirect buffer
553 *
554 * @ring: amdgpu_ring pointer
555 * @job: job to retrieve vmid from
556 * @ib: indirect buffer to execute
557 * @flags: unused
558 *
559 * Write ring commands to execute the indirect buffer
560 */
561static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
562 struct amdgpu_job *job,
563 struct amdgpu_ib *ib,
564 uint32_t flags)
565{
566 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
567 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
568 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
569 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
570 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
571 amdgpu_ring_write(ring, v: ib->length_dw);
572}
573
574static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
575{
576 int i;
577
578 WARN_ON(ring->wptr % 2 || count % 2);
579
580 for (i = 0; i < count / 2; i++) {
581 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
582 amdgpu_ring_write(ring, v: 0);
583 }
584}
585
586static bool uvd_v5_0_is_idle(void *handle)
587{
588 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
589
590 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
591}
592
593static int uvd_v5_0_wait_for_idle(void *handle)
594{
595 unsigned i;
596 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
597
598 for (i = 0; i < adev->usec_timeout; i++) {
599 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
600 return 0;
601 }
602 return -ETIMEDOUT;
603}
604
605static int uvd_v5_0_soft_reset(void *handle)
606{
607 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
608
609 uvd_v5_0_stop(adev);
610
611 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
612 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
613 mdelay(5);
614
615 return uvd_v5_0_start(adev);
616}
617
618static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
619 struct amdgpu_irq_src *source,
620 unsigned type,
621 enum amdgpu_interrupt_state state)
622{
623 // TODO
624 return 0;
625}
626
627static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
628 struct amdgpu_irq_src *source,
629 struct amdgpu_iv_entry *entry)
630{
631 DRM_DEBUG("IH: UVD TRAP\n");
632 amdgpu_fence_process(ring: &adev->uvd.inst->ring);
633 return 0;
634}
635
636static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
637{
638 uint32_t data1, data3, suvd_flags;
639
640 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
641 data3 = RREG32(mmUVD_CGC_GATE);
642
643 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
644 UVD_SUVD_CGC_GATE__SIT_MASK |
645 UVD_SUVD_CGC_GATE__SMP_MASK |
646 UVD_SUVD_CGC_GATE__SCM_MASK |
647 UVD_SUVD_CGC_GATE__SDB_MASK;
648
649 if (enable) {
650 data3 |= (UVD_CGC_GATE__SYS_MASK |
651 UVD_CGC_GATE__UDEC_MASK |
652 UVD_CGC_GATE__MPEG2_MASK |
653 UVD_CGC_GATE__RBC_MASK |
654 UVD_CGC_GATE__LMI_MC_MASK |
655 UVD_CGC_GATE__IDCT_MASK |
656 UVD_CGC_GATE__MPRD_MASK |
657 UVD_CGC_GATE__MPC_MASK |
658 UVD_CGC_GATE__LBSI_MASK |
659 UVD_CGC_GATE__LRBBM_MASK |
660 UVD_CGC_GATE__UDEC_RE_MASK |
661 UVD_CGC_GATE__UDEC_CM_MASK |
662 UVD_CGC_GATE__UDEC_IT_MASK |
663 UVD_CGC_GATE__UDEC_DB_MASK |
664 UVD_CGC_GATE__UDEC_MP_MASK |
665 UVD_CGC_GATE__WCB_MASK |
666 UVD_CGC_GATE__JPEG_MASK |
667 UVD_CGC_GATE__SCPU_MASK);
668 /* only in pg enabled, we can gate clock to vcpu*/
669 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
670 data3 |= UVD_CGC_GATE__VCPU_MASK;
671 data3 &= ~UVD_CGC_GATE__REGS_MASK;
672 data1 |= suvd_flags;
673 } else {
674 data3 = 0;
675 data1 = 0;
676 }
677
678 WREG32(mmUVD_SUVD_CGC_GATE, data1);
679 WREG32(mmUVD_CGC_GATE, data3);
680}
681
682static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
683{
684 uint32_t data, data2;
685
686 data = RREG32(mmUVD_CGC_CTRL);
687 data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
688
689
690 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
691 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
692
693
694 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
695 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
696 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
697
698 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
699 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
700 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
701 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
702 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
703 UVD_CGC_CTRL__SYS_MODE_MASK |
704 UVD_CGC_CTRL__UDEC_MODE_MASK |
705 UVD_CGC_CTRL__MPEG2_MODE_MASK |
706 UVD_CGC_CTRL__REGS_MODE_MASK |
707 UVD_CGC_CTRL__RBC_MODE_MASK |
708 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
709 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
710 UVD_CGC_CTRL__IDCT_MODE_MASK |
711 UVD_CGC_CTRL__MPRD_MODE_MASK |
712 UVD_CGC_CTRL__MPC_MODE_MASK |
713 UVD_CGC_CTRL__LBSI_MODE_MASK |
714 UVD_CGC_CTRL__LRBBM_MODE_MASK |
715 UVD_CGC_CTRL__WCB_MODE_MASK |
716 UVD_CGC_CTRL__VCPU_MODE_MASK |
717 UVD_CGC_CTRL__JPEG_MODE_MASK |
718 UVD_CGC_CTRL__SCPU_MODE_MASK);
719 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
720 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
721 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
722 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
723 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
724
725 WREG32(mmUVD_CGC_CTRL, data);
726 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
727}
728
729#if 0
730static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
731{
732 uint32_t data, data1, cgc_flags, suvd_flags;
733
734 data = RREG32(mmUVD_CGC_GATE);
735 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
736
737 cgc_flags = UVD_CGC_GATE__SYS_MASK |
738 UVD_CGC_GATE__UDEC_MASK |
739 UVD_CGC_GATE__MPEG2_MASK |
740 UVD_CGC_GATE__RBC_MASK |
741 UVD_CGC_GATE__LMI_MC_MASK |
742 UVD_CGC_GATE__IDCT_MASK |
743 UVD_CGC_GATE__MPRD_MASK |
744 UVD_CGC_GATE__MPC_MASK |
745 UVD_CGC_GATE__LBSI_MASK |
746 UVD_CGC_GATE__LRBBM_MASK |
747 UVD_CGC_GATE__UDEC_RE_MASK |
748 UVD_CGC_GATE__UDEC_CM_MASK |
749 UVD_CGC_GATE__UDEC_IT_MASK |
750 UVD_CGC_GATE__UDEC_DB_MASK |
751 UVD_CGC_GATE__UDEC_MP_MASK |
752 UVD_CGC_GATE__WCB_MASK |
753 UVD_CGC_GATE__VCPU_MASK |
754 UVD_CGC_GATE__SCPU_MASK;
755
756 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
757 UVD_SUVD_CGC_GATE__SIT_MASK |
758 UVD_SUVD_CGC_GATE__SMP_MASK |
759 UVD_SUVD_CGC_GATE__SCM_MASK |
760 UVD_SUVD_CGC_GATE__SDB_MASK;
761
762 data |= cgc_flags;
763 data1 |= suvd_flags;
764
765 WREG32(mmUVD_CGC_GATE, data);
766 WREG32(mmUVD_SUVD_CGC_GATE, data1);
767}
768#endif
769
770static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
771 bool enable)
772{
773 u32 orig, data;
774
775 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
776 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
777 data |= 0xfff;
778 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
779
780 orig = data = RREG32(mmUVD_CGC_CTRL);
781 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
782 if (orig != data)
783 WREG32(mmUVD_CGC_CTRL, data);
784 } else {
785 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
786 data &= ~0xfff;
787 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
788
789 orig = data = RREG32(mmUVD_CGC_CTRL);
790 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
791 if (orig != data)
792 WREG32(mmUVD_CGC_CTRL, data);
793 }
794}
795
796static int uvd_v5_0_set_clockgating_state(void *handle,
797 enum amd_clockgating_state state)
798{
799 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
800 bool enable = (state == AMD_CG_STATE_GATE);
801
802 if (enable) {
803 /* wait for STATUS to clear */
804 if (uvd_v5_0_wait_for_idle(handle))
805 return -EBUSY;
806 uvd_v5_0_enable_clock_gating(adev, enable: true);
807
808 /* enable HW gates because UVD is idle */
809/* uvd_v5_0_set_hw_clock_gating(adev); */
810 } else {
811 uvd_v5_0_enable_clock_gating(adev, enable: false);
812 }
813
814 uvd_v5_0_set_sw_clock_gating(adev);
815 return 0;
816}
817
818static int uvd_v5_0_set_powergating_state(void *handle,
819 enum amd_powergating_state state)
820{
821 /* This doesn't actually powergate the UVD block.
822 * That's done in the dpm code via the SMC. This
823 * just re-inits the block as necessary. The actual
824 * gating still happens in the dpm code. We should
825 * revisit this when there is a cleaner line between
826 * the smc and the hw blocks
827 */
828 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
829 int ret = 0;
830
831 if (state == AMD_PG_STATE_GATE) {
832 uvd_v5_0_stop(adev);
833 } else {
834 ret = uvd_v5_0_start(adev);
835 if (ret)
836 goto out;
837 }
838
839out:
840 return ret;
841}
842
843static void uvd_v5_0_get_clockgating_state(void *handle, u64 *flags)
844{
845 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
846 int data;
847
848 mutex_lock(&adev->pm.mutex);
849
850 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
851 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
852 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
853 goto out;
854 }
855
856 /* AMD_CG_SUPPORT_UVD_MGCG */
857 data = RREG32(mmUVD_CGC_CTRL);
858 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
859 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
860
861out:
862 mutex_unlock(lock: &adev->pm.mutex);
863}
864
865static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
866 .name = "uvd_v5_0",
867 .early_init = uvd_v5_0_early_init,
868 .late_init = NULL,
869 .sw_init = uvd_v5_0_sw_init,
870 .sw_fini = uvd_v5_0_sw_fini,
871 .hw_init = uvd_v5_0_hw_init,
872 .hw_fini = uvd_v5_0_hw_fini,
873 .prepare_suspend = uvd_v5_0_prepare_suspend,
874 .suspend = uvd_v5_0_suspend,
875 .resume = uvd_v5_0_resume,
876 .is_idle = uvd_v5_0_is_idle,
877 .wait_for_idle = uvd_v5_0_wait_for_idle,
878 .soft_reset = uvd_v5_0_soft_reset,
879 .set_clockgating_state = uvd_v5_0_set_clockgating_state,
880 .set_powergating_state = uvd_v5_0_set_powergating_state,
881 .get_clockgating_state = uvd_v5_0_get_clockgating_state,
882};
883
884static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
885 .type = AMDGPU_RING_TYPE_UVD,
886 .align_mask = 0xf,
887 .support_64bit_ptrs = false,
888 .no_user_fence = true,
889 .get_rptr = uvd_v5_0_ring_get_rptr,
890 .get_wptr = uvd_v5_0_ring_get_wptr,
891 .set_wptr = uvd_v5_0_ring_set_wptr,
892 .parse_cs = amdgpu_uvd_ring_parse_cs,
893 .emit_frame_size =
894 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */
895 .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */
896 .emit_ib = uvd_v5_0_ring_emit_ib,
897 .emit_fence = uvd_v5_0_ring_emit_fence,
898 .test_ring = uvd_v5_0_ring_test_ring,
899 .test_ib = amdgpu_uvd_ring_test_ib,
900 .insert_nop = uvd_v5_0_ring_insert_nop,
901 .pad_ib = amdgpu_ring_generic_pad_ib,
902 .begin_use = amdgpu_uvd_ring_begin_use,
903 .end_use = amdgpu_uvd_ring_end_use,
904};
905
906static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
907{
908 adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs;
909}
910
911static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
912 .set = uvd_v5_0_set_interrupt_state,
913 .process = uvd_v5_0_process_interrupt,
914};
915
916static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
917{
918 adev->uvd.inst->irq.num_types = 1;
919 adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs;
920}
921
922const struct amdgpu_ip_block_version uvd_v5_0_ip_block =
923{
924 .type = AMD_IP_BLOCK_TYPE_UVD,
925 .major = 5,
926 .minor = 0,
927 .rev = 0,
928 .funcs = &uvd_v5_0_ip_funcs,
929};
930

source code of linux/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c