1/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2/*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef KFD_CRAT_H_INCLUDED
25#define KFD_CRAT_H_INCLUDED
26
27#include <linux/types.h>
28
29#pragma pack(1)
30
31/*
32 * 4CC signature values for the CRAT and CDIT ACPI tables
33 */
34
35#define CRAT_SIGNATURE "CRAT"
36#define CDIT_SIGNATURE "CDIT"
37
38/*
39 * Component Resource Association Table (CRAT)
40 */
41
42#define CRAT_OEMID_LENGTH 6
43#define CRAT_OEMTABLEID_LENGTH 8
44#define CRAT_RESERVED_LENGTH 6
45
46#define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1)
47
48/* Compute Unit flags */
49#define COMPUTE_UNIT_CPU (1 << 0) /* Create Virtual CRAT for CPU */
50#define COMPUTE_UNIT_GPU (1 << 1) /* Create Virtual CRAT for GPU */
51
52struct crat_header {
53 uint32_t signature;
54 uint32_t length;
55 uint8_t revision;
56 uint8_t checksum;
57 uint8_t oem_id[CRAT_OEMID_LENGTH];
58 uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];
59 uint32_t oem_revision;
60 uint32_t creator_id;
61 uint32_t creator_revision;
62 uint32_t total_entries;
63 uint16_t num_domains;
64 uint8_t reserved[CRAT_RESERVED_LENGTH];
65};
66
67/*
68 * The header structure is immediately followed by total_entries of the
69 * data definitions
70 */
71
72/*
73 * The currently defined subtype entries in the CRAT
74 */
75#define CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY 0
76#define CRAT_SUBTYPE_MEMORY_AFFINITY 1
77#define CRAT_SUBTYPE_CACHE_AFFINITY 2
78#define CRAT_SUBTYPE_TLB_AFFINITY 3
79#define CRAT_SUBTYPE_CCOMPUTE_AFFINITY 4
80#define CRAT_SUBTYPE_IOLINK_AFFINITY 5
81#define CRAT_SUBTYPE_MAX 6
82
83#define CRAT_SIBLINGMAP_SIZE 32
84
85/*
86 * ComputeUnit Affinity structure and definitions
87 */
88#define CRAT_CU_FLAGS_ENABLED 0x00000001
89#define CRAT_CU_FLAGS_HOT_PLUGGABLE 0x00000002
90#define CRAT_CU_FLAGS_CPU_PRESENT 0x00000004
91#define CRAT_CU_FLAGS_GPU_PRESENT 0x00000008
92#define CRAT_CU_FLAGS_IOMMU_PRESENT 0x00000010
93#define CRAT_CU_FLAGS_RESERVED 0xffffffe0
94
95#define CRAT_COMPUTEUNIT_RESERVED_LENGTH 4
96
97struct crat_subtype_computeunit {
98 uint8_t type;
99 uint8_t length;
100 uint16_t reserved;
101 uint32_t flags;
102 uint32_t proximity_domain;
103 uint32_t processor_id_low;
104 uint16_t num_cpu_cores;
105 uint16_t num_simd_cores;
106 uint16_t max_waves_simd;
107 uint16_t io_count;
108 uint16_t hsa_capability;
109 uint16_t lds_size_in_kb;
110 uint8_t wave_front_size;
111 uint8_t num_banks;
112 uint16_t micro_engine_id;
113 uint8_t array_count;
114 uint8_t num_cu_per_array;
115 uint8_t num_simd_per_cu;
116 uint8_t max_slots_scatch_cu;
117 uint8_t reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];
118};
119
120/*
121 * HSA Memory Affinity structure and definitions
122 */
123#define CRAT_MEM_FLAGS_ENABLED 0x00000001
124#define CRAT_MEM_FLAGS_HOT_PLUGGABLE 0x00000002
125#define CRAT_MEM_FLAGS_NON_VOLATILE 0x00000004
126#define CRAT_MEM_FLAGS_RESERVED 0xfffffff8
127
128#define CRAT_MEMORY_RESERVED_LENGTH 8
129
130struct crat_subtype_memory {
131 uint8_t type;
132 uint8_t length;
133 uint16_t reserved;
134 uint32_t flags;
135 uint32_t proximity_domain;
136 uint32_t base_addr_low;
137 uint32_t base_addr_high;
138 uint32_t length_low;
139 uint32_t length_high;
140 uint32_t width;
141 uint8_t visibility_type; /* for virtual (dGPU) CRAT */
142 uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];
143};
144
145/*
146 * HSA Cache Affinity structure and definitions
147 */
148#define CRAT_CACHE_FLAGS_ENABLED 0x00000001
149#define CRAT_CACHE_FLAGS_DATA_CACHE 0x00000002
150#define CRAT_CACHE_FLAGS_INST_CACHE 0x00000004
151#define CRAT_CACHE_FLAGS_CPU_CACHE 0x00000008
152#define CRAT_CACHE_FLAGS_SIMD_CACHE 0x00000010
153#define CRAT_CACHE_FLAGS_RESERVED 0xffffffe0
154
155#define CRAT_CACHE_RESERVED_LENGTH 8
156
157struct crat_subtype_cache {
158 uint8_t type;
159 uint8_t length;
160 uint16_t reserved;
161 uint32_t flags;
162 uint32_t processor_id_low;
163 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
164 uint32_t cache_size;
165 uint8_t cache_level;
166 uint8_t lines_per_tag;
167 uint16_t cache_line_size;
168 uint8_t associativity;
169 uint8_t cache_properties;
170 uint16_t cache_latency;
171 uint8_t reserved2[CRAT_CACHE_RESERVED_LENGTH];
172};
173
174/*
175 * HSA TLB Affinity structure and definitions
176 */
177#define CRAT_TLB_FLAGS_ENABLED 0x00000001
178#define CRAT_TLB_FLAGS_DATA_TLB 0x00000002
179#define CRAT_TLB_FLAGS_INST_TLB 0x00000004
180#define CRAT_TLB_FLAGS_CPU_TLB 0x00000008
181#define CRAT_TLB_FLAGS_SIMD_TLB 0x00000010
182#define CRAT_TLB_FLAGS_RESERVED 0xffffffe0
183
184#define CRAT_TLB_RESERVED_LENGTH 4
185
186struct crat_subtype_tlb {
187 uint8_t type;
188 uint8_t length;
189 uint16_t reserved;
190 uint32_t flags;
191 uint32_t processor_id_low;
192 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
193 uint32_t tlb_level;
194 uint8_t data_tlb_associativity_2mb;
195 uint8_t data_tlb_size_2mb;
196 uint8_t instruction_tlb_associativity_2mb;
197 uint8_t instruction_tlb_size_2mb;
198 uint8_t data_tlb_associativity_4k;
199 uint8_t data_tlb_size_4k;
200 uint8_t instruction_tlb_associativity_4k;
201 uint8_t instruction_tlb_size_4k;
202 uint8_t data_tlb_associativity_1gb;
203 uint8_t data_tlb_size_1gb;
204 uint8_t instruction_tlb_associativity_1gb;
205 uint8_t instruction_tlb_size_1gb;
206 uint8_t reserved2[CRAT_TLB_RESERVED_LENGTH];
207};
208
209/*
210 * HSA CCompute/APU Affinity structure and definitions
211 */
212#define CRAT_CCOMPUTE_FLAGS_ENABLED 0x00000001
213#define CRAT_CCOMPUTE_FLAGS_RESERVED 0xfffffffe
214
215#define CRAT_CCOMPUTE_RESERVED_LENGTH 16
216
217struct crat_subtype_ccompute {
218 uint8_t type;
219 uint8_t length;
220 uint16_t reserved;
221 uint32_t flags;
222 uint32_t processor_id_low;
223 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
224 uint32_t apu_size;
225 uint8_t reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];
226};
227
228/*
229 * HSA IO Link Affinity structure and definitions
230 */
231#define CRAT_IOLINK_FLAGS_ENABLED (1 << 0)
232#define CRAT_IOLINK_FLAGS_NON_COHERENT (1 << 1)
233#define CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT (1 << 2)
234#define CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT (1 << 3)
235#define CRAT_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA (1 << 4)
236#define CRAT_IOLINK_FLAGS_BI_DIRECTIONAL (1 << 31)
237#define CRAT_IOLINK_FLAGS_RESERVED_MASK 0x7fffffe0
238
239/*
240 * IO interface types
241 */
242#define CRAT_IOLINK_TYPE_UNDEFINED 0
243#define CRAT_IOLINK_TYPE_HYPERTRANSPORT 1
244#define CRAT_IOLINK_TYPE_PCIEXPRESS 2
245#define CRAT_IOLINK_TYPE_AMBA 3
246#define CRAT_IOLINK_TYPE_MIPI 4
247#define CRAT_IOLINK_TYPE_QPI_1_1 5
248#define CRAT_IOLINK_TYPE_RESERVED1 6
249#define CRAT_IOLINK_TYPE_RESERVED2 7
250#define CRAT_IOLINK_TYPE_RAPID_IO 8
251#define CRAT_IOLINK_TYPE_INFINIBAND 9
252#define CRAT_IOLINK_TYPE_RESERVED3 10
253#define CRAT_IOLINK_TYPE_XGMI 11
254#define CRAT_IOLINK_TYPE_XGOP 12
255#define CRAT_IOLINK_TYPE_GZ 13
256#define CRAT_IOLINK_TYPE_ETHERNET_RDMA 14
257#define CRAT_IOLINK_TYPE_RDMA_OTHER 15
258#define CRAT_IOLINK_TYPE_OTHER 16
259#define CRAT_IOLINK_TYPE_MAX 255
260
261#define CRAT_IOLINK_RESERVED_LENGTH 24
262
263struct crat_subtype_iolink {
264 uint8_t type;
265 uint8_t length;
266 uint16_t reserved;
267 uint32_t flags;
268 uint32_t proximity_domain_from;
269 uint32_t proximity_domain_to;
270 uint8_t io_interface_type;
271 uint8_t version_major;
272 uint16_t version_minor;
273 uint32_t minimum_latency;
274 uint32_t maximum_latency;
275 uint32_t minimum_bandwidth_mbs;
276 uint32_t maximum_bandwidth_mbs;
277 uint32_t recommended_transfer_size;
278 uint8_t reserved2[CRAT_IOLINK_RESERVED_LENGTH - 1];
279 uint8_t num_hops_xgmi;
280};
281
282/*
283 * HSA generic sub-type header
284 */
285
286#define CRAT_SUBTYPE_FLAGS_ENABLED 0x00000001
287
288struct crat_subtype_generic {
289 uint8_t type;
290 uint8_t length;
291 uint16_t reserved;
292 uint32_t flags;
293};
294
295/*
296 * Component Locality Distance Information Table (CDIT)
297 */
298#define CDIT_OEMID_LENGTH 6
299#define CDIT_OEMTABLEID_LENGTH 8
300
301struct cdit_header {
302 uint32_t signature;
303 uint32_t length;
304 uint8_t revision;
305 uint8_t checksum;
306 uint8_t oem_id[CDIT_OEMID_LENGTH];
307 uint8_t oem_table_id[CDIT_OEMTABLEID_LENGTH];
308 uint32_t oem_revision;
309 uint32_t creator_id;
310 uint32_t creator_revision;
311 uint32_t total_entries;
312 uint16_t num_domains;
313 uint8_t entry[1];
314};
315
316#pragma pack()
317
318struct kfd_dev;
319
320int kfd_create_crat_image_acpi(void **crat_image, size_t *size);
321void kfd_destroy_crat_image(void *crat_image);
322int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
323 uint32_t proximity_domain);
324int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
325 int flags, struct kfd_dev *kdev,
326 uint32_t proximity_domain);
327
328#endif /* KFD_CRAT_H_INCLUDED */
329

source code of linux/drivers/gpu/drm/amd/amdkfd/kfd_crat.h