1/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2/*
3 * Copyright 2016-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#ifndef F32_MES_PM4_PACKETS_H
26#define F32_MES_PM4_PACKETS_H
27
28#ifndef PM4_MES_HEADER_DEFINED
29#define PM4_MES_HEADER_DEFINED
30union PM4_MES_TYPE_3_HEADER {
31 struct {
32 uint32_t reserved1 : 8; /* < reserved */
33 uint32_t opcode : 8; /* < IT opcode */
34 uint32_t count : 14;/* < number of DWORDs - 1 in the
35 * information body.
36 */
37 uint32_t type : 2; /* < packet identifier.
38 * It should be 3 for type 3 packets
39 */
40 };
41 uint32_t u32All;
42};
43#endif /* PM4_MES_HEADER_DEFINED */
44
45/*--------------------MES_SET_RESOURCES--------------------*/
46
47#ifndef PM4_MES_SET_RESOURCES_DEFINED
48#define PM4_MES_SET_RESOURCES_DEFINED
49enum mes_set_resources_queue_type_enum {
50 queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
51 queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
52 queue_type__mes_set_resources__hsa_debug_interface_queue = 4
53};
54
55
56struct pm4_mes_set_resources {
57 union {
58 union PM4_MES_TYPE_3_HEADER header; /* header */
59 uint32_t ordinal1;
60 };
61
62 union {
63 struct {
64 uint32_t vmid_mask:16;
65 uint32_t unmap_latency:8;
66 uint32_t reserved1:5;
67 enum mes_set_resources_queue_type_enum queue_type:3;
68 } bitfields2;
69 uint32_t ordinal2;
70 };
71
72 uint32_t queue_mask_lo;
73 uint32_t queue_mask_hi;
74 uint32_t gws_mask_lo;
75 uint32_t gws_mask_hi;
76
77 union {
78 struct {
79 uint32_t oac_mask:16;
80 uint32_t reserved2:16;
81 } bitfields7;
82 uint32_t ordinal7;
83 };
84
85 union {
86 struct {
87 uint32_t gds_heap_base:10;
88 uint32_t reserved3:1;
89 uint32_t gds_heap_size:10;
90 uint32_t reserved4:11;
91 } bitfields8;
92 uint32_t ordinal8;
93 };
94
95};
96#endif
97
98/*--------------------MES_RUN_LIST--------------------*/
99
100#ifndef PM4_MES_RUN_LIST_DEFINED
101#define PM4_MES_RUN_LIST_DEFINED
102
103struct pm4_mes_runlist {
104 union {
105 union PM4_MES_TYPE_3_HEADER header; /* header */
106 uint32_t ordinal1;
107 };
108
109 union {
110 struct {
111 uint32_t reserved1:2;
112 uint32_t ib_base_lo:30;
113 } bitfields2;
114 uint32_t ordinal2;
115 };
116
117 uint32_t ib_base_hi;
118
119 union {
120 struct {
121 uint32_t ib_size:20;
122 uint32_t chain:1;
123 uint32_t offload_polling:1;
124 uint32_t chained_runlist_idle_disable:1;
125 uint32_t valid:1;
126 uint32_t process_cnt:4;
127 uint32_t reserved3:4;
128 } bitfields4;
129 uint32_t ordinal4;
130 };
131
132};
133#endif
134
135/*--------------------MES_MAP_PROCESS--------------------*/
136
137#ifndef PM4_MES_MAP_PROCESS_DEFINED
138#define PM4_MES_MAP_PROCESS_DEFINED
139
140struct pm4_mes_map_process {
141 union {
142 union PM4_MES_TYPE_3_HEADER header; /* header */
143 uint32_t ordinal1;
144 };
145
146 union {
147 struct {
148 uint32_t pasid:16;
149 uint32_t reserved1:8;
150 uint32_t diq_enable:1;
151 uint32_t process_quantum:7;
152 } bitfields2;
153 uint32_t ordinal2;
154 };
155
156 uint32_t vm_context_page_table_base_addr_lo32;
157
158 uint32_t vm_context_page_table_base_addr_hi32;
159
160 uint32_t sh_mem_bases;
161
162 uint32_t sh_mem_config;
163
164 uint32_t sq_shader_tba_lo;
165
166 uint32_t sq_shader_tba_hi;
167
168 uint32_t sq_shader_tma_lo;
169
170 uint32_t sq_shader_tma_hi;
171
172 uint32_t reserved6;
173
174 uint32_t gds_addr_lo;
175
176 uint32_t gds_addr_hi;
177
178 union {
179 struct {
180 uint32_t num_gws:7;
181 uint32_t sdma_enable:1;
182 uint32_t num_oac:4;
183 uint32_t gds_size_hi:4;
184 uint32_t gds_size:6;
185 uint32_t num_queues:10;
186 } bitfields14;
187 uint32_t ordinal14;
188 };
189
190 uint32_t completion_signal_lo;
191
192 uint32_t completion_signal_hi;
193
194};
195
196#endif
197
198/*--------------------MES_MAP_PROCESS_VM--------------------*/
199
200#ifndef PM4_MES_MAP_PROCESS_VM_DEFINED
201#define PM4_MES_MAP_PROCESS_VM_DEFINED
202
203struct PM4_MES_MAP_PROCESS_VM {
204 union {
205 union PM4_MES_TYPE_3_HEADER header; /* header */
206 uint32_t ordinal1;
207 };
208
209 uint32_t reserved1;
210
211 uint32_t vm_context_cntl;
212
213 uint32_t reserved2;
214
215 uint32_t vm_context_page_table_end_addr_lo32;
216
217 uint32_t vm_context_page_table_end_addr_hi32;
218
219 uint32_t vm_context_page_table_start_addr_lo32;
220
221 uint32_t vm_context_page_table_start_addr_hi32;
222
223 uint32_t reserved3;
224
225 uint32_t reserved4;
226
227 uint32_t reserved5;
228
229 uint32_t reserved6;
230
231 uint32_t reserved7;
232
233 uint32_t reserved8;
234
235 uint32_t completion_signal_lo32;
236
237 uint32_t completion_signal_hi32;
238
239};
240#endif
241
242/*--------------------MES_MAP_QUEUES--------------------*/
243
244#ifndef PM4_MES_MAP_QUEUES_VI_DEFINED
245#define PM4_MES_MAP_QUEUES_VI_DEFINED
246enum mes_map_queues_queue_sel_enum {
247 queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0,
248queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1
249};
250
251enum mes_map_queues_queue_type_enum {
252 queue_type__mes_map_queues__normal_compute_vi = 0,
253 queue_type__mes_map_queues__debug_interface_queue_vi = 1,
254 queue_type__mes_map_queues__normal_latency_static_queue_vi = 2,
255queue_type__mes_map_queues__low_latency_static_queue_vi = 3
256};
257
258enum mes_map_queues_engine_sel_enum {
259 engine_sel__mes_map_queues__compute_vi = 0,
260 engine_sel__mes_map_queues__sdma0_vi = 2,
261 engine_sel__mes_map_queues__sdma1_vi = 3
262};
263
264enum mes_map_queues_extended_engine_sel_enum {
265 extended_engine_sel__mes_map_queues__legacy_engine_sel = 0,
266 extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1
267};
268
269struct pm4_mes_map_queues {
270 union {
271 union PM4_MES_TYPE_3_HEADER header; /* header */
272 uint32_t ordinal1;
273 };
274
275 union {
276 struct {
277 uint32_t reserved1:2;
278 enum mes_map_queues_extended_engine_sel_enum extended_engine_sel:2;
279 enum mes_map_queues_queue_sel_enum queue_sel:2;
280 uint32_t reserved5:6;
281 uint32_t gws_control_queue:1;
282 uint32_t reserved2:8;
283 enum mes_map_queues_queue_type_enum queue_type:3;
284 uint32_t reserved3:2;
285 enum mes_map_queues_engine_sel_enum engine_sel:3;
286 uint32_t num_queues:3;
287 } bitfields2;
288 uint32_t ordinal2;
289 };
290
291 union {
292 struct {
293 uint32_t reserved3:1;
294 uint32_t check_disable:1;
295 uint32_t doorbell_offset:26;
296 uint32_t reserved4:4;
297 } bitfields3;
298 uint32_t ordinal3;
299 };
300
301 uint32_t mqd_addr_lo;
302 uint32_t mqd_addr_hi;
303 uint32_t wptr_addr_lo;
304 uint32_t wptr_addr_hi;
305};
306#endif
307
308/*--------------------MES_QUERY_STATUS--------------------*/
309
310#ifndef PM4_MES_QUERY_STATUS_DEFINED
311#define PM4_MES_QUERY_STATUS_DEFINED
312enum mes_query_status_interrupt_sel_enum {
313 interrupt_sel__mes_query_status__completion_status = 0,
314 interrupt_sel__mes_query_status__process_status = 1,
315 interrupt_sel__mes_query_status__queue_status = 2
316};
317
318enum mes_query_status_command_enum {
319 command__mes_query_status__interrupt_only = 0,
320 command__mes_query_status__fence_only_immediate = 1,
321 command__mes_query_status__fence_only_after_write_ack = 2,
322 command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
323};
324
325enum mes_query_status_engine_sel_enum {
326 engine_sel__mes_query_status__compute = 0,
327 engine_sel__mes_query_status__sdma0_queue = 2,
328 engine_sel__mes_query_status__sdma1_queue = 3
329};
330
331struct pm4_mes_query_status {
332 union {
333 union PM4_MES_TYPE_3_HEADER header; /* header */
334 uint32_t ordinal1;
335 };
336
337 union {
338 struct {
339 uint32_t context_id:28;
340 enum mes_query_status_interrupt_sel_enum interrupt_sel:2;
341 enum mes_query_status_command_enum command:2;
342 } bitfields2;
343 uint32_t ordinal2;
344 };
345
346 union {
347 struct {
348 uint32_t pasid:16;
349 uint32_t reserved1:16;
350 } bitfields3a;
351 struct {
352 uint32_t reserved2:2;
353 uint32_t doorbell_offset:26;
354 enum mes_query_status_engine_sel_enum engine_sel:3;
355 uint32_t reserved3:1;
356 } bitfields3b;
357 uint32_t ordinal3;
358 };
359
360 uint32_t addr_lo;
361 uint32_t addr_hi;
362 uint32_t data_lo;
363 uint32_t data_hi;
364};
365#endif
366
367/*--------------------MES_UNMAP_QUEUES--------------------*/
368
369#ifndef PM4_MES_UNMAP_QUEUES_DEFINED
370#define PM4_MES_UNMAP_QUEUES_DEFINED
371enum mes_unmap_queues_action_enum {
372 action__mes_unmap_queues__preempt_queues = 0,
373 action__mes_unmap_queues__reset_queues = 1,
374 action__mes_unmap_queues__disable_process_queues = 2,
375 action__mes_unmap_queues__reserved = 3
376};
377
378enum mes_unmap_queues_queue_sel_enum {
379 queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
380 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
381 queue_sel__mes_unmap_queues__unmap_all_queues = 2,
382 queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3
383};
384
385enum mes_unmap_queues_engine_sel_enum {
386 engine_sel__mes_unmap_queues__compute = 0,
387 engine_sel__mes_unmap_queues__sdma0 = 2,
388 engine_sel__mes_unmap_queues__sdmal = 3
389};
390
391enum mes_unmap_queues_extended_engine_sel_enum {
392 extended_engine_sel__mes_unmap_queues__legacy_engine_sel = 0,
393 extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = 1
394};
395
396struct pm4_mes_unmap_queues {
397 union {
398 union PM4_MES_TYPE_3_HEADER header; /* header */
399 uint32_t ordinal1;
400 };
401
402 union {
403 struct {
404 enum mes_unmap_queues_action_enum action:2;
405 enum mes_unmap_queues_extended_engine_sel_enum extended_engine_sel:2;
406 enum mes_unmap_queues_queue_sel_enum queue_sel:2;
407 uint32_t reserved2:20;
408 enum mes_unmap_queues_engine_sel_enum engine_sel:3;
409 uint32_t num_queues:3;
410 } bitfields2;
411 uint32_t ordinal2;
412 };
413
414 union {
415 struct {
416 uint32_t pasid:16;
417 uint32_t reserved3:16;
418 } bitfields3a;
419 struct {
420 uint32_t reserved4:2;
421 uint32_t doorbell_offset0:26;
422 int32_t reserved5:4;
423 } bitfields3b;
424 uint32_t ordinal3;
425 };
426
427 union {
428 struct {
429 uint32_t reserved6:2;
430 uint32_t doorbell_offset1:26;
431 uint32_t reserved7:4;
432 } bitfields4;
433 uint32_t ordinal4;
434 };
435
436 union {
437 struct {
438 uint32_t reserved8:2;
439 uint32_t doorbell_offset2:26;
440 uint32_t reserved9:4;
441 } bitfields5;
442 uint32_t ordinal5;
443 };
444
445 union {
446 struct {
447 uint32_t reserved10:2;
448 uint32_t doorbell_offset3:26;
449 uint32_t reserved11:4;
450 } bitfields6;
451 uint32_t ordinal6;
452 };
453};
454#endif
455
456#ifndef PM4_MEC_RELEASE_MEM_DEFINED
457#define PM4_MEC_RELEASE_MEM_DEFINED
458
459enum mec_release_mem_event_index_enum {
460 event_index__mec_release_mem__end_of_pipe = 5,
461 event_index__mec_release_mem__shader_done = 6
462};
463
464enum mec_release_mem_cache_policy_enum {
465 cache_policy__mec_release_mem__lru = 0,
466 cache_policy__mec_release_mem__stream = 1
467};
468
469enum mec_release_mem_pq_exe_status_enum {
470 pq_exe_status__mec_release_mem__default = 0,
471 pq_exe_status__mec_release_mem__phase_update = 1
472};
473
474enum mec_release_mem_dst_sel_enum {
475 dst_sel__mec_release_mem__memory_controller = 0,
476 dst_sel__mec_release_mem__tc_l2 = 1,
477 dst_sel__mec_release_mem__queue_write_pointer_register = 2,
478 dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3
479};
480
481enum mec_release_mem_int_sel_enum {
482 int_sel__mec_release_mem__none = 0,
483 int_sel__mec_release_mem__send_interrupt_only = 1,
484 int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2,
485 int_sel__mec_release_mem__send_data_after_write_confirm = 3,
486 int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4,
487 int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5,
488 int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6
489};
490
491enum mec_release_mem_data_sel_enum {
492 data_sel__mec_release_mem__none = 0,
493 data_sel__mec_release_mem__send_32_bit_low = 1,
494 data_sel__mec_release_mem__send_64_bit_data = 2,
495 data_sel__mec_release_mem__send_gpu_clock_counter = 3,
496 data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4,
497 data_sel__mec_release_mem__store_gds_data_to_memory = 5
498};
499
500struct pm4_mec_release_mem {
501 union {
502 union PM4_MES_TYPE_3_HEADER header; /*header */
503 unsigned int ordinal1;
504 };
505
506 union {
507 struct {
508 unsigned int event_type:6;
509 unsigned int reserved1:2;
510 enum mec_release_mem_event_index_enum event_index:4;
511 unsigned int tcl1_vol_action_ena:1;
512 unsigned int tc_vol_action_ena:1;
513 unsigned int reserved2:1;
514 unsigned int tc_wb_action_ena:1;
515 unsigned int tcl1_action_ena:1;
516 unsigned int tc_action_ena:1;
517 uint32_t reserved3:1;
518 uint32_t tc_nc_action_ena:1;
519 uint32_t tc_wc_action_ena:1;
520 uint32_t tc_md_action_ena:1;
521 uint32_t reserved4:3;
522 enum mec_release_mem_cache_policy_enum cache_policy:2;
523 uint32_t reserved5:2;
524 enum mec_release_mem_pq_exe_status_enum pq_exe_status:1;
525 uint32_t reserved6:2;
526 } bitfields2;
527 unsigned int ordinal2;
528 };
529
530 union {
531 struct {
532 uint32_t reserved7:16;
533 enum mec_release_mem_dst_sel_enum dst_sel:2;
534 uint32_t reserved8:6;
535 enum mec_release_mem_int_sel_enum int_sel:3;
536 uint32_t reserved9:2;
537 enum mec_release_mem_data_sel_enum data_sel:3;
538 } bitfields3;
539 unsigned int ordinal3;
540 };
541
542 union {
543 struct {
544 uint32_t reserved10:2;
545 unsigned int address_lo_32b:30;
546 } bitfields4;
547 struct {
548 uint32_t reserved11:3;
549 uint32_t address_lo_64b:29;
550 } bitfields4b;
551 uint32_t reserved12;
552 unsigned int ordinal4;
553 };
554
555 union {
556 uint32_t address_hi;
557 uint32_t reserved13;
558 uint32_t ordinal5;
559 };
560
561 union {
562 uint32_t data_lo;
563 uint32_t cmp_data_lo;
564 struct {
565 uint32_t dw_offset:16;
566 uint32_t num_dwords:16;
567 } bitfields6c;
568 uint32_t reserved14;
569 uint32_t ordinal6;
570 };
571
572 union {
573 uint32_t data_hi;
574 uint32_t cmp_data_hi;
575 uint32_t reserved15;
576 uint32_t reserved16;
577 uint32_t ordinal7;
578 };
579
580 uint32_t int_ctxid;
581
582};
583
584#endif
585
586enum {
587 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
588};
589#endif
590
591

source code of linux/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h