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1/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2/*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#ifndef KFD_PM4_HEADERS_DIQ_H_
26#define KFD_PM4_HEADERS_DIQ_H_
27
28/*--------------------_INDIRECT_BUFFER-------------------- */
29
30#ifndef _PM4__INDIRECT_BUFFER_DEFINED
31#define _PM4__INDIRECT_BUFFER_DEFINED
32enum _INDIRECT_BUFFER_cache_policy_enum {
33 cache_policy___indirect_buffer__lru = 0,
34 cache_policy___indirect_buffer__stream = 1,
35 cache_policy___indirect_buffer__bypass = 2
36};
37
38enum {
39 IT_INDIRECT_BUFFER_PASID = 0x5C
40};
41
42struct pm4__indirect_buffer_pasid {
43 union {
44 union PM4_MES_TYPE_3_HEADER header; /* header */
45 unsigned int ordinal1;
46 };
47
48 union {
49 struct {
50 unsigned int reserved1:2;
51 unsigned int ib_base_lo:30;
52 } bitfields2;
53 unsigned int ordinal2;
54 };
55
56 union {
57 struct {
58 unsigned int ib_base_hi:16;
59 unsigned int reserved2:16;
60 } bitfields3;
61 unsigned int ordinal3;
62 };
63
64 union {
65 unsigned int control;
66 unsigned int ordinal4;
67 };
68
69 union {
70 struct {
71 unsigned int pasid:10;
72 unsigned int reserved4:22;
73 } bitfields5;
74 unsigned int ordinal5;
75 };
76
77};
78
79#endif
80
81/*--------------------_RELEASE_MEM-------------------- */
82
83#ifndef _PM4__RELEASE_MEM_DEFINED
84#define _PM4__RELEASE_MEM_DEFINED
85enum _RELEASE_MEM_event_index_enum {
86 event_index___release_mem__end_of_pipe = 5,
87 event_index___release_mem__shader_done = 6
88};
89
90enum _RELEASE_MEM_cache_policy_enum {
91 cache_policy___release_mem__lru = 0,
92 cache_policy___release_mem__stream = 1,
93 cache_policy___release_mem__bypass = 2
94};
95
96enum _RELEASE_MEM_dst_sel_enum {
97 dst_sel___release_mem__memory_controller = 0,
98 dst_sel___release_mem__tc_l2 = 1,
99 dst_sel___release_mem__queue_write_pointer_register = 2,
100 dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3
101};
102
103enum _RELEASE_MEM_int_sel_enum {
104 int_sel___release_mem__none = 0,
105 int_sel___release_mem__send_interrupt_only = 1,
106 int_sel___release_mem__send_interrupt_after_write_confirm = 2,
107 int_sel___release_mem__send_data_after_write_confirm = 3
108};
109
110enum _RELEASE_MEM_data_sel_enum {
111 data_sel___release_mem__none = 0,
112 data_sel___release_mem__send_32_bit_low = 1,
113 data_sel___release_mem__send_64_bit_data = 2,
114 data_sel___release_mem__send_gpu_clock_counter = 3,
115 data_sel___release_mem__send_cp_perfcounter_hi_lo = 4,
116 data_sel___release_mem__store_gds_data_to_memory = 5
117};
118
119struct pm4__release_mem {
120 union {
121 union PM4_MES_TYPE_3_HEADER header; /*header */
122 unsigned int ordinal1;
123 };
124
125 union {
126 struct {
127 unsigned int event_type:6;
128 unsigned int reserved1:2;
129 enum _RELEASE_MEM_event_index_enum event_index:4;
130 unsigned int tcl1_vol_action_ena:1;
131 unsigned int tc_vol_action_ena:1;
132 unsigned int reserved2:1;
133 unsigned int tc_wb_action_ena:1;
134 unsigned int tcl1_action_ena:1;
135 unsigned int tc_action_ena:1;
136 unsigned int reserved3:6;
137 unsigned int atc:1;
138 enum _RELEASE_MEM_cache_policy_enum cache_policy:2;
139 unsigned int reserved4:5;
140 } bitfields2;
141 unsigned int ordinal2;
142 };
143
144 union {
145 struct {
146 unsigned int reserved5:16;
147 enum _RELEASE_MEM_dst_sel_enum dst_sel:2;
148 unsigned int reserved6:6;
149 enum _RELEASE_MEM_int_sel_enum int_sel:3;
150 unsigned int reserved7:2;
151 enum _RELEASE_MEM_data_sel_enum data_sel:3;
152 } bitfields3;
153 unsigned int ordinal3;
154 };
155
156 union {
157 struct {
158 unsigned int reserved8:2;
159 unsigned int address_lo_32b:30;
160 } bitfields4;
161 struct {
162 unsigned int reserved9:3;
163 unsigned int address_lo_64b:29;
164 } bitfields5;
165 unsigned int ordinal4;
166 };
167
168 unsigned int address_hi;
169
170 unsigned int data_lo;
171
172 unsigned int data_hi;
173
174};
175#endif
176
177
178/*--------------------_SET_CONFIG_REG-------------------- */
179
180#ifndef _PM4__SET_CONFIG_REG_DEFINED
181#define _PM4__SET_CONFIG_REG_DEFINED
182
183struct pm4__set_config_reg {
184 union {
185 union PM4_MES_TYPE_3_HEADER header; /*header */
186 unsigned int ordinal1;
187 };
188
189 union {
190 struct {
191 unsigned int reg_offset:16;
192 unsigned int reserved1:7;
193 unsigned int vmid_shift:5;
194 unsigned int insert_vmid:1;
195 unsigned int reserved2:3;
196 } bitfields2;
197 unsigned int ordinal2;
198 };
199
200 unsigned int reg_data[1]; /*1..N of these fields */
201
202};
203#endif
204
205/*--------------------_WAIT_REG_MEM-------------------- */
206
207#ifndef _PM4__WAIT_REG_MEM_DEFINED
208#define _PM4__WAIT_REG_MEM_DEFINED
209enum _WAIT_REG_MEM_function_enum {
210 function___wait_reg_mem__always_pass = 0,
211 function___wait_reg_mem__less_than_ref_value = 1,
212 function___wait_reg_mem__less_than_equal_to_the_ref_value = 2,
213 function___wait_reg_mem__equal_to_the_reference_value = 3,
214 function___wait_reg_mem__not_equal_reference_value = 4,
215 function___wait_reg_mem__greater_than_or_equal_reference_value = 5,
216 function___wait_reg_mem__greater_than_reference_value = 6,
217 function___wait_reg_mem__reserved = 7
218};
219
220enum _WAIT_REG_MEM_mem_space_enum {
221 mem_space___wait_reg_mem__register_space = 0,
222 mem_space___wait_reg_mem__memory_space = 1
223};
224
225enum _WAIT_REG_MEM_operation_enum {
226 operation___wait_reg_mem__wait_reg_mem = 0,
227 operation___wait_reg_mem__wr_wait_wr_reg = 1
228};
229
230struct pm4__wait_reg_mem {
231 union {
232 union PM4_MES_TYPE_3_HEADER header; /*header */
233 unsigned int ordinal1;
234 };
235
236 union {
237 struct {
238 enum _WAIT_REG_MEM_function_enum function:3;
239 unsigned int reserved1:1;
240 enum _WAIT_REG_MEM_mem_space_enum mem_space:2;
241 enum _WAIT_REG_MEM_operation_enum operation:2;
242 unsigned int reserved2:24;
243 } bitfields2;
244 unsigned int ordinal2;
245 };
246
247 union {
248 struct {
249 unsigned int reserved3:2;
250 unsigned int memory_poll_addr_lo:30;
251 } bitfields3;
252 struct {
253 unsigned int register_poll_addr:16;
254 unsigned int reserved4:16;
255 } bitfields4;
256 struct {
257 unsigned int register_write_addr:16;
258 unsigned int reserved5:16;
259 } bitfields5;
260 unsigned int ordinal3;
261 };
262
263 union {
264 struct {
265 unsigned int poll_address_hi:16;
266 unsigned int reserved6:16;
267 } bitfields6;
268 struct {
269 unsigned int register_write_addr:16;
270 unsigned int reserved7:16;
271 } bitfields7;
272 unsigned int ordinal4;
273 };
274
275 unsigned int reference;
276
277 unsigned int mask;
278
279 union {
280 struct {
281 unsigned int poll_interval:16;
282 unsigned int reserved8:16;
283 } bitfields8;
284 unsigned int ordinal7;
285 };
286
287};
288#endif
289
290
291#endif /* KFD_PM4_HEADERS_DIQ_H_ */
292

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source code of linux/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h