1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <drm/drm_crtc.h>
27#include <drm/drm_vblank.h>
28
29#include "amdgpu.h"
30#include "amdgpu_dm.h"
31#include "dc.h"
32#include "amdgpu_securedisplay.h"
33
34static const char *const pipe_crc_sources[] = {
35 "none",
36 "crtc",
37 "crtc dither",
38 "dprx",
39 "dprx dither",
40 "auto",
41};
42
43static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
44{
45 if (!source || !strcmp(source, "none"))
46 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
47 if (!strcmp(source, "auto") || !strcmp(source, "crtc"))
48 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC;
49 if (!strcmp(source, "dprx"))
50 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX;
51 if (!strcmp(source, "crtc dither"))
52 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER;
53 if (!strcmp(source, "dprx dither"))
54 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER;
55
56 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
57}
58
59static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src)
60{
61 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
62 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER);
63}
64
65static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src)
66{
67 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) ||
68 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER);
69}
70
71static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src)
72{
73 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) ||
74 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) ||
75 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE);
76}
77
78const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
79 size_t *count)
80{
81 *count = ARRAY_SIZE(pipe_crc_sources);
82 return pipe_crc_sources;
83}
84
85#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
86static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc, struct dc_stream_state *stream)
87{
88 struct drm_device *drm_dev = crtc->dev;
89 struct amdgpu_display_manager *dm = &drm_to_adev(ddev: drm_dev)->dm;
90 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
91 bool was_activated;
92
93 spin_lock_irq(lock: &drm_dev->event_lock);
94 was_activated = acrtc->dm_irq_params.window_param.activated;
95 acrtc->dm_irq_params.window_param.x_start = 0;
96 acrtc->dm_irq_params.window_param.y_start = 0;
97 acrtc->dm_irq_params.window_param.x_end = 0;
98 acrtc->dm_irq_params.window_param.y_end = 0;
99 acrtc->dm_irq_params.window_param.activated = false;
100 acrtc->dm_irq_params.window_param.update_win = false;
101 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
102 spin_unlock_irq(lock: &drm_dev->event_lock);
103
104 /* Disable secure_display if it was enabled */
105 if (was_activated) {
106 /* stop ROI update on this crtc */
107 flush_work(work: &dm->secure_display_ctxs[crtc->index].notify_ta_work);
108 flush_work(work: &dm->secure_display_ctxs[crtc->index].forward_roi_work);
109 dc_stream_forward_crc_window(stream, NULL, is_stop: true);
110 }
111}
112
113static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work)
114{
115 struct secure_display_context *secure_display_ctx;
116 struct psp_context *psp;
117 struct ta_securedisplay_cmd *securedisplay_cmd;
118 struct drm_crtc *crtc;
119 struct dc_stream_state *stream;
120 uint8_t phy_inst;
121 int ret;
122
123 secure_display_ctx = container_of(work, struct secure_display_context, notify_ta_work);
124 crtc = secure_display_ctx->crtc;
125
126 if (!crtc)
127 return;
128
129 psp = &drm_to_adev(ddev: crtc->dev)->psp;
130
131 if (!psp->securedisplay_context.context.initialized) {
132 DRM_DEBUG_DRIVER("Secure Display fails to notify PSP TA\n");
133 return;
134 }
135
136 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream;
137 phy_inst = stream->link->link_enc_hw_inst;
138
139 /* need lock for multiple crtcs to use the command buffer */
140 mutex_lock(&psp->securedisplay_context.mutex);
141
142 psp_prep_securedisplay_cmd_buf(psp, cmd: &securedisplay_cmd,
143 command_id: TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
144
145 securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst;
146
147 /* PSP TA is expected to finish data transmission over I2C within current frame,
148 * even there are up to 4 crtcs request to send in this frame.
149 */
150 ret = psp_securedisplay_invoke(psp, ta_cmd_id: TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
151
152 if (!ret) {
153 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS)
154 psp_securedisplay_parse_resp_status(psp, status: securedisplay_cmd->status);
155 }
156
157 mutex_unlock(lock: &psp->securedisplay_context.mutex);
158}
159
160static void
161amdgpu_dm_forward_crc_window(struct work_struct *work)
162{
163 struct secure_display_context *secure_display_ctx;
164 struct amdgpu_display_manager *dm;
165 struct drm_crtc *crtc;
166 struct dc_stream_state *stream;
167
168 secure_display_ctx = container_of(work, struct secure_display_context, forward_roi_work);
169 crtc = secure_display_ctx->crtc;
170
171 if (!crtc)
172 return;
173
174 dm = &drm_to_adev(ddev: crtc->dev)->dm;
175 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream;
176
177 mutex_lock(&dm->dc_lock);
178 dc_stream_forward_crc_window(stream, rect: &secure_display_ctx->rect, is_stop: false);
179 mutex_unlock(lock: &dm->dc_lock);
180}
181
182bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc)
183{
184 struct drm_device *drm_dev = crtc->dev;
185 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
186 bool ret = false;
187
188 spin_lock_irq(lock: &drm_dev->event_lock);
189 ret = acrtc->dm_irq_params.window_param.activated;
190 spin_unlock_irq(lock: &drm_dev->event_lock);
191
192 return ret;
193}
194#endif
195
196int
197amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
198 size_t *values_cnt)
199{
200 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(source: src_name);
201
202 if (source < 0) {
203 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
204 src_name, crtc->index);
205 return -EINVAL;
206 }
207
208 *values_cnt = 3;
209 return 0;
210}
211
212int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
213 struct dm_crtc_state *dm_crtc_state,
214 enum amdgpu_dm_pipe_crc_source source)
215{
216 struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
217 struct dc_stream_state *stream_state = dm_crtc_state->stream;
218 bool enable = amdgpu_dm_is_valid_crc_source(source);
219 int ret = 0;
220
221 /* Configuration will be deferred to stream enable. */
222 if (!stream_state)
223 return -EINVAL;
224
225 mutex_lock(&adev->dm.dc_lock);
226
227 /* Enable or disable CRTC CRC generation */
228 if (dm_is_crc_source_crtc(src: source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
229 if (!dc_stream_configure_crc(dc: stream_state->ctx->dc,
230 stream: stream_state, NULL, enable, continuous: enable)) {
231 ret = -EINVAL;
232 goto unlock;
233 }
234 }
235
236 /* Configure dithering */
237 if (!dm_need_crc_dither(src: source)) {
238 dc_stream_set_dither_option(stream: stream_state, option: DITHER_OPTION_TRUN8);
239 dc_stream_set_dyn_expansion(dc: stream_state->ctx->dc, stream: stream_state,
240 option: DYN_EXPANSION_DISABLE);
241 } else {
242 dc_stream_set_dither_option(stream: stream_state,
243 option: DITHER_OPTION_DEFAULT);
244 dc_stream_set_dyn_expansion(dc: stream_state->ctx->dc, stream: stream_state,
245 option: DYN_EXPANSION_AUTO);
246 }
247
248unlock:
249 mutex_unlock(lock: &adev->dm.dc_lock);
250
251 return ret;
252}
253
254int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
255{
256 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(source: src_name);
257 enum amdgpu_dm_pipe_crc_source cur_crc_src;
258 struct drm_crtc_commit *commit;
259 struct dm_crtc_state *crtc_state;
260 struct drm_device *drm_dev = crtc->dev;
261 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
262 struct drm_dp_aux *aux = NULL;
263 bool enable = false;
264 bool enabled = false;
265 int ret = 0;
266
267 if (source < 0) {
268 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
269 src_name, crtc->index);
270 return -EINVAL;
271 }
272
273 ret = drm_modeset_lock(lock: &crtc->mutex, NULL);
274 if (ret)
275 return ret;
276
277 spin_lock(lock: &crtc->commit_lock);
278 commit = list_first_entry_or_null(&crtc->commit_list,
279 struct drm_crtc_commit, commit_entry);
280 if (commit)
281 drm_crtc_commit_get(commit);
282 spin_unlock(lock: &crtc->commit_lock);
283
284 if (commit) {
285 /*
286 * Need to wait for all outstanding programming to complete
287 * in commit tail since it can modify CRC related fields and
288 * hardware state. Since we're holding the CRTC lock we're
289 * guaranteed that no other commit work can be queued off
290 * before we modify the state below.
291 */
292 ret = wait_for_completion_interruptible_timeout(
293 x: &commit->hw_done, timeout: 10 * HZ);
294 if (ret)
295 goto cleanup;
296 }
297
298 enable = amdgpu_dm_is_valid_crc_source(source);
299 crtc_state = to_dm_crtc_state(crtc->state);
300 spin_lock_irq(lock: &drm_dev->event_lock);
301 cur_crc_src = acrtc->dm_irq_params.crc_src;
302 spin_unlock_irq(lock: &drm_dev->event_lock);
303
304 /*
305 * USER REQ SRC | CURRENT SRC | BEHAVIOR
306 * -----------------------------
307 * None | None | Do nothing
308 * None | CRTC | Disable CRTC CRC, set default to dither
309 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither
310 * None | CRTC DITHER | Disable CRTC CRC
311 * None | DPRX DITHER | Disable DPRX CRC, need 'aux'
312 * CRTC | XXXX | Enable CRTC CRC, no dither
313 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither
314 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither
315 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither
316 */
317 if (dm_is_crc_source_dprx(src: source) ||
318 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
319 dm_is_crc_source_dprx(src: cur_crc_src))) {
320 struct amdgpu_dm_connector *aconn = NULL;
321 struct drm_connector *connector;
322 struct drm_connector_list_iter conn_iter;
323
324 drm_connector_list_iter_begin(dev: crtc->dev, iter: &conn_iter);
325 drm_for_each_connector_iter(connector, &conn_iter) {
326 if (!connector->state || connector->state->crtc != crtc)
327 continue;
328
329 aconn = to_amdgpu_dm_connector(connector);
330 break;
331 }
332 drm_connector_list_iter_end(iter: &conn_iter);
333
334 if (!aconn) {
335 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
336 ret = -EINVAL;
337 goto cleanup;
338 }
339
340 aux = (aconn->mst_output_port) ? &aconn->mst_output_port->aux : &aconn->dm_dp_aux.aux;
341
342 if (!aux) {
343 DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
344 ret = -EINVAL;
345 goto cleanup;
346 }
347
348 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
349 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) {
350 DRM_DEBUG_DRIVER("No DP connector available for CRC source\n");
351 ret = -EINVAL;
352 goto cleanup;
353 }
354
355 }
356
357#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
358 /* Reset secure_display when we change crc source from debugfs */
359 amdgpu_dm_set_crc_window_default(crtc, stream: crtc_state->stream);
360#endif
361
362 if (amdgpu_dm_crtc_configure_crc_source(crtc, dm_crtc_state: crtc_state, source)) {
363 ret = -EINVAL;
364 goto cleanup;
365 }
366
367 /*
368 * Reading the CRC requires the vblank interrupt handler to be
369 * enabled. Keep a reference until CRC capture stops.
370 */
371 enabled = amdgpu_dm_is_valid_crc_source(source: cur_crc_src);
372 if (!enabled && enable) {
373 ret = drm_crtc_vblank_get(crtc);
374 if (ret)
375 goto cleanup;
376
377 if (dm_is_crc_source_dprx(src: source)) {
378 if (drm_dp_start_crc(aux, crtc)) {
379 DRM_DEBUG_DRIVER("dp start crc failed\n");
380 ret = -EINVAL;
381 goto cleanup;
382 }
383 }
384 } else if (enabled && !enable) {
385 drm_crtc_vblank_put(crtc);
386 if (dm_is_crc_source_dprx(src: source)) {
387 if (drm_dp_stop_crc(aux)) {
388 DRM_DEBUG_DRIVER("dp stop crc failed\n");
389 ret = -EINVAL;
390 goto cleanup;
391 }
392 }
393 }
394
395 spin_lock_irq(lock: &drm_dev->event_lock);
396 acrtc->dm_irq_params.crc_src = source;
397 spin_unlock_irq(lock: &drm_dev->event_lock);
398
399 /* Reset crc_skipped on dm state */
400 crtc_state->crc_skip_count = 0;
401
402cleanup:
403 if (commit)
404 drm_crtc_commit_put(commit);
405
406 drm_modeset_unlock(lock: &crtc->mutex);
407
408 return ret;
409}
410
411/**
412 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC.
413 * @crtc: DRM CRTC object.
414 *
415 * This function should be called at the end of a vblank, when the fb has been
416 * fully processed through the pipe.
417 */
418void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
419{
420 struct dm_crtc_state *crtc_state;
421 struct dc_stream_state *stream_state;
422 struct drm_device *drm_dev = NULL;
423 enum amdgpu_dm_pipe_crc_source cur_crc_src;
424 struct amdgpu_crtc *acrtc = NULL;
425 uint32_t crcs[3];
426 unsigned long flags;
427
428 if (crtc == NULL)
429 return;
430
431 crtc_state = to_dm_crtc_state(crtc->state);
432 stream_state = crtc_state->stream;
433 acrtc = to_amdgpu_crtc(crtc);
434 drm_dev = crtc->dev;
435
436 spin_lock_irqsave(&drm_dev->event_lock, flags);
437 cur_crc_src = acrtc->dm_irq_params.crc_src;
438 spin_unlock_irqrestore(lock: &drm_dev->event_lock, flags);
439
440 /* Early return if CRC capture is not enabled. */
441 if (!amdgpu_dm_is_valid_crc_source(source: cur_crc_src))
442 return;
443
444 /*
445 * Since flipping and crc enablement happen asynchronously, we - more
446 * often than not - will be returning an 'uncooked' crc on first frame.
447 * Probably because hw isn't ready yet. For added security, skip the
448 * first two CRC values.
449 */
450 if (crtc_state->crc_skip_count < 2) {
451 crtc_state->crc_skip_count += 1;
452 return;
453 }
454
455 if (dm_is_crc_source_crtc(src: cur_crc_src)) {
456 if (!dc_stream_get_crc(dc: stream_state->ctx->dc, stream: stream_state,
457 r_cr: &crcs[0], g_y: &crcs[1], b_cb: &crcs[2]))
458 return;
459
460 drm_crtc_add_crc_entry(crtc, has_frame: true,
461 frame: drm_crtc_accurate_vblank_count(crtc), crcs);
462 }
463}
464
465#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
466void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)
467{
468 struct drm_device *drm_dev = NULL;
469 enum amdgpu_dm_pipe_crc_source cur_crc_src;
470 struct amdgpu_crtc *acrtc = NULL;
471 struct amdgpu_device *adev = NULL;
472 struct secure_display_context *secure_display_ctx = NULL;
473 unsigned long flags1;
474
475 if (crtc == NULL)
476 return;
477
478 acrtc = to_amdgpu_crtc(crtc);
479 adev = drm_to_adev(ddev: crtc->dev);
480 drm_dev = crtc->dev;
481
482 spin_lock_irqsave(&drm_dev->event_lock, flags1);
483 cur_crc_src = acrtc->dm_irq_params.crc_src;
484
485 /* Early return if CRC capture is not enabled. */
486 if (!amdgpu_dm_is_valid_crc_source(source: cur_crc_src) ||
487 !dm_is_crc_source_crtc(src: cur_crc_src))
488 goto cleanup;
489
490 if (!acrtc->dm_irq_params.window_param.activated)
491 goto cleanup;
492
493 if (acrtc->dm_irq_params.window_param.skip_frame_cnt) {
494 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1;
495 goto cleanup;
496 }
497
498 secure_display_ctx = &adev->dm.secure_display_ctxs[acrtc->crtc_id];
499 if (WARN_ON(secure_display_ctx->crtc != crtc)) {
500 /* We have set the crtc when creating secure_display_context,
501 * don't expect it to be changed here.
502 */
503 secure_display_ctx->crtc = crtc;
504 }
505
506 if (acrtc->dm_irq_params.window_param.update_win) {
507 /* prepare work for dmub to update ROI */
508 secure_display_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start;
509 secure_display_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start;
510 secure_display_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end -
511 acrtc->dm_irq_params.window_param.x_start;
512 secure_display_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end -
513 acrtc->dm_irq_params.window_param.y_start;
514 schedule_work(work: &secure_display_ctx->forward_roi_work);
515
516 acrtc->dm_irq_params.window_param.update_win = false;
517
518 /* Statically skip 1 frame, because we may need to wait below things
519 * before sending ROI to dmub:
520 * 1. We defer the work by using system workqueue.
521 * 2. We may need to wait for dc_lock before accessing dmub.
522 */
523 acrtc->dm_irq_params.window_param.skip_frame_cnt = 1;
524
525 } else {
526 /* prepare work for psp to read ROI/CRC and send to I2C */
527 schedule_work(work: &secure_display_ctx->notify_ta_work);
528 }
529
530cleanup:
531 spin_unlock_irqrestore(lock: &drm_dev->event_lock, flags: flags1);
532}
533
534struct secure_display_context *
535amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev)
536{
537 struct secure_display_context *secure_display_ctxs = NULL;
538 int i;
539
540 secure_display_ctxs = kcalloc(n: adev->mode_info.num_crtc,
541 size: sizeof(struct secure_display_context),
542 GFP_KERNEL);
543
544 if (!secure_display_ctxs)
545 return NULL;
546
547 for (i = 0; i < adev->mode_info.num_crtc; i++) {
548 INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window);
549 INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read);
550 secure_display_ctxs[i].crtc = &adev->mode_info.crtcs[i]->base;
551 }
552
553 return secure_display_ctxs;
554}
555#endif
556

source code of linux/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c