| 1 | // SPDX-License-Identifier: MIT |
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| 2 | /* |
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| 3 | * Copyright 2022 Advanced Micro Devices, Inc. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be included in |
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| 13 | * all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: AMD |
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| 24 | * |
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| 25 | */ |
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| 26 | |
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| 27 | #ifndef __AMDGPU_DM_PLANE_H__ |
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| 28 | #define __AMDGPU_DM_PLANE_H__ |
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| 29 | |
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| 30 | #include "dc.h" |
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| 31 | |
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| 32 | void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, |
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| 33 | struct drm_plane_state *old_plane_state); |
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| 34 | |
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| 35 | int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, |
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| 36 | const struct drm_plane_state *state, |
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| 37 | struct dc_scaling_info *scaling_info); |
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| 38 | |
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| 39 | int amdgpu_dm_plane_helper_check_state(struct drm_plane_state *state, |
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| 40 | struct drm_crtc_state *new_crtc_state); |
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| 41 | |
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| 42 | int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, |
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| 43 | const struct amdgpu_framebuffer *afb, |
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| 44 | const enum surface_pixel_format format, |
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| 45 | const enum dc_rotation_angle rotation, |
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| 46 | const uint64_t tiling_flags, |
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| 47 | union dc_tiling_info *tiling_info, |
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| 48 | struct plane_size *plane_size, |
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| 49 | struct dc_plane_dcc_param *dcc, |
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| 50 | struct dc_plane_address *address, |
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| 51 | bool tmz_surface, |
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| 52 | bool force_disable_dcc); |
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| 53 | |
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| 54 | int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, |
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| 55 | struct drm_plane *plane, |
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| 56 | unsigned long possible_crtcs, |
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| 57 | const struct dc_plane_cap *plane_cap); |
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| 58 | |
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| 59 | const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd); |
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| 60 | |
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| 61 | void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, |
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| 62 | bool *per_pixel_alpha, bool *pre_multiplied_alpha, |
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| 63 | bool *global_alpha, int *global_alpha_value); |
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| 64 | |
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| 65 | bool amdgpu_dm_plane_is_video_format(uint32_t format); |
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| 66 | #endif |
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| 67 | |
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