1 | /* |
2 | * Copyright 2021 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include "amdgpu_dm_psr.h" |
27 | #include "dc_dmub_srv.h" |
28 | #include "dc.h" |
29 | #include "dm_helpers.h" |
30 | #include "amdgpu_dm.h" |
31 | #include "modules/power/power_helpers.h" |
32 | |
33 | static bool link_supports_psrsu(struct dc_link *link) |
34 | { |
35 | struct dc *dc = link->ctx->dc; |
36 | |
37 | if (!dc->caps.dmcub_support) |
38 | return false; |
39 | |
40 | if (dc->ctx->dce_version < DCN_VERSION_3_1) |
41 | return false; |
42 | |
43 | if (!is_psr_su_specific_panel(link)) |
44 | return false; |
45 | |
46 | if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP || |
47 | !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) |
48 | return false; |
49 | |
50 | if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED && |
51 | !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap) |
52 | return false; |
53 | |
54 | return dc_dmub_check_min_version(srv: dc->ctx->dmub_srv->dmub); |
55 | } |
56 | |
57 | /* |
58 | * amdgpu_dm_set_psr_caps() - set link psr capabilities |
59 | * @link: link |
60 | * |
61 | */ |
62 | void amdgpu_dm_set_psr_caps(struct dc_link *link) |
63 | { |
64 | if (!(link->connector_signal & SIGNAL_TYPE_EDP)) { |
65 | link->psr_settings.psr_feature_enabled = false; |
66 | return; |
67 | } |
68 | |
69 | if (link->type == dc_connection_none) { |
70 | link->psr_settings.psr_feature_enabled = false; |
71 | return; |
72 | } |
73 | |
74 | if (link->dpcd_caps.psr_info.psr_version == 0) { |
75 | link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; |
76 | link->psr_settings.psr_feature_enabled = false; |
77 | |
78 | } else { |
79 | if (link_supports_psrsu(link)) |
80 | link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; |
81 | else |
82 | link->psr_settings.psr_version = DC_PSR_VERSION_1; |
83 | |
84 | link->psr_settings.psr_feature_enabled = true; |
85 | } |
86 | |
87 | DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n" , |
88 | link->psr_settings.psr_feature_enabled, |
89 | link->psr_settings.psr_version, |
90 | link->dpcd_caps.psr_info.psr_version, |
91 | link->dpcd_caps.psr_info.psr_dpcd_caps.raw, |
92 | link->dpcd_caps.psr_info.psr2_su_y_granularity_cap); |
93 | |
94 | } |
95 | |
96 | /* |
97 | * amdgpu_dm_link_setup_psr() - configure psr link |
98 | * @stream: stream state |
99 | * |
100 | * Return: true if success |
101 | */ |
102 | bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) |
103 | { |
104 | struct dc_link *link = NULL; |
105 | struct psr_config psr_config = {0}; |
106 | struct psr_context psr_context = {0}; |
107 | struct dc *dc = NULL; |
108 | bool ret = false; |
109 | |
110 | if (stream == NULL) |
111 | return false; |
112 | |
113 | link = stream->link; |
114 | dc = link->ctx->dc; |
115 | |
116 | if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) { |
117 | mod_power_calc_psr_configs(psr_config: &psr_config, link, stream); |
118 | |
119 | /* linux DM specific updating for psr config fields */ |
120 | psr_config.allow_smu_optimizations = |
121 | (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) && |
122 | mod_power_only_edp(context: dc->current_state, stream); |
123 | psr_config.allow_multi_disp_optimizations = |
124 | (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); |
125 | |
126 | if (!psr_su_set_dsc_slice_height(dc, link, stream, config: &psr_config)) |
127 | return false; |
128 | |
129 | ret = dc_link_setup_psr(dc_link: link, stream, psr_config: &psr_config, psr_context: &psr_context); |
130 | |
131 | } |
132 | DRM_DEBUG_DRIVER("PSR link: %d\n" , link->psr_settings.psr_feature_enabled); |
133 | |
134 | return ret; |
135 | } |
136 | |
137 | /* |
138 | * amdgpu_dm_psr_enable() - enable psr f/w |
139 | * @stream: stream state |
140 | * |
141 | * Return: true if success |
142 | */ |
143 | bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) |
144 | { |
145 | struct dc_link *link = stream->link; |
146 | unsigned int vsync_rate_hz = 0; |
147 | struct dc_static_screen_params params = {0}; |
148 | /* Calculate number of static frames before generating interrupt to |
149 | * enter PSR. |
150 | */ |
151 | // Init fail safe of 2 frames static |
152 | unsigned int num_frames_static = 2; |
153 | unsigned int power_opt = 0; |
154 | bool psr_enable = true; |
155 | |
156 | DRM_DEBUG_DRIVER("Enabling psr...\n" ); |
157 | |
158 | vsync_rate_hz = div64_u64(dividend: div64_u64(dividend: ( |
159 | stream->timing.pix_clk_100hz * 100), |
160 | divisor: stream->timing.v_total), |
161 | divisor: stream->timing.h_total); |
162 | |
163 | /* Round up |
164 | * Calculate number of frames such that at least 30 ms of time has |
165 | * passed. |
166 | */ |
167 | if (vsync_rate_hz != 0) { |
168 | unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; |
169 | |
170 | num_frames_static = (30000 / frame_time_microsec) + 1; |
171 | } |
172 | |
173 | params.triggers.cursor_update = true; |
174 | params.triggers.overlay_update = true; |
175 | params.triggers.surface_update = true; |
176 | params.num_frames = num_frames_static; |
177 | |
178 | dc_stream_set_static_screen_params(dc: link->ctx->dc, |
179 | stream: &stream, num_streams: 1, |
180 | params: ¶ms); |
181 | |
182 | /* |
183 | * Only enable static-screen optimizations for PSR1. For PSR SU, this |
184 | * causes vstartup interrupt issues, used by amdgpu_dm to send vblank |
185 | * events. |
186 | */ |
187 | if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) |
188 | power_opt |= psr_power_opt_z10_static_screen; |
189 | |
190 | return dc_link_set_psr_allow_active(dc_link: link, enable: &psr_enable, wait: false, force_static: false, power_opts: &power_opt); |
191 | } |
192 | |
193 | /* |
194 | * amdgpu_dm_psr_disable() - disable psr f/w |
195 | * @stream: stream state |
196 | * |
197 | * Return: true if success |
198 | */ |
199 | bool amdgpu_dm_psr_disable(struct dc_stream_state *stream) |
200 | { |
201 | unsigned int power_opt = 0; |
202 | bool psr_enable = false; |
203 | |
204 | DRM_DEBUG_DRIVER("Disabling psr...\n" ); |
205 | |
206 | return dc_link_set_psr_allow_active(dc_link: stream->link, enable: &psr_enable, wait: true, force_static: false, power_opts: &power_opt); |
207 | } |
208 | |
209 | /* |
210 | * amdgpu_dm_psr_disable() - disable psr f/w |
211 | * if psr is enabled on any stream |
212 | * |
213 | * Return: true if success |
214 | */ |
215 | bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) |
216 | { |
217 | DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n" ); |
218 | return dc_set_psr_allow_active(dc: dm->dc, enable: false); |
219 | } |
220 | |
221 | |