1 | /* |
2 | * Copyright 2012-2023 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef DC_INTERFACE_H_ |
27 | #define DC_INTERFACE_H_ |
28 | |
29 | #include "dc_types.h" |
30 | #include "grph_object_defs.h" |
31 | #include "logger_types.h" |
32 | #include "hdcp_msg_types.h" |
33 | #include "gpio_types.h" |
34 | #include "link_service_types.h" |
35 | #include "grph_object_ctrl_defs.h" |
36 | #include <inc/hw/opp.h> |
37 | |
38 | #include "hwss/hw_sequencer.h" |
39 | #include "inc/compressor.h" |
40 | #include "inc/hw/dmcu.h" |
41 | #include "dml/display_mode_lib.h" |
42 | |
43 | #include "dml2/dml2_wrapper.h" |
44 | |
45 | struct abm_save_restore; |
46 | |
47 | /* forward declaration */ |
48 | struct aux_payload; |
49 | struct set_config_cmd_payload; |
50 | struct dmub_notification; |
51 | |
52 | #define DC_VER "3.2.256" |
53 | |
54 | #define MAX_SURFACES 3 |
55 | #define MAX_PLANES 6 |
56 | #define MAX_STREAMS 6 |
57 | #define MIN_VIEWPORT_SIZE 12 |
58 | #define MAX_NUM_EDP 2 |
59 | |
60 | /* Display Core Interfaces */ |
61 | struct dc_versions { |
62 | const char *dc_ver; |
63 | struct dmcu_version dmcu_version; |
64 | }; |
65 | |
66 | enum dp_protocol_version { |
67 | DP_VERSION_1_4 = 0, |
68 | DP_VERSION_2_1, |
69 | DP_VERSION_UNKNOWN, |
70 | }; |
71 | |
72 | enum dc_plane_type { |
73 | DC_PLANE_TYPE_INVALID, |
74 | DC_PLANE_TYPE_DCE_RGB, |
75 | DC_PLANE_TYPE_DCE_UNDERLAY, |
76 | DC_PLANE_TYPE_DCN_UNIVERSAL, |
77 | }; |
78 | |
79 | // Sizes defined as multiples of 64KB |
80 | enum det_size { |
81 | DET_SIZE_DEFAULT = 0, |
82 | DET_SIZE_192KB = 3, |
83 | DET_SIZE_256KB = 4, |
84 | DET_SIZE_320KB = 5, |
85 | DET_SIZE_384KB = 6 |
86 | }; |
87 | |
88 | |
89 | struct dc_plane_cap { |
90 | enum dc_plane_type type; |
91 | uint32_t per_pixel_alpha : 1; |
92 | struct { |
93 | uint32_t argb8888 : 1; |
94 | uint32_t nv12 : 1; |
95 | uint32_t fp16 : 1; |
96 | uint32_t p010 : 1; |
97 | uint32_t ayuv : 1; |
98 | } pixel_format_support; |
99 | // max upscaling factor x1000 |
100 | // upscaling factors are always >= 1 |
101 | // for example, 1080p -> 8K is 4.0, or 4000 raw value |
102 | struct { |
103 | uint32_t argb8888; |
104 | uint32_t nv12; |
105 | uint32_t fp16; |
106 | } max_upscale_factor; |
107 | // max downscale factor x1000 |
108 | // downscale factors are always <= 1 |
109 | // for example, 8K -> 1080p is 0.25, or 250 raw value |
110 | struct { |
111 | uint32_t argb8888; |
112 | uint32_t nv12; |
113 | uint32_t fp16; |
114 | } max_downscale_factor; |
115 | // minimal width/height |
116 | uint32_t min_width; |
117 | uint32_t min_height; |
118 | }; |
119 | |
120 | /** |
121 | * DOC: color-management-caps |
122 | * |
123 | * **Color management caps (DPP and MPC)** |
124 | * |
125 | * Modules/color calculates various color operations which are translated to |
126 | * abstracted HW. DCE 5-12 had almost no important changes, but starting with |
127 | * DCN1, every new generation comes with fairly major differences in color |
128 | * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can |
129 | * decide mapping to HW block based on logical capabilities. |
130 | */ |
131 | |
132 | /** |
133 | * struct rom_curve_caps - predefined transfer function caps for degamma and regamma |
134 | * @srgb: RGB color space transfer func |
135 | * @bt2020: BT.2020 transfer func |
136 | * @gamma2_2: standard gamma |
137 | * @pq: perceptual quantizer transfer function |
138 | * @hlg: hybrid log–gamma transfer function |
139 | */ |
140 | struct rom_curve_caps { |
141 | uint16_t srgb : 1; |
142 | uint16_t bt2020 : 1; |
143 | uint16_t gamma2_2 : 1; |
144 | uint16_t pq : 1; |
145 | uint16_t hlg : 1; |
146 | }; |
147 | |
148 | /** |
149 | * struct dpp_color_caps - color pipeline capabilities for display pipe and |
150 | * plane blocks |
151 | * |
152 | * @dcn_arch: all DCE generations treated the same |
153 | * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, |
154 | * just plain 256-entry lookup |
155 | * @icsc: input color space conversion |
156 | * @dgam_ram: programmable degamma LUT |
157 | * @post_csc: post color space conversion, before gamut remap |
158 | * @gamma_corr: degamma correction |
159 | * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared |
160 | * with MPC by setting mpc:shared_3d_lut flag |
161 | * @ogam_ram: programmable out/blend gamma LUT |
162 | * @ocsc: output color space conversion |
163 | * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes |
164 | * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT |
165 | * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT |
166 | * |
167 | * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) |
168 | */ |
169 | struct dpp_color_caps { |
170 | uint16_t dcn_arch : 1; |
171 | uint16_t input_lut_shared : 1; |
172 | uint16_t icsc : 1; |
173 | uint16_t dgam_ram : 1; |
174 | uint16_t post_csc : 1; |
175 | uint16_t gamma_corr : 1; |
176 | uint16_t hw_3d_lut : 1; |
177 | uint16_t ogam_ram : 1; |
178 | uint16_t ocsc : 1; |
179 | uint16_t dgam_rom_for_yuv : 1; |
180 | struct rom_curve_caps dgam_rom_caps; |
181 | struct rom_curve_caps ogam_rom_caps; |
182 | }; |
183 | |
184 | /** |
185 | * struct mpc_color_caps - color pipeline capabilities for multiple pipe and |
186 | * plane combined blocks |
187 | * |
188 | * @gamut_remap: color transformation matrix |
189 | * @ogam_ram: programmable out gamma LUT |
190 | * @ocsc: output color space conversion matrix |
191 | * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT |
192 | * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single |
193 | * instance |
194 | * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT |
195 | */ |
196 | struct mpc_color_caps { |
197 | uint16_t gamut_remap : 1; |
198 | uint16_t ogam_ram : 1; |
199 | uint16_t ocsc : 1; |
200 | uint16_t num_3dluts : 3; |
201 | uint16_t shared_3d_lut:1; |
202 | struct rom_curve_caps ogam_rom_caps; |
203 | }; |
204 | |
205 | /** |
206 | * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks |
207 | * @dpp: color pipes caps for DPP |
208 | * @mpc: color pipes caps for MPC |
209 | */ |
210 | struct dc_color_caps { |
211 | struct dpp_color_caps dpp; |
212 | struct mpc_color_caps mpc; |
213 | }; |
214 | |
215 | struct dc_dmub_caps { |
216 | bool psr; |
217 | bool mclk_sw; |
218 | bool subvp_psr; |
219 | bool gecc_enable; |
220 | }; |
221 | |
222 | struct dc_caps { |
223 | uint32_t max_streams; |
224 | uint32_t max_links; |
225 | uint32_t max_audios; |
226 | uint32_t max_slave_planes; |
227 | uint32_t max_slave_yuv_planes; |
228 | uint32_t max_slave_rgb_planes; |
229 | uint32_t max_planes; |
230 | uint32_t max_downscale_ratio; |
231 | uint32_t i2c_speed_in_khz; |
232 | uint32_t i2c_speed_in_khz_hdcp; |
233 | uint32_t dmdata_alloc_size; |
234 | unsigned int max_cursor_size; |
235 | unsigned int max_video_width; |
236 | /* |
237 | * max video plane width that can be safely assumed to be always |
238 | * supported by single DPP pipe. |
239 | */ |
240 | unsigned int max_optimizable_video_width; |
241 | unsigned int min_horizontal_blanking_period; |
242 | int linear_pitch_alignment; |
243 | bool dcc_const_color; |
244 | bool dynamic_audio; |
245 | bool is_apu; |
246 | bool dual_link_dvi; |
247 | bool post_blend_color_processing; |
248 | bool force_dp_tps4_for_cp2520; |
249 | bool disable_dp_clk_share; |
250 | bool psp_setup_panel_mode; |
251 | bool extended_aux_timeout_support; |
252 | bool dmcub_support; |
253 | bool zstate_support; |
254 | bool ips_support; |
255 | uint32_t num_of_internal_disp; |
256 | enum dp_protocol_version max_dp_protocol_version; |
257 | unsigned int mall_size_per_mem_channel; |
258 | unsigned int mall_size_total; |
259 | unsigned int cursor_cache_size; |
260 | struct dc_plane_cap planes[MAX_PLANES]; |
261 | struct dc_color_caps color; |
262 | struct dc_dmub_caps dmub_caps; |
263 | bool dp_hpo; |
264 | bool dp_hdmi21_pcon_support; |
265 | bool edp_dsc_support; |
266 | bool vbios_lttpr_aware; |
267 | bool vbios_lttpr_enable; |
268 | uint32_t max_otg_num; |
269 | uint32_t max_cab_allocation_bytes; |
270 | uint32_t cache_line_size; |
271 | uint32_t cache_num_ways; |
272 | uint16_t subvp_fw_processing_delay_us; |
273 | uint8_t subvp_drr_max_vblank_margin_us; |
274 | uint16_t subvp_prefetch_end_to_mall_start_us; |
275 | uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height |
276 | uint16_t subvp_pstate_allow_width_us; |
277 | uint16_t subvp_vertical_int_margin_us; |
278 | bool seamless_odm; |
279 | uint32_t max_v_total; |
280 | uint32_t max_disp_clock_khz_at_vmin; |
281 | uint8_t subvp_drr_vblank_start_margin_us; |
282 | }; |
283 | |
284 | struct dc_bug_wa { |
285 | bool no_connect_phy_config; |
286 | bool dedcn20_305_wa; |
287 | bool skip_clock_update; |
288 | bool lt_early_cr_pattern; |
289 | struct { |
290 | uint8_t uclk : 1; |
291 | uint8_t fclk : 1; |
292 | uint8_t dcfclk : 1; |
293 | uint8_t dcfclk_ds: 1; |
294 | } clock_update_disable_mask; |
295 | }; |
296 | struct dc_dcc_surface_param { |
297 | struct dc_size surface_size; |
298 | enum surface_pixel_format format; |
299 | enum swizzle_mode_values swizzle_mode; |
300 | enum dc_scan_direction scan; |
301 | }; |
302 | |
303 | struct dc_dcc_setting { |
304 | unsigned int max_compressed_blk_size; |
305 | unsigned int max_uncompressed_blk_size; |
306 | bool independent_64b_blks; |
307 | //These bitfields to be used starting with DCN |
308 | struct { |
309 | uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) |
310 | uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN |
311 | uint32_t dcc_256_128_128 : 1; //available starting with DCN |
312 | uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) |
313 | } dcc_controls; |
314 | }; |
315 | |
316 | struct dc_surface_dcc_cap { |
317 | union { |
318 | struct { |
319 | struct dc_dcc_setting rgb; |
320 | } grph; |
321 | |
322 | struct { |
323 | struct dc_dcc_setting luma; |
324 | struct dc_dcc_setting chroma; |
325 | } video; |
326 | }; |
327 | |
328 | bool capable; |
329 | bool const_color_support; |
330 | }; |
331 | |
332 | struct dc_static_screen_params { |
333 | struct { |
334 | bool force_trigger; |
335 | bool cursor_update; |
336 | bool surface_update; |
337 | bool overlay_update; |
338 | } triggers; |
339 | unsigned int num_frames; |
340 | }; |
341 | |
342 | |
343 | /* Surface update type is used by dc_update_surfaces_and_stream |
344 | * The update type is determined at the very beginning of the function based |
345 | * on parameters passed in and decides how much programming (or updating) is |
346 | * going to be done during the call. |
347 | * |
348 | * UPDATE_TYPE_FAST is used for really fast updates that do not require much |
349 | * logical calculations or hardware register programming. This update MUST be |
350 | * ISR safe on windows. Currently fast update will only be used to flip surface |
351 | * address. |
352 | * |
353 | * UPDATE_TYPE_MED is used for slower updates which require significant hw |
354 | * re-programming however do not affect bandwidth consumption or clock |
355 | * requirements. At present, this is the level at which front end updates |
356 | * that do not require us to run bw_calcs happen. These are in/out transfer func |
357 | * updates, viewport offset changes, recout size changes and pixel depth changes. |
358 | * This update can be done at ISR, but we want to minimize how often this happens. |
359 | * |
360 | * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our |
361 | * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front |
362 | * end related. Any time viewport dimensions, recout dimensions, scaling ratios or |
363 | * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do |
364 | * a full update. This cannot be done at ISR level and should be a rare event. |
365 | * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting |
366 | * underscan we don't expect to see this call at all. |
367 | */ |
368 | |
369 | enum surface_update_type { |
370 | UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ |
371 | UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ |
372 | UPDATE_TYPE_FULL, /* may need to shuffle resources */ |
373 | }; |
374 | |
375 | /* Forward declaration*/ |
376 | struct dc; |
377 | struct dc_plane_state; |
378 | struct dc_state; |
379 | |
380 | |
381 | struct dc_cap_funcs { |
382 | bool (*get_dcc_compression_cap)(const struct dc *dc, |
383 | const struct dc_dcc_surface_param *input, |
384 | struct dc_surface_dcc_cap *output); |
385 | bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); |
386 | }; |
387 | |
388 | struct link_training_settings; |
389 | |
390 | union allow_lttpr_non_transparent_mode { |
391 | struct { |
392 | bool DP1_4A : 1; |
393 | bool DP2_0 : 1; |
394 | } bits; |
395 | unsigned char raw; |
396 | }; |
397 | |
398 | /* Structure to hold configuration flags set by dm at dc creation. */ |
399 | struct dc_config { |
400 | bool gpu_vm_support; |
401 | bool disable_disp_pll_sharing; |
402 | bool fbc_support; |
403 | bool disable_fractional_pwm; |
404 | bool allow_seamless_boot_optimization; |
405 | bool seamless_boot_edp_requested; |
406 | bool edp_not_connected; |
407 | bool edp_no_power_sequencing; |
408 | bool force_enum_edp; |
409 | bool forced_clocks; |
410 | union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; |
411 | bool multi_mon_pp_mclk_switch; |
412 | bool disable_dmcu; |
413 | bool enable_4to1MPC; |
414 | bool enable_windowed_mpo_odm; |
415 | bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 |
416 | uint32_t allow_edp_hotplug_detection; |
417 | bool clamp_min_dcfclk; |
418 | uint64_t vblank_alignment_dto_params; |
419 | uint8_t vblank_alignment_max_frame_time_diff; |
420 | bool is_asymmetric_memory; |
421 | bool is_single_rank_dimm; |
422 | bool is_vmin_only_asic; |
423 | bool use_pipe_ctx_sync_logic; |
424 | bool ignore_dpref_ss; |
425 | bool enable_mipi_converter_optimization; |
426 | bool use_default_clock_table; |
427 | bool force_bios_enable_lttpr; |
428 | uint8_t force_bios_fixed_vs; |
429 | int sdpif_request_limit_words_per_umc; |
430 | bool use_old_fixed_vs_sequence; |
431 | bool dc_mode_clk_limit_support; |
432 | bool EnableMinDispClkODM; |
433 | bool enable_auto_dpm_test_logs; |
434 | unsigned int disable_ips; |
435 | }; |
436 | |
437 | enum visual_confirm { |
438 | VISUAL_CONFIRM_DISABLE = 0, |
439 | VISUAL_CONFIRM_SURFACE = 1, |
440 | VISUAL_CONFIRM_HDR = 2, |
441 | VISUAL_CONFIRM_MPCTREE = 4, |
442 | VISUAL_CONFIRM_PSR = 5, |
443 | VISUAL_CONFIRM_SWAPCHAIN = 6, |
444 | VISUAL_CONFIRM_FAMS = 7, |
445 | VISUAL_CONFIRM_SWIZZLE = 9, |
446 | VISUAL_CONFIRM_REPLAY = 12, |
447 | VISUAL_CONFIRM_SUBVP = 14, |
448 | VISUAL_CONFIRM_MCLK_SWITCH = 16, |
449 | }; |
450 | |
451 | enum dc_psr_power_opts { |
452 | psr_power_opt_invalid = 0x0, |
453 | psr_power_opt_smu_opt_static_screen = 0x1, |
454 | psr_power_opt_z10_static_screen = 0x10, |
455 | psr_power_opt_ds_disable_allow = 0x100, |
456 | }; |
457 | |
458 | enum dml_hostvm_override_opts { |
459 | DML_HOSTVM_NO_OVERRIDE = 0x0, |
460 | DML_HOSTVM_OVERRIDE_FALSE = 0x1, |
461 | DML_HOSTVM_OVERRIDE_TRUE = 0x2, |
462 | }; |
463 | |
464 | enum dcc_option { |
465 | DCC_ENABLE = 0, |
466 | DCC_DISABLE = 1, |
467 | DCC_HALF_REQ_DISALBE = 2, |
468 | }; |
469 | |
470 | /** |
471 | * enum pipe_split_policy - Pipe split strategy supported by DCN |
472 | * |
473 | * This enum is used to define the pipe split policy supported by DCN. By |
474 | * default, DC favors MPC_SPLIT_DYNAMIC. |
475 | */ |
476 | enum pipe_split_policy { |
477 | /** |
478 | * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the |
479 | * pipe in order to bring the best trade-off between performance and |
480 | * power consumption. This is the recommended option. |
481 | */ |
482 | MPC_SPLIT_DYNAMIC = 0, |
483 | |
484 | /** |
485 | * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not |
486 | * try any sort of split optimization. |
487 | */ |
488 | MPC_SPLIT_AVOID = 1, |
489 | |
490 | /** |
491 | * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to |
492 | * optimize the pipe utilization when using a single display; if the |
493 | * user connects to a second display, DC will avoid pipe split. |
494 | */ |
495 | MPC_SPLIT_AVOID_MULT_DISP = 2, |
496 | }; |
497 | |
498 | enum wm_report_mode { |
499 | WM_REPORT_DEFAULT = 0, |
500 | WM_REPORT_OVERRIDE = 1, |
501 | }; |
502 | enum dtm_pstate{ |
503 | dtm_level_p0 = 0,/*highest voltage*/ |
504 | dtm_level_p1, |
505 | dtm_level_p2, |
506 | dtm_level_p3, |
507 | dtm_level_p4,/*when active_display_count = 0*/ |
508 | }; |
509 | |
510 | enum dcn_pwr_state { |
511 | DCN_PWR_STATE_UNKNOWN = -1, |
512 | DCN_PWR_STATE_MISSION_MODE = 0, |
513 | DCN_PWR_STATE_LOW_POWER = 3, |
514 | }; |
515 | |
516 | enum dcn_zstate_support_state { |
517 | DCN_ZSTATE_SUPPORT_UNKNOWN, |
518 | DCN_ZSTATE_SUPPORT_ALLOW, |
519 | DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, |
520 | DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, |
521 | DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, |
522 | DCN_ZSTATE_SUPPORT_DISALLOW, |
523 | }; |
524 | |
525 | /* |
526 | * struct dc_clocks - DC pipe clocks |
527 | * |
528 | * For any clocks that may differ per pipe only the max is stored in this |
529 | * structure |
530 | */ |
531 | struct dc_clocks { |
532 | int dispclk_khz; |
533 | int actual_dispclk_khz; |
534 | int dppclk_khz; |
535 | int actual_dppclk_khz; |
536 | int disp_dpp_voltage_level_khz; |
537 | int dcfclk_khz; |
538 | int socclk_khz; |
539 | int dcfclk_deep_sleep_khz; |
540 | int fclk_khz; |
541 | int phyclk_khz; |
542 | int dramclk_khz; |
543 | bool p_state_change_support; |
544 | enum dcn_zstate_support_state zstate_support; |
545 | bool dtbclk_en; |
546 | int ref_dtbclk_khz; |
547 | bool fclk_p_state_change_support; |
548 | enum dcn_pwr_state pwr_state; |
549 | /* |
550 | * Elements below are not compared for the purposes of |
551 | * optimization required |
552 | */ |
553 | bool prev_p_state_change_support; |
554 | bool fclk_prev_p_state_change_support; |
555 | int num_ways; |
556 | |
557 | /* |
558 | * @fw_based_mclk_switching |
559 | * |
560 | * DC has a mechanism that leverage the variable refresh rate to switch |
561 | * memory clock in cases that we have a large latency to achieve the |
562 | * memory clock change and a short vblank window. DC has some |
563 | * requirements to enable this feature, and this field describes if the |
564 | * system support or not such a feature. |
565 | */ |
566 | bool fw_based_mclk_switching; |
567 | bool fw_based_mclk_switching_shut_down; |
568 | int prev_num_ways; |
569 | enum dtm_pstate dtm_level; |
570 | int max_supported_dppclk_khz; |
571 | int max_supported_dispclk_khz; |
572 | int bw_dppclk_khz; /*a copy of dppclk_khz*/ |
573 | int bw_dispclk_khz; |
574 | }; |
575 | |
576 | struct dc_bw_validation_profile { |
577 | bool enable; |
578 | |
579 | unsigned long long total_ticks; |
580 | unsigned long long voltage_level_ticks; |
581 | unsigned long long watermark_ticks; |
582 | unsigned long long rq_dlg_ticks; |
583 | |
584 | unsigned long long total_count; |
585 | unsigned long long skip_fast_count; |
586 | unsigned long long skip_pass_count; |
587 | unsigned long long skip_fail_count; |
588 | }; |
589 | |
590 | #define BW_VAL_TRACE_SETUP() \ |
591 | unsigned long long end_tick = 0; \ |
592 | unsigned long long voltage_level_tick = 0; \ |
593 | unsigned long long watermark_tick = 0; \ |
594 | unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ |
595 | dm_get_timestamp(dc->ctx) : 0 |
596 | |
597 | #define BW_VAL_TRACE_COUNT() \ |
598 | if (dc->debug.bw_val_profile.enable) \ |
599 | dc->debug.bw_val_profile.total_count++ |
600 | |
601 | #define BW_VAL_TRACE_SKIP(status) \ |
602 | if (dc->debug.bw_val_profile.enable) { \ |
603 | if (!voltage_level_tick) \ |
604 | voltage_level_tick = dm_get_timestamp(dc->ctx); \ |
605 | dc->debug.bw_val_profile.skip_ ## status ## _count++; \ |
606 | } |
607 | |
608 | #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ |
609 | if (dc->debug.bw_val_profile.enable) \ |
610 | voltage_level_tick = dm_get_timestamp(dc->ctx) |
611 | |
612 | #define BW_VAL_TRACE_END_WATERMARKS() \ |
613 | if (dc->debug.bw_val_profile.enable) \ |
614 | watermark_tick = dm_get_timestamp(dc->ctx) |
615 | |
616 | #define BW_VAL_TRACE_FINISH() \ |
617 | if (dc->debug.bw_val_profile.enable) { \ |
618 | end_tick = dm_get_timestamp(dc->ctx); \ |
619 | dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ |
620 | dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ |
621 | if (watermark_tick) { \ |
622 | dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ |
623 | dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ |
624 | } \ |
625 | } |
626 | |
627 | union mem_low_power_enable_options { |
628 | struct { |
629 | bool vga: 1; |
630 | bool i2c: 1; |
631 | bool dmcu: 1; |
632 | bool dscl: 1; |
633 | bool cm: 1; |
634 | bool mpc: 1; |
635 | bool optc: 1; |
636 | bool vpg: 1; |
637 | bool afmt: 1; |
638 | } bits; |
639 | uint32_t u32All; |
640 | }; |
641 | |
642 | union root_clock_optimization_options { |
643 | struct { |
644 | bool dpp: 1; |
645 | bool dsc: 1; |
646 | bool hdmistream: 1; |
647 | bool hdmichar: 1; |
648 | bool dpstream: 1; |
649 | bool symclk32_se: 1; |
650 | bool symclk32_le: 1; |
651 | bool symclk_fe: 1; |
652 | bool physymclk: 1; |
653 | bool dpiasymclk: 1; |
654 | uint32_t reserved: 22; |
655 | } bits; |
656 | uint32_t u32All; |
657 | }; |
658 | |
659 | union fine_grain_clock_gating_enable_options { |
660 | struct { |
661 | bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ |
662 | bool dchub : 1; /* Display controller hub */ |
663 | bool dchubbub : 1; |
664 | bool dpp : 1; /* Display pipes and planes */ |
665 | bool opp : 1; /* Output pixel processing */ |
666 | bool optc : 1; /* Output pipe timing combiner */ |
667 | bool dio : 1; /* Display output */ |
668 | bool dwb : 1; /* Display writeback */ |
669 | bool mmhubbub : 1; /* Multimedia hub */ |
670 | bool dmu : 1; /* Display core management unit */ |
671 | bool az : 1; /* Azalia */ |
672 | bool dchvm : 1; |
673 | bool dsc : 1; /* Display stream compression */ |
674 | |
675 | uint32_t reserved : 19; |
676 | } bits; |
677 | uint32_t u32All; |
678 | }; |
679 | |
680 | enum pg_hw_pipe_resources { |
681 | PG_HUBP = 0, |
682 | PG_DPP, |
683 | PG_DSC, |
684 | PG_MPCC, |
685 | PG_OPP, |
686 | PG_OPTC, |
687 | PG_HW_PIPE_RESOURCES_NUM_ELEMENT |
688 | }; |
689 | |
690 | enum pg_hw_resources { |
691 | PG_DCCG = 0, |
692 | PG_DCIO, |
693 | PG_DIO, |
694 | PG_DCHUBBUB, |
695 | PG_DCHVM, |
696 | PG_DWB, |
697 | PG_HPO, |
698 | PG_HW_RESOURCES_NUM_ELEMENT |
699 | }; |
700 | |
701 | struct pg_block_update { |
702 | bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; |
703 | bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; |
704 | }; |
705 | |
706 | union dpia_debug_options { |
707 | struct { |
708 | uint32_t disable_dpia:1; /* bit 0 */ |
709 | uint32_t force_non_lttpr:1; /* bit 1 */ |
710 | uint32_t extend_aux_rd_interval:1; /* bit 2 */ |
711 | uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ |
712 | uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ |
713 | uint32_t reserved:27; |
714 | } bits; |
715 | uint32_t raw; |
716 | }; |
717 | |
718 | /* AUX wake work around options |
719 | * 0: enable/disable work around |
720 | * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS |
721 | * 15-2: reserved |
722 | * 31-16: timeout in ms |
723 | */ |
724 | union aux_wake_wa_options { |
725 | struct { |
726 | uint32_t enable_wa : 1; |
727 | uint32_t use_default_timeout : 1; |
728 | uint32_t rsvd: 14; |
729 | uint32_t timeout_ms : 16; |
730 | } bits; |
731 | uint32_t raw; |
732 | }; |
733 | |
734 | struct dc_debug_data { |
735 | uint32_t ltFailCount; |
736 | uint32_t i2cErrorCount; |
737 | uint32_t auxErrorCount; |
738 | }; |
739 | |
740 | struct dc_phy_addr_space_config { |
741 | struct { |
742 | uint64_t start_addr; |
743 | uint64_t end_addr; |
744 | uint64_t fb_top; |
745 | uint64_t fb_offset; |
746 | uint64_t fb_base; |
747 | uint64_t agp_top; |
748 | uint64_t agp_bot; |
749 | uint64_t agp_base; |
750 | } system_aperture; |
751 | |
752 | struct { |
753 | uint64_t page_table_start_addr; |
754 | uint64_t page_table_end_addr; |
755 | uint64_t page_table_base_addr; |
756 | bool base_addr_is_mc_addr; |
757 | } gart_config; |
758 | |
759 | bool valid; |
760 | bool is_hvm_enabled; |
761 | uint64_t page_table_default_page_addr; |
762 | }; |
763 | |
764 | struct dc_virtual_addr_space_config { |
765 | uint64_t page_table_base_addr; |
766 | uint64_t page_table_start_addr; |
767 | uint64_t page_table_end_addr; |
768 | uint32_t page_table_block_size_in_bytes; |
769 | uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid |
770 | }; |
771 | |
772 | struct dc_bounding_box_overrides { |
773 | int sr_exit_time_ns; |
774 | int sr_enter_plus_exit_time_ns; |
775 | int sr_exit_z8_time_ns; |
776 | int sr_enter_plus_exit_z8_time_ns; |
777 | int urgent_latency_ns; |
778 | int percent_of_ideal_drambw; |
779 | int dram_clock_change_latency_ns; |
780 | int dummy_clock_change_latency_ns; |
781 | int fclk_clock_change_latency_ns; |
782 | /* This forces a hard min on the DCFCLK we use |
783 | * for DML. Unlike the debug option for forcing |
784 | * DCFCLK, this override affects watermark calculations |
785 | */ |
786 | int min_dcfclk_mhz; |
787 | }; |
788 | |
789 | struct dc_state; |
790 | struct resource_pool; |
791 | struct dce_hwseq; |
792 | struct link_service; |
793 | |
794 | /* |
795 | * struct dc_debug_options - DC debug struct |
796 | * |
797 | * This struct provides a simple mechanism for developers to change some |
798 | * configurations, enable/disable features, and activate extra debug options. |
799 | * This can be very handy to narrow down whether some specific feature is |
800 | * causing an issue or not. |
801 | */ |
802 | struct dc_debug_options { |
803 | bool native422_support; |
804 | bool disable_dsc; |
805 | enum visual_confirm visual_confirm; |
806 | int visual_confirm_rect_height; |
807 | |
808 | bool sanity_checks; |
809 | bool max_disp_clk; |
810 | bool surface_trace; |
811 | bool timing_trace; |
812 | bool clock_trace; |
813 | bool validation_trace; |
814 | bool bandwidth_calcs_trace; |
815 | int max_downscale_src_width; |
816 | |
817 | /* stutter efficiency related */ |
818 | bool disable_stutter; |
819 | bool use_max_lb; |
820 | enum dcc_option disable_dcc; |
821 | |
822 | /* |
823 | * @pipe_split_policy: Define which pipe split policy is used by the |
824 | * display core. |
825 | */ |
826 | enum pipe_split_policy pipe_split_policy; |
827 | bool force_single_disp_pipe_split; |
828 | bool voltage_align_fclk; |
829 | bool disable_min_fclk; |
830 | |
831 | bool disable_dfs_bypass; |
832 | bool disable_dpp_power_gate; |
833 | bool disable_hubp_power_gate; |
834 | bool disable_dsc_power_gate; |
835 | bool disable_optc_power_gate; |
836 | bool disable_hpo_power_gate; |
837 | int dsc_min_slice_height_override; |
838 | int dsc_bpp_increment_div; |
839 | bool disable_pplib_wm_range; |
840 | enum wm_report_mode pplib_wm_report_mode; |
841 | unsigned int min_disp_clk_khz; |
842 | unsigned int min_dpp_clk_khz; |
843 | unsigned int min_dram_clk_khz; |
844 | int sr_exit_time_dpm0_ns; |
845 | int sr_enter_plus_exit_time_dpm0_ns; |
846 | int sr_exit_time_ns; |
847 | int sr_enter_plus_exit_time_ns; |
848 | int sr_exit_z8_time_ns; |
849 | int sr_enter_plus_exit_z8_time_ns; |
850 | int urgent_latency_ns; |
851 | uint32_t underflow_assert_delay_us; |
852 | int percent_of_ideal_drambw; |
853 | int dram_clock_change_latency_ns; |
854 | bool optimized_watermark; |
855 | int always_scale; |
856 | bool disable_pplib_clock_request; |
857 | bool disable_clock_gate; |
858 | bool disable_mem_low_power; |
859 | bool pstate_enabled; |
860 | bool disable_dmcu; |
861 | bool force_abm_enable; |
862 | bool disable_stereo_support; |
863 | bool vsr_support; |
864 | bool performance_trace; |
865 | bool az_endpoint_mute_only; |
866 | bool always_use_regamma; |
867 | bool recovery_enabled; |
868 | bool avoid_vbios_exec_table; |
869 | bool scl_reset_length10; |
870 | bool hdmi20_disable; |
871 | bool skip_detection_link_training; |
872 | uint32_t edid_read_retry_times; |
873 | unsigned int force_odm_combine; //bit vector based on otg inst |
874 | unsigned int seamless_boot_odm_combine; |
875 | unsigned int force_odm_combine_4to1; //bit vector based on otg inst |
876 | int minimum_z8_residency_time; |
877 | bool disable_z9_mpc; |
878 | unsigned int force_fclk_khz; |
879 | bool enable_tri_buf; |
880 | bool dmub_offload_enabled; |
881 | bool dmcub_emulation; |
882 | bool disable_idle_power_optimizations; |
883 | unsigned int mall_size_override; |
884 | unsigned int mall_additional_timer_percent; |
885 | bool mall_error_as_fatal; |
886 | bool dmub_command_table; /* for testing only */ |
887 | struct dc_bw_validation_profile bw_val_profile; |
888 | bool disable_fec; |
889 | bool disable_48mhz_pwrdwn; |
890 | /* This forces a hard min on the DCFCLK requested to SMU/PP |
891 | * watermarks are not affected. |
892 | */ |
893 | unsigned int force_min_dcfclk_mhz; |
894 | int dwb_fi_phase; |
895 | bool disable_timing_sync; |
896 | bool cm_in_bypass; |
897 | int force_clock_mode;/*every mode change.*/ |
898 | |
899 | bool disable_dram_clock_change_vactive_support; |
900 | bool validate_dml_output; |
901 | bool enable_dmcub_surface_flip; |
902 | bool usbc_combo_phy_reset_wa; |
903 | bool enable_dram_clock_change_one_display_vactive; |
904 | /* TODO - remove once tested */ |
905 | bool legacy_dp2_lt; |
906 | bool set_mst_en_for_sst; |
907 | bool disable_uhbr; |
908 | bool force_dp2_lt_fallback_method; |
909 | bool ignore_cable_id; |
910 | union mem_low_power_enable_options enable_mem_low_power; |
911 | union root_clock_optimization_options root_clock_optimization; |
912 | union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; |
913 | bool hpo_optimization; |
914 | bool force_vblank_alignment; |
915 | |
916 | /* Enable dmub aux for legacy ddc */ |
917 | bool enable_dmub_aux_for_legacy_ddc; |
918 | bool disable_fams; |
919 | bool disable_fams_gaming; |
920 | /* FEC/PSR1 sequence enable delay in 100us */ |
921 | uint8_t fec_enable_delay_in100us; |
922 | bool enable_driver_sequence_debug; |
923 | enum det_size crb_alloc_policy; |
924 | int crb_alloc_policy_min_disp_count; |
925 | bool disable_z10; |
926 | bool enable_z9_disable_interface; |
927 | bool psr_skip_crtc_disable; |
928 | union dpia_debug_options dpia_debug; |
929 | bool disable_fixed_vs_aux_timeout_wa; |
930 | uint32_t fixed_vs_aux_delay_config_wa; |
931 | bool force_disable_subvp; |
932 | bool force_subvp_mclk_switch; |
933 | bool allow_sw_cursor_fallback; |
934 | unsigned int force_subvp_num_ways; |
935 | unsigned int force_mall_ss_num_ways; |
936 | bool ; |
937 | uint32_t ; |
938 | bool force_usr_allow; |
939 | /* uses value at boot and disables switch */ |
940 | bool disable_dtb_ref_clk_switch; |
941 | bool extended_blank_optimization; |
942 | union aux_wake_wa_options aux_wake_wa; |
943 | uint32_t mst_start_top_delay; |
944 | uint8_t psr_power_use_phy_fsm; |
945 | enum dml_hostvm_override_opts dml_hostvm_override; |
946 | bool dml_disallow_alternate_prefetch_modes; |
947 | bool use_legacy_soc_bb_mechanism; |
948 | bool exit_idle_opt_for_cursor_updates; |
949 | bool using_dml2; |
950 | bool enable_single_display_2to1_odm_policy; |
951 | bool enable_double_buffered_dsc_pg_support; |
952 | bool enable_dp_dig_pixel_rate_div_policy; |
953 | enum lttpr_mode lttpr_mode_override; |
954 | unsigned int dsc_delay_factor_wa_x1000; |
955 | unsigned int min_prefetch_in_strobe_ns; |
956 | bool disable_unbounded_requesting; |
957 | bool dig_fifo_off_in_blank; |
958 | bool temp_mst_deallocation_sequence; |
959 | bool override_dispclk_programming; |
960 | bool otg_crc_db; |
961 | bool disallow_dispclk_dppclk_ds; |
962 | bool disable_fpo_optimizations; |
963 | bool support_eDP1_5; |
964 | uint32_t fpo_vactive_margin_us; |
965 | bool disable_fpo_vactive; |
966 | bool disable_boot_optimizations; |
967 | bool override_odm_optimization; |
968 | bool minimize_dispclk_using_odm; |
969 | bool disable_subvp_high_refresh; |
970 | bool disable_dp_plus_plus_wa; |
971 | uint32_t fpo_vactive_min_active_margin_us; |
972 | uint32_t fpo_vactive_max_blank_us; |
973 | bool enable_hpo_pg_support; |
974 | bool enable_legacy_fast_update; |
975 | bool disable_dc_mode_overwrite; |
976 | bool replay_skip_crtc_disabled; |
977 | bool ignore_pg;/*do nothing, let pmfw control it*/ |
978 | bool psp_disabled_wa; |
979 | unsigned int ips2_eval_delay_us; |
980 | unsigned int ips2_entry_delay_us; |
981 | }; |
982 | |
983 | struct gpu_info_soc_bounding_box_v1_0; |
984 | |
985 | /* Generic structure that can be used to query properties of DC. More fields |
986 | * can be added as required. |
987 | */ |
988 | struct dc_current_properties { |
989 | unsigned int cursor_size_limit; |
990 | }; |
991 | |
992 | struct dc { |
993 | struct dc_debug_options debug; |
994 | struct dc_versions versions; |
995 | struct dc_caps caps; |
996 | struct dc_cap_funcs cap_funcs; |
997 | struct dc_config config; |
998 | struct dc_bounding_box_overrides bb_overrides; |
999 | struct dc_bug_wa work_arounds; |
1000 | struct dc_context *ctx; |
1001 | struct dc_phy_addr_space_config vm_pa_config; |
1002 | |
1003 | uint8_t link_count; |
1004 | struct dc_link *links[MAX_PIPES * 2]; |
1005 | struct link_service *link_srv; |
1006 | |
1007 | struct dc_state *current_state; |
1008 | struct resource_pool *res_pool; |
1009 | |
1010 | struct clk_mgr *clk_mgr; |
1011 | |
1012 | /* Display Engine Clock levels */ |
1013 | struct dm_pp_clock_levels sclk_lvls; |
1014 | |
1015 | /* Inputs into BW and WM calculations. */ |
1016 | struct bw_calcs_dceip *bw_dceip; |
1017 | struct bw_calcs_vbios *bw_vbios; |
1018 | struct dcn_soc_bounding_box *dcn_soc; |
1019 | struct dcn_ip_params *dcn_ip; |
1020 | struct display_mode_lib dml; |
1021 | |
1022 | /* HW functions */ |
1023 | struct hw_sequencer_funcs hwss; |
1024 | struct dce_hwseq *hwseq; |
1025 | |
1026 | /* Require to optimize clocks and bandwidth for added/removed planes */ |
1027 | bool optimized_required; |
1028 | bool wm_optimized_required; |
1029 | bool idle_optimizations_allowed; |
1030 | bool enable_c20_dtm_b0; |
1031 | |
1032 | /* Require to maintain clocks and bandwidth for UEFI enabled HW */ |
1033 | |
1034 | /* FBC compressor */ |
1035 | struct compressor *fbc_compressor; |
1036 | |
1037 | struct dc_debug_data debug_data; |
1038 | struct dpcd_vendor_signature vendor_signature; |
1039 | |
1040 | const char *build_id; |
1041 | struct vm_helper *vm_helper; |
1042 | |
1043 | uint32_t *dcn_reg_offsets; |
1044 | uint32_t *nbio_reg_offsets; |
1045 | uint32_t *clk_reg_offsets; |
1046 | |
1047 | /* Scratch memory */ |
1048 | struct { |
1049 | struct { |
1050 | /* |
1051 | * For matching clock_limits table in driver with table |
1052 | * from PMFW. |
1053 | */ |
1054 | struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; |
1055 | } update_bw_bounding_box; |
1056 | } scratch; |
1057 | |
1058 | struct dml2_configuration_options dml2_options; |
1059 | }; |
1060 | |
1061 | enum frame_buffer_mode { |
1062 | FRAME_BUFFER_MODE_LOCAL_ONLY = 0, |
1063 | FRAME_BUFFER_MODE_ZFB_ONLY, |
1064 | FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, |
1065 | } ; |
1066 | |
1067 | struct dchub_init_data { |
1068 | int64_t zfb_phys_addr_base; |
1069 | int64_t zfb_mc_base_addr; |
1070 | uint64_t zfb_size_in_byte; |
1071 | enum frame_buffer_mode fb_mode; |
1072 | bool dchub_initialzied; |
1073 | bool dchub_info_valid; |
1074 | }; |
1075 | |
1076 | struct dc_init_data { |
1077 | struct hw_asic_id asic_id; |
1078 | void *driver; /* ctx */ |
1079 | struct cgs_device *cgs_device; |
1080 | struct dc_bounding_box_overrides bb_overrides; |
1081 | |
1082 | int num_virtual_links; |
1083 | /* |
1084 | * If 'vbios_override' not NULL, it will be called instead |
1085 | * of the real VBIOS. Intended use is Diagnostics on FPGA. |
1086 | */ |
1087 | struct dc_bios *vbios_override; |
1088 | enum dce_environment dce_environment; |
1089 | |
1090 | struct dmub_offload_funcs *dmub_if; |
1091 | struct dc_reg_helper_state *dmub_offload; |
1092 | |
1093 | struct dc_config flags; |
1094 | uint64_t log_mask; |
1095 | |
1096 | struct dpcd_vendor_signature vendor_signature; |
1097 | bool force_smu_not_present; |
1098 | /* |
1099 | * IP offset for run time initializaion of register addresses |
1100 | * |
1101 | * DCN3.5+ will fail dc_create() if these fields are null for them. They are |
1102 | * applicable starting with DCN32/321 and are not used for ASICs upstreamed |
1103 | * before them. |
1104 | */ |
1105 | uint32_t *dcn_reg_offsets; |
1106 | uint32_t *nbio_reg_offsets; |
1107 | uint32_t *clk_reg_offsets; |
1108 | }; |
1109 | |
1110 | struct dc_callback_init { |
1111 | struct cp_psp cp_psp; |
1112 | }; |
1113 | |
1114 | struct dc *dc_create(const struct dc_init_data *init_params); |
1115 | void dc_hardware_init(struct dc *dc); |
1116 | |
1117 | int dc_get_vmid_use_vector(struct dc *dc); |
1118 | void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); |
1119 | /* Returns the number of vmids supported */ |
1120 | int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); |
1121 | void dc_init_callbacks(struct dc *dc, |
1122 | const struct dc_callback_init *init_params); |
1123 | void dc_deinit_callbacks(struct dc *dc); |
1124 | void dc_destroy(struct dc **dc); |
1125 | |
1126 | /* Surface Interfaces */ |
1127 | |
1128 | enum { |
1129 | TRANSFER_FUNC_POINTS = 1025 |
1130 | }; |
1131 | |
1132 | struct dc_hdr_static_metadata { |
1133 | /* display chromaticities and white point in units of 0.00001 */ |
1134 | unsigned int chromaticity_green_x; |
1135 | unsigned int chromaticity_green_y; |
1136 | unsigned int chromaticity_blue_x; |
1137 | unsigned int chromaticity_blue_y; |
1138 | unsigned int chromaticity_red_x; |
1139 | unsigned int chromaticity_red_y; |
1140 | unsigned int chromaticity_white_point_x; |
1141 | unsigned int chromaticity_white_point_y; |
1142 | |
1143 | uint32_t min_luminance; |
1144 | uint32_t max_luminance; |
1145 | uint32_t maximum_content_light_level; |
1146 | uint32_t maximum_frame_average_light_level; |
1147 | }; |
1148 | |
1149 | enum dc_transfer_func_type { |
1150 | TF_TYPE_PREDEFINED, |
1151 | TF_TYPE_DISTRIBUTED_POINTS, |
1152 | TF_TYPE_BYPASS, |
1153 | TF_TYPE_HWPWL |
1154 | }; |
1155 | |
1156 | struct dc_transfer_func_distributed_points { |
1157 | struct fixed31_32 red[TRANSFER_FUNC_POINTS]; |
1158 | struct fixed31_32 green[TRANSFER_FUNC_POINTS]; |
1159 | struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; |
1160 | |
1161 | uint16_t end_exponent; |
1162 | uint16_t x_point_at_y1_red; |
1163 | uint16_t x_point_at_y1_green; |
1164 | uint16_t x_point_at_y1_blue; |
1165 | }; |
1166 | |
1167 | enum dc_transfer_func_predefined { |
1168 | TRANSFER_FUNCTION_SRGB, |
1169 | TRANSFER_FUNCTION_BT709, |
1170 | TRANSFER_FUNCTION_PQ, |
1171 | TRANSFER_FUNCTION_LINEAR, |
1172 | TRANSFER_FUNCTION_UNITY, |
1173 | TRANSFER_FUNCTION_HLG, |
1174 | TRANSFER_FUNCTION_HLG12, |
1175 | TRANSFER_FUNCTION_GAMMA22, |
1176 | TRANSFER_FUNCTION_GAMMA24, |
1177 | TRANSFER_FUNCTION_GAMMA26 |
1178 | }; |
1179 | |
1180 | |
1181 | struct dc_transfer_func { |
1182 | struct kref refcount; |
1183 | enum dc_transfer_func_type type; |
1184 | enum dc_transfer_func_predefined tf; |
1185 | /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ |
1186 | uint32_t sdr_ref_white_level; |
1187 | union { |
1188 | struct pwl_params pwl; |
1189 | struct dc_transfer_func_distributed_points tf_pts; |
1190 | }; |
1191 | }; |
1192 | |
1193 | |
1194 | union dc_3dlut_state { |
1195 | struct { |
1196 | uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ |
1197 | uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ |
1198 | uint32_t rmu_mux_num:3; /*index of mux to use*/ |
1199 | uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ |
1200 | uint32_t mpc_rmu1_mux:4; |
1201 | uint32_t mpc_rmu2_mux:4; |
1202 | uint32_t reserved:15; |
1203 | } bits; |
1204 | uint32_t raw; |
1205 | }; |
1206 | |
1207 | |
1208 | struct dc_3dlut { |
1209 | struct kref refcount; |
1210 | struct tetrahedral_params lut_3d; |
1211 | struct fixed31_32 hdr_multiplier; |
1212 | union dc_3dlut_state state; |
1213 | }; |
1214 | /* |
1215 | * This structure is filled in by dc_surface_get_status and contains |
1216 | * the last requested address and the currently active address so the called |
1217 | * can determine if there are any outstanding flips |
1218 | */ |
1219 | struct dc_plane_status { |
1220 | struct dc_plane_address requested_address; |
1221 | struct dc_plane_address current_address; |
1222 | bool is_flip_pending; |
1223 | bool is_right_eye; |
1224 | }; |
1225 | |
1226 | union surface_update_flags { |
1227 | |
1228 | struct { |
1229 | uint32_t addr_update:1; |
1230 | /* Medium updates */ |
1231 | uint32_t dcc_change:1; |
1232 | uint32_t color_space_change:1; |
1233 | uint32_t horizontal_mirror_change:1; |
1234 | uint32_t per_pixel_alpha_change:1; |
1235 | uint32_t global_alpha_change:1; |
1236 | uint32_t hdr_mult:1; |
1237 | uint32_t rotation_change:1; |
1238 | uint32_t swizzle_change:1; |
1239 | uint32_t scaling_change:1; |
1240 | uint32_t position_change:1; |
1241 | uint32_t in_transfer_func_change:1; |
1242 | uint32_t input_csc_change:1; |
1243 | uint32_t coeff_reduction_change:1; |
1244 | uint32_t output_tf_change:1; |
1245 | uint32_t pixel_format_change:1; |
1246 | uint32_t plane_size_change:1; |
1247 | uint32_t gamut_remap_change:1; |
1248 | |
1249 | /* Full updates */ |
1250 | uint32_t new_plane:1; |
1251 | uint32_t bpp_change:1; |
1252 | uint32_t gamma_change:1; |
1253 | uint32_t bandwidth_change:1; |
1254 | uint32_t clock_change:1; |
1255 | uint32_t stereo_format_change:1; |
1256 | uint32_t lut_3d:1; |
1257 | uint32_t tmz_changed:1; |
1258 | uint32_t full_update:1; |
1259 | } bits; |
1260 | |
1261 | uint32_t raw; |
1262 | }; |
1263 | |
1264 | struct dc_plane_state { |
1265 | struct dc_plane_address address; |
1266 | struct dc_plane_flip_time time; |
1267 | bool triplebuffer_flips; |
1268 | struct scaling_taps scaling_quality; |
1269 | struct rect src_rect; |
1270 | struct rect dst_rect; |
1271 | struct rect clip_rect; |
1272 | |
1273 | struct plane_size plane_size; |
1274 | union dc_tiling_info tiling_info; |
1275 | |
1276 | struct dc_plane_dcc_param dcc; |
1277 | |
1278 | struct dc_gamma *gamma_correction; |
1279 | struct dc_transfer_func *in_transfer_func; |
1280 | struct dc_bias_and_scale *bias_and_scale; |
1281 | struct dc_csc_transform input_csc_color_matrix; |
1282 | struct fixed31_32 coeff_reduction_factor; |
1283 | struct fixed31_32 hdr_mult; |
1284 | struct colorspace_transform gamut_remap_matrix; |
1285 | |
1286 | // TODO: No longer used, remove |
1287 | struct dc_hdr_static_metadata hdr_static_ctx; |
1288 | |
1289 | enum dc_color_space color_space; |
1290 | |
1291 | struct dc_3dlut *lut3d_func; |
1292 | struct dc_transfer_func *in_shaper_func; |
1293 | struct dc_transfer_func *blend_tf; |
1294 | |
1295 | struct dc_transfer_func *gamcor_tf; |
1296 | enum surface_pixel_format format; |
1297 | enum dc_rotation_angle rotation; |
1298 | enum plane_stereo_format stereo_format; |
1299 | |
1300 | bool is_tiling_rotated; |
1301 | bool per_pixel_alpha; |
1302 | bool pre_multiplied_alpha; |
1303 | bool global_alpha; |
1304 | int global_alpha_value; |
1305 | bool visible; |
1306 | bool flip_immediate; |
1307 | bool horizontal_mirror; |
1308 | int layer_index; |
1309 | |
1310 | union surface_update_flags update_flags; |
1311 | bool flip_int_enabled; |
1312 | bool skip_manual_trigger; |
1313 | |
1314 | /* private to DC core */ |
1315 | struct dc_plane_status status; |
1316 | struct dc_context *ctx; |
1317 | |
1318 | /* HACK: Workaround for forcing full reprogramming under some conditions */ |
1319 | bool force_full_update; |
1320 | |
1321 | bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead |
1322 | |
1323 | /* private to dc_surface.c */ |
1324 | enum dc_irq_source irq_source; |
1325 | struct kref refcount; |
1326 | struct tg_color visual_confirm_color; |
1327 | |
1328 | bool is_statically_allocated; |
1329 | }; |
1330 | |
1331 | struct dc_plane_info { |
1332 | struct plane_size plane_size; |
1333 | union dc_tiling_info tiling_info; |
1334 | struct dc_plane_dcc_param dcc; |
1335 | enum surface_pixel_format format; |
1336 | enum dc_rotation_angle rotation; |
1337 | enum plane_stereo_format stereo_format; |
1338 | enum dc_color_space color_space; |
1339 | bool horizontal_mirror; |
1340 | bool visible; |
1341 | bool per_pixel_alpha; |
1342 | bool pre_multiplied_alpha; |
1343 | bool global_alpha; |
1344 | int global_alpha_value; |
1345 | bool input_csc_enabled; |
1346 | int layer_index; |
1347 | }; |
1348 | |
1349 | struct dc_scaling_info { |
1350 | struct rect src_rect; |
1351 | struct rect dst_rect; |
1352 | struct rect clip_rect; |
1353 | struct scaling_taps scaling_quality; |
1354 | }; |
1355 | |
1356 | struct dc_fast_update { |
1357 | const struct dc_flip_addrs *flip_addr; |
1358 | const struct dc_gamma *gamma; |
1359 | const struct colorspace_transform *gamut_remap_matrix; |
1360 | const struct dc_csc_transform *input_csc_color_matrix; |
1361 | const struct fixed31_32 *coeff_reduction_factor; |
1362 | struct dc_transfer_func *out_transfer_func; |
1363 | struct dc_csc_transform *output_csc_transform; |
1364 | }; |
1365 | |
1366 | struct dc_surface_update { |
1367 | struct dc_plane_state *surface; |
1368 | |
1369 | /* isr safe update parameters. null means no updates */ |
1370 | const struct dc_flip_addrs *flip_addr; |
1371 | const struct dc_plane_info *plane_info; |
1372 | const struct dc_scaling_info *scaling_info; |
1373 | struct fixed31_32 hdr_mult; |
1374 | /* following updates require alloc/sleep/spin that is not isr safe, |
1375 | * null means no updates |
1376 | */ |
1377 | const struct dc_gamma *gamma; |
1378 | const struct dc_transfer_func *in_transfer_func; |
1379 | |
1380 | const struct dc_csc_transform *input_csc_color_matrix; |
1381 | const struct fixed31_32 *coeff_reduction_factor; |
1382 | const struct dc_transfer_func *func_shaper; |
1383 | const struct dc_3dlut *lut3d_func; |
1384 | const struct dc_transfer_func *blend_tf; |
1385 | const struct colorspace_transform *gamut_remap_matrix; |
1386 | }; |
1387 | |
1388 | /* |
1389 | * Create a new surface with default parameters; |
1390 | */ |
1391 | struct dc_plane_state *dc_create_plane_state(struct dc *dc); |
1392 | const struct dc_plane_status *dc_plane_get_status( |
1393 | const struct dc_plane_state *plane_state); |
1394 | |
1395 | void dc_plane_state_retain(struct dc_plane_state *plane_state); |
1396 | void dc_plane_state_release(struct dc_plane_state *plane_state); |
1397 | |
1398 | void dc_gamma_retain(struct dc_gamma *dc_gamma); |
1399 | void dc_gamma_release(struct dc_gamma **dc_gamma); |
1400 | struct dc_gamma *dc_create_gamma(void); |
1401 | |
1402 | void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); |
1403 | void dc_transfer_func_release(struct dc_transfer_func *dc_tf); |
1404 | struct dc_transfer_func *dc_create_transfer_func(void); |
1405 | |
1406 | struct dc_3dlut *dc_create_3dlut_func(void); |
1407 | void dc_3dlut_func_release(struct dc_3dlut *lut); |
1408 | void dc_3dlut_func_retain(struct dc_3dlut *lut); |
1409 | |
1410 | void dc_post_update_surfaces_to_stream( |
1411 | struct dc *dc); |
1412 | |
1413 | #include "dc_stream.h" |
1414 | |
1415 | /** |
1416 | * struct dc_validation_set - Struct to store surface/stream associations for validation |
1417 | */ |
1418 | struct dc_validation_set { |
1419 | /** |
1420 | * @stream: Stream state properties |
1421 | */ |
1422 | struct dc_stream_state *stream; |
1423 | |
1424 | /** |
1425 | * @plane_states: Surface state |
1426 | */ |
1427 | struct dc_plane_state *plane_states[MAX_SURFACES]; |
1428 | |
1429 | /** |
1430 | * @plane_count: Total of active planes |
1431 | */ |
1432 | uint8_t plane_count; |
1433 | }; |
1434 | |
1435 | bool dc_validate_boot_timing(const struct dc *dc, |
1436 | const struct dc_sink *sink, |
1437 | struct dc_crtc_timing *crtc_timing); |
1438 | |
1439 | enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); |
1440 | |
1441 | void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); |
1442 | |
1443 | enum dc_status dc_validate_with_context(struct dc *dc, |
1444 | const struct dc_validation_set set[], |
1445 | int set_count, |
1446 | struct dc_state *context, |
1447 | bool fast_validate); |
1448 | |
1449 | bool dc_set_generic_gpio_for_stereo(bool enable, |
1450 | struct gpio_service *gpio_service); |
1451 | |
1452 | /* |
1453 | * fast_validate: we return after determining if we can support the new state, |
1454 | * but before we populate the programming info |
1455 | */ |
1456 | enum dc_status dc_validate_global_state( |
1457 | struct dc *dc, |
1458 | struct dc_state *new_ctx, |
1459 | bool fast_validate); |
1460 | |
1461 | |
1462 | void dc_resource_state_construct( |
1463 | const struct dc *dc, |
1464 | struct dc_state *dst_ctx); |
1465 | |
1466 | bool dc_acquire_release_mpc_3dlut( |
1467 | struct dc *dc, bool acquire, |
1468 | struct dc_stream_state *stream, |
1469 | struct dc_3dlut **lut, |
1470 | struct dc_transfer_func **shaper); |
1471 | |
1472 | void dc_resource_state_copy_construct( |
1473 | const struct dc_state *src_ctx, |
1474 | struct dc_state *dst_ctx); |
1475 | |
1476 | void dc_resource_state_copy_construct_current( |
1477 | const struct dc *dc, |
1478 | struct dc_state *dst_ctx); |
1479 | |
1480 | void dc_resource_state_destruct(struct dc_state *context); |
1481 | |
1482 | bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); |
1483 | |
1484 | enum dc_status dc_commit_streams(struct dc *dc, |
1485 | struct dc_stream_state *streams[], |
1486 | uint8_t stream_count); |
1487 | |
1488 | struct dc_state *dc_create_state(struct dc *dc); |
1489 | struct dc_state *dc_copy_state(struct dc_state *src_ctx); |
1490 | void dc_retain_state(struct dc_state *context); |
1491 | void dc_release_state(struct dc_state *context); |
1492 | |
1493 | struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, |
1494 | struct dc_stream_state *stream, |
1495 | int mpcc_inst); |
1496 | |
1497 | |
1498 | uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); |
1499 | |
1500 | void dc_set_disable_128b_132b_stream_overhead(bool disable); |
1501 | |
1502 | /* The function returns minimum bandwidth required to drive a given timing |
1503 | * return - minimum required timing bandwidth in kbps. |
1504 | */ |
1505 | uint32_t dc_bandwidth_in_kbps_from_timing( |
1506 | const struct dc_crtc_timing *timing, |
1507 | const enum dc_link_encoding_format link_encoding); |
1508 | |
1509 | /* Link Interfaces */ |
1510 | /* |
1511 | * A link contains one or more sinks and their connected status. |
1512 | * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. |
1513 | */ |
1514 | struct dc_link { |
1515 | struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; |
1516 | unsigned int sink_count; |
1517 | struct dc_sink *local_sink; |
1518 | unsigned int link_index; |
1519 | enum dc_connection_type type; |
1520 | enum signal_type connector_signal; |
1521 | enum dc_irq_source irq_source_hpd; |
1522 | enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ |
1523 | |
1524 | bool is_hpd_filter_disabled; |
1525 | bool dp_ss_off; |
1526 | |
1527 | /** |
1528 | * @link_state_valid: |
1529 | * |
1530 | * If there is no link and local sink, this variable should be set to |
1531 | * false. Otherwise, it should be set to true; usually, the function |
1532 | * core_link_enable_stream sets this field to true. |
1533 | */ |
1534 | bool link_state_valid; |
1535 | bool aux_access_disabled; |
1536 | bool sync_lt_in_progress; |
1537 | bool skip_stream_reenable; |
1538 | bool is_internal_display; |
1539 | /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ |
1540 | bool is_dig_mapping_flexible; |
1541 | bool hpd_status; /* HPD status of link without physical HPD pin. */ |
1542 | bool is_hpd_pending; /* Indicates a new received hpd */ |
1543 | bool is_automated; /* Indicates automated testing */ |
1544 | |
1545 | bool edp_sink_present; |
1546 | |
1547 | struct dp_trace dp_trace; |
1548 | |
1549 | /* caps is the same as reported_link_cap. link_traing use |
1550 | * reported_link_cap. Will clean up. TODO |
1551 | */ |
1552 | struct dc_link_settings reported_link_cap; |
1553 | struct dc_link_settings verified_link_cap; |
1554 | struct dc_link_settings cur_link_settings; |
1555 | struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; |
1556 | struct dc_link_settings preferred_link_setting; |
1557 | /* preferred_training_settings are override values that |
1558 | * come from DM. DM is responsible for the memory |
1559 | * management of the override pointers. |
1560 | */ |
1561 | struct dc_link_training_overrides preferred_training_settings; |
1562 | struct dp_audio_test_data audio_test_data; |
1563 | |
1564 | uint8_t ddc_hw_inst; |
1565 | |
1566 | uint8_t hpd_src; |
1567 | |
1568 | uint8_t link_enc_hw_inst; |
1569 | /* DIG link encoder ID. Used as index in link encoder resource pool. |
1570 | * For links with fixed mapping to DIG, this is not changed after dc_link |
1571 | * object creation. |
1572 | */ |
1573 | enum engine_id eng_id; |
1574 | enum engine_id dpia_preferred_eng_id; |
1575 | |
1576 | bool test_pattern_enabled; |
1577 | enum dp_test_pattern current_test_pattern; |
1578 | union compliance_test_state compliance_test_state; |
1579 | |
1580 | void *priv; |
1581 | |
1582 | struct ddc_service *ddc; |
1583 | |
1584 | enum dp_panel_mode panel_mode; |
1585 | bool aux_mode; |
1586 | |
1587 | /* Private to DC core */ |
1588 | |
1589 | const struct dc *dc; |
1590 | |
1591 | struct dc_context *ctx; |
1592 | |
1593 | struct panel_cntl *panel_cntl; |
1594 | struct link_encoder *link_enc; |
1595 | struct graphics_object_id link_id; |
1596 | /* Endpoint type distinguishes display endpoints which do not have entries |
1597 | * in the BIOS connector table from those that do. Helps when tracking link |
1598 | * encoder to display endpoint assignments. |
1599 | */ |
1600 | enum display_endpoint_type ep_type; |
1601 | union ddi_channel_mapping ddi_channel_mapping; |
1602 | struct connector_device_tag_info device_tag; |
1603 | struct dpcd_caps dpcd_caps; |
1604 | uint32_t dongle_max_pix_clk; |
1605 | unsigned short chip_caps; |
1606 | unsigned int dpcd_sink_count; |
1607 | struct hdcp_caps hdcp_caps; |
1608 | enum edp_revision edp_revision; |
1609 | union dpcd_sink_ext_caps dpcd_sink_ext_caps; |
1610 | |
1611 | struct backlight_settings backlight_settings; |
1612 | struct psr_settings psr_settings; |
1613 | |
1614 | struct replay_settings replay_settings; |
1615 | |
1616 | /* Drive settings read from integrated info table */ |
1617 | struct dc_lane_settings bios_forced_drive_settings; |
1618 | |
1619 | /* Vendor specific LTTPR workaround variables */ |
1620 | uint8_t vendor_specific_lttpr_link_rate_wa; |
1621 | bool apply_vendor_specific_lttpr_link_rate_wa; |
1622 | |
1623 | /* MST record stream using this link */ |
1624 | struct link_flags { |
1625 | bool dp_keep_receiver_powered; |
1626 | bool dp_skip_DID2; |
1627 | bool dp_skip_reset_segment; |
1628 | bool dp_skip_fs_144hz; |
1629 | bool dp_mot_reset_segment; |
1630 | /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ |
1631 | bool dpia_mst_dsc_always_on; |
1632 | /* Forced DPIA into TBT3 compatibility mode. */ |
1633 | bool dpia_forced_tbt3_mode; |
1634 | bool dongle_mode_timing_override; |
1635 | bool blank_stream_on_ocs_change; |
1636 | bool read_dpcd204h_on_irq_hpd; |
1637 | } wa_flags; |
1638 | struct link_mst_stream_allocation_table mst_stream_alloc_table; |
1639 | |
1640 | struct dc_link_status link_status; |
1641 | struct dprx_states dprx_states; |
1642 | |
1643 | struct gpio *hpd_gpio; |
1644 | enum dc_link_fec_state fec_state; |
1645 | bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly |
1646 | |
1647 | struct dc_panel_config panel_config; |
1648 | struct phy_state phy_state; |
1649 | // BW ALLOCATON USB4 ONLY |
1650 | struct dc_dpia_bw_alloc dpia_bw_alloc_config; |
1651 | bool skip_implict_edp_power_control; |
1652 | }; |
1653 | |
1654 | /* Return an enumerated dc_link. |
1655 | * dc_link order is constant and determined at |
1656 | * boot time. They cannot be created or destroyed. |
1657 | * Use dc_get_caps() to get number of links. |
1658 | */ |
1659 | struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); |
1660 | |
1661 | /* Return instance id of the edp link. Inst 0 is primary edp link. */ |
1662 | bool dc_get_edp_link_panel_inst(const struct dc *dc, |
1663 | const struct dc_link *link, |
1664 | unsigned int *inst_out); |
1665 | |
1666 | /* Return an array of link pointers to edp links. */ |
1667 | void dc_get_edp_links(const struct dc *dc, |
1668 | struct dc_link **edp_links, |
1669 | int *edp_num); |
1670 | |
1671 | void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, |
1672 | bool powerOn); |
1673 | |
1674 | /* The function initiates detection handshake over the given link. It first |
1675 | * determines if there are display connections over the link. If so it initiates |
1676 | * detection protocols supported by the connected receiver device. The function |
1677 | * contains protocol specific handshake sequences which are sometimes mandatory |
1678 | * to establish a proper connection between TX and RX. So it is always |
1679 | * recommended to call this function as the first link operation upon HPD event |
1680 | * or power up event. Upon completion, the function will update link structure |
1681 | * in place based on latest RX capabilities. The function may also cause dpms |
1682 | * to be reset to off for all currently enabled streams to the link. It is DM's |
1683 | * responsibility to serialize detection and DPMS updates. |
1684 | * |
1685 | * @reason - Indicate which event triggers this detection. dc may customize |
1686 | * detection flow depending on the triggering events. |
1687 | * return false - if detection is not fully completed. This could happen when |
1688 | * there is an unrecoverable error during detection or detection is partially |
1689 | * completed (detection has been delegated to dm mst manager ie. |
1690 | * link->connection_type == dc_connection_mst_branch when returning false). |
1691 | * return true - detection is completed, link has been fully updated with latest |
1692 | * detection result. |
1693 | */ |
1694 | bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); |
1695 | |
1696 | struct dc_sink_init_data; |
1697 | |
1698 | /* When link connection type is dc_connection_mst_branch, remote sink can be |
1699 | * added to the link. The interface creates a remote sink and associates it with |
1700 | * current link. The sink will be retained by link until remove remote sink is |
1701 | * called. |
1702 | * |
1703 | * @dc_link - link the remote sink will be added to. |
1704 | * @edid - byte array of EDID raw data. |
1705 | * @len - size of the edid in byte |
1706 | * @init_data - |
1707 | */ |
1708 | struct dc_sink *dc_link_add_remote_sink( |
1709 | struct dc_link *dc_link, |
1710 | const uint8_t *edid, |
1711 | int len, |
1712 | struct dc_sink_init_data *init_data); |
1713 | |
1714 | /* Remove remote sink from a link with dc_connection_mst_branch connection type. |
1715 | * @link - link the sink should be removed from |
1716 | * @sink - sink to be removed. |
1717 | */ |
1718 | void dc_link_remove_remote_sink( |
1719 | struct dc_link *link, |
1720 | struct dc_sink *sink); |
1721 | |
1722 | /* Enable HPD interrupt handler for a given link */ |
1723 | void dc_link_enable_hpd(const struct dc_link *link); |
1724 | |
1725 | /* Disable HPD interrupt handler for a given link */ |
1726 | void dc_link_disable_hpd(const struct dc_link *link); |
1727 | |
1728 | /* determine if there is a sink connected to the link |
1729 | * |
1730 | * @type - dc_connection_single if connected, dc_connection_none otherwise. |
1731 | * return - false if an unexpected error occurs, true otherwise. |
1732 | * |
1733 | * NOTE: This function doesn't detect downstream sink connections i.e |
1734 | * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will |
1735 | * return dc_connection_single if the branch device is connected despite of |
1736 | * downstream sink's connection status. |
1737 | */ |
1738 | bool dc_link_detect_connection_type(struct dc_link *link, |
1739 | enum dc_connection_type *type); |
1740 | |
1741 | /* query current hpd pin value |
1742 | * return - true HPD is asserted (HPD high), false otherwise (HPD low) |
1743 | * |
1744 | */ |
1745 | bool dc_link_get_hpd_state(struct dc_link *link); |
1746 | |
1747 | /* Getter for cached link status from given link */ |
1748 | const struct dc_link_status *dc_link_get_status(const struct dc_link *link); |
1749 | |
1750 | /* enable/disable hardware HPD filter. |
1751 | * |
1752 | * @link - The link the HPD pin is associated with. |
1753 | * @enable = true - enable hardware HPD filter. HPD event will only queued to irq |
1754 | * handler once after no HPD change has been detected within dc default HPD |
1755 | * filtering interval since last HPD event. i.e if display keeps toggling hpd |
1756 | * pulses within default HPD interval, no HPD event will be received until HPD |
1757 | * toggles have stopped. Then HPD event will be queued to irq handler once after |
1758 | * dc default HPD filtering interval since last HPD event. |
1759 | * |
1760 | * @enable = false - disable hardware HPD filter. HPD event will be queued |
1761 | * immediately to irq handler after no HPD change has been detected within |
1762 | * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). |
1763 | */ |
1764 | void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); |
1765 | |
1766 | /* submit i2c read/write payloads through ddc channel |
1767 | * @link_index - index to a link with ddc in i2c mode |
1768 | * @cmd - i2c command structure |
1769 | * return - true if success, false otherwise. |
1770 | */ |
1771 | bool dc_submit_i2c( |
1772 | struct dc *dc, |
1773 | uint32_t link_index, |
1774 | struct i2c_command *cmd); |
1775 | |
1776 | /* submit i2c read/write payloads through oem channel |
1777 | * @link_index - index to a link with ddc in i2c mode |
1778 | * @cmd - i2c command structure |
1779 | * return - true if success, false otherwise. |
1780 | */ |
1781 | bool dc_submit_i2c_oem( |
1782 | struct dc *dc, |
1783 | struct i2c_command *cmd); |
1784 | |
1785 | enum aux_return_code_type; |
1786 | /* Attempt to transfer the given aux payload. This function does not perform |
1787 | * retries or handle error states. The reply is returned in the payload->reply |
1788 | * and the result through operation_result. Returns the number of bytes |
1789 | * transferred,or -1 on a failure. |
1790 | */ |
1791 | int dc_link_aux_transfer_raw(struct ddc_service *ddc, |
1792 | struct aux_payload *payload, |
1793 | enum aux_return_code_type *operation_result); |
1794 | |
1795 | bool dc_is_oem_i2c_device_present( |
1796 | struct dc *dc, |
1797 | size_t slave_address |
1798 | ); |
1799 | |
1800 | /* return true if the connected receiver supports the hdcp version */ |
1801 | bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); |
1802 | bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); |
1803 | |
1804 | /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). |
1805 | * |
1806 | * TODO - When defer_handling is true the function will have a different purpose. |
1807 | * It no longer does complete hpd rx irq handling. We should create a separate |
1808 | * interface specifically for this case. |
1809 | * |
1810 | * Return: |
1811 | * true - Downstream port status changed. DM should call DC to do the |
1812 | * detection. |
1813 | * false - no change in Downstream port status. No further action required |
1814 | * from DM. |
1815 | */ |
1816 | bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, |
1817 | union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, |
1818 | bool defer_handling, bool *has_left_work); |
1819 | /* handle DP specs define test automation sequence*/ |
1820 | void dc_link_dp_handle_automated_test(struct dc_link *link); |
1821 | |
1822 | /* handle DP Link loss sequence and try to recover RX link loss with best |
1823 | * effort |
1824 | */ |
1825 | void dc_link_dp_handle_link_loss(struct dc_link *link); |
1826 | |
1827 | /* Determine if hpd rx irq should be handled or ignored |
1828 | * return true - hpd rx irq should be handled. |
1829 | * return false - it is safe to ignore hpd rx irq event |
1830 | */ |
1831 | bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); |
1832 | |
1833 | /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. |
1834 | * @link - link the hpd irq data associated with |
1835 | * @hpd_irq_dpcd_data - input hpd irq data |
1836 | * return - true if hpd irq data indicates a link lost |
1837 | */ |
1838 | bool dc_link_check_link_loss_status(struct dc_link *link, |
1839 | union hpd_irq_data *hpd_irq_dpcd_data); |
1840 | |
1841 | /* Read hpd rx irq data from a given link |
1842 | * @link - link where the hpd irq data should be read from |
1843 | * @irq_data - output hpd irq data |
1844 | * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data |
1845 | * read has failed. |
1846 | */ |
1847 | enum dc_status dc_link_dp_read_hpd_rx_irq_data( |
1848 | struct dc_link *link, |
1849 | union hpd_irq_data *irq_data); |
1850 | |
1851 | /* The function clears recorded DP RX states in the link. DM should call this |
1852 | * function when it is resuming from S3 power state to previously connected links. |
1853 | * |
1854 | * TODO - in the future we should consider to expand link resume interface to |
1855 | * support clearing previous rx states. So we don't have to rely on dm to call |
1856 | * this interface explicitly. |
1857 | */ |
1858 | void dc_link_clear_dprx_states(struct dc_link *link); |
1859 | |
1860 | /* Destruct the mst topology of the link and reset the allocated payload table |
1861 | * |
1862 | * NOTE: this should only be called if DM chooses not to call dc_link_detect but |
1863 | * still wants to reset MST topology on an unplug event */ |
1864 | bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); |
1865 | |
1866 | /* The function calculates effective DP link bandwidth when a given link is |
1867 | * using the given link settings. |
1868 | * |
1869 | * return - total effective link bandwidth in kbps. |
1870 | */ |
1871 | uint32_t dc_link_bandwidth_kbps( |
1872 | const struct dc_link *link, |
1873 | const struct dc_link_settings *link_setting); |
1874 | |
1875 | /* The function takes a snapshot of current link resource allocation state |
1876 | * @dc: pointer to dc of the dm calling this |
1877 | * @map: a dc link resource snapshot defined internally to dc. |
1878 | * |
1879 | * DM needs to capture a snapshot of current link resource allocation mapping |
1880 | * and store it in its persistent storage. |
1881 | * |
1882 | * Some of the link resource is using first come first serve policy. |
1883 | * The allocation mapping depends on original hotplug order. This information |
1884 | * is lost after driver is loaded next time. The snapshot is used in order to |
1885 | * restore link resource to its previous state so user will get consistent |
1886 | * link capability allocation across reboot. |
1887 | * |
1888 | */ |
1889 | void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); |
1890 | |
1891 | /* This function restores link resource allocation state from a snapshot |
1892 | * @dc: pointer to dc of the dm calling this |
1893 | * @map: a dc link resource snapshot defined internally to dc. |
1894 | * |
1895 | * DM needs to call this function after initial link detection on boot and |
1896 | * before first commit streams to restore link resource allocation state |
1897 | * from previous boot session. |
1898 | * |
1899 | * Some of the link resource is using first come first serve policy. |
1900 | * The allocation mapping depends on original hotplug order. This information |
1901 | * is lost after driver is loaded next time. The snapshot is used in order to |
1902 | * restore link resource to its previous state so user will get consistent |
1903 | * link capability allocation across reboot. |
1904 | * |
1905 | */ |
1906 | void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); |
1907 | |
1908 | /* TODO: this is not meant to be exposed to DM. Should switch to stream update |
1909 | * interface i.e stream_update->dsc_config |
1910 | */ |
1911 | bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); |
1912 | |
1913 | /* translate a raw link rate data to bandwidth in kbps */ |
1914 | uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); |
1915 | |
1916 | /* determine the optimal bandwidth given link and required bw. |
1917 | * @link - current detected link |
1918 | * @req_bw - requested bandwidth in kbps |
1919 | * @link_settings - returned most optimal link settings that can fit the |
1920 | * requested bandwidth |
1921 | * return - false if link can't support requested bandwidth, true if link |
1922 | * settings is found. |
1923 | */ |
1924 | bool dc_link_decide_edp_link_settings(struct dc_link *link, |
1925 | struct dc_link_settings *link_settings, |
1926 | uint32_t req_bw); |
1927 | |
1928 | /* return the max dp link settings can be driven by the link without considering |
1929 | * connected RX device and its capability |
1930 | */ |
1931 | bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, |
1932 | struct dc_link_settings *max_link_enc_cap); |
1933 | |
1934 | /* determine when the link is driving MST mode, what DP link channel coding |
1935 | * format will be used. The decision will remain unchanged until next HPD event. |
1936 | * |
1937 | * @link - a link with DP RX connection |
1938 | * return - if stream is committed to this link with MST signal type, type of |
1939 | * channel coding format dc will choose. |
1940 | */ |
1941 | enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( |
1942 | const struct dc_link *link); |
1943 | |
1944 | /* get max dp link settings the link can enable with all things considered. (i.e |
1945 | * TX/RX/Cable capabilities and dp override policies. |
1946 | * |
1947 | * @link - a link with DP RX connection |
1948 | * return - max dp link settings the link can enable. |
1949 | * |
1950 | */ |
1951 | const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); |
1952 | |
1953 | /* Get the highest encoding format that the link supports; highest meaning the |
1954 | * encoding format which supports the maximum bandwidth. |
1955 | * |
1956 | * @link - a link with DP RX connection |
1957 | * return - highest encoding format link supports. |
1958 | */ |
1959 | enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); |
1960 | |
1961 | /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected |
1962 | * to a link with dp connector signal type. |
1963 | * @link - a link with dp connector signal type |
1964 | * return - true if connected, false otherwise |
1965 | */ |
1966 | bool dc_link_is_dp_sink_present(struct dc_link *link); |
1967 | |
1968 | /* Force DP lane settings update to main-link video signal and notify the change |
1969 | * to DP RX via DPCD. This is a debug interface used for video signal integrity |
1970 | * tuning purpose. The interface assumes link has already been enabled with DP |
1971 | * signal. |
1972 | * |
1973 | * @lt_settings - a container structure with desired hw_lane_settings |
1974 | */ |
1975 | void dc_link_set_drive_settings(struct dc *dc, |
1976 | struct link_training_settings *lt_settings, |
1977 | struct dc_link *link); |
1978 | |
1979 | /* Enable a test pattern in Link or PHY layer in an active link for compliance |
1980 | * test or debugging purpose. The test pattern will remain until next un-plug. |
1981 | * |
1982 | * @link - active link with DP signal output enabled. |
1983 | * @test_pattern - desired test pattern to output. |
1984 | * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. |
1985 | * @test_pattern_color_space - for video test pattern choose a desired color |
1986 | * space. |
1987 | * @p_link_settings - For PHY pattern choose a desired link settings |
1988 | * @p_custom_pattern - some test pattern will require a custom input to |
1989 | * customize some pattern details. Otherwise keep it to NULL. |
1990 | * @cust_pattern_size - size of the custom pattern input. |
1991 | * |
1992 | */ |
1993 | bool dc_link_dp_set_test_pattern( |
1994 | struct dc_link *link, |
1995 | enum dp_test_pattern test_pattern, |
1996 | enum dp_test_pattern_color_space test_pattern_color_space, |
1997 | const struct link_training_settings *p_link_settings, |
1998 | const unsigned char *p_custom_pattern, |
1999 | unsigned int cust_pattern_size); |
2000 | |
2001 | /* Force DP link settings to always use a specific value until reboot to a |
2002 | * specific link. If link has already been enabled, the interface will also |
2003 | * switch to desired link settings immediately. This is a debug interface to |
2004 | * generic dp issue trouble shooting. |
2005 | */ |
2006 | void dc_link_set_preferred_link_settings(struct dc *dc, |
2007 | struct dc_link_settings *link_setting, |
2008 | struct dc_link *link); |
2009 | |
2010 | /* Force DP link to customize a specific link training behavior by overriding to |
2011 | * standard DP specs defined protocol. This is a debug interface to trouble shoot |
2012 | * display specific link training issues or apply some display specific |
2013 | * workaround in link training. |
2014 | * |
2015 | * @link_settings - if not NULL, force preferred link settings to the link. |
2016 | * @lt_override - a set of override pointers. If any pointer is none NULL, dc |
2017 | * will apply this particular override in future link training. If NULL is |
2018 | * passed in, dc resets previous overrides. |
2019 | * NOTE: DM must keep the memory from override pointers until DM resets preferred |
2020 | * training settings. |
2021 | */ |
2022 | void dc_link_set_preferred_training_settings(struct dc *dc, |
2023 | struct dc_link_settings *link_setting, |
2024 | struct dc_link_training_overrides *lt_overrides, |
2025 | struct dc_link *link, |
2026 | bool skip_immediate_retrain); |
2027 | |
2028 | /* return - true if FEC is supported with connected DP RX, false otherwise */ |
2029 | bool dc_link_is_fec_supported(const struct dc_link *link); |
2030 | |
2031 | /* query FEC enablement policy to determine if FEC will be enabled by dc during |
2032 | * link enablement. |
2033 | * return - true if FEC should be enabled, false otherwise. |
2034 | */ |
2035 | bool dc_link_should_enable_fec(const struct dc_link *link); |
2036 | |
2037 | /* determine lttpr mode the current link should be enabled with a specific link |
2038 | * settings. |
2039 | */ |
2040 | enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, |
2041 | struct dc_link_settings *link_setting); |
2042 | |
2043 | /* Force DP RX to update its power state. |
2044 | * NOTE: this interface doesn't update dp main-link. Calling this function will |
2045 | * cause DP TX main-link and DP RX power states out of sync. DM has to restore |
2046 | * RX power state back upon finish DM specific execution requiring DP RX in a |
2047 | * specific power state. |
2048 | * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power |
2049 | * state. |
2050 | */ |
2051 | void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); |
2052 | |
2053 | /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite |
2054 | * current value read from extended receiver cap from 02200h - 0220Fh. |
2055 | * Some DP RX has problems of providing accurate DP receiver caps from extended |
2056 | * field, this interface is a workaround to revert link back to use base caps. |
2057 | */ |
2058 | void dc_link_overwrite_extended_receiver_cap( |
2059 | struct dc_link *link); |
2060 | |
2061 | void dc_link_edp_panel_backlight_power_on(struct dc_link *link, |
2062 | bool wait_for_hpd); |
2063 | |
2064 | /* Set backlight level of an embedded panel (eDP, LVDS). |
2065 | * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer |
2066 | * and 16 bit fractional, where 1.0 is max backlight value. |
2067 | */ |
2068 | bool dc_link_set_backlight_level(const struct dc_link *dc_link, |
2069 | uint32_t backlight_pwm_u16_16, |
2070 | uint32_t frame_ramp); |
2071 | |
2072 | /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ |
2073 | bool dc_link_set_backlight_level_nits(struct dc_link *link, |
2074 | bool isHDR, |
2075 | uint32_t backlight_millinits, |
2076 | uint32_t transition_time_in_ms); |
2077 | |
2078 | bool dc_link_get_backlight_level_nits(struct dc_link *link, |
2079 | uint32_t *backlight_millinits, |
2080 | uint32_t *backlight_millinits_peak); |
2081 | |
2082 | int dc_link_get_backlight_level(const struct dc_link *dc_link); |
2083 | |
2084 | int dc_link_get_target_backlight_pwm(const struct dc_link *link); |
2085 | |
2086 | bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, |
2087 | bool wait, bool force_static, const unsigned int *power_opts); |
2088 | |
2089 | bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); |
2090 | |
2091 | bool dc_link_setup_psr(struct dc_link *dc_link, |
2092 | const struct dc_stream_state *stream, struct psr_config *psr_config, |
2093 | struct psr_context *psr_context); |
2094 | |
2095 | bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); |
2096 | |
2097 | /* On eDP links this function call will stall until T12 has elapsed. |
2098 | * If the panel is not in power off state, this function will return |
2099 | * immediately. |
2100 | */ |
2101 | bool dc_link_wait_for_t12(struct dc_link *link); |
2102 | |
2103 | /* Determine if dp trace has been initialized to reflect upto date result * |
2104 | * return - true if trace is initialized and has valid data. False dp trace |
2105 | * doesn't have valid result. |
2106 | */ |
2107 | bool dc_dp_trace_is_initialized(struct dc_link *link); |
2108 | |
2109 | /* Query a dp trace flag to indicate if the current dp trace data has been |
2110 | * logged before |
2111 | */ |
2112 | bool dc_dp_trace_is_logged(struct dc_link *link, |
2113 | bool in_detection); |
2114 | |
2115 | /* Set dp trace flag to indicate whether DM has already logged the current dp |
2116 | * trace data. DM can set is_logged to true upon logging and check |
2117 | * dc_dp_trace_is_logged before logging to avoid logging the same result twice. |
2118 | */ |
2119 | void dc_dp_trace_set_is_logged_flag(struct dc_link *link, |
2120 | bool in_detection, |
2121 | bool is_logged); |
2122 | |
2123 | /* Obtain driver time stamp for last dp link training end. The time stamp is |
2124 | * formatted based on dm_get_timestamp DM function. |
2125 | * @in_detection - true to get link training end time stamp of last link |
2126 | * training in detection sequence. false to get link training end time stamp |
2127 | * of last link training in commit (dpms) sequence |
2128 | */ |
2129 | unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, |
2130 | bool in_detection); |
2131 | |
2132 | /* Get how many link training attempts dc has done with latest sequence. |
2133 | * @in_detection - true to get link training count of last link |
2134 | * training in detection sequence. false to get link training count of last link |
2135 | * training in commit (dpms) sequence |
2136 | */ |
2137 | const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, |
2138 | bool in_detection); |
2139 | |
2140 | /* Get how many link loss has happened since last link training attempts */ |
2141 | unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); |
2142 | |
2143 | /* |
2144 | * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS |
2145 | */ |
2146 | /* |
2147 | * Send a request from DP-Tx requesting to allocate BW remotely after |
2148 | * allocating it locally. This will get processed by CM and a CB function |
2149 | * will be called. |
2150 | * |
2151 | * @link: pointer to the dc_link struct instance |
2152 | * @req_bw: The requested bw in Kbyte to allocated |
2153 | * |
2154 | * return: none |
2155 | */ |
2156 | void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); |
2157 | |
2158 | /* |
2159 | * Handle function for when the status of the Request above is complete. |
2160 | * We will find out the result of allocating on CM and update structs. |
2161 | * |
2162 | * @link: pointer to the dc_link struct instance |
2163 | * @bw: Allocated or Estimated BW depending on the result |
2164 | * @result: Response type |
2165 | * |
2166 | * return: none |
2167 | */ |
2168 | void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, |
2169 | uint8_t bw, uint8_t result); |
2170 | |
2171 | /* |
2172 | * Handle the USB4 BW Allocation related functionality here: |
2173 | * Plug => Try to allocate max bw from timing parameters supported by the sink |
2174 | * Unplug => de-allocate bw |
2175 | * |
2176 | * @link: pointer to the dc_link struct instance |
2177 | * @peak_bw: Peak bw used by the link/sink |
2178 | * |
2179 | * return: allocated bw else return 0 |
2180 | */ |
2181 | int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( |
2182 | struct dc_link *link, int peak_bw); |
2183 | |
2184 | /* |
2185 | * Validate the BW of all the valid DPIA links to make sure it doesn't exceed |
2186 | * available BW for each host router |
2187 | * |
2188 | * @dc: pointer to dc struct |
2189 | * @stream: pointer to all possible streams |
2190 | * @num_streams: number of valid DPIA streams |
2191 | * |
2192 | * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE |
2193 | */ |
2194 | bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, |
2195 | const unsigned int count); |
2196 | |
2197 | /* Sink Interfaces - A sink corresponds to a display output device */ |
2198 | |
2199 | struct dc_container_id { |
2200 | // 128bit GUID in binary form |
2201 | unsigned char guid[16]; |
2202 | // 8 byte port ID -> ELD.PortID |
2203 | unsigned int portId[2]; |
2204 | // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName |
2205 | unsigned short manufacturerName; |
2206 | // 2 byte product code -> ELD.ProductCode |
2207 | unsigned short productCode; |
2208 | }; |
2209 | |
2210 | |
2211 | struct dc_sink_dsc_caps { |
2212 | // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), |
2213 | // 'false' if they are sink's DSC caps |
2214 | bool is_virtual_dpcd_dsc; |
2215 | #if defined(CONFIG_DRM_AMD_DC_FP) |
2216 | // 'true' if MST topology supports DSC passthrough for sink |
2217 | // 'false' if MST topology does not support DSC passthrough |
2218 | bool is_dsc_passthrough_supported; |
2219 | #endif |
2220 | struct dsc_dec_dpcd_caps dsc_dec_caps; |
2221 | }; |
2222 | |
2223 | struct dc_sink_fec_caps { |
2224 | bool is_rx_fec_supported; |
2225 | bool is_topology_fec_supported; |
2226 | }; |
2227 | |
2228 | struct scdc_caps { |
2229 | union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; |
2230 | union hdmi_scdc_device_id_data device_id; |
2231 | }; |
2232 | |
2233 | /* |
2234 | * The sink structure contains EDID and other display device properties |
2235 | */ |
2236 | struct dc_sink { |
2237 | enum signal_type sink_signal; |
2238 | struct dc_edid dc_edid; /* raw edid */ |
2239 | struct dc_edid_caps edid_caps; /* parse display caps */ |
2240 | struct dc_container_id *dc_container_id; |
2241 | uint32_t dongle_max_pix_clk; |
2242 | void *priv; |
2243 | struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; |
2244 | bool converter_disable_audio; |
2245 | |
2246 | struct scdc_caps scdc_caps; |
2247 | struct dc_sink_dsc_caps dsc_caps; |
2248 | struct dc_sink_fec_caps fec_caps; |
2249 | |
2250 | bool is_vsc_sdp_colorimetry_supported; |
2251 | |
2252 | /* private to DC core */ |
2253 | struct dc_link *link; |
2254 | struct dc_context *ctx; |
2255 | |
2256 | uint32_t sink_id; |
2257 | |
2258 | /* private to dc_sink.c */ |
2259 | // refcount must be the last member in dc_sink, since we want the |
2260 | // sink structure to be logically cloneable up to (but not including) |
2261 | // refcount |
2262 | struct kref refcount; |
2263 | }; |
2264 | |
2265 | void dc_sink_retain(struct dc_sink *sink); |
2266 | void dc_sink_release(struct dc_sink *sink); |
2267 | |
2268 | struct dc_sink_init_data { |
2269 | enum signal_type sink_signal; |
2270 | struct dc_link *link; |
2271 | uint32_t dongle_max_pix_clk; |
2272 | bool converter_disable_audio; |
2273 | }; |
2274 | |
2275 | struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); |
2276 | |
2277 | /* Newer interfaces */ |
2278 | struct dc_cursor { |
2279 | struct dc_plane_address address; |
2280 | struct dc_cursor_attributes attributes; |
2281 | }; |
2282 | |
2283 | |
2284 | /* Interrupt interfaces */ |
2285 | enum dc_irq_source dc_interrupt_to_irq_source( |
2286 | struct dc *dc, |
2287 | uint32_t src_id, |
2288 | uint32_t ext_id); |
2289 | bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); |
2290 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); |
2291 | enum dc_irq_source dc_get_hpd_irq_source_at_index( |
2292 | struct dc *dc, uint32_t link_index); |
2293 | |
2294 | void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); |
2295 | |
2296 | /* Power Interfaces */ |
2297 | |
2298 | void dc_set_power_state( |
2299 | struct dc *dc, |
2300 | enum dc_acpi_cm_power_state power_state); |
2301 | void dc_resume(struct dc *dc); |
2302 | |
2303 | void dc_power_down_on_boot(struct dc *dc); |
2304 | |
2305 | /* |
2306 | * HDCP Interfaces |
2307 | */ |
2308 | enum hdcp_message_status dc_process_hdcp_msg( |
2309 | enum signal_type signal, |
2310 | struct dc_link *link, |
2311 | struct hdcp_protection_message *message_info); |
2312 | bool dc_is_dmcu_initialized(struct dc *dc); |
2313 | |
2314 | enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); |
2315 | void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); |
2316 | |
2317 | bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, |
2318 | struct dc_cursor_attributes *cursor_attr); |
2319 | |
2320 | void dc_allow_idle_optimizations(struct dc *dc, bool allow); |
2321 | bool dc_dmub_is_ips_idle_state(struct dc *dc); |
2322 | |
2323 | /* set min and max memory clock to lowest and highest DPM level, respectively */ |
2324 | void dc_unlock_memory_clock_frequency(struct dc *dc); |
2325 | |
2326 | /* set min memory clock to the min required for current mode, max to maxDPM */ |
2327 | void dc_lock_memory_clock_frequency(struct dc *dc); |
2328 | |
2329 | /* set soft max for memclk, to be used for AC/DC switching clock limitations */ |
2330 | void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); |
2331 | |
2332 | /* cleanup on driver unload */ |
2333 | void dc_hardware_release(struct dc *dc); |
2334 | |
2335 | /* disables fw based mclk switch */ |
2336 | void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); |
2337 | |
2338 | bool dc_set_psr_allow_active(struct dc *dc, bool enable); |
2339 | void dc_z10_restore(const struct dc *dc); |
2340 | void dc_z10_save_init(struct dc *dc); |
2341 | |
2342 | bool dc_is_dmub_outbox_supported(struct dc *dc); |
2343 | bool dc_enable_dmub_notifications(struct dc *dc); |
2344 | |
2345 | bool dc_abm_save_restore( |
2346 | struct dc *dc, |
2347 | struct dc_stream_state *stream, |
2348 | struct abm_save_restore *pData); |
2349 | |
2350 | void dc_enable_dmub_outbox(struct dc *dc); |
2351 | |
2352 | bool dc_process_dmub_aux_transfer_async(struct dc *dc, |
2353 | uint32_t link_index, |
2354 | struct aux_payload *payload); |
2355 | |
2356 | /* Get dc link index from dpia port index */ |
2357 | uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, |
2358 | uint8_t dpia_port_index); |
2359 | |
2360 | bool dc_process_dmub_set_config_async(struct dc *dc, |
2361 | uint32_t link_index, |
2362 | struct set_config_cmd_payload *payload, |
2363 | struct dmub_notification *notify); |
2364 | |
2365 | enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, |
2366 | uint32_t link_index, |
2367 | uint8_t mst_alloc_slots, |
2368 | uint8_t *mst_slots_in_use); |
2369 | |
2370 | void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, |
2371 | uint32_t hpd_int_enable); |
2372 | |
2373 | void dc_print_dmub_diagnostic_data(const struct dc *dc); |
2374 | |
2375 | void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); |
2376 | |
2377 | struct dc_power_profile { |
2378 | int power_level; /* Lower is better */ |
2379 | }; |
2380 | |
2381 | struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); |
2382 | |
2383 | /* DSC Interfaces */ |
2384 | #include "dc_dsc.h" |
2385 | |
2386 | /* Disable acc mode Interfaces */ |
2387 | void dc_disable_accelerated_mode(struct dc *dc); |
2388 | |
2389 | bool dc_is_timing_changed(struct dc_stream_state *cur_stream, |
2390 | struct dc_stream_state *new_stream); |
2391 | |
2392 | #endif /* DC_INTERFACE_H_ */ |
2393 | |