1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dc.h"
27#include "dc_dmub_srv.h"
28#include "../dmub/dmub_srv.h"
29#include "dm_helpers.h"
30#include "dc_hw_types.h"
31#include "core_types.h"
32#include "../basics/conversion.h"
33#include "cursor_reg_cache.h"
34#include "resource.h"
35#include "clk_mgr.h"
36
37#define CTX dc_dmub_srv->ctx
38#define DC_LOGGER CTX->logger
39
40static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,
41 struct dmub_srv *dmub)
42{
43 dc_srv->dmub = dmub;
44 dc_srv->ctx = dc->ctx;
45}
46
47struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)
48{
49 struct dc_dmub_srv *dc_srv =
50 kzalloc(size: sizeof(struct dc_dmub_srv), GFP_KERNEL);
51
52 if (dc_srv == NULL) {
53 BREAK_TO_DEBUGGER();
54 return NULL;
55 }
56
57 dc_dmub_srv_construct(dc_srv, dc, dmub);
58
59 return dc_srv;
60}
61
62void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)
63{
64 if (*dmub_srv) {
65 kfree(objp: *dmub_srv);
66 *dmub_srv = NULL;
67 }
68}
69
70void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
71{
72 struct dmub_srv *dmub = dc_dmub_srv->dmub;
73 struct dc_context *dc_ctx = dc_dmub_srv->ctx;
74 enum dmub_status status;
75
76 status = dmub_srv_wait_for_idle(dmub, timeout_us: 100000);
77 if (status != DMUB_STATUS_OK) {
78 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
79 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
80 }
81}
82
83void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)
84{
85 struct dmub_srv *dmub = dc_dmub_srv->dmub;
86 struct dc_context *dc_ctx = dc_dmub_srv->ctx;
87 enum dmub_status status = DMUB_STATUS_OK;
88
89 status = dmub_srv_clear_inbox0_ack(dmub);
90 if (status != DMUB_STATUS_OK) {
91 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status);
92 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
93 }
94}
95
96void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)
97{
98 struct dmub_srv *dmub = dc_dmub_srv->dmub;
99 struct dc_context *dc_ctx = dc_dmub_srv->ctx;
100 enum dmub_status status = DMUB_STATUS_OK;
101
102 status = dmub_srv_wait_for_inbox0_ack(dmub, timeout_us: 100000);
103 if (status != DMUB_STATUS_OK) {
104 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n");
105 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
106 }
107}
108
109void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dc_dmub_srv,
110 union dmub_inbox0_data_register data)
111{
112 struct dmub_srv *dmub = dc_dmub_srv->dmub;
113 struct dc_context *dc_ctx = dc_dmub_srv->ctx;
114 enum dmub_status status = DMUB_STATUS_OK;
115
116 status = dmub_srv_send_inbox0_cmd(dmub, data);
117 if (status != DMUB_STATUS_OK) {
118 DC_ERROR("Error sending INBOX0 cmd\n");
119 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
120 }
121}
122
123bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
124{
125 return dc_dmub_srv_cmd_run_list(dc_dmub_srv, count: 1, cmd_list: cmd, wait_type);
126}
127
128bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type)
129{
130 struct dc_context *dc_ctx;
131 struct dmub_srv *dmub;
132 enum dmub_status status;
133 int i;
134
135 if (!dc_dmub_srv || !dc_dmub_srv->dmub)
136 return false;
137
138 dc_ctx = dc_dmub_srv->ctx;
139 dmub = dc_dmub_srv->dmub;
140
141 for (i = 0 ; i < count; i++) {
142 // Queue command
143 status = dmub_srv_cmd_queue(dmub, cmd: &cmd_list[i]);
144
145 if (status == DMUB_STATUS_QUEUE_FULL) {
146 /* Execute and wait for queue to become empty again. */
147 dmub_srv_cmd_execute(dmub);
148 dmub_srv_wait_for_idle(dmub, timeout_us: 100000);
149
150 /* Requeue the command. */
151 status = dmub_srv_cmd_queue(dmub, cmd: &cmd_list[i]);
152 }
153
154 if (status != DMUB_STATUS_OK) {
155 DC_ERROR("Error queueing DMUB command: status=%d\n", status);
156 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
157 return false;
158 }
159 }
160
161 status = dmub_srv_cmd_execute(dmub);
162 if (status != DMUB_STATUS_OK) {
163 DC_ERROR("Error starting DMUB execution: status=%d\n", status);
164 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
165 return false;
166 }
167
168 // Wait for DMUB to process command
169 if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {
170 status = dmub_srv_wait_for_idle(dmub, timeout_us: 100000);
171
172 if (status != DMUB_STATUS_OK) {
173 DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
174 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
175 return false;
176 }
177
178 // Copy data back from ring buffer into command
179 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
180 dmub_rb_get_return_data(rb: &dmub->inbox1_rb, cmd: cmd_list);
181 }
182
183 return true;
184}
185
186bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
187{
188 struct dmub_srv *dmub;
189 struct dc_context *dc_ctx;
190 union dmub_fw_boot_status boot_status;
191 enum dmub_status status;
192
193 if (!dc_dmub_srv || !dc_dmub_srv->dmub)
194 return false;
195
196 dmub = dc_dmub_srv->dmub;
197 dc_ctx = dc_dmub_srv->ctx;
198
199 status = dmub_srv_get_fw_boot_status(dmub, status: &boot_status);
200 if (status != DMUB_STATUS_OK) {
201 DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
202 return false;
203 }
204
205 return boot_status.bits.optimized_init_done;
206}
207
208bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
209 unsigned int stream_mask)
210{
211 struct dmub_srv *dmub;
212 const uint32_t timeout = 30;
213
214 if (!dc_dmub_srv || !dc_dmub_srv->dmub)
215 return false;
216
217 dmub = dc_dmub_srv->dmub;
218
219 return dmub_srv_send_gpint_command(
220 dmub, command_code: DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
221 param: stream_mask, timeout_us: timeout) == DMUB_STATUS_OK;
222}
223
224bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
225{
226 struct dmub_srv *dmub;
227 struct dc_context *dc_ctx;
228 union dmub_fw_boot_status boot_status;
229 enum dmub_status status;
230
231 if (!dc_dmub_srv || !dc_dmub_srv->dmub)
232 return false;
233
234 dmub = dc_dmub_srv->dmub;
235 dc_ctx = dc_dmub_srv->ctx;
236
237 status = dmub_srv_get_fw_boot_status(dmub, status: &boot_status);
238 if (status != DMUB_STATUS_OK) {
239 DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
240 return false;
241 }
242
243 return boot_status.bits.restore_required;
244}
245
246bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
247{
248 struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;
249 return dmub_srv_get_outbox0_msg(dmub, entry);
250}
251
252void dc_dmub_trace_event_control(struct dc *dc, bool enable)
253{
254 dm_helpers_dmub_outbox_interrupt_control(ctx: dc->ctx, enable);
255}
256
257void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)
258{
259 union dmub_rb_cmd cmd = { 0 };
260
261 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
262 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE;
263 cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max;
264 cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min;
265 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
266
267 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
268
269 // Send the command to the DMCUB.
270 dm_execute_dmub_cmd(ctx: dc->ctx, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT);
271}
272
273void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
274{
275 union dmub_rb_cmd cmd = { 0 };
276
277 cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
278 cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
279 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
280
281 cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
282
283 // Send the command to the DMCUB.
284 dm_execute_dmub_cmd(ctx: dc->ctx, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT);
285}
286
287static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)
288{
289 uint8_t pipes = 0;
290 int i = 0;
291
292 for (i = 0; i < MAX_PIPES; i++) {
293 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
294
295 if (pipe->stream == stream && pipe->stream_res.tg)
296 pipes = i;
297 }
298 return pipes;
299}
300
301static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,
302 struct pipe_ctx *head_pipe,
303 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data)
304{
305 int j;
306 int pipe_idx = 0;
307
308 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;
309 for (j = 0; j < dc->res_pool->pipe_count; j++) {
310 struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
311
312 if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
313 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;
314 }
315 }
316 fams_pipe_data->pipe_count = pipe_idx;
317}
318
319bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
320{
321 union dmub_rb_cmd cmd = { 0 };
322 struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data;
323 int i = 0, k = 0;
324 int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it.
325 uint8_t visual_confirm_enabled;
326 int pipe_idx = 0;
327
328 if (dc == NULL)
329 return false;
330
331 visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;
332
333 // Format command.
334 cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
335 cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL;
336 cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate;
337 cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled;
338
339 if (should_manage_pstate) {
340 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
341 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
342
343 if (!pipe->stream)
344 continue;
345
346 /* If FAMS is being used to support P-State and there is a stream
347 * that does not use FAMS, we are in an FPO + VActive scenario.
348 * Assign vactive stretch margin in this case.
349 */
350 if (!pipe->stream->fpo_in_use) {
351 cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us;
352 break;
353 }
354 pipe_idx++;
355 }
356 }
357
358 for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
359 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
360
361 if (resource_is_pipe_type(pipe_ctx: pipe, type: OTG_MASTER) && pipe->stream->fpo_in_use) {
362 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
363 uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;
364
365 config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
366 config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
367 config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
368 config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, stream: pipe->stream);
369 dc_dmub_srv_populate_fams_pipe_info(dc, context, head_pipe: pipe, fams_pipe_data: &config_data->pipe_data[k]);
370 k++;
371 }
372 }
373 cmd.fw_assisted_mclk_switch.header.payload_bytes =
374 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header);
375
376 // Send the command to the DMCUB.
377 dm_execute_dmub_cmd(ctx: dc->ctx, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT);
378
379 return true;
380}
381
382void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv)
383{
384 union dmub_rb_cmd cmd = { 0 };
385
386 if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
387 return;
388
389 memset(&cmd, 0, sizeof(cmd));
390
391 /* Prepare fw command */
392 cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS;
393 cmd.query_feature_caps.header.sub_type = 0;
394 cmd.query_feature_caps.header.ret_status = 1;
395 cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);
396
397 /* If command was processed, copy feature caps to dmub srv */
398 if (dm_execute_dmub_cmd(ctx: dc_dmub_srv->ctx, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
399 cmd.query_feature_caps.header.ret_status == 0) {
400 memcpy(&dc_dmub_srv->dmub->feature_caps,
401 &cmd.query_feature_caps.query_feature_caps_data,
402 sizeof(struct dmub_feature_caps));
403 }
404}
405
406void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)
407{
408 union dmub_rb_cmd cmd = { 0 };
409 unsigned int panel_inst = 0;
410
411 dc_get_edp_link_panel_inst(dc, link: pipe_ctx->stream->link, inst_out: &panel_inst);
412
413 memset(&cmd, 0, sizeof(cmd));
414
415 // Prepare fw command
416 cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
417 cmd.visual_confirm_color.header.sub_type = 0;
418 cmd.visual_confirm_color.header.ret_status = 1;
419 cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
420 cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
421
422 // If command was processed, copy feature caps to dmub srv
423 if (dm_execute_dmub_cmd(ctx: dc->ctx, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
424 cmd.visual_confirm_color.header.ret_status == 0) {
425 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
426 &cmd.visual_confirm_color.visual_confirm_color_data,
427 sizeof(struct dmub_visual_confirm_color));
428 }
429}
430
431/**
432 * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command
433 *
434 * @dc: [in] current dc state
435 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
436 * @vblank_pipe: [in] pipe_ctx for the DRR pipe
437 * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info
438 *
439 * Populate the DMCUB SubVP command with DRR pipe info. All the information
440 * required for calculating the SubVP + DRR microschedule is populated here.
441 *
442 * High level algorithm:
443 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
444 * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule
445 * 3. Populate the drr_info with the min and max supported vtotal values
446 */
447static void populate_subvp_cmd_drr_info(struct dc *dc,
448 struct pipe_ctx *subvp_pipe,
449 struct pipe_ctx *vblank_pipe,
450 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data)
451{
452 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
453 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
454 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
455 uint16_t drr_frame_us = 0;
456 uint16_t min_drr_supported_us = 0;
457 uint16_t max_drr_supported_us = 0;
458 uint16_t max_drr_vblank_us = 0;
459 uint16_t max_drr_mallregion_us = 0;
460 uint16_t mall_region_us = 0;
461 uint16_t prefetch_us = 0;
462 uint16_t subvp_active_us = 0;
463 uint16_t drr_active_us = 0;
464 uint16_t min_vtotal_supported = 0;
465 uint16_t max_vtotal_supported = 0;
466
467 pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;
468 pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
469 pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
470
471 drr_frame_us = div64_u64(dividend: ((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000),
472 divisor: (((uint64_t)drr_timing->pix_clk_100hz * 100)));
473 // P-State allow width and FW delays already included phantom_timing->v_addressable
474 mall_region_us = div64_u64(dividend: ((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000),
475 divisor: (((uint64_t)phantom_timing->pix_clk_100hz * 100)));
476 min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
477 min_vtotal_supported = div64_u64(dividend: ((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us),
478 divisor: (((uint64_t)drr_timing->h_total * 1000000)));
479
480 prefetch_us = div64_u64(dividend: ((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000),
481 divisor: (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
482 subvp_active_us = div64_u64(dividend: ((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000),
483 divisor: (((uint64_t)main_timing->pix_clk_100hz * 100)));
484 drr_active_us = div64_u64(dividend: ((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000),
485 divisor: (((uint64_t)drr_timing->pix_clk_100hz * 100)));
486 max_drr_vblank_us = div64_u64(dividend: (subvp_active_us - prefetch_us -
487 dc->caps.subvp_fw_processing_delay_us - drr_active_us), divisor: 2) + drr_active_us;
488 max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;
489 max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
490 max_vtotal_supported = div64_u64(dividend: ((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us),
491 divisor: (((uint64_t)drr_timing->h_total * 1000000)));
492
493 /* When calculating the max vtotal supported for SubVP + DRR cases, add
494 * margin due to possible rounding errors (being off by 1 line in the
495 * FW calculation can incorrectly push the P-State switch to wait 1 frame
496 * longer).
497 */
498 max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
499
500 pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
501 pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
502 pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
503}
504
505/**
506 * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command
507 *
508 * @dc: [in] current dc state
509 * @context: [in] new dc state
510 * @cmd: [in] DMUB cmd to be populated with SubVP info
511 * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe
512 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
513 *
514 * Populate the DMCUB SubVP command with VBLANK pipe info. All the information
515 * required to calculate the microschedule for SubVP + VBLANK case is stored in
516 * the pipe_data (subvp_data and vblank_data). Also check if the VBLANK pipe
517 * is a DRR display -- if it is make a call to populate drr_info.
518 */
519static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,
520 struct dc_state *context,
521 union dmub_rb_cmd *cmd,
522 struct pipe_ctx *vblank_pipe,
523 uint8_t cmd_pipe_index)
524{
525 uint32_t i;
526 struct pipe_ctx *pipe = NULL;
527 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
528 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
529
530 // Find the SubVP pipe
531 for (i = 0; i < dc->res_pool->pipe_count; i++) {
532 pipe = &context->res_ctx.pipe_ctx[i];
533
534 // We check for master pipe, but it shouldn't matter since we only need
535 // the pipe for timing info (stream should be same for any pipe splits)
536 if (!resource_is_pipe_type(pipe_ctx: pipe, type: OTG_MASTER) ||
537 !resource_is_pipe_type(pipe_ctx: pipe, type: DPP_PIPE))
538 continue;
539
540 // Find the SubVP pipe
541 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
542 break;
543 }
544
545 pipe_data->mode = VBLANK;
546 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
547 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
548 vblank_pipe->stream->timing.v_front_porch;
549 pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
550 pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;
551 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;
552 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;
553 pipe_data->pipe_config.vblank_data.vblank_end =
554 vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
555
556 if (vblank_pipe->stream->ignore_msa_timing_param &&
557 (vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed))
558 populate_subvp_cmd_drr_info(dc, subvp_pipe: pipe, vblank_pipe, pipe_data);
559}
560
561/**
562 * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case
563 *
564 * @dc: [in] current dc state
565 * @context: [in] new dc state
566 * @cmd: [in] DMUB cmd to be populated with SubVP info
567 * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2)
568 *
569 * For SubVP + SubVP, we use a single vertical interrupt to start the
570 * microschedule for both SubVP pipes. In order for this to work correctly, the
571 * MALL REGION of both SubVP pipes must start at the same time. This function
572 * lengthens the prefetch end to mall start delay of the SubVP pipe that has
573 * the shorter prefetch so that both MALL REGION's will start at the same time.
574 */
575static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
576 struct dc_state *context,
577 union dmub_rb_cmd *cmd,
578 struct pipe_ctx *subvp_pipes[])
579{
580 uint32_t subvp0_prefetch_us = 0;
581 uint32_t subvp1_prefetch_us = 0;
582 uint32_t prefetch_delta_us = 0;
583 struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing;
584 struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing;
585 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
586
587 subvp0_prefetch_us = div64_u64(dividend: ((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
588 (uint64_t)phantom_timing0->h_total * 1000000),
589 divisor: (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
590 subvp1_prefetch_us = div64_u64(dividend: ((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
591 (uint64_t)phantom_timing1->h_total * 1000000),
592 divisor: (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
593
594 // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
595 // should increase it's prefetch time to match the other
596 if (subvp0_prefetch_us > subvp1_prefetch_us) {
597 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
598 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
599 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
600 div64_u64(dividend: ((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
601 ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
602 divisor: ((uint64_t)phantom_timing1->h_total * 1000000));
603
604 } else if (subvp1_prefetch_us > subvp0_prefetch_us) {
605 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
606 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
607 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
608 div64_u64(dividend: ((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
609 ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
610 divisor: ((uint64_t)phantom_timing0->h_total * 1000000));
611 }
612}
613
614/**
615 * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command
616 *
617 * @dc: [in] current dc state
618 * @context: [in] new dc state
619 * @cmd: [in] DMUB cmd to be populated with SubVP info
620 * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
621 * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
622 *
623 * Populate the DMCUB SubVP command with SubVP pipe info. All the information
624 * required to calculate the microschedule for the SubVP pipe is stored in the
625 * pipe_data of the DMCUB SubVP command.
626 */
627static void populate_subvp_cmd_pipe_info(struct dc *dc,
628 struct dc_state *context,
629 union dmub_rb_cmd *cmd,
630 struct pipe_ctx *subvp_pipe,
631 uint8_t cmd_pipe_index)
632{
633 uint32_t j;
634 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
635 &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
636 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
637 struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
638 uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;
639
640 pipe_data->mode = SUBVP;
641 pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
642 pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;
643 pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;
644 pipe_data->pipe_config.subvp_data.main_vblank_start =
645 main_timing->v_total - main_timing->v_front_porch;
646 pipe_data->pipe_config.subvp_data.main_vblank_end =
647 main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
648 pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
649 pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;
650 pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param &&
651 (subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed);
652
653 /* Calculate the scaling factor from the src and dst height.
654 * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.
655 * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor"
656 *
657 * Make sure to combine stream and plane scaling together.
658 */
659 reduce_fraction(num: subvp_pipe->stream->src.height, den: subvp_pipe->stream->dst.height,
660 out_num: &out_num_stream, out_den: &out_den_stream);
661 reduce_fraction(num: subvp_pipe->plane_state->src_rect.height, den: subvp_pipe->plane_state->dst_rect.height,
662 out_num: &out_num_plane, out_den: &out_den_plane);
663 reduce_fraction(num: out_num_stream * out_num_plane, den: out_den_stream * out_den_plane, out_num: &out_num, out_den: &out_den);
664 pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
665 pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
666
667 // Prefetch lines is equal to VACTIVE + BP + VSYNC
668 pipe_data->pipe_config.subvp_data.prefetch_lines =
669 phantom_timing->v_total - phantom_timing->v_front_porch;
670
671 // Round up
672 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
673 div64_u64(dividend: ((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
674 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), divisor: ((uint64_t)phantom_timing->h_total * 1000000));
675 pipe_data->pipe_config.subvp_data.processing_delay_lines =
676 div64_u64(dividend: ((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
677 ((uint64_t)phantom_timing->h_total * 1000000 - 1)), divisor: ((uint64_t)phantom_timing->h_total * 1000000));
678
679 if (subvp_pipe->bottom_pipe) {
680 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;
681 } else if (subvp_pipe->next_odm_pipe) {
682 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
683 } else {
684 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0;
685 }
686
687 // Find phantom pipe index based on phantom stream
688 for (j = 0; j < dc->res_pool->pipe_count; j++) {
689 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
690
691 if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) {
692 pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;
693 if (phantom_pipe->bottom_pipe) {
694 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;
695 } else if (phantom_pipe->next_odm_pipe) {
696 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
697 } else {
698 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0;
699 }
700 break;
701 }
702 }
703}
704
705/**
706 * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command
707 *
708 * @dc: [in] current dc state
709 * @context: [in] new dc state
710 * @enable: [in] if true enables the pipes population
711 *
712 * This function loops through each pipe and populates the DMUB SubVP CMD info
713 * based on the pipe (e.g. SubVP, VBLANK).
714 */
715void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
716 struct dc_state *context,
717 bool enable)
718{
719 uint8_t cmd_pipe_index = 0;
720 uint32_t i, pipe_idx;
721 uint8_t subvp_count = 0;
722 union dmub_rb_cmd cmd;
723 struct pipe_ctx *subvp_pipes[2];
724 uint32_t wm_val_refclk = 0;
725
726 memset(&cmd, 0, sizeof(cmd));
727 // FW command for SUBVP
728 cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
729 cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD;
730 cmd.fw_assisted_mclk_switch_v2.header.payload_bytes =
731 sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header);
732
733 for (i = 0; i < dc->res_pool->pipe_count; i++) {
734 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
735
736 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe
737 */
738 if (resource_is_pipe_type(pipe_ctx: pipe, type: OTG_MASTER) &&
739 resource_is_pipe_type(pipe_ctx: pipe, type: DPP_PIPE) &&
740 pipe->stream->mall_stream_config.type == SUBVP_MAIN)
741 subvp_pipes[subvp_count++] = pipe;
742 }
743
744 if (enable) {
745 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd
746 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
747 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
748
749 if (!pipe->stream)
750 continue;
751
752 /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe.
753 * Any ODM or MPC splits being used in SubVP will be handled internally in
754 * populate_subvp_cmd_pipe_info
755 */
756 if (resource_is_pipe_type(pipe_ctx: pipe, type: OTG_MASTER) &&
757 resource_is_pipe_type(pipe_ctx: pipe, type: DPP_PIPE) &&
758 pipe->stream->mall_stream_config.paired_stream &&
759 pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
760 populate_subvp_cmd_pipe_info(dc, context, cmd: &cmd, subvp_pipe: pipe, cmd_pipe_index: cmd_pipe_index++);
761 } else if (resource_is_pipe_type(pipe_ctx: pipe, type: OTG_MASTER) &&
762 resource_is_pipe_type(pipe_ctx: pipe, type: DPP_PIPE) &&
763 pipe->stream->mall_stream_config.type == SUBVP_NONE) {
764 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where
765 // we run through DML without calculating "natural" P-state support
766 populate_subvp_cmd_vblank_pipe_info(dc, context, cmd: &cmd, vblank_pipe: pipe, cmd_pipe_index: cmd_pipe_index++);
767
768 }
769 pipe_idx++;
770 }
771 if (subvp_count == 2) {
772 update_subvp_prefetch_end_to_mall_start(dc, context, cmd: &cmd, subvp_pipes);
773 }
774 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
775 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;
776
777 // Store the original watermark value for this SubVP config so we can lower it when the
778 // MCLK switch starts
779 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
780 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
781
782 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
783 }
784
785 dm_execute_dmub_cmd(ctx: dc->ctx, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT);
786}
787
788bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
789{
790 if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
791 return false;
792 return dmub_srv_get_diagnostic_data(dmub: dc_dmub_srv->dmub, diag_data);
793}
794
795void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
796{
797 struct dmub_diagnostic_data diag_data = {0};
798
799 if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
800 DC_LOG_ERROR("%s: invalid parameters.", __func__);
801 return;
802 }
803
804 if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, diag_data: &diag_data)) {
805 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);
806 return;
807 }
808
809 DC_LOG_DEBUG("DMCUB STATE:");
810 DC_LOG_DEBUG(" dmcub_version : %08x", diag_data.dmcub_version);
811 DC_LOG_DEBUG(" scratch [0] : %08x", diag_data.scratch[0]);
812 DC_LOG_DEBUG(" scratch [1] : %08x", diag_data.scratch[1]);
813 DC_LOG_DEBUG(" scratch [2] : %08x", diag_data.scratch[2]);
814 DC_LOG_DEBUG(" scratch [3] : %08x", diag_data.scratch[3]);
815 DC_LOG_DEBUG(" scratch [4] : %08x", diag_data.scratch[4]);
816 DC_LOG_DEBUG(" scratch [5] : %08x", diag_data.scratch[5]);
817 DC_LOG_DEBUG(" scratch [6] : %08x", diag_data.scratch[6]);
818 DC_LOG_DEBUG(" scratch [7] : %08x", diag_data.scratch[7]);
819 DC_LOG_DEBUG(" scratch [8] : %08x", diag_data.scratch[8]);
820 DC_LOG_DEBUG(" scratch [9] : %08x", diag_data.scratch[9]);
821 DC_LOG_DEBUG(" scratch [10] : %08x", diag_data.scratch[10]);
822 DC_LOG_DEBUG(" scratch [11] : %08x", diag_data.scratch[11]);
823 DC_LOG_DEBUG(" scratch [12] : %08x", diag_data.scratch[12]);
824 DC_LOG_DEBUG(" scratch [13] : %08x", diag_data.scratch[13]);
825 DC_LOG_DEBUG(" scratch [14] : %08x", diag_data.scratch[14]);
826 DC_LOG_DEBUG(" scratch [15] : %08x", diag_data.scratch[15]);
827 DC_LOG_DEBUG(" pc : %08x", diag_data.pc);
828 DC_LOG_DEBUG(" unk_fault_addr : %08x", diag_data.undefined_address_fault_addr);
829 DC_LOG_DEBUG(" inst_fault_addr : %08x", diag_data.inst_fetch_fault_addr);
830 DC_LOG_DEBUG(" data_fault_addr : %08x", diag_data.data_write_fault_addr);
831 DC_LOG_DEBUG(" inbox1_rptr : %08x", diag_data.inbox1_rptr);
832 DC_LOG_DEBUG(" inbox1_wptr : %08x", diag_data.inbox1_wptr);
833 DC_LOG_DEBUG(" inbox1_size : %08x", diag_data.inbox1_size);
834 DC_LOG_DEBUG(" inbox0_rptr : %08x", diag_data.inbox0_rptr);
835 DC_LOG_DEBUG(" inbox0_wptr : %08x", diag_data.inbox0_wptr);
836 DC_LOG_DEBUG(" inbox0_size : %08x", diag_data.inbox0_size);
837 DC_LOG_DEBUG(" is_enabled : %d", diag_data.is_dmcub_enabled);
838 DC_LOG_DEBUG(" is_soft_reset : %d", diag_data.is_dmcub_soft_reset);
839 DC_LOG_DEBUG(" is_secure_reset : %d", diag_data.is_dmcub_secure_reset);
840 DC_LOG_DEBUG(" is_traceport_en : %d", diag_data.is_traceport_en);
841 DC_LOG_DEBUG(" is_cw0_en : %d", diag_data.is_cw0_enabled);
842 DC_LOG_DEBUG(" is_cw6_en : %d", diag_data.is_cw6_enabled);
843}
844
845static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
846{
847 struct pipe_ctx *test_pipe, *split_pipe;
848 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data;
849 struct rect r1 = scl_data->recout, r2, r2_half;
850 int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b;
851 int cur_layer = pipe_ctx->plane_state->layer_index;
852
853 /**
854 * Disable the cursor if there's another pipe above this with a
855 * plane that contains this pipe's viewport to prevent double cursor
856 * and incorrect scaling artifacts.
857 */
858 for (test_pipe = pipe_ctx->top_pipe; test_pipe;
859 test_pipe = test_pipe->top_pipe) {
860 // Skip invisible layer and pipe-split plane on same layer
861 if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer)
862 continue;
863
864 r2 = test_pipe->plane_res.scl_data.recout;
865 r2_r = r2.x + r2.width;
866 r2_b = r2.y + r2.height;
867 split_pipe = test_pipe;
868
869 /**
870 * There is another half plane on same layer because of
871 * pipe-split, merge together per same height.
872 */
873 for (split_pipe = pipe_ctx->top_pipe; split_pipe;
874 split_pipe = split_pipe->top_pipe)
875 if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {
876 r2_half = split_pipe->plane_res.scl_data.recout;
877 r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x;
878 r2.width = r2.width + r2_half.width;
879 r2_r = r2.x + r2.width;
880 break;
881 }
882
883 if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b)
884 return true;
885 }
886
887 return false;
888}
889
890static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)
891{
892 if (pipe_ctx->plane_state != NULL) {
893 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
894 return false;
895
896 if (dc_can_pipe_disable_cursor(pipe_ctx))
897 return false;
898 }
899
900 if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
901 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&
902 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)
903 return true;
904
905 if (pipe_ctx->stream->link->replay_settings.config.replay_supported)
906 return true;
907
908 return false;
909}
910
911static void dc_build_cursor_update_payload0(
912 struct pipe_ctx *pipe_ctx, uint8_t p_idx,
913 struct dmub_cmd_update_cursor_payload0 *payload)
914{
915 struct hubp *hubp = pipe_ctx->plane_res.hubp;
916 unsigned int panel_inst = 0;
917
918 if (!dc_get_edp_link_panel_inst(dc: hubp->ctx->dc,
919 link: pipe_ctx->stream->link, inst_out: &panel_inst))
920 return;
921
922 /* Payload: Cursor Rect is built from position & attribute
923 * x & y are obtained from postion
924 */
925 payload->cursor_rect.x = hubp->cur_rect.x;
926 payload->cursor_rect.y = hubp->cur_rect.y;
927 /* w & h are obtained from attribute */
928 payload->cursor_rect.width = hubp->cur_rect.w;
929 payload->cursor_rect.height = hubp->cur_rect.h;
930
931 payload->enable = hubp->pos.cur_ctl.bits.cur_enable;
932 payload->pipe_idx = p_idx;
933 payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
934 payload->panel_inst = panel_inst;
935}
936
937static void dc_build_cursor_position_update_payload0(
938 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx,
939 const struct hubp *hubp, const struct dpp *dpp)
940{
941 /* Hubp */
942 pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw;
943 pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;
944 pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;
945 pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;
946
947 /* dpp */
948 pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;
949 pl->position_cfg.pipe_idx = p_idx;
950}
951
952static void dc_build_cursor_attribute_update_payload1(
953 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx,
954 const struct hubp *hubp, const struct dpp *dpp)
955{
956 /* Hubp */
957 pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;
958 pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;
959 pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw;
960 pl_A->aHubp.size.raw = hubp->att.size.raw;
961 pl_A->aHubp.settings.raw = hubp->att.settings.raw;
962
963 /* dpp */
964 pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;
965}
966
967/**
968 * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command
969 *
970 * @pCtx: [in] pipe context
971 * @pipe_idx: [in] pipe index
972 *
973 * This function would store the cursor related information and pass it into
974 * dmub
975 */
976void dc_send_update_cursor_info_to_dmu(
977 struct pipe_ctx *pCtx, uint8_t pipe_idx)
978{
979 union dmub_rb_cmd cmd[2];
980 union dmub_cmd_update_cursor_info_data *update_cursor_info_0 =
981 &cmd[0].update_cursor_info.update_cursor_info_data;
982
983 memset(cmd, 0, sizeof(cmd));
984
985 if (!dc_dmub_should_update_cursor_data(pipe_ctx: pCtx))
986 return;
987 /*
988 * Since we use multi_cmd_pending for dmub command, the 2nd command is
989 * only assigned to store cursor attributes info.
990 * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other
991 * is to store cursor position info.
992 *
993 * Command heaer type must be the same type if using multi_cmd_pending.
994 * Besides, while process 2nd command in DMU, the sub type is useless.
995 * So it's meanless to pass the sub type header with different type.
996 */
997
998 {
999 /* Build Payload#0 Header */
1000 cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1001 cmd[0].update_cursor_info.header.payload_bytes =
1002 sizeof(cmd[0].update_cursor_info.update_cursor_info_data);
1003 cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd
1004
1005 /* Prepare Payload */
1006 dc_build_cursor_update_payload0(pipe_ctx: pCtx, p_idx: pipe_idx, payload: &update_cursor_info_0->payload0);
1007
1008 dc_build_cursor_position_update_payload0(pl: &update_cursor_info_0->payload0, p_idx: pipe_idx,
1009 hubp: pCtx->plane_res.hubp, dpp: pCtx->plane_res.dpp);
1010 }
1011 {
1012 /* Build Payload#1 Header */
1013 cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1014 cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg);
1015 cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command.
1016
1017 dc_build_cursor_attribute_update_payload1(
1018 pl_A: &cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg,
1019 p_idx: pipe_idx, hubp: pCtx->plane_res.hubp, dpp: pCtx->plane_res.dpp);
1020
1021 /* Combine 2nd cmds update_curosr_info to DMU */
1022 dm_execute_dmub_cmd_list(ctx: pCtx->stream->ctx, count: 2, cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT);
1023 }
1024}
1025
1026bool dc_dmub_check_min_version(struct dmub_srv *srv)
1027{
1028 if (!srv->hw_funcs.is_psrsu_supported)
1029 return true;
1030 return srv->hw_funcs.is_psrsu_supported(srv);
1031}
1032
1033void dc_dmub_srv_enable_dpia_trace(const struct dc *dc)
1034{
1035 struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;
1036 struct dmub_srv *dmub;
1037 enum dmub_status status;
1038 static const uint32_t timeout_us = 30;
1039
1040 if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
1041 DC_LOG_ERROR("%s: invalid parameters.", __func__);
1042 return;
1043 }
1044
1045 dmub = dc_dmub_srv->dmub;
1046
1047 status = dmub_srv_send_gpint_command(dmub, command_code: DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1, param: 0x0010, timeout_us);
1048 if (status != DMUB_STATUS_OK) {
1049 DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1050 return;
1051 }
1052
1053 status = dmub_srv_send_gpint_command(dmub, command_code: DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK, param: 0x0000, timeout_us);
1054 if (status != DMUB_STATUS_OK) {
1055 DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1056 return;
1057 }
1058
1059 DC_LOG_DEBUG("Enabled DPIA trace\n");
1060}
1061
1062void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index)
1063{
1064 dmub_srv_subvp_save_surf_addr(dmub: dc_dmub_srv->dmub, addr, subvp_index);
1065}
1066
1067bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)
1068{
1069 struct dc_context *dc_ctx = dc_dmub_srv->ctx;
1070 enum dmub_status status;
1071
1072 if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
1073 return true;
1074
1075 if (wait) {
1076 status = dmub_srv_wait_for_hw_pwr_up(dmub: dc_dmub_srv->dmub, timeout_us: 500000);
1077 if (status != DMUB_STATUS_OK) {
1078 DC_ERROR("Error querying DMUB hw power up status: error=%d\n", status);
1079 return false;
1080 }
1081 } else
1082 return dmub_srv_is_hw_pwr_up(dmub: dc_dmub_srv->dmub);
1083
1084 return true;
1085}
1086
1087void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
1088{
1089 union dmub_rb_cmd cmd = {0};
1090
1091 if (dc->debug.dmcub_emulation)
1092 return;
1093
1094 memset(&cmd, 0, sizeof(cmd));
1095 cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT;
1096 cmd.idle_opt_notify_idle.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE;
1097 cmd.idle_opt_notify_idle.header.payload_bytes =
1098 sizeof(cmd.idle_opt_notify_idle) -
1099 sizeof(cmd.idle_opt_notify_idle.header);
1100
1101 cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;
1102
1103 if (allow_idle) {
1104 if (dc->hwss.set_idle_state)
1105 dc->hwss.set_idle_state(dc, true);
1106 }
1107
1108 dm_execute_dmub_cmd(ctx: dc->ctx, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT);
1109}
1110
1111void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
1112{
1113 const uint32_t max_num_polls = 10000;
1114 uint32_t allow_state = 0;
1115 uint32_t commit_state = 0;
1116 uint32_t i;
1117
1118 if (dc->debug.dmcub_emulation)
1119 return;
1120
1121 if (!dc->idle_optimizations_allowed)
1122 return;
1123
1124 if (dc->hwss.get_idle_state &&
1125 dc->hwss.set_idle_state &&
1126 dc->clk_mgr->funcs->exit_low_power_state) {
1127
1128 allow_state = dc->hwss.get_idle_state(dc);
1129 dc->hwss.set_idle_state(dc, false);
1130
1131 if (allow_state & DMUB_IPS2_ALLOW_MASK) {
1132 // Wait for evaluation time
1133 udelay(dc->debug.ips2_eval_delay_us);
1134 commit_state = dc->hwss.get_idle_state(dc);
1135 if (commit_state & DMUB_IPS2_COMMIT_MASK) {
1136 // Tell PMFW to exit low power state
1137 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1138
1139 // Wait for IPS2 entry upper bound
1140 udelay(dc->debug.ips2_entry_delay_us);
1141 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1142
1143 for (i = 0; i < max_num_polls; ++i) {
1144 commit_state = dc->hwss.get_idle_state(dc);
1145 if (!(commit_state & DMUB_IPS2_COMMIT_MASK))
1146 break;
1147
1148 udelay(1);
1149 }
1150 ASSERT(i < max_num_polls);
1151
1152 if (!dc_dmub_srv_is_hw_pwr_up(dc_dmub_srv: dc->ctx->dmub_srv, wait: true))
1153 ASSERT(0);
1154
1155 /* TODO: See if we can return early here - IPS2 should go
1156 * back directly to IPS0 and clear the flags, but it will
1157 * be safer to directly notify DMCUB of this.
1158 */
1159 allow_state = dc->hwss.get_idle_state(dc);
1160 }
1161 }
1162
1163 dc_dmub_srv_notify_idle(dc, allow_idle: false);
1164 if (allow_state & DMUB_IPS1_ALLOW_MASK) {
1165 for (i = 0; i < max_num_polls; ++i) {
1166 commit_state = dc->hwss.get_idle_state(dc);
1167 if (!(commit_state & DMUB_IPS1_COMMIT_MASK))
1168 break;
1169
1170 udelay(1);
1171 }
1172 ASSERT(i < max_num_polls);
1173 }
1174 }
1175
1176 if (!dc_dmub_srv_is_hw_pwr_up(dc_dmub_srv: dc->ctx->dmub_srv, wait: true))
1177 ASSERT(0);
1178}
1179
1180

source code of linux/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c