1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#ifndef DC_TYPES_H_
26#define DC_TYPES_H_
27
28/* AND EdidUtility only needs a portion
29 * of this file, including the rest only
30 * causes additional issues.
31 */
32#include "os_types.h"
33#include "fixed31_32.h"
34#include "irq_types.h"
35#include "dc_ddc_types.h"
36#include "dc_dp_types.h"
37#include "dc_hdmi_types.h"
38#include "dc_hw_types.h"
39#include "dal_types.h"
40#include "grph_object_defs.h"
41#include "grph_object_ctrl_defs.h"
42
43#include "dm_cp_psp.h"
44
45/* forward declarations */
46struct dc_plane_state;
47struct dc_stream_state;
48struct dc_link;
49struct dc_sink;
50struct dal;
51struct dc_dmub_srv;
52
53/********************************
54 * Environment definitions
55 ********************************/
56enum dce_environment {
57 DCE_ENV_PRODUCTION_DRV = 0,
58 /* Emulation on FPGA, in "Maximus" System.
59 * This environment enforces that *only* DC registers accessed.
60 * (access to non-DC registers will hang FPGA) */
61 DCE_ENV_FPGA_MAXIMUS,
62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
63 * requirements of Diagnostics team. */
64 DCE_ENV_DIAG,
65 /*
66 * Guest VM system, DC HW may exist but is not virtualized and
67 * should not be used. SW support for VDI only.
68 */
69 DCE_ENV_VIRTUAL_HW
70};
71
72struct dc_perf_trace {
73 unsigned long read_count;
74 unsigned long write_count;
75 unsigned long last_entry_read;
76 unsigned long last_entry_write;
77};
78
79#define MAX_SURFACE_NUM 6
80#define NUM_PIXEL_FORMATS 10
81
82enum tiling_mode {
83 TILING_MODE_INVALID,
84 TILING_MODE_LINEAR,
85 TILING_MODE_TILED,
86 TILING_MODE_COUNT
87};
88
89enum view_3d_format {
90 VIEW_3D_FORMAT_NONE = 0,
91 VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
92 VIEW_3D_FORMAT_SIDE_BY_SIDE,
93 VIEW_3D_FORMAT_TOP_AND_BOTTOM,
94 VIEW_3D_FORMAT_COUNT,
95 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
96};
97
98enum plane_stereo_format {
99 PLANE_STEREO_FORMAT_NONE = 0,
100 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
101 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
102 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
103 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
104 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
105 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
106};
107
108/* TODO: Find way to calculate number of bits
109 * Please increase if pixel_format enum increases
110 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
111 */
112
113enum dc_edid_connector_type {
114 DC_EDID_CONNECTOR_UNKNOWN = 0,
115 DC_EDID_CONNECTOR_ANALOG = 1,
116 DC_EDID_CONNECTOR_DIGITAL = 10,
117 DC_EDID_CONNECTOR_DVI = 11,
118 DC_EDID_CONNECTOR_HDMIA = 12,
119 DC_EDID_CONNECTOR_MDDI = 14,
120 DC_EDID_CONNECTOR_DISPLAYPORT = 15
121};
122
123enum dc_edid_status {
124 EDID_OK,
125 EDID_BAD_INPUT,
126 EDID_NO_RESPONSE,
127 EDID_BAD_CHECKSUM,
128 EDID_THE_SAME,
129 EDID_FALL_BACK,
130 EDID_PARTIAL_VALID,
131};
132
133enum act_return_status {
134 ACT_SUCCESS,
135 ACT_LINK_LOST,
136 ACT_FAILED
137};
138
139/* audio capability from EDID*/
140struct dc_cea_audio_mode {
141 uint8_t format_code; /* ucData[0] [6:3]*/
142 uint8_t channel_count; /* ucData[0] [2:0]*/
143 uint8_t sample_rate; /* ucData[1]*/
144 union {
145 uint8_t sample_size; /* for LPCM*/
146 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
147 uint8_t max_bit_rate;
148 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
149 };
150};
151
152struct dc_edid {
153 uint32_t length;
154 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
155};
156
157/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
158 * is used. In this case we assume speaker location are: front left, front
159 * right and front center. */
160#define DEFAULT_SPEAKER_LOCATION 5
161
162#define DC_MAX_AUDIO_DESC_COUNT 16
163
164#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
165
166struct dc_panel_patch {
167 unsigned int dppowerup_delay;
168 unsigned int extra_t12_ms;
169 unsigned int extra_delay_backlight_off;
170 unsigned int extra_t7_ms;
171 unsigned int skip_scdc_overwrite;
172 unsigned int delay_ignore_msa;
173 unsigned int disable_fec;
174 unsigned int extra_t3_ms;
175 unsigned int max_dsc_target_bpp_limit;
176 unsigned int embedded_tiled_slave;
177 unsigned int disable_fams;
178 unsigned int skip_avmute;
179 unsigned int mst_start_top_delay;
180};
181
182struct dc_edid_caps {
183 /* sink identification */
184 uint16_t manufacturer_id;
185 uint16_t product_id;
186 uint32_t serial_number;
187 uint8_t manufacture_week;
188 uint8_t manufacture_year;
189 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
190
191 /* audio caps */
192 uint8_t speaker_flags;
193 uint32_t audio_mode_count;
194 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
195 uint32_t audio_latency;
196 uint32_t video_latency;
197
198 uint8_t qs_bit;
199 uint8_t qy_bit;
200
201 uint32_t max_tmds_clk_mhz;
202
203 /*HDMI 2.0 caps*/
204 bool lte_340mcsc_scramble;
205
206 bool edid_hdmi;
207 bool hdr_supported;
208
209 struct dc_panel_patch panel_patch;
210};
211
212struct dc_mode_flags {
213 /* note: part of refresh rate flag*/
214 uint32_t INTERLACE :1;
215 /* native display timing*/
216 uint32_t NATIVE :1;
217 /* preferred is the recommended mode, one per display */
218 uint32_t PREFERRED :1;
219 /* true if this mode should use reduced blanking timings
220 *_not_ related to the Reduced Blanking adjustment*/
221 uint32_t REDUCED_BLANKING :1;
222 /* note: part of refreshrate flag*/
223 uint32_t VIDEO_OPTIMIZED_RATE :1;
224 /* should be reported to upper layers as mode_flags*/
225 uint32_t PACKED_PIXEL_FORMAT :1;
226 /*< preferred view*/
227 uint32_t PREFERRED_VIEW :1;
228 /* this timing should be used only in tiled mode*/
229 uint32_t TILED_MODE :1;
230 uint32_t DSE_MODE :1;
231 /* Refresh rate divider when Miracast sink is using a
232 different rate than the output display device
233 Must be zero for wired displays and non-zero for
234 Miracast displays*/
235 uint32_t MIRACAST_REFRESH_DIVIDER;
236};
237
238
239enum dc_timing_source {
240 TIMING_SOURCE_UNDEFINED,
241
242 /* explicitly specifed by user, most important*/
243 TIMING_SOURCE_USER_FORCED,
244 TIMING_SOURCE_USER_OVERRIDE,
245 TIMING_SOURCE_CUSTOM,
246 TIMING_SOURCE_EXPLICIT,
247
248 /* explicitly specified by the display device, more important*/
249 TIMING_SOURCE_EDID_CEA_SVD_3D,
250 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
251 TIMING_SOURCE_EDID_CEA_SVD_420,
252 TIMING_SOURCE_EDID_DETAILED,
253 TIMING_SOURCE_EDID_ESTABLISHED,
254 TIMING_SOURCE_EDID_STANDARD,
255 TIMING_SOURCE_EDID_CEA_SVD,
256 TIMING_SOURCE_EDID_CVT_3BYTE,
257 TIMING_SOURCE_EDID_4BYTE,
258 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB,
259 TIMING_SOURCE_EDID_CEA_RID,
260 TIMING_SOURCE_VBIOS,
261 TIMING_SOURCE_CV,
262 TIMING_SOURCE_TV,
263 TIMING_SOURCE_HDMI_VIC,
264
265 /* implicitly specified by display device, still safe but less important*/
266 TIMING_SOURCE_DEFAULT,
267
268 /* only used for custom base modes */
269 TIMING_SOURCE_CUSTOM_BASE,
270
271 /* these timing might not work, least important*/
272 TIMING_SOURCE_RANGELIMIT,
273 TIMING_SOURCE_OS_FORCED,
274 TIMING_SOURCE_IMPLICIT,
275
276 /* only used by default mode list*/
277 TIMING_SOURCE_BASICMODE,
278
279 TIMING_SOURCE_COUNT
280};
281
282
283struct stereo_3d_features {
284 bool supported ;
285 bool allTimings ;
286 bool cloneMode ;
287 bool scaling ;
288 bool singleFrameSWPacked;
289};
290
291enum dc_timing_support_method {
292 TIMING_SUPPORT_METHOD_UNDEFINED,
293 TIMING_SUPPORT_METHOD_EXPLICIT,
294 TIMING_SUPPORT_METHOD_IMPLICIT,
295 TIMING_SUPPORT_METHOD_NATIVE
296};
297
298struct dc_mode_info {
299 uint32_t pixel_width;
300 uint32_t pixel_height;
301 uint32_t field_rate;
302 /* Vertical refresh rate for progressive modes.
303 * Field rate for interlaced modes.*/
304
305 enum dc_timing_standard timing_standard;
306 enum dc_timing_source timing_source;
307 struct dc_mode_flags flags;
308};
309
310enum dc_power_state {
311 DC_POWER_STATE_ON = 1,
312 DC_POWER_STATE_STANDBY,
313 DC_POWER_STATE_SUSPEND,
314 DC_POWER_STATE_OFF
315};
316
317/* DC PowerStates */
318enum dc_video_power_state {
319 DC_VIDEO_POWER_UNSPECIFIED = 0,
320 DC_VIDEO_POWER_ON = 1,
321 DC_VIDEO_POWER_STANDBY,
322 DC_VIDEO_POWER_SUSPEND,
323 DC_VIDEO_POWER_OFF,
324 DC_VIDEO_POWER_HIBERNATE,
325 DC_VIDEO_POWER_SHUTDOWN,
326 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
327 DC_VIDEO_POWER_AFTER_RESET,
328 DC_VIDEO_POWER_MAXIMUM
329};
330
331enum dc_acpi_cm_power_state {
332 DC_ACPI_CM_POWER_STATE_D0 = 1,
333 DC_ACPI_CM_POWER_STATE_D1 = 2,
334 DC_ACPI_CM_POWER_STATE_D2 = 4,
335 DC_ACPI_CM_POWER_STATE_D3 = 8
336};
337
338enum dc_connection_type {
339 dc_connection_none,
340 dc_connection_single,
341 dc_connection_mst_branch,
342 dc_connection_sst_branch
343};
344
345struct dc_csc_adjustments {
346 struct fixed31_32 contrast;
347 struct fixed31_32 saturation;
348 struct fixed31_32 brightness;
349 struct fixed31_32 hue;
350};
351
352/* Scaling format */
353enum scaling_transformation {
354 SCALING_TRANSFORMATION_UNINITIALIZED,
355 SCALING_TRANSFORMATION_IDENTITY = 0x0001,
356 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
357 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
358 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
359 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
360 SCALING_TRANSFORMATION_INVALID = 0x80000000,
361
362 /* Flag the first and last */
363 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
364 SCALING_TRANSFORMATION_END =
365 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
366};
367
368enum display_content_type {
369 DISPLAY_CONTENT_TYPE_NO_DATA = 0,
370 DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
371 DISPLAY_CONTENT_TYPE_PHOTO = 2,
372 DISPLAY_CONTENT_TYPE_CINEMA = 4,
373 DISPLAY_CONTENT_TYPE_GAME = 8
374};
375
376enum cm_gamut_adjust_type {
377 CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
378 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
379 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */
380};
381
382struct cm_grph_csc_adjustment {
383 struct fixed31_32 temperature_matrix[12];
384 enum cm_gamut_adjust_type gamut_adjust_type;
385 enum cm_gamut_coef_format gamut_coef_format;
386};
387
388/* writeback */
389struct dwb_stereo_params {
390 bool stereo_enabled; /* false: normal mode, true: 3D stereo */
391 enum dwb_stereo_type stereo_type; /* indicates stereo format */
392 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */
393 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */
394};
395
396struct dc_dwb_cnv_params {
397 unsigned int src_width; /* input active width */
398 unsigned int src_height; /* input active height (half-active height in interlaced mode) */
399 unsigned int crop_width; /* cropped window width at cnv output */
400 bool crop_en; /* window cropping enable in cnv */
401 unsigned int crop_height; /* cropped window height at cnv output */
402 unsigned int crop_x; /* cropped window start x value at cnv output */
403 unsigned int crop_y; /* cropped window start y value at cnv output */
404 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */
405 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */
406 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */
407 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */
408 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */
409};
410
411struct dc_dwb_params {
412 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */
413 unsigned int hdr_mult; /* must be in FP1.6.12 */
414 struct cm_grph_csc_adjustment csc_params;
415 struct dwb_stereo_params stereo_params;
416 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */
417 unsigned int dest_width; /* Destination width */
418 unsigned int dest_height; /* Destination height */
419 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
420 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */
421 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */
422 struct scaling_taps scaler_taps; /* Scaling taps */
423 enum dwb_subsample_position subsample_position;
424 struct dc_transfer_func *out_transfer_func;
425};
426
427/* audio*/
428
429union audio_sample_rates {
430 struct sample_rates {
431 uint8_t RATE_32:1;
432 uint8_t RATE_44_1:1;
433 uint8_t RATE_48:1;
434 uint8_t RATE_88_2:1;
435 uint8_t RATE_96:1;
436 uint8_t RATE_176_4:1;
437 uint8_t RATE_192:1;
438 } rate;
439
440 uint8_t all;
441};
442
443struct audio_speaker_flags {
444 uint32_t FL_FR:1;
445 uint32_t LFE:1;
446 uint32_t FC:1;
447 uint32_t RL_RR:1;
448 uint32_t RC:1;
449 uint32_t FLC_FRC:1;
450 uint32_t RLC_RRC:1;
451 uint32_t SUPPORT_AI:1;
452};
453
454struct audio_speaker_info {
455 uint32_t ALLSPEAKERS:7;
456 uint32_t SUPPORT_AI:1;
457};
458
459
460struct audio_info_flags {
461
462 union {
463
464 struct audio_speaker_flags speaker_flags;
465 struct audio_speaker_info info;
466
467 uint8_t all;
468 };
469};
470
471enum audio_format_code {
472 AUDIO_FORMAT_CODE_FIRST = 1,
473 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
474
475 AUDIO_FORMAT_CODE_AC3,
476 /*Layers 1 & 2 */
477 AUDIO_FORMAT_CODE_MPEG1,
478 /*MPEG1 Layer 3 */
479 AUDIO_FORMAT_CODE_MP3,
480 /*multichannel */
481 AUDIO_FORMAT_CODE_MPEG2,
482 AUDIO_FORMAT_CODE_AAC,
483 AUDIO_FORMAT_CODE_DTS,
484 AUDIO_FORMAT_CODE_ATRAC,
485 AUDIO_FORMAT_CODE_1BITAUDIO,
486 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
487 AUDIO_FORMAT_CODE_DTS_HD,
488 AUDIO_FORMAT_CODE_MAT_MLP,
489 AUDIO_FORMAT_CODE_DST,
490 AUDIO_FORMAT_CODE_WMAPRO,
491 AUDIO_FORMAT_CODE_LAST,
492 AUDIO_FORMAT_CODE_COUNT =
493 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
494};
495
496struct audio_mode {
497 /* ucData[0] [6:3] */
498 enum audio_format_code format_code;
499 /* ucData[0] [2:0] */
500 uint8_t channel_count;
501 /* ucData[1] */
502 union audio_sample_rates sample_rates;
503 union {
504 /* for LPCM */
505 uint8_t sample_size;
506 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
507 uint8_t max_bit_rate;
508 /* for Audio Formats 9-15 */
509 uint8_t vendor_specific;
510 };
511};
512
513struct audio_info {
514 struct audio_info_flags flags;
515 uint32_t video_latency;
516 uint32_t audio_latency;
517 uint32_t display_index;
518 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
519 uint32_t manufacture_id;
520 uint32_t product_id;
521 /* PortID used for ContainerID when defined */
522 uint32_t port_id[2];
523 uint32_t mode_count;
524 /* this field must be last in this struct */
525 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
526};
527struct audio_check {
528 unsigned int audio_packet_type;
529 unsigned int max_audiosample_rate;
530 unsigned int acat;
531};
532enum dc_infoframe_type {
533 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
534 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
535 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
536 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
537 DC_DP_INFOFRAME_TYPE_PPS = 0x10,
538};
539
540struct dc_info_packet {
541 bool valid;
542 uint8_t hb0;
543 uint8_t hb1;
544 uint8_t hb2;
545 uint8_t hb3;
546 uint8_t sb[32];
547};
548
549struct dc_info_packet_128 {
550 bool valid;
551 uint8_t hb0;
552 uint8_t hb1;
553 uint8_t hb2;
554 uint8_t hb3;
555 uint8_t sb[128];
556};
557
558#define DC_PLANE_UPDATE_TIMES_MAX 10
559
560struct dc_plane_flip_time {
561 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
562 unsigned int index;
563 unsigned int prev_update_time_in_us;
564};
565
566enum dc_psr_state {
567 PSR_STATE0 = 0x0,
568 PSR_STATE1,
569 PSR_STATE1a,
570 PSR_STATE2,
571 PSR_STATE2a,
572 PSR_STATE2b,
573 PSR_STATE3,
574 PSR_STATE3Init,
575 PSR_STATE4,
576 PSR_STATE4a,
577 PSR_STATE4b,
578 PSR_STATE4c,
579 PSR_STATE4d,
580 PSR_STATE4_FULL_FRAME,
581 PSR_STATE4a_FULL_FRAME,
582 PSR_STATE4b_FULL_FRAME,
583 PSR_STATE4c_FULL_FRAME,
584 PSR_STATE4_FULL_FRAME_POWERUP,
585 PSR_STATE4_FULL_FRAME_HW_LOCK,
586 PSR_STATE5,
587 PSR_STATE5a,
588 PSR_STATE5b,
589 PSR_STATE5c,
590 PSR_STATE_HWLOCK_MGR,
591 PSR_STATE_POLLVUPDATE,
592 PSR_STATE_INVALID = 0xFF
593};
594
595struct psr_config {
596 unsigned char psr_version;
597 unsigned int psr_rfb_setup_time;
598 bool psr_exit_link_training_required;
599 bool psr_frame_capture_indication_req;
600 unsigned int psr_sdp_transmit_line_num_deadline;
601 bool allow_smu_optimizations;
602 bool allow_multi_disp_optimizations;
603 /* Panel self refresh 2 selective update granularity required */
604 bool su_granularity_required;
605 /* psr2 selective update y granularity capability */
606 uint8_t su_y_granularity;
607 unsigned int line_time_in_us;
608 uint8_t rate_control_caps;
609 uint16_t dsc_slice_height;
610};
611
612union dmcu_psr_level {
613 struct {
614 unsigned int SKIP_CRC:1;
615 unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
616 unsigned int SKIP_PHY_POWER_DOWN:1;
617 unsigned int SKIP_AUX_ACK_CHECK:1;
618 unsigned int SKIP_CRTC_DISABLE:1;
619 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
620 unsigned int SKIP_SMU_NOTIFICATION:1;
621 unsigned int SKIP_AUTO_STATE_ADVANCE:1;
622 unsigned int DISABLE_PSR_ENTRY_ABORT:1;
623 unsigned int SKIP_SINGLE_OTG_DISABLE:1;
624 unsigned int DISABLE_ALPM:1;
625 unsigned int ALPM_DEFAULT_PD_MODE:1;
626 unsigned int RESERVED:20;
627 } bits;
628 unsigned int u32all;
629};
630
631enum physical_phy_id {
632 PHYLD_0,
633 PHYLD_1,
634 PHYLD_2,
635 PHYLD_3,
636 PHYLD_4,
637 PHYLD_5,
638 PHYLD_6,
639 PHYLD_7,
640 PHYLD_8,
641 PHYLD_9,
642 PHYLD_COUNT,
643 PHYLD_UNKNOWN = (-1L)
644};
645
646enum phy_type {
647 PHY_TYPE_UNKNOWN = 1,
648 PHY_TYPE_PCIE_PHY = 2,
649 PHY_TYPE_UNIPHY = 3,
650};
651
652struct psr_context {
653 /* ddc line */
654 enum channel_id channel;
655 /* Transmitter id */
656 enum transmitter transmitterId;
657 /* Engine Id is used for Dig Be source select */
658 enum engine_id engineId;
659 /* Controller Id used for Dig Fe source select */
660 enum controller_id controllerId;
661 /* Pcie or Uniphy */
662 enum phy_type phyType;
663 /* Physical PHY Id used by SMU interpretation */
664 enum physical_phy_id smuPhyId;
665 /* Vertical total pixels from crtc timing.
666 * This is used for static screen detection.
667 * ie. If we want to detect half a frame,
668 * we use this to determine the hyst lines.
669 */
670 unsigned int crtcTimingVerticalTotal;
671 /* PSR supported from panel capabilities and
672 * current display configuration
673 */
674 bool psrSupportedDisplayConfig;
675 /* Whether fast link training is supported by the panel */
676 bool psrExitLinkTrainingRequired;
677 /* If RFB setup time is greater than the total VBLANK time,
678 * it is not possible for the sink to capture the video frame
679 * in the same frame the SDP is sent. In this case,
680 * the frame capture indication bit should be set and an extra
681 * static frame should be transmitted to the sink.
682 */
683 bool psrFrameCaptureIndicationReq;
684 /* Set the last possible line SDP may be transmitted without violating
685 * the RFB setup time or entering the active video frame.
686 */
687 unsigned int sdpTransmitLineNumDeadline;
688 /* The VSync rate in Hz used to calculate the
689 * step size for smooth brightness feature
690 */
691 unsigned int vsync_rate_hz;
692 unsigned int skipPsrWaitForPllLock;
693 unsigned int numberOfControllers;
694 /* Unused, for future use. To indicate that first changed frame from
695 * state3 shouldn't result in psr_inactive, but rather to perform
696 * an automatic single frame rfb_update.
697 */
698 bool rfb_update_auto_en;
699 /* Number of frame before entering static screen */
700 unsigned int timehyst_frames;
701 /* Partial frames before entering static screen */
702 unsigned int hyst_lines;
703 /* # of repeated AUX transaction attempts to make before
704 * indicating failure to the driver
705 */
706 unsigned int aux_repeats;
707 /* Controls hw blocks to power down during PSR active state */
708 union dmcu_psr_level psr_level;
709 /* Controls additional delay after remote frame capture before
710 * continuing powerd own
711 */
712 unsigned int frame_delay;
713 bool allow_smu_optimizations;
714 bool allow_multi_disp_optimizations;
715 /* Panel self refresh 2 selective update granularity required */
716 bool su_granularity_required;
717 /* psr2 selective update y granularity capability */
718 uint8_t su_y_granularity;
719 unsigned int line_time_in_us;
720 uint8_t rate_control_caps;
721 uint16_t dsc_slice_height;
722};
723
724struct colorspace_transform {
725 struct fixed31_32 matrix[12];
726 bool enable_remap;
727};
728
729enum i2c_mot_mode {
730 I2C_MOT_UNDEF,
731 I2C_MOT_TRUE,
732 I2C_MOT_FALSE
733};
734
735struct AsicStateEx {
736 unsigned int memoryClock;
737 unsigned int displayClock;
738 unsigned int engineClock;
739 unsigned int maxSupportedDppClock;
740 unsigned int dppClock;
741 unsigned int socClock;
742 unsigned int dcfClockDeepSleep;
743 unsigned int fClock;
744 unsigned int phyClock;
745};
746
747
748enum dc_clock_type {
749 DC_CLOCK_TYPE_DISPCLK = 0,
750 DC_CLOCK_TYPE_DPPCLK = 1,
751};
752
753struct dc_clock_config {
754 uint32_t max_clock_khz;
755 uint32_t min_clock_khz;
756 uint32_t bw_requirequired_clock_khz;
757 uint32_t current_clock_khz;/*current clock in use*/
758};
759
760struct hw_asic_id {
761 uint32_t chip_id;
762 uint32_t chip_family;
763 uint32_t pci_revision_id;
764 uint32_t hw_internal_rev;
765 uint32_t vram_type;
766 uint32_t vram_width;
767 uint32_t feature_flags;
768 uint32_t fake_paths_num;
769 void *atombios_base_address;
770};
771
772struct dc_context {
773 struct dc *dc;
774
775 void *driver_context; /* e.g. amdgpu_device */
776 struct dal_logger *logger;
777 struct dc_perf_trace *perf_trace;
778 void *cgs_device;
779
780 enum dce_environment dce_environment;
781 struct hw_asic_id asic_id;
782
783 /* todo: below should probably move to dc. to facilitate removal
784 * of AS we will store these here
785 */
786 enum dce_version dce_version;
787 struct dc_bios *dc_bios;
788 bool created_bios;
789 struct gpio_service *gpio_service;
790 uint32_t dc_sink_id_count;
791 uint32_t dc_stream_id_count;
792 uint32_t dc_edp_id_count;
793 uint64_t fbc_gpu_addr;
794 struct dc_dmub_srv *dmub_srv;
795 struct cp_psp cp_psp;
796 uint32_t *dcn_reg_offsets;
797 uint32_t *nbio_reg_offsets;
798 uint32_t *clk_reg_offsets;
799};
800
801/* DSC DPCD capabilities */
802union dsc_slice_caps1 {
803 struct {
804 uint8_t NUM_SLICES_1 : 1;
805 uint8_t NUM_SLICES_2 : 1;
806 uint8_t RESERVED : 1;
807 uint8_t NUM_SLICES_4 : 1;
808 uint8_t NUM_SLICES_6 : 1;
809 uint8_t NUM_SLICES_8 : 1;
810 uint8_t NUM_SLICES_10 : 1;
811 uint8_t NUM_SLICES_12 : 1;
812 } bits;
813 uint8_t raw;
814};
815
816union dsc_slice_caps2 {
817 struct {
818 uint8_t NUM_SLICES_16 : 1;
819 uint8_t NUM_SLICES_20 : 1;
820 uint8_t NUM_SLICES_24 : 1;
821 uint8_t RESERVED : 5;
822 } bits;
823 uint8_t raw;
824};
825
826union dsc_color_formats {
827 struct {
828 uint8_t RGB : 1;
829 uint8_t YCBCR_444 : 1;
830 uint8_t YCBCR_SIMPLE_422 : 1;
831 uint8_t YCBCR_NATIVE_422 : 1;
832 uint8_t YCBCR_NATIVE_420 : 1;
833 uint8_t RESERVED : 3;
834 } bits;
835 uint8_t raw;
836};
837
838union dsc_color_depth {
839 struct {
840 uint8_t RESERVED1 : 1;
841 uint8_t COLOR_DEPTH_8_BPC : 1;
842 uint8_t COLOR_DEPTH_10_BPC : 1;
843 uint8_t COLOR_DEPTH_12_BPC : 1;
844 uint8_t RESERVED2 : 3;
845 } bits;
846 uint8_t raw;
847};
848
849struct dsc_dec_dpcd_caps {
850 bool is_dsc_supported;
851 uint8_t dsc_version;
852 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
853 union dsc_slice_caps1 slice_caps1;
854 union dsc_slice_caps2 slice_caps2;
855 int32_t lb_bit_depth;
856 bool is_block_pred_supported;
857 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
858 union dsc_color_formats color_formats;
859 union dsc_color_depth color_depth;
860 int32_t throughput_mode_0_mps; /* In MPs */
861 int32_t throughput_mode_1_mps; /* In MPs */
862 int32_t max_slice_width;
863 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
864
865 /* Extended DSC caps */
866 uint32_t branch_overall_throughput_0_mps; /* In MPs */
867 uint32_t branch_overall_throughput_1_mps; /* In MPs */
868 uint32_t branch_max_line_width;
869 bool is_dp; /* Decoded format */
870};
871
872struct dc_golden_table {
873 uint16_t dc_golden_table_ver;
874 uint32_t aux_dphy_rx_control0_val;
875 uint32_t aux_dphy_tx_control_val;
876 uint32_t aux_dphy_rx_control1_val;
877 uint32_t dc_gpio_aux_ctrl_0_val;
878 uint32_t dc_gpio_aux_ctrl_1_val;
879 uint32_t dc_gpio_aux_ctrl_2_val;
880 uint32_t dc_gpio_aux_ctrl_3_val;
881 uint32_t dc_gpio_aux_ctrl_4_val;
882 uint32_t dc_gpio_aux_ctrl_5_val;
883};
884
885enum dc_gpu_mem_alloc_type {
886 DC_MEM_ALLOC_TYPE_GART,
887 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
888 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
889 DC_MEM_ALLOC_TYPE_AGP
890};
891
892enum dc_link_encoding_format {
893 DC_LINK_ENCODING_UNSPECIFIED = 0,
894 DC_LINK_ENCODING_DP_8b_10b,
895 DC_LINK_ENCODING_DP_128b_132b,
896 DC_LINK_ENCODING_HDMI_TMDS,
897 DC_LINK_ENCODING_HDMI_FRL
898};
899
900enum dc_psr_version {
901 DC_PSR_VERSION_1 = 0,
902 DC_PSR_VERSION_SU_1 = 1,
903 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
904};
905
906/* Possible values of display_endpoint_id.endpoint */
907enum display_endpoint_type {
908 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */
909 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */
910 DISPLAY_ENDPOINT_UNKNOWN = -1
911};
912
913/* Extends graphics_object_id with an additional member 'ep_type' for
914 * distinguishing between physical endpoints (with entries in BIOS connector table) and
915 * logical endpoints.
916 */
917struct display_endpoint_id {
918 struct graphics_object_id link_id;
919 enum display_endpoint_type ep_type;
920};
921
922#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
923struct otg_phy_mux {
924 uint8_t phy_output_num;
925 uint8_t otg_output_num;
926};
927#endif
928
929enum dc_detect_reason {
930 DETECT_REASON_BOOT,
931 DETECT_REASON_RESUMEFROMS3S4,
932 DETECT_REASON_HPD,
933 DETECT_REASON_HPDRX,
934 DETECT_REASON_FALLBACK,
935 DETECT_REASON_RETRAIN,
936 DETECT_REASON_TDR,
937};
938
939struct dc_link_status {
940 bool link_active;
941 struct dpcd_caps *dpcd_caps;
942};
943
944union hdcp_rx_caps {
945 struct {
946 uint8_t version;
947 uint8_t reserved;
948 struct {
949 uint8_t repeater : 1;
950 uint8_t hdcp_capable : 1;
951 uint8_t reserved : 6;
952 } byte0;
953 } fields;
954 uint8_t raw[3];
955};
956
957union hdcp_bcaps {
958 struct {
959 uint8_t HDCP_CAPABLE:1;
960 uint8_t REPEATER:1;
961 uint8_t RESERVED:6;
962 } bits;
963 uint8_t raw;
964};
965
966struct hdcp_caps {
967 union hdcp_rx_caps rx_caps;
968 union hdcp_bcaps bcaps;
969};
970
971/* DP MST stream allocation (payload bandwidth number) */
972struct link_mst_stream_allocation {
973 /* DIG front */
974 const struct stream_encoder *stream_enc;
975 /* HPO DP Stream Encoder */
976 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
977 /* associate DRM payload table with DC stream encoder */
978 uint8_t vcp_id;
979 /* number of slots required for the DP stream in transport packet */
980 uint8_t slot_count;
981};
982
983#define MAX_CONTROLLER_NUM 6
984
985/* DP MST stream allocation table */
986struct link_mst_stream_allocation_table {
987 /* number of DP video streams */
988 int stream_count;
989 /* array of stream allocations */
990 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
991};
992
993struct backlight_settings {
994 uint32_t backlight_millinits;
995};
996
997/* PSR feature flags */
998struct psr_settings {
999 bool psr_feature_enabled; // PSR is supported by sink
1000 bool psr_allow_active; // PSR is currently active
1001 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD
1002 bool psr_vtotal_control_support; // Vtotal control is supported by sink
1003 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU
1004
1005 /* These parameters are calculated in Driver,
1006 * based on display timing and Sink capabilities.
1007 * If VBLANK region is too small and Sink takes a long time
1008 * to set up RFB, it may take an extra frame to enter PSR state.
1009 */
1010 bool psr_frame_capture_indication_req;
1011 unsigned int psr_sdp_transmit_line_num_deadline;
1012 uint8_t force_ffu_mode;
1013 unsigned int psr_power_opt;
1014};
1015
1016enum replay_coasting_vtotal_type {
1017 PR_COASTING_TYPE_NOM = 0,
1018 PR_COASTING_TYPE_STATIC,
1019 PR_COASTING_TYPE_FULL_SCREEN_VIDEO,
1020 PR_COASTING_TYPE_TEST_HARNESS,
1021 PR_COASTING_TYPE_NUM,
1022};
1023
1024union replay_error_status {
1025 struct {
1026 unsigned char STATE_TRANSITION_ERROR :1;
1027 unsigned char LINK_CRC_ERROR :1;
1028 unsigned char DESYNC_ERROR :1;
1029 unsigned char RESERVED :5;
1030 } bits;
1031 unsigned char raw;
1032};
1033
1034struct replay_config {
1035 bool replay_supported; // Replay feature is supported
1036 unsigned int replay_power_opt_supported; // Power opt flags that are supported
1037 bool replay_smu_opt_supported; // SMU optimization is supported
1038 unsigned int replay_enable_option; // Replay enablement option
1039 uint32_t debug_flags; // Replay debug flags
1040 bool replay_timing_sync_supported; // Replay desync is supported
1041 union replay_error_status replay_error_status; // Replay error status
1042};
1043
1044/* Replay feature flags */
1045struct replay_settings {
1046 struct replay_config config; // Replay configuration
1047 bool replay_feature_enabled; // Replay feature is ready for activating
1048 bool replay_allow_active; // Replay is currently active
1049 unsigned int replay_power_opt_active; // Power opt flags that are activated currently
1050 bool replay_smu_opt_enable; // SMU optimization is enabled
1051 uint16_t coasting_vtotal; // Current Coasting vtotal
1052 uint16_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; // Coasting vtotal table
1053};
1054
1055/* To split out "global" and "per-panel" config settings.
1056 * Add a struct dc_panel_config under dc_link
1057 */
1058struct dc_panel_config {
1059 /* extra panel power sequence parameters */
1060 struct pps {
1061 unsigned int extra_t3_ms;
1062 unsigned int extra_t7_ms;
1063 unsigned int extra_delay_backlight_off;
1064 unsigned int extra_post_t7_ms;
1065 unsigned int extra_pre_t11_ms;
1066 unsigned int extra_t12_ms;
1067 unsigned int extra_post_OUI_ms;
1068 } pps;
1069 /* nit brightness */
1070 struct nits_brightness {
1071 unsigned int peak; /* nits */
1072 unsigned int max_avg; /* nits */
1073 unsigned int min; /* 1/10000 nits */
1074 unsigned int max_nonboost_brightness_millinits;
1075 unsigned int min_brightness_millinits;
1076 } nits_brightness;
1077 /* PSR */
1078 struct psr {
1079 bool disable_psr;
1080 bool disallow_psrsu;
1081 bool disallow_replay;
1082 bool rc_disable;
1083 bool rc_allow_static_screen;
1084 bool rc_allow_fullscreen_VPB;
1085 unsigned int replay_enable_option;
1086 } psr;
1087 /* ABM */
1088 struct varib {
1089 unsigned int varibright_feature_enable;
1090 unsigned int def_varibright_level;
1091 unsigned int abm_config_setting;
1092 } varib;
1093 /* edp DSC */
1094 struct dsc {
1095 bool disable_dsc_edp;
1096 unsigned int force_dsc_edp_policy;
1097 } dsc;
1098 /* eDP ILR */
1099 struct ilr {
1100 bool optimize_edp_link_rate; /* eDP ILR */
1101 } ilr;
1102};
1103
1104/*
1105 * USB4 DPIA BW ALLOCATION STRUCTS
1106 */
1107struct dc_dpia_bw_alloc {
1108 int sink_verified_bw; // The Verified BW that sink can allocated and use that has been verified already
1109 int sink_allocated_bw; // The Actual Allocated BW that sink currently allocated
1110 int sink_max_bw; // The Max BW that sink can require/support
1111 int estimated_bw; // The estimated available BW for this DPIA
1112 int bw_granularity; // BW Granularity
1113 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM
1114 bool response_ready; // Response ready from the CM side
1115};
1116
1117#define MAX_SINKS_PER_LINK 4
1118
1119enum dc_hpd_enable_select {
1120 HPD_EN_FOR_ALL_EDP = 0,
1121 HPD_EN_FOR_PRIMARY_EDP_ONLY,
1122 HPD_EN_FOR_SECONDARY_EDP_ONLY,
1123};
1124
1125#endif /* DC_TYPES_H_ */
1126

source code of linux/drivers/gpu/drm/amd/display/dc/dc_types.h