1 | /* |
2 | * GFX_7_2 Register documentation |
3 | * |
4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included |
14 | * in all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
22 | */ |
23 | |
24 | #ifndef GFX_7_2_D_H |
25 | #define GFX_7_2_D_H |
26 | |
27 | #define mmCB_BLEND_RED 0xa105 |
28 | #define mmCB_BLEND_GREEN 0xa106 |
29 | #define mmCB_BLEND_BLUE 0xa107 |
30 | #define mmCB_BLEND_ALPHA 0xa108 |
31 | #define mmCB_COLOR_CONTROL 0xa202 |
32 | #define mmCB_BLEND0_CONTROL 0xa1e0 |
33 | #define mmCB_BLEND1_CONTROL 0xa1e1 |
34 | #define mmCB_BLEND2_CONTROL 0xa1e2 |
35 | #define mmCB_BLEND3_CONTROL 0xa1e3 |
36 | #define mmCB_BLEND4_CONTROL 0xa1e4 |
37 | #define mmCB_BLEND5_CONTROL 0xa1e5 |
38 | #define mmCB_BLEND6_CONTROL 0xa1e6 |
39 | #define mmCB_BLEND7_CONTROL 0xa1e7 |
40 | #define mmCB_COLOR0_BASE 0xa318 |
41 | #define mmCB_COLOR1_BASE 0xa327 |
42 | #define mmCB_COLOR2_BASE 0xa336 |
43 | #define mmCB_COLOR3_BASE 0xa345 |
44 | #define mmCB_COLOR4_BASE 0xa354 |
45 | #define mmCB_COLOR5_BASE 0xa363 |
46 | #define mmCB_COLOR6_BASE 0xa372 |
47 | #define mmCB_COLOR7_BASE 0xa381 |
48 | #define mmCB_COLOR0_PITCH 0xa319 |
49 | #define mmCB_COLOR1_PITCH 0xa328 |
50 | #define mmCB_COLOR2_PITCH 0xa337 |
51 | #define mmCB_COLOR3_PITCH 0xa346 |
52 | #define mmCB_COLOR4_PITCH 0xa355 |
53 | #define mmCB_COLOR5_PITCH 0xa364 |
54 | #define mmCB_COLOR6_PITCH 0xa373 |
55 | #define mmCB_COLOR7_PITCH 0xa382 |
56 | #define mmCB_COLOR0_SLICE 0xa31a |
57 | #define mmCB_COLOR1_SLICE 0xa329 |
58 | #define mmCB_COLOR2_SLICE 0xa338 |
59 | #define mmCB_COLOR3_SLICE 0xa347 |
60 | #define mmCB_COLOR4_SLICE 0xa356 |
61 | #define mmCB_COLOR5_SLICE 0xa365 |
62 | #define mmCB_COLOR6_SLICE 0xa374 |
63 | #define mmCB_COLOR7_SLICE 0xa383 |
64 | #define mmCB_COLOR0_VIEW 0xa31b |
65 | #define mmCB_COLOR1_VIEW 0xa32a |
66 | #define mmCB_COLOR2_VIEW 0xa339 |
67 | #define mmCB_COLOR3_VIEW 0xa348 |
68 | #define mmCB_COLOR4_VIEW 0xa357 |
69 | #define mmCB_COLOR5_VIEW 0xa366 |
70 | #define mmCB_COLOR6_VIEW 0xa375 |
71 | #define mmCB_COLOR7_VIEW 0xa384 |
72 | #define mmCB_COLOR0_INFO 0xa31c |
73 | #define mmCB_COLOR1_INFO 0xa32b |
74 | #define mmCB_COLOR2_INFO 0xa33a |
75 | #define mmCB_COLOR3_INFO 0xa349 |
76 | #define mmCB_COLOR4_INFO 0xa358 |
77 | #define mmCB_COLOR5_INFO 0xa367 |
78 | #define mmCB_COLOR6_INFO 0xa376 |
79 | #define mmCB_COLOR7_INFO 0xa385 |
80 | #define mmCB_COLOR0_ATTRIB 0xa31d |
81 | #define mmCB_COLOR1_ATTRIB 0xa32c |
82 | #define mmCB_COLOR2_ATTRIB 0xa33b |
83 | #define mmCB_COLOR3_ATTRIB 0xa34a |
84 | #define mmCB_COLOR4_ATTRIB 0xa359 |
85 | #define mmCB_COLOR5_ATTRIB 0xa368 |
86 | #define mmCB_COLOR6_ATTRIB 0xa377 |
87 | #define mmCB_COLOR7_ATTRIB 0xa386 |
88 | #define mmCB_COLOR0_CMASK 0xa31f |
89 | #define mmCB_COLOR1_CMASK 0xa32e |
90 | #define mmCB_COLOR2_CMASK 0xa33d |
91 | #define mmCB_COLOR3_CMASK 0xa34c |
92 | #define mmCB_COLOR4_CMASK 0xa35b |
93 | #define mmCB_COLOR5_CMASK 0xa36a |
94 | #define mmCB_COLOR6_CMASK 0xa379 |
95 | #define mmCB_COLOR7_CMASK 0xa388 |
96 | #define mmCB_COLOR0_CMASK_SLICE 0xa320 |
97 | #define mmCB_COLOR1_CMASK_SLICE 0xa32f |
98 | #define mmCB_COLOR2_CMASK_SLICE 0xa33e |
99 | #define mmCB_COLOR3_CMASK_SLICE 0xa34d |
100 | #define mmCB_COLOR4_CMASK_SLICE 0xa35c |
101 | #define mmCB_COLOR5_CMASK_SLICE 0xa36b |
102 | #define mmCB_COLOR6_CMASK_SLICE 0xa37a |
103 | #define mmCB_COLOR7_CMASK_SLICE 0xa389 |
104 | #define mmCB_COLOR0_FMASK 0xa321 |
105 | #define mmCB_COLOR1_FMASK 0xa330 |
106 | #define mmCB_COLOR2_FMASK 0xa33f |
107 | #define mmCB_COLOR3_FMASK 0xa34e |
108 | #define mmCB_COLOR4_FMASK 0xa35d |
109 | #define mmCB_COLOR5_FMASK 0xa36c |
110 | #define mmCB_COLOR6_FMASK 0xa37b |
111 | #define mmCB_COLOR7_FMASK 0xa38a |
112 | #define mmCB_COLOR0_FMASK_SLICE 0xa322 |
113 | #define mmCB_COLOR1_FMASK_SLICE 0xa331 |
114 | #define mmCB_COLOR2_FMASK_SLICE 0xa340 |
115 | #define mmCB_COLOR3_FMASK_SLICE 0xa34f |
116 | #define mmCB_COLOR4_FMASK_SLICE 0xa35e |
117 | #define mmCB_COLOR5_FMASK_SLICE 0xa36d |
118 | #define mmCB_COLOR6_FMASK_SLICE 0xa37c |
119 | #define mmCB_COLOR7_FMASK_SLICE 0xa38b |
120 | #define mmCB_COLOR0_CLEAR_WORD0 0xa323 |
121 | #define mmCB_COLOR1_CLEAR_WORD0 0xa332 |
122 | #define mmCB_COLOR2_CLEAR_WORD0 0xa341 |
123 | #define mmCB_COLOR3_CLEAR_WORD0 0xa350 |
124 | #define mmCB_COLOR4_CLEAR_WORD0 0xa35f |
125 | #define mmCB_COLOR5_CLEAR_WORD0 0xa36e |
126 | #define mmCB_COLOR6_CLEAR_WORD0 0xa37d |
127 | #define mmCB_COLOR7_CLEAR_WORD0 0xa38c |
128 | #define mmCB_COLOR0_CLEAR_WORD1 0xa324 |
129 | #define mmCB_COLOR1_CLEAR_WORD1 0xa333 |
130 | #define mmCB_COLOR2_CLEAR_WORD1 0xa342 |
131 | #define mmCB_COLOR3_CLEAR_WORD1 0xa351 |
132 | #define mmCB_COLOR4_CLEAR_WORD1 0xa360 |
133 | #define mmCB_COLOR5_CLEAR_WORD1 0xa36f |
134 | #define mmCB_COLOR6_CLEAR_WORD1 0xa37e |
135 | #define mmCB_COLOR7_CLEAR_WORD1 0xa38d |
136 | #define mmCB_TARGET_MASK 0xa08e |
137 | #define mmCB_SHADER_MASK 0xa08f |
138 | #define mmCB_HW_CONTROL 0x2684 |
139 | #define mmCB_HW_CONTROL_1 0x2685 |
140 | #define mmCB_HW_CONTROL_2 0x2686 |
141 | #define mmCB_HW_CONTROL_3 0x2683 |
142 | #define mmCB_PERFCOUNTER_FILTER 0xdc00 |
143 | #define mmCB_PERFCOUNTER0_SELECT 0xdc01 |
144 | #define mmCB_PERFCOUNTER0_SELECT1 0xdc02 |
145 | #define mmCB_PERFCOUNTER1_SELECT 0xdc03 |
146 | #define mmCB_PERFCOUNTER2_SELECT 0xdc04 |
147 | #define mmCB_PERFCOUNTER3_SELECT 0xdc05 |
148 | #define mmCB_PERFCOUNTER0_LO 0xd406 |
149 | #define mmCB_PERFCOUNTER1_LO 0xd408 |
150 | #define mmCB_PERFCOUNTER2_LO 0xd40a |
151 | #define mmCB_PERFCOUNTER3_LO 0xd40c |
152 | #define mmCB_PERFCOUNTER0_HI 0xd407 |
153 | #define mmCB_PERFCOUNTER1_HI 0xd409 |
154 | #define mmCB_PERFCOUNTER2_HI 0xd40b |
155 | #define mmCB_PERFCOUNTER3_HI 0xd40d |
156 | #define mmCB_CGTT_SCLK_CTRL 0xf0a8 |
157 | #define mmCB_DEBUG_BUS_1 0x2699 |
158 | #define mmCB_DEBUG_BUS_2 0x269a |
159 | #define mmCB_DEBUG_BUS_3 0x269b |
160 | #define mmCB_DEBUG_BUS_4 0x269c |
161 | #define mmCB_DEBUG_BUS_5 0x269d |
162 | #define mmCB_DEBUG_BUS_6 0x269e |
163 | #define mmCB_DEBUG_BUS_7 0x269f |
164 | #define mmCB_DEBUG_BUS_8 0x26a0 |
165 | #define mmCB_DEBUG_BUS_9 0x26a1 |
166 | #define mmCB_DEBUG_BUS_10 0x26a2 |
167 | #define mmCB_DEBUG_BUS_11 0x26a3 |
168 | #define mmCB_DEBUG_BUS_12 0x26a4 |
169 | #define mmCB_DEBUG_BUS_13 0x26a5 |
170 | #define mmCB_DEBUG_BUS_14 0x26a6 |
171 | #define mmCB_DEBUG_BUS_15 0x26a7 |
172 | #define mmCB_DEBUG_BUS_16 0x26a8 |
173 | #define mmCB_DEBUG_BUS_17 0x26a9 |
174 | #define mmCB_DEBUG_BUS_18 0x26aa |
175 | #define mmCP_DFY_CNTL 0x3020 |
176 | #define mmCP_DFY_STAT 0x3021 |
177 | #define mmCP_DFY_ADDR_HI 0x3022 |
178 | #define mmCP_DFY_ADDR_LO 0x3023 |
179 | #define mmCP_DFY_DATA_0 0x3024 |
180 | #define mmCP_DFY_DATA_1 0x3025 |
181 | #define mmCP_DFY_DATA_2 0x3026 |
182 | #define mmCP_DFY_DATA_3 0x3027 |
183 | #define mmCP_DFY_DATA_4 0x3028 |
184 | #define mmCP_DFY_DATA_5 0x3029 |
185 | #define mmCP_DFY_DATA_6 0x302a |
186 | #define mmCP_DFY_DATA_7 0x302b |
187 | #define mmCP_DFY_DATA_8 0x302c |
188 | #define mmCP_DFY_DATA_9 0x302d |
189 | #define mmCP_DFY_DATA_10 0x302e |
190 | #define mmCP_DFY_DATA_11 0x302f |
191 | #define mmCP_DFY_DATA_12 0x3030 |
192 | #define mmCP_DFY_DATA_13 0x3031 |
193 | #define mmCP_DFY_DATA_14 0x3032 |
194 | #define mmCP_DFY_DATA_15 0x3033 |
195 | #define mmCP_RB0_BASE 0x3040 |
196 | #define mmCP_RB0_BASE_HI 0x30b1 |
197 | #define mmCP_RB_BASE 0x3040 |
198 | #define mmCP_RB1_BASE 0x3060 |
199 | #define mmCP_RB1_BASE_HI 0x30b2 |
200 | #define mmCP_RB2_BASE 0x3065 |
201 | #define mmCP_RB0_CNTL 0x3041 |
202 | #define mmCP_RB_CNTL 0x3041 |
203 | #define mmCP_RB1_CNTL 0x3061 |
204 | #define mmCP_RB2_CNTL 0x3066 |
205 | #define mmCP_RB_RPTR_WR 0x3042 |
206 | #define mmCP_RB0_RPTR_ADDR 0x3043 |
207 | #define mmCP_RB_RPTR_ADDR 0x3043 |
208 | #define mmCP_RB1_RPTR_ADDR 0x3062 |
209 | #define mmCP_RB2_RPTR_ADDR 0x3067 |
210 | #define mmCP_RB0_RPTR_ADDR_HI 0x3044 |
211 | #define mmCP_RB_RPTR_ADDR_HI 0x3044 |
212 | #define mmCP_RB1_RPTR_ADDR_HI 0x3063 |
213 | #define mmCP_RB2_RPTR_ADDR_HI 0x3068 |
214 | #define mmCP_RB0_WPTR 0x3045 |
215 | #define mmCP_RB_WPTR 0x3045 |
216 | #define mmCP_RB1_WPTR 0x3064 |
217 | #define mmCP_RB2_WPTR 0x3069 |
218 | #define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 |
219 | #define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 |
220 | #define mmGC_PRIV_MODE 0x3048 |
221 | #define mmCP_INT_CNTL 0x3049 |
222 | #define mmCP_INT_CNTL_RING0 0x306a |
223 | #define mmCP_INT_CNTL_RING1 0x306b |
224 | #define mmCP_INT_CNTL_RING2 0x306c |
225 | #define mmCP_INT_STATUS 0x304a |
226 | #define mmCP_INT_STATUS_RING0 0x306d |
227 | #define mmCP_INT_STATUS_RING1 0x306e |
228 | #define mmCP_INT_STATUS_RING2 0x306f |
229 | #define mmCP_DEVICE_ID 0x304b |
230 | #define mmCP_RING_PRIORITY_CNTS 0x304c |
231 | #define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c |
232 | #define mmCP_RING0_PRIORITY 0x304d |
233 | #define mmCP_ME0_PIPE0_PRIORITY 0x304d |
234 | #define mmCP_RING1_PRIORITY 0x304e |
235 | #define mmCP_ME0_PIPE1_PRIORITY 0x304e |
236 | #define mmCP_RING2_PRIORITY 0x304f |
237 | #define mmCP_ME0_PIPE2_PRIORITY 0x304f |
238 | #define mmCP_ENDIAN_SWAP 0x3050 |
239 | #define mmCP_RB_VMID 0x3051 |
240 | #define mmCP_ME0_PIPE0_VMID 0x3052 |
241 | #define mmCP_ME0_PIPE1_VMID 0x3053 |
242 | #define mmCP_PFP_UCODE_ADDR 0x3054 |
243 | #define mmCP_PFP_UCODE_DATA 0x3055 |
244 | #define mmCP_ME_RAM_RADDR 0x3056 |
245 | #define mmCP_ME_RAM_WADDR 0x3057 |
246 | #define mmCP_ME_RAM_DATA 0x3058 |
247 | #define mmCGTT_CPC_CLK_CTRL 0xf0b2 |
248 | #define mmCGTT_CPF_CLK_CTRL 0xf0b1 |
249 | #define mmCGTT_CP_CLK_CTRL 0xf0b0 |
250 | #define mmCP_CE_UCODE_ADDR 0x305a |
251 | #define mmCP_CE_UCODE_DATA 0x305b |
252 | #define mmCP_MEC_ME1_UCODE_ADDR 0x305c |
253 | #define mmCP_MEC_ME1_UCODE_DATA 0x305d |
254 | #define mmCP_MEC_ME2_UCODE_ADDR 0x305e |
255 | #define mmCP_MEC_ME2_UCODE_DATA 0x305f |
256 | #define mmCP_PWR_CNTL 0x3078 |
257 | #define mmCP_MEM_SLP_CNTL 0x3079 |
258 | #define mmCP_ECC_FIRSTOCCURRENCE 0x307a |
259 | #define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b |
260 | #define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c |
261 | #define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d |
262 | #define mmCP_CPF_DEBUG 0x3080 |
263 | #define mmCP_FETCHER_SOURCE 0x3082 |
264 | #define mmCP_PQ_WPTR_POLL_CNTL 0x3083 |
265 | #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 |
266 | #define mmCPC_INT_CNTL 0x30b4 |
267 | #define mmCP_ME1_PIPE0_INT_CNTL 0x3085 |
268 | #define mmCP_ME1_PIPE1_INT_CNTL 0x3086 |
269 | #define mmCP_ME1_PIPE2_INT_CNTL 0x3087 |
270 | #define mmCP_ME1_PIPE3_INT_CNTL 0x3088 |
271 | #define mmCP_ME2_PIPE0_INT_CNTL 0x3089 |
272 | #define mmCP_ME2_PIPE1_INT_CNTL 0x308a |
273 | #define mmCP_ME2_PIPE2_INT_CNTL 0x308b |
274 | #define mmCP_ME2_PIPE3_INT_CNTL 0x308c |
275 | #define mmCPC_INT_STATUS 0x30b5 |
276 | #define mmCP_ME1_PIPE0_INT_STATUS 0x308d |
277 | #define mmCP_ME1_PIPE1_INT_STATUS 0x308e |
278 | #define mmCP_ME1_PIPE2_INT_STATUS 0x308f |
279 | #define mmCP_ME1_PIPE3_INT_STATUS 0x3090 |
280 | #define mmCP_ME2_PIPE0_INT_STATUS 0x3091 |
281 | #define mmCP_ME2_PIPE1_INT_STATUS 0x3092 |
282 | #define mmCP_ME2_PIPE2_INT_STATUS 0x3093 |
283 | #define mmCP_ME2_PIPE3_INT_STATUS 0x3094 |
284 | #define mmCP_ME1_INT_STAT_DEBUG 0x3095 |
285 | #define mmCP_ME2_INT_STAT_DEBUG 0x3096 |
286 | #define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099 |
287 | #define mmCP_ME1_PIPE0_PRIORITY 0x309a |
288 | #define mmCP_ME1_PIPE1_PRIORITY 0x309b |
289 | #define mmCP_ME1_PIPE2_PRIORITY 0x309c |
290 | #define mmCP_ME1_PIPE3_PRIORITY 0x309d |
291 | #define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e |
292 | #define mmCP_ME2_PIPE0_PRIORITY 0x309f |
293 | #define mmCP_ME2_PIPE1_PRIORITY 0x30a0 |
294 | #define mmCP_ME2_PIPE2_PRIORITY 0x30a1 |
295 | #define mmCP_ME2_PIPE3_PRIORITY 0x30a2 |
296 | #define mmCP_CE_PRGRM_CNTR_START 0x30a3 |
297 | #define mmCP_PFP_PRGRM_CNTR_START 0x30a4 |
298 | #define mmCP_ME_PRGRM_CNTR_START 0x30a5 |
299 | #define mmCP_MEC1_PRGRM_CNTR_START 0x30a6 |
300 | #define mmCP_MEC2_PRGRM_CNTR_START 0x30a7 |
301 | #define mmCP_CE_INTR_ROUTINE_START 0x30a8 |
302 | #define mmCP_PFP_INTR_ROUTINE_START 0x30a9 |
303 | #define mmCP_ME_INTR_ROUTINE_START 0x30aa |
304 | #define mmCP_MEC1_INTR_ROUTINE_START 0x30ab |
305 | #define mmCP_MEC2_INTR_ROUTINE_START 0x30ac |
306 | #define mmCP_CONTEXT_CNTL 0x30ad |
307 | #define mmCP_MAX_CONTEXT 0x30ae |
308 | #define mmCP_IQ_WAIT_TIME1 0x30af |
309 | #define mmCP_IQ_WAIT_TIME2 0x30b0 |
310 | #define mmCP_VMID_RESET 0x30b3 |
311 | #define mmCP_VMID_PREEMPT 0x30b6 |
312 | #define mmCPC_INT_CNTX_ID 0x30b7 |
313 | #define mmCP_PQ_STATUS 0x30b8 |
314 | #define mmCP_CPC_STATUS 0x2084 |
315 | #define mmCP_CPC_BUSY_STAT 0x2085 |
316 | #define mmCP_CPC_STALLED_STAT1 0x2086 |
317 | #define mmCP_CPF_STATUS 0x2087 |
318 | #define mmCP_CPF_BUSY_STAT 0x2088 |
319 | #define mmCP_CPF_STALLED_STAT1 0x2089 |
320 | #define mmCP_CPC_MC_CNTL 0x208a |
321 | #define mmCP_CPC_GRBM_FREE_COUNT 0x208b |
322 | #define mmCP_MEC_CNTL 0x208d |
323 | #define 0x208e |
324 | #define 0x208f |
325 | #define mmCP_CPC_SCRATCH_INDEX 0x2090 |
326 | #define mmCP_CPC_SCRATCH_DATA 0x2091 |
327 | #define mmCPG_PERFCOUNTER1_SELECT 0xd800 |
328 | #define mmCPG_PERFCOUNTER1_LO 0xd000 |
329 | #define mmCPG_PERFCOUNTER1_HI 0xd001 |
330 | #define mmCPG_PERFCOUNTER0_SELECT1 0xd801 |
331 | #define mmCPG_PERFCOUNTER0_SELECT 0xd802 |
332 | #define mmCPG_PERFCOUNTER0_LO 0xd002 |
333 | #define mmCPG_PERFCOUNTER0_HI 0xd003 |
334 | #define mmCPC_PERFCOUNTER1_SELECT 0xd803 |
335 | #define mmCPC_PERFCOUNTER1_LO 0xd004 |
336 | #define mmCPC_PERFCOUNTER1_HI 0xd005 |
337 | #define mmCPC_PERFCOUNTER0_SELECT1 0xd804 |
338 | #define mmCPC_PERFCOUNTER0_SELECT 0xd809 |
339 | #define mmCPC_PERFCOUNTER0_LO 0xd006 |
340 | #define mmCPC_PERFCOUNTER0_HI 0xd007 |
341 | #define mmCPF_PERFCOUNTER1_SELECT 0xd805 |
342 | #define mmCPF_PERFCOUNTER1_LO 0xd008 |
343 | #define mmCPF_PERFCOUNTER1_HI 0xd009 |
344 | #define mmCPF_PERFCOUNTER0_SELECT1 0xd806 |
345 | #define mmCPF_PERFCOUNTER0_SELECT 0xd807 |
346 | #define mmCPF_PERFCOUNTER0_LO 0xd00a |
347 | #define mmCPF_PERFCOUNTER0_HI 0xd00b |
348 | #define mmCP_CPC_HALT_HYST_COUNT 0x20a7 |
349 | #define mmCP_DRAW_OBJECT 0xd810 |
350 | #define mmCP_DRAW_OBJECT_COUNTER 0xd811 |
351 | #define mmCP_DRAW_WINDOW_MASK_HI 0xd812 |
352 | #define mmCP_DRAW_WINDOW_HI 0xd813 |
353 | #define mmCP_DRAW_WINDOW_LO 0xd814 |
354 | #define mmCP_DRAW_WINDOW_CNTL 0xd815 |
355 | #define mmCP_PRT_LOD_STATS_CNTL0 0x20ad |
356 | #define mmCP_PRT_LOD_STATS_CNTL1 0x20ae |
357 | #define mmCP_PRT_LOD_STATS_CNTL2 0x20af |
358 | #define mmCP_CE_COMPARE_COUNT 0x20c0 |
359 | #define mmCP_CE_DE_COUNT 0x20c1 |
360 | #define mmCP_DE_CE_COUNT 0x20c2 |
361 | #define mmCP_DE_LAST_INVAL_COUNT 0x20c3 |
362 | #define mmCP_DE_DE_COUNT 0x20c4 |
363 | #define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5 |
364 | #define mmCP_EOP_DONE_DATA_CNTL 0xc0d6 |
365 | #define mmCP_EOP_DONE_ADDR_LO 0xc000 |
366 | #define mmCP_EOP_DONE_ADDR_HI 0xc001 |
367 | #define mmCP_EOP_DONE_DATA_LO 0xc002 |
368 | #define mmCP_EOP_DONE_DATA_HI 0xc003 |
369 | #define mmCP_EOP_LAST_FENCE_LO 0xc004 |
370 | #define mmCP_EOP_LAST_FENCE_HI 0xc005 |
371 | #define mmCP_STREAM_OUT_ADDR_LO 0xc006 |
372 | #define mmCP_STREAM_OUT_ADDR_HI 0xc007 |
373 | #define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008 |
374 | #define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009 |
375 | #define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a |
376 | #define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b |
377 | #define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c |
378 | #define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d |
379 | #define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e |
380 | #define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f |
381 | #define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010 |
382 | #define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011 |
383 | #define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012 |
384 | #define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013 |
385 | #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014 |
386 | #define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015 |
387 | #define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016 |
388 | #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017 |
389 | #define mmCP_PIPE_STATS_ADDR_LO 0xc018 |
390 | #define mmCP_PIPE_STATS_ADDR_HI 0xc019 |
391 | #define mmCP_VGT_IAVERT_COUNT_LO 0xc01a |
392 | #define mmCP_VGT_IAVERT_COUNT_HI 0xc01b |
393 | #define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c |
394 | #define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d |
395 | #define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e |
396 | #define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f |
397 | #define mmCP_VGT_VSINVOC_COUNT_LO 0xc020 |
398 | #define mmCP_VGT_VSINVOC_COUNT_HI 0xc021 |
399 | #define mmCP_VGT_GSINVOC_COUNT_LO 0xc022 |
400 | #define mmCP_VGT_GSINVOC_COUNT_HI 0xc023 |
401 | #define mmCP_VGT_HSINVOC_COUNT_LO 0xc024 |
402 | #define mmCP_VGT_HSINVOC_COUNT_HI 0xc025 |
403 | #define mmCP_VGT_DSINVOC_COUNT_LO 0xc026 |
404 | #define mmCP_VGT_DSINVOC_COUNT_HI 0xc027 |
405 | #define mmCP_PA_CINVOC_COUNT_LO 0xc028 |
406 | #define mmCP_PA_CINVOC_COUNT_HI 0xc029 |
407 | #define mmCP_PA_CPRIM_COUNT_LO 0xc02a |
408 | #define mmCP_PA_CPRIM_COUNT_HI 0xc02b |
409 | #define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c |
410 | #define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d |
411 | #define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e |
412 | #define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f |
413 | #define mmCP_VGT_CSINVOC_COUNT_LO 0xc030 |
414 | #define mmCP_VGT_CSINVOC_COUNT_HI 0xc031 |
415 | #define mmCP_STRMOUT_CNTL 0xc03f |
416 | #define mmSCRATCH_REG0 0xc040 |
417 | #define mmSCRATCH_REG1 0xc041 |
418 | #define mmSCRATCH_REG2 0xc042 |
419 | #define mmSCRATCH_REG3 0xc043 |
420 | #define mmSCRATCH_REG4 0xc044 |
421 | #define mmSCRATCH_REG5 0xc045 |
422 | #define mmSCRATCH_REG6 0xc046 |
423 | #define mmSCRATCH_REG7 0xc047 |
424 | #define mmSCRATCH_UMSK 0xc050 |
425 | #define mmSCRATCH_ADDR 0xc051 |
426 | #define mmCP_PFP_ATOMIC_PREOP_LO 0xc052 |
427 | #define mmCP_PFP_ATOMIC_PREOP_HI 0xc053 |
428 | #define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054 |
429 | #define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055 |
430 | #define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056 |
431 | #define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057 |
432 | #define mmCP_APPEND_ADDR_LO 0xc058 |
433 | #define mmCP_APPEND_ADDR_HI 0xc059 |
434 | #define mmCP_APPEND_DATA 0xc05a |
435 | #define mmCP_APPEND_LAST_CS_FENCE 0xc05b |
436 | #define mmCP_APPEND_LAST_PS_FENCE 0xc05c |
437 | #define mmCP_ATOMIC_PREOP_LO 0xc05d |
438 | #define mmCP_ME_ATOMIC_PREOP_LO 0xc05d |
439 | #define mmCP_ATOMIC_PREOP_HI 0xc05e |
440 | #define mmCP_ME_ATOMIC_PREOP_HI 0xc05e |
441 | #define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f |
442 | #define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f |
443 | #define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060 |
444 | #define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060 |
445 | #define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061 |
446 | #define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061 |
447 | #define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062 |
448 | #define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062 |
449 | #define mmCP_ME_MC_WADDR_LO 0xc069 |
450 | #define mmCP_ME_MC_WADDR_HI 0xc06a |
451 | #define mmCP_ME_MC_WDATA_LO 0xc06b |
452 | #define mmCP_ME_MC_WDATA_HI 0xc06c |
453 | #define mmCP_ME_MC_RADDR_LO 0xc06d |
454 | #define mmCP_ME_MC_RADDR_HI 0xc06e |
455 | #define mmCP_SEM_WAIT_TIMER 0xc06f |
456 | #define mmCP_SIG_SEM_ADDR_LO 0xc070 |
457 | #define mmCP_SIG_SEM_ADDR_HI 0xc071 |
458 | #define mmCP_WAIT_SEM_ADDR_LO 0xc075 |
459 | #define mmCP_WAIT_SEM_ADDR_HI 0xc076 |
460 | #define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074 |
461 | #define mmCP_COHER_START_DELAY 0xc07b |
462 | #define mmCP_COHER_CNTL 0xc07c |
463 | #define mmCP_COHER_SIZE 0xc07d |
464 | #define mmCP_COHER_SIZE_HI 0xc08c |
465 | #define mmCP_COHER_BASE 0xc07e |
466 | #define mmCP_COHER_BASE_HI 0xc079 |
467 | #define mmCP_COHER_STATUS 0xc07f |
468 | #define mmCOHER_DEST_BASE_0 0xa092 |
469 | #define mmCOHER_DEST_BASE_1 0xa093 |
470 | #define mmCOHER_DEST_BASE_2 0xa07e |
471 | #define mmCOHER_DEST_BASE_3 0xa07f |
472 | #define mmCOHER_DEST_BASE_HI_0 0xa07a |
473 | #define mmCOHER_DEST_BASE_HI_1 0xa07b |
474 | #define mmCOHER_DEST_BASE_HI_2 0xa07c |
475 | #define mmCOHER_DEST_BASE_HI_3 0xa07d |
476 | #define mmCP_DMA_ME_SRC_ADDR 0xc080 |
477 | #define mmCP_DMA_ME_SRC_ADDR_HI 0xc081 |
478 | #define mmCP_DMA_ME_DST_ADDR 0xc082 |
479 | #define mmCP_DMA_ME_DST_ADDR_HI 0xc083 |
480 | #define mmCP_DMA_ME_CONTROL 0xc078 |
481 | #define mmCP_DMA_ME_COMMAND 0xc084 |
482 | #define mmCP_DMA_PFP_SRC_ADDR 0xc085 |
483 | #define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086 |
484 | #define mmCP_DMA_PFP_DST_ADDR 0xc087 |
485 | #define mmCP_DMA_PFP_DST_ADDR_HI 0xc088 |
486 | #define mmCP_DMA_PFP_CONTROL 0xc077 |
487 | #define mmCP_DMA_PFP_COMMAND 0xc089 |
488 | #define mmCP_DMA_CNTL 0xc08a |
489 | #define mmCP_DMA_READ_TAGS 0xc08b |
490 | #define mmCP_PFP_IB_CONTROL 0xc08d |
491 | #define mmCP_PFP_LOAD_CONTROL 0xc08e |
492 | #define mmCP_SCRATCH_INDEX 0xc08f |
493 | #define mmCP_SCRATCH_DATA 0xc090 |
494 | #define mmCP_RB_OFFSET 0xc091 |
495 | #define mmCP_IB1_OFFSET 0xc092 |
496 | #define mmCP_IB2_OFFSET 0xc093 |
497 | #define mmCP_IB1_PREAMBLE_BEGIN 0xc094 |
498 | #define mmCP_IB1_PREAMBLE_END 0xc095 |
499 | #define mmCP_IB2_PREAMBLE_BEGIN 0xc096 |
500 | #define mmCP_IB2_PREAMBLE_END 0xc097 |
501 | #define mmCP_CE_IB1_OFFSET 0xc098 |
502 | #define mmCP_CE_IB2_OFFSET 0xc099 |
503 | #define mmCP_CE_COUNTER 0xc09a |
504 | #define mmCP_STALLED_STAT1 0x219d |
505 | #define mmCP_STALLED_STAT2 0x219e |
506 | #define mmCP_STALLED_STAT3 0x219c |
507 | #define mmCP_BUSY_STAT 0x219f |
508 | #define mmCP_STAT 0x21a0 |
509 | #define 0x21a1 |
510 | #define 0x21a2 |
511 | #define mmCP_GRBM_FREE_COUNT 0x21a3 |
512 | #define 0x21a4 |
513 | #define mmCP_MC_PACK_DELAY_CNT 0x21a7 |
514 | #define mmCP_MC_TAG_CNTL 0x21a8 |
515 | #define mmCP_MC_TAG_DATA 0x21a9 |
516 | #define mmCP_CSF_STAT 0x21b4 |
517 | #define mmCP_CSF_CNTL 0x21b5 |
518 | #define mmCP_ME_CNTL 0x21b6 |
519 | #define mmCP_CNTX_STAT 0x21b8 |
520 | #define mmCP_ME_PREEMPTION 0x21b9 |
521 | #define mmCP_RB0_RPTR 0x21c0 |
522 | #define mmCP_RB_RPTR 0x21c0 |
523 | #define mmCP_RB1_RPTR 0x21bf |
524 | #define mmCP_RB2_RPTR 0x21be |
525 | #define mmCP_RB_WPTR_DELAY 0x21c1 |
526 | #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 |
527 | #define mmCP_CE_INIT_BASE_LO 0xc0c3 |
528 | #define mmCP_CE_INIT_BASE_HI 0xc0c4 |
529 | #define mmCP_CE_INIT_BUFSZ 0xc0c5 |
530 | #define mmCP_CE_IB1_BASE_LO 0xc0c6 |
531 | #define mmCP_CE_IB1_BASE_HI 0xc0c7 |
532 | #define mmCP_CE_IB1_BUFSZ 0xc0c8 |
533 | #define mmCP_CE_IB2_BASE_LO 0xc0c9 |
534 | #define mmCP_CE_IB2_BASE_HI 0xc0ca |
535 | #define mmCP_CE_IB2_BUFSZ 0xc0cb |
536 | #define mmCP_IB1_BASE_LO 0xc0cc |
537 | #define mmCP_IB1_BASE_HI 0xc0cd |
538 | #define mmCP_IB1_BUFSZ 0xc0ce |
539 | #define mmCP_IB2_BASE_LO 0xc0cf |
540 | #define mmCP_IB2_BASE_HI 0xc0d0 |
541 | #define mmCP_IB2_BUFSZ 0xc0d1 |
542 | #define mmCP_ST_BASE_LO 0xc0d2 |
543 | #define mmCP_ST_BASE_HI 0xc0d3 |
544 | #define mmCP_ST_BUFSZ 0xc0d4 |
545 | #define mmCP_ROQ_THRESHOLDS 0x21bc |
546 | #define mmCP_MEQ_STQ_THRESHOLD 0x21bd |
547 | #define mmCP_ROQ1_THRESHOLDS 0x21d5 |
548 | #define mmCP_ROQ2_THRESHOLDS 0x21d6 |
549 | #define mmCP_STQ_THRESHOLDS 0x21d7 |
550 | #define mmCP_QUEUE_THRESHOLDS 0x21d8 |
551 | #define mmCP_MEQ_THRESHOLDS 0x21d9 |
552 | #define mmCP_ROQ_AVAIL 0x21da |
553 | #define mmCP_STQ_AVAIL 0x21db |
554 | #define mmCP_ROQ2_AVAIL 0x21dc |
555 | #define mmCP_MEQ_AVAIL 0x21dd |
556 | #define mmCP_CMD_INDEX 0x21de |
557 | #define mmCP_CMD_DATA 0x21df |
558 | #define mmCP_ROQ_RB_STAT 0x21e0 |
559 | #define mmCP_ROQ_IB1_STAT 0x21e1 |
560 | #define mmCP_ROQ_IB2_STAT 0x21e2 |
561 | #define mmCP_STQ_STAT 0x21e3 |
562 | #define mmCP_STQ_WR_STAT 0x21e4 |
563 | #define mmCP_MEQ_STAT 0x21e5 |
564 | #define mmCP_CEQ1_AVAIL 0x21e6 |
565 | #define mmCP_CEQ2_AVAIL 0x21e7 |
566 | #define mmCP_CE_ROQ_RB_STAT 0x21e8 |
567 | #define mmCP_CE_ROQ_IB1_STAT 0x21e9 |
568 | #define mmCP_CE_ROQ_IB2_STAT 0x21ea |
569 | #define mmCP_INT_STAT_DEBUG 0x21f7 |
570 | #define mmCP_PERFMON_CNTL 0xd808 |
571 | #define mmCP_PERFMON_CNTX_CNTL 0xa0d8 |
572 | #define mmCP_RINGID 0xa0d9 |
573 | #define mmCP_PIPEID 0xa0d9 |
574 | #define mmCP_VMID 0xa0da |
575 | #define mmCP_HPD_ROQ_OFFSETS 0x3240 |
576 | #define mmCP_HPD_EOP_BASE_ADDR 0x3241 |
577 | #define mmCP_HPD_EOP_BASE_ADDR_HI 0x3242 |
578 | #define mmCP_HPD_EOP_VMID 0x3243 |
579 | #define mmCP_HPD_EOP_CONTROL 0x3244 |
580 | #define mmCP_MQD_BASE_ADDR 0x3245 |
581 | #define mmCP_MQD_BASE_ADDR_HI 0x3246 |
582 | #define mmCP_HQD_ACTIVE 0x3247 |
583 | #define mmCP_HQD_VMID 0x3248 |
584 | #define mmCP_HQD_PERSISTENT_STATE 0x3249 |
585 | #define mmCP_HQD_PIPE_PRIORITY 0x324a |
586 | #define mmCP_HQD_QUEUE_PRIORITY 0x324b |
587 | #define mmCP_HQD_QUANTUM 0x324c |
588 | #define mmCP_HQD_PQ_BASE 0x324d |
589 | #define mmCP_HQD_PQ_BASE_HI 0x324e |
590 | #define mmCP_HQD_PQ_RPTR 0x324f |
591 | #define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 |
592 | #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251 |
593 | #define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 |
594 | #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 |
595 | #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 |
596 | #define mmCP_HQD_PQ_WPTR 0x3255 |
597 | #define mmCP_HQD_PQ_CONTROL 0x3256 |
598 | #define mmCP_HQD_IB_BASE_ADDR 0x3257 |
599 | #define mmCP_HQD_IB_BASE_ADDR_HI 0x3258 |
600 | #define mmCP_HQD_IB_RPTR 0x3259 |
601 | #define mmCP_HQD_IB_CONTROL 0x325a |
602 | #define mmCP_HQD_IQ_TIMER 0x325b |
603 | #define mmCP_HQD_IQ_RPTR 0x325c |
604 | #define mmCP_HQD_DEQUEUE_REQUEST 0x325d |
605 | #define mmCP_HQD_DMA_OFFLOAD 0x325e |
606 | #define mmCP_HQD_SEMA_CMD 0x325f |
607 | #define mmCP_HQD_MSG_TYPE 0x3260 |
608 | #define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261 |
609 | #define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262 |
610 | #define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263 |
611 | #define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264 |
612 | #define mmCP_HQD_HQ_SCHEDULER0 0x3265 |
613 | #define mmCP_HQD_HQ_SCHEDULER1 0x3266 |
614 | #define mmCP_MQD_CONTROL 0x3267 |
615 | #define mmDB_Z_READ_BASE 0xa012 |
616 | #define mmDB_STENCIL_READ_BASE 0xa013 |
617 | #define mmDB_Z_WRITE_BASE 0xa014 |
618 | #define mmDB_STENCIL_WRITE_BASE 0xa015 |
619 | #define mmDB_DEPTH_INFO 0xa00f |
620 | #define mmDB_Z_INFO 0xa010 |
621 | #define mmDB_STENCIL_INFO 0xa011 |
622 | #define mmDB_DEPTH_SIZE 0xa016 |
623 | #define mmDB_DEPTH_SLICE 0xa017 |
624 | #define mmDB_DEPTH_VIEW 0xa002 |
625 | #define mmDB_RENDER_CONTROL 0xa000 |
626 | #define mmDB_COUNT_CONTROL 0xa001 |
627 | #define mmDB_RENDER_OVERRIDE 0xa003 |
628 | #define mmDB_RENDER_OVERRIDE2 0xa004 |
629 | #define mmDB_EQAA 0xa201 |
630 | #define mmDB_SHADER_CONTROL 0xa203 |
631 | #define mmDB_DEPTH_BOUNDS_MIN 0xa008 |
632 | #define mmDB_DEPTH_BOUNDS_MAX 0xa009 |
633 | #define mmDB_STENCIL_CLEAR 0xa00a |
634 | #define mmDB_DEPTH_CLEAR 0xa00b |
635 | #define mmDB_HTILE_DATA_BASE 0xa005 |
636 | #define mmDB_HTILE_SURFACE 0xa2af |
637 | #define mmDB_PRELOAD_CONTROL 0xa2b2 |
638 | #define mmDB_STENCILREFMASK 0xa10c |
639 | #define mmDB_STENCILREFMASK_BF 0xa10d |
640 | #define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0 |
641 | #define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1 |
642 | #define mmDB_DEPTH_CONTROL 0xa200 |
643 | #define mmDB_STENCIL_CONTROL 0xa10b |
644 | #define mmDB_ALPHA_TO_MASK 0xa2dc |
645 | #define mmDB_PERFCOUNTER0_SELECT 0xdc40 |
646 | #define mmDB_PERFCOUNTER1_SELECT 0xdc42 |
647 | #define mmDB_PERFCOUNTER2_SELECT 0xdc44 |
648 | #define mmDB_PERFCOUNTER3_SELECT 0xdc46 |
649 | #define mmDB_PERFCOUNTER0_SELECT1 0xdc41 |
650 | #define mmDB_PERFCOUNTER1_SELECT1 0xdc43 |
651 | #define mmDB_PERFCOUNTER0_LO 0xd440 |
652 | #define mmDB_PERFCOUNTER1_LO 0xd442 |
653 | #define mmDB_PERFCOUNTER2_LO 0xd444 |
654 | #define mmDB_PERFCOUNTER3_LO 0xd446 |
655 | #define mmDB_PERFCOUNTER0_HI 0xd441 |
656 | #define mmDB_PERFCOUNTER1_HI 0xd443 |
657 | #define mmDB_PERFCOUNTER2_HI 0xd445 |
658 | #define mmDB_PERFCOUNTER3_HI 0xd447 |
659 | #define mmDB_DEBUG 0x260c |
660 | #define mmDB_DEBUG2 0x260d |
661 | #define mmDB_DEBUG3 0x260e |
662 | #define mmDB_DEBUG4 0x260f |
663 | #define mmDB_CREDIT_LIMIT 0x2614 |
664 | #define mmDB_WATERMARKS 0x2615 |
665 | #define mmDB_SUBTILE_CONTROL 0x2616 |
666 | #define mmDB_FREE_CACHELINES 0x2617 |
667 | #define mmDB_FIFO_DEPTH1 0x2618 |
668 | #define mmDB_FIFO_DEPTH2 0x2619 |
669 | #define mmDB_CGTT_CLK_CTRL_0 0xf0a4 |
670 | #define mmDB_ZPASS_COUNT_LOW 0xc3fe |
671 | #define mmDB_ZPASS_COUNT_HI 0xc3ff |
672 | #define mmDB_RING_CONTROL 0x261b |
673 | #define mmDB_READ_DEBUG_0 0x2620 |
674 | #define mmDB_READ_DEBUG_1 0x2621 |
675 | #define mmDB_READ_DEBUG_2 0x2622 |
676 | #define mmDB_READ_DEBUG_3 0x2623 |
677 | #define mmDB_READ_DEBUG_4 0x2624 |
678 | #define mmDB_READ_DEBUG_5 0x2625 |
679 | #define mmDB_READ_DEBUG_6 0x2626 |
680 | #define mmDB_READ_DEBUG_7 0x2627 |
681 | #define mmDB_READ_DEBUG_8 0x2628 |
682 | #define mmDB_READ_DEBUG_9 0x2629 |
683 | #define mmDB_READ_DEBUG_A 0x262a |
684 | #define mmDB_READ_DEBUG_B 0x262b |
685 | #define mmDB_READ_DEBUG_C 0x262c |
686 | #define mmDB_READ_DEBUG_D 0x262d |
687 | #define mmDB_READ_DEBUG_E 0x262e |
688 | #define mmDB_READ_DEBUG_F 0x262f |
689 | #define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0 |
690 | #define mmDB_OCCLUSION_COUNT0_HI 0xc3c1 |
691 | #define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2 |
692 | #define mmDB_OCCLUSION_COUNT1_HI 0xc3c3 |
693 | #define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4 |
694 | #define mmDB_OCCLUSION_COUNT2_HI 0xc3c5 |
695 | #define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6 |
696 | #define mmDB_OCCLUSION_COUNT3_HI 0xc3c7 |
697 | #define mmCC_RB_REDUNDANCY 0x263c |
698 | #define mmCC_RB_BACKEND_DISABLE 0x263d |
699 | #define mmGC_USER_RB_REDUNDANCY 0x26de |
700 | #define mmGC_USER_RB_BACKEND_DISABLE 0x26df |
701 | #define mmGB_ADDR_CONFIG 0x263e |
702 | #define mmGB_BACKEND_MAP 0x263f |
703 | #define mmGB_GPU_ID 0x2640 |
704 | #define mmCC_RB_DAISY_CHAIN 0x2641 |
705 | #define mmGB_TILE_MODE0 0x2644 |
706 | #define mmGB_TILE_MODE1 0x2645 |
707 | #define mmGB_TILE_MODE2 0x2646 |
708 | #define mmGB_TILE_MODE3 0x2647 |
709 | #define mmGB_TILE_MODE4 0x2648 |
710 | #define mmGB_TILE_MODE5 0x2649 |
711 | #define mmGB_TILE_MODE6 0x264a |
712 | #define mmGB_TILE_MODE7 0x264b |
713 | #define mmGB_TILE_MODE8 0x264c |
714 | #define mmGB_TILE_MODE9 0x264d |
715 | #define mmGB_TILE_MODE10 0x264e |
716 | #define mmGB_TILE_MODE11 0x264f |
717 | #define mmGB_TILE_MODE12 0x2650 |
718 | #define mmGB_TILE_MODE13 0x2651 |
719 | #define mmGB_TILE_MODE14 0x2652 |
720 | #define mmGB_TILE_MODE15 0x2653 |
721 | #define mmGB_TILE_MODE16 0x2654 |
722 | #define mmGB_TILE_MODE17 0x2655 |
723 | #define mmGB_TILE_MODE18 0x2656 |
724 | #define mmGB_TILE_MODE19 0x2657 |
725 | #define mmGB_TILE_MODE20 0x2658 |
726 | #define mmGB_TILE_MODE21 0x2659 |
727 | #define mmGB_TILE_MODE22 0x265a |
728 | #define mmGB_TILE_MODE23 0x265b |
729 | #define mmGB_TILE_MODE24 0x265c |
730 | #define mmGB_TILE_MODE25 0x265d |
731 | #define mmGB_TILE_MODE26 0x265e |
732 | #define mmGB_TILE_MODE27 0x265f |
733 | #define mmGB_TILE_MODE28 0x2660 |
734 | #define mmGB_TILE_MODE29 0x2661 |
735 | #define mmGB_TILE_MODE30 0x2662 |
736 | #define mmGB_TILE_MODE31 0x2663 |
737 | #define mmGB_MACROTILE_MODE0 0x2664 |
738 | #define mmGB_MACROTILE_MODE1 0x2665 |
739 | #define mmGB_MACROTILE_MODE2 0x2666 |
740 | #define mmGB_MACROTILE_MODE3 0x2667 |
741 | #define mmGB_MACROTILE_MODE4 0x2668 |
742 | #define mmGB_MACROTILE_MODE5 0x2669 |
743 | #define mmGB_MACROTILE_MODE6 0x266a |
744 | #define mmGB_MACROTILE_MODE7 0x266b |
745 | #define mmGB_MACROTILE_MODE8 0x266c |
746 | #define mmGB_MACROTILE_MODE9 0x266d |
747 | #define mmGB_MACROTILE_MODE10 0x266e |
748 | #define mmGB_MACROTILE_MODE11 0x266f |
749 | #define mmGB_MACROTILE_MODE12 0x2670 |
750 | #define mmGB_MACROTILE_MODE13 0x2671 |
751 | #define mmGB_MACROTILE_MODE14 0x2672 |
752 | #define mmGB_MACROTILE_MODE15 0x2673 |
753 | #define mmGB_EDC_MODE 0x307e |
754 | #define mmCC_GC_EDC_CONFIG 0x3098 |
755 | #define mmRAS_SIGNATURE_CONTROL 0x3380 |
756 | #define mmRAS_SIGNATURE_MASK 0x3381 |
757 | #define mmRAS_SX_SIGNATURE0 0x3382 |
758 | #define mmRAS_SX_SIGNATURE1 0x3383 |
759 | #define mmRAS_SX_SIGNATURE2 0x3384 |
760 | #define mmRAS_SX_SIGNATURE3 0x3385 |
761 | #define mmRAS_DB_SIGNATURE0 0x338b |
762 | #define mmRAS_PA_SIGNATURE0 0x338c |
763 | #define mmRAS_VGT_SIGNATURE0 0x338d |
764 | #define mmRAS_SQ_SIGNATURE0 0x338e |
765 | #define mmRAS_SC_SIGNATURE0 0x338f |
766 | #define mmRAS_SC_SIGNATURE1 0x3390 |
767 | #define mmRAS_SC_SIGNATURE2 0x3391 |
768 | #define mmRAS_SC_SIGNATURE3 0x3392 |
769 | #define mmRAS_SC_SIGNATURE4 0x3393 |
770 | #define mmRAS_SC_SIGNATURE5 0x3394 |
771 | #define mmRAS_SC_SIGNATURE6 0x3395 |
772 | #define mmRAS_SC_SIGNATURE7 0x3396 |
773 | #define mmRAS_IA_SIGNATURE0 0x3397 |
774 | #define mmRAS_IA_SIGNATURE1 0x3398 |
775 | #define mmRAS_SPI_SIGNATURE0 0x3399 |
776 | #define mmRAS_SPI_SIGNATURE1 0x339a |
777 | #define mmRAS_TA_SIGNATURE0 0x339b |
778 | #define mmRAS_TD_SIGNATURE0 0x339c |
779 | #define mmRAS_CB_SIGNATURE0 0x339d |
780 | #define mmRAS_BCI_SIGNATURE0 0x339e |
781 | #define mmRAS_BCI_SIGNATURE1 0x339f |
782 | #define mmGRBM_CAM_INDEX 0x3000 |
783 | #define mmGRBM_CAM_DATA 0x3001 |
784 | #define mmGRBM_CNTL 0x2000 |
785 | #define mmGRBM_SKEW_CNTL 0x2001 |
786 | #define mmGRBM_PWR_CNTL 0x2003 |
787 | #define mmGRBM_STATUS 0x2004 |
788 | #define mmGRBM_STATUS2 0x2002 |
789 | #define mmGRBM_STATUS_SE0 0x2005 |
790 | #define mmGRBM_STATUS_SE1 0x2006 |
791 | #define mmGRBM_STATUS_SE2 0x200e |
792 | #define mmGRBM_STATUS_SE3 0x200f |
793 | #define mmGRBM_SOFT_RESET 0x2008 |
794 | #define mmGRBM_DEBUG_CNTL 0x2009 |
795 | #define mmGRBM_DEBUG_DATA 0x200a |
796 | #define mmGRBM_GFX_INDEX 0xc200 |
797 | #define mmGRBM_GFX_CLKEN_CNTL 0x200c |
798 | #define mmGRBM_WAIT_IDLE_CLOCKS 0x200d |
799 | #define mmGRBM_DEBUG 0x2014 |
800 | #define mmGRBM_DEBUG_SNAPSHOT 0x2015 |
801 | #define mmGRBM_READ_ERROR 0x2016 |
802 | #define mmGRBM_READ_ERROR2 0x2017 |
803 | #define mmGRBM_INT_CNTL 0x2018 |
804 | #define mmGRBM_PERFCOUNTER0_SELECT 0xd840 |
805 | #define mmGRBM_PERFCOUNTER1_SELECT 0xd841 |
806 | #define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842 |
807 | #define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843 |
808 | #define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844 |
809 | #define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845 |
810 | #define mmGRBM_PERFCOUNTER0_LO 0xd040 |
811 | #define mmGRBM_PERFCOUNTER0_HI 0xd041 |
812 | #define mmGRBM_PERFCOUNTER1_LO 0xd043 |
813 | #define mmGRBM_PERFCOUNTER1_HI 0xd044 |
814 | #define mmGRBM_SE0_PERFCOUNTER_LO 0xd045 |
815 | #define mmGRBM_SE0_PERFCOUNTER_HI 0xd046 |
816 | #define mmGRBM_SE1_PERFCOUNTER_LO 0xd047 |
817 | #define mmGRBM_SE1_PERFCOUNTER_HI 0xd048 |
818 | #define mmGRBM_SE2_PERFCOUNTER_LO 0xd049 |
819 | #define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a |
820 | #define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b |
821 | #define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c |
822 | #define mmGRBM_SCRATCH_REG0 0x2040 |
823 | #define mmGRBM_SCRATCH_REG1 0x2041 |
824 | #define mmGRBM_SCRATCH_REG2 0x2042 |
825 | #define mmGRBM_SCRATCH_REG3 0x2043 |
826 | #define mmGRBM_SCRATCH_REG4 0x2044 |
827 | #define mmGRBM_SCRATCH_REG5 0x2045 |
828 | #define mmGRBM_SCRATCH_REG6 0x2046 |
829 | #define mmGRBM_SCRATCH_REG7 0x2047 |
830 | #define mmDEBUG_INDEX 0x203c |
831 | #define mmDEBUG_DATA 0x203d |
832 | #define mmGRBM_NOWHERE 0x203f |
833 | #define mmPA_CL_VPORT_XSCALE 0xa10f |
834 | #define mmPA_CL_VPORT_XOFFSET 0xa110 |
835 | #define mmPA_CL_VPORT_YSCALE 0xa111 |
836 | #define mmPA_CL_VPORT_YOFFSET 0xa112 |
837 | #define mmPA_CL_VPORT_ZSCALE 0xa113 |
838 | #define mmPA_CL_VPORT_ZOFFSET 0xa114 |
839 | #define mmPA_CL_VPORT_XSCALE_1 0xa115 |
840 | #define mmPA_CL_VPORT_XSCALE_2 0xa11b |
841 | #define mmPA_CL_VPORT_XSCALE_3 0xa121 |
842 | #define mmPA_CL_VPORT_XSCALE_4 0xa127 |
843 | #define mmPA_CL_VPORT_XSCALE_5 0xa12d |
844 | #define mmPA_CL_VPORT_XSCALE_6 0xa133 |
845 | #define mmPA_CL_VPORT_XSCALE_7 0xa139 |
846 | #define mmPA_CL_VPORT_XSCALE_8 0xa13f |
847 | #define mmPA_CL_VPORT_XSCALE_9 0xa145 |
848 | #define mmPA_CL_VPORT_XSCALE_10 0xa14b |
849 | #define mmPA_CL_VPORT_XSCALE_11 0xa151 |
850 | #define mmPA_CL_VPORT_XSCALE_12 0xa157 |
851 | #define mmPA_CL_VPORT_XSCALE_13 0xa15d |
852 | #define mmPA_CL_VPORT_XSCALE_14 0xa163 |
853 | #define mmPA_CL_VPORT_XSCALE_15 0xa169 |
854 | #define mmPA_CL_VPORT_XOFFSET_1 0xa116 |
855 | #define mmPA_CL_VPORT_XOFFSET_2 0xa11c |
856 | #define mmPA_CL_VPORT_XOFFSET_3 0xa122 |
857 | #define mmPA_CL_VPORT_XOFFSET_4 0xa128 |
858 | #define mmPA_CL_VPORT_XOFFSET_5 0xa12e |
859 | #define mmPA_CL_VPORT_XOFFSET_6 0xa134 |
860 | #define mmPA_CL_VPORT_XOFFSET_7 0xa13a |
861 | #define mmPA_CL_VPORT_XOFFSET_8 0xa140 |
862 | #define mmPA_CL_VPORT_XOFFSET_9 0xa146 |
863 | #define mmPA_CL_VPORT_XOFFSET_10 0xa14c |
864 | #define mmPA_CL_VPORT_XOFFSET_11 0xa152 |
865 | #define mmPA_CL_VPORT_XOFFSET_12 0xa158 |
866 | #define mmPA_CL_VPORT_XOFFSET_13 0xa15e |
867 | #define mmPA_CL_VPORT_XOFFSET_14 0xa164 |
868 | #define mmPA_CL_VPORT_XOFFSET_15 0xa16a |
869 | #define mmPA_CL_VPORT_YSCALE_1 0xa117 |
870 | #define mmPA_CL_VPORT_YSCALE_2 0xa11d |
871 | #define mmPA_CL_VPORT_YSCALE_3 0xa123 |
872 | #define mmPA_CL_VPORT_YSCALE_4 0xa129 |
873 | #define mmPA_CL_VPORT_YSCALE_5 0xa12f |
874 | #define mmPA_CL_VPORT_YSCALE_6 0xa135 |
875 | #define mmPA_CL_VPORT_YSCALE_7 0xa13b |
876 | #define mmPA_CL_VPORT_YSCALE_8 0xa141 |
877 | #define mmPA_CL_VPORT_YSCALE_9 0xa147 |
878 | #define mmPA_CL_VPORT_YSCALE_10 0xa14d |
879 | #define mmPA_CL_VPORT_YSCALE_11 0xa153 |
880 | #define mmPA_CL_VPORT_YSCALE_12 0xa159 |
881 | #define mmPA_CL_VPORT_YSCALE_13 0xa15f |
882 | #define mmPA_CL_VPORT_YSCALE_14 0xa165 |
883 | #define mmPA_CL_VPORT_YSCALE_15 0xa16b |
884 | #define mmPA_CL_VPORT_YOFFSET_1 0xa118 |
885 | #define mmPA_CL_VPORT_YOFFSET_2 0xa11e |
886 | #define mmPA_CL_VPORT_YOFFSET_3 0xa124 |
887 | #define mmPA_CL_VPORT_YOFFSET_4 0xa12a |
888 | #define mmPA_CL_VPORT_YOFFSET_5 0xa130 |
889 | #define mmPA_CL_VPORT_YOFFSET_6 0xa136 |
890 | #define mmPA_CL_VPORT_YOFFSET_7 0xa13c |
891 | #define mmPA_CL_VPORT_YOFFSET_8 0xa142 |
892 | #define mmPA_CL_VPORT_YOFFSET_9 0xa148 |
893 | #define mmPA_CL_VPORT_YOFFSET_10 0xa14e |
894 | #define mmPA_CL_VPORT_YOFFSET_11 0xa154 |
895 | #define mmPA_CL_VPORT_YOFFSET_12 0xa15a |
896 | #define mmPA_CL_VPORT_YOFFSET_13 0xa160 |
897 | #define mmPA_CL_VPORT_YOFFSET_14 0xa166 |
898 | #define mmPA_CL_VPORT_YOFFSET_15 0xa16c |
899 | #define mmPA_CL_VPORT_ZSCALE_1 0xa119 |
900 | #define mmPA_CL_VPORT_ZSCALE_2 0xa11f |
901 | #define mmPA_CL_VPORT_ZSCALE_3 0xa125 |
902 | #define mmPA_CL_VPORT_ZSCALE_4 0xa12b |
903 | #define mmPA_CL_VPORT_ZSCALE_5 0xa131 |
904 | #define mmPA_CL_VPORT_ZSCALE_6 0xa137 |
905 | #define mmPA_CL_VPORT_ZSCALE_7 0xa13d |
906 | #define mmPA_CL_VPORT_ZSCALE_8 0xa143 |
907 | #define mmPA_CL_VPORT_ZSCALE_9 0xa149 |
908 | #define mmPA_CL_VPORT_ZSCALE_10 0xa14f |
909 | #define mmPA_CL_VPORT_ZSCALE_11 0xa155 |
910 | #define mmPA_CL_VPORT_ZSCALE_12 0xa15b |
911 | #define mmPA_CL_VPORT_ZSCALE_13 0xa161 |
912 | #define mmPA_CL_VPORT_ZSCALE_14 0xa167 |
913 | #define mmPA_CL_VPORT_ZSCALE_15 0xa16d |
914 | #define mmPA_CL_VPORT_ZOFFSET_1 0xa11a |
915 | #define mmPA_CL_VPORT_ZOFFSET_2 0xa120 |
916 | #define mmPA_CL_VPORT_ZOFFSET_3 0xa126 |
917 | #define mmPA_CL_VPORT_ZOFFSET_4 0xa12c |
918 | #define mmPA_CL_VPORT_ZOFFSET_5 0xa132 |
919 | #define mmPA_CL_VPORT_ZOFFSET_6 0xa138 |
920 | #define mmPA_CL_VPORT_ZOFFSET_7 0xa13e |
921 | #define mmPA_CL_VPORT_ZOFFSET_8 0xa144 |
922 | #define mmPA_CL_VPORT_ZOFFSET_9 0xa14a |
923 | #define mmPA_CL_VPORT_ZOFFSET_10 0xa150 |
924 | #define mmPA_CL_VPORT_ZOFFSET_11 0xa156 |
925 | #define mmPA_CL_VPORT_ZOFFSET_12 0xa15c |
926 | #define mmPA_CL_VPORT_ZOFFSET_13 0xa162 |
927 | #define mmPA_CL_VPORT_ZOFFSET_14 0xa168 |
928 | #define mmPA_CL_VPORT_ZOFFSET_15 0xa16e |
929 | #define mmPA_CL_VTE_CNTL 0xa206 |
930 | #define mmPA_CL_VS_OUT_CNTL 0xa207 |
931 | #define mmPA_CL_NANINF_CNTL 0xa208 |
932 | #define mmPA_CL_CLIP_CNTL 0xa204 |
933 | #define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa |
934 | #define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb |
935 | #define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc |
936 | #define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd |
937 | #define mmPA_CL_UCP_0_X 0xa16f |
938 | #define mmPA_CL_UCP_0_Y 0xa170 |
939 | #define mmPA_CL_UCP_0_Z 0xa171 |
940 | #define mmPA_CL_UCP_0_W 0xa172 |
941 | #define mmPA_CL_UCP_1_X 0xa173 |
942 | #define mmPA_CL_UCP_1_Y 0xa174 |
943 | #define mmPA_CL_UCP_1_Z 0xa175 |
944 | #define mmPA_CL_UCP_1_W 0xa176 |
945 | #define mmPA_CL_UCP_2_X 0xa177 |
946 | #define mmPA_CL_UCP_2_Y 0xa178 |
947 | #define mmPA_CL_UCP_2_Z 0xa179 |
948 | #define mmPA_CL_UCP_2_W 0xa17a |
949 | #define mmPA_CL_UCP_3_X 0xa17b |
950 | #define mmPA_CL_UCP_3_Y 0xa17c |
951 | #define mmPA_CL_UCP_3_Z 0xa17d |
952 | #define mmPA_CL_UCP_3_W 0xa17e |
953 | #define mmPA_CL_UCP_4_X 0xa17f |
954 | #define mmPA_CL_UCP_4_Y 0xa180 |
955 | #define mmPA_CL_UCP_4_Z 0xa181 |
956 | #define mmPA_CL_UCP_4_W 0xa182 |
957 | #define mmPA_CL_UCP_5_X 0xa183 |
958 | #define mmPA_CL_UCP_5_Y 0xa184 |
959 | #define mmPA_CL_UCP_5_Z 0xa185 |
960 | #define mmPA_CL_UCP_5_W 0xa186 |
961 | #define mmPA_CL_POINT_X_RAD 0xa1f5 |
962 | #define mmPA_CL_POINT_Y_RAD 0xa1f6 |
963 | #define mmPA_CL_POINT_SIZE 0xa1f7 |
964 | #define mmPA_CL_POINT_CULL_RAD 0xa1f8 |
965 | #define mmPA_CL_ENHANCE 0x2285 |
966 | #define mmPA_CL_RESET_DEBUG 0x2286 |
967 | #define mmPA_SU_VTX_CNTL 0xa2f9 |
968 | #define mmPA_SU_POINT_SIZE 0xa280 |
969 | #define mmPA_SU_POINT_MINMAX 0xa281 |
970 | #define mmPA_SU_LINE_CNTL 0xa282 |
971 | #define mmPA_SU_LINE_STIPPLE_CNTL 0xa209 |
972 | #define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a |
973 | #define mmPA_SU_PRIM_FILTER_CNTL 0xa20b |
974 | #define mmPA_SU_SC_MODE_CNTL 0xa205 |
975 | #define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de |
976 | #define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df |
977 | #define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0 |
978 | #define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1 |
979 | #define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2 |
980 | #define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3 |
981 | #define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d |
982 | #define mmPA_SU_LINE_STIPPLE_VALUE 0xc280 |
983 | #define mmPA_SU_PERFCOUNTER0_SELECT 0xd900 |
984 | #define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901 |
985 | #define mmPA_SU_PERFCOUNTER1_SELECT 0xd902 |
986 | #define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903 |
987 | #define mmPA_SU_PERFCOUNTER2_SELECT 0xd904 |
988 | #define mmPA_SU_PERFCOUNTER3_SELECT 0xd905 |
989 | #define mmPA_SU_PERFCOUNTER0_LO 0xd100 |
990 | #define mmPA_SU_PERFCOUNTER0_HI 0xd101 |
991 | #define mmPA_SU_PERFCOUNTER1_LO 0xd102 |
992 | #define mmPA_SU_PERFCOUNTER1_HI 0xd103 |
993 | #define mmPA_SU_PERFCOUNTER2_LO 0xd104 |
994 | #define mmPA_SU_PERFCOUNTER2_HI 0xd105 |
995 | #define mmPA_SU_PERFCOUNTER3_LO 0xd106 |
996 | #define mmPA_SU_PERFCOUNTER3_HI 0xd107 |
997 | #define mmPA_SC_AA_CONFIG 0xa2f8 |
998 | #define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e |
999 | #define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f |
1000 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe |
1001 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff |
1002 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300 |
1003 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301 |
1004 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302 |
1005 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303 |
1006 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304 |
1007 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305 |
1008 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306 |
1009 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307 |
1010 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308 |
1011 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309 |
1012 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a |
1013 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b |
1014 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c |
1015 | #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d |
1016 | #define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5 |
1017 | #define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6 |
1018 | #define mmPA_SC_CLIPRECT_0_TL 0xa084 |
1019 | #define mmPA_SC_CLIPRECT_0_BR 0xa085 |
1020 | #define mmPA_SC_CLIPRECT_1_TL 0xa086 |
1021 | #define mmPA_SC_CLIPRECT_1_BR 0xa087 |
1022 | #define mmPA_SC_CLIPRECT_2_TL 0xa088 |
1023 | #define mmPA_SC_CLIPRECT_2_BR 0xa089 |
1024 | #define mmPA_SC_CLIPRECT_3_TL 0xa08a |
1025 | #define mmPA_SC_CLIPRECT_3_BR 0xa08b |
1026 | #define mmPA_SC_CLIPRECT_RULE 0xa083 |
1027 | #define mmPA_SC_EDGERULE 0xa08c |
1028 | #define mmPA_SC_LINE_CNTL 0xa2f7 |
1029 | #define mmPA_SC_LINE_STIPPLE 0xa283 |
1030 | #define mmPA_SC_MODE_CNTL_0 0xa292 |
1031 | #define mmPA_SC_MODE_CNTL_1 0xa293 |
1032 | #define mmPA_SC_RASTER_CONFIG 0xa0d4 |
1033 | #define mmPA_SC_RASTER_CONFIG_1 0xa0d5 |
1034 | #define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6 |
1035 | #define mmPA_SC_GENERIC_SCISSOR_TL 0xa090 |
1036 | #define mmPA_SC_GENERIC_SCISSOR_BR 0xa091 |
1037 | #define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c |
1038 | #define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d |
1039 | #define mmPA_SC_WINDOW_OFFSET 0xa080 |
1040 | #define mmPA_SC_WINDOW_SCISSOR_TL 0xa081 |
1041 | #define mmPA_SC_WINDOW_SCISSOR_BR 0xa082 |
1042 | #define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094 |
1043 | #define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096 |
1044 | #define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098 |
1045 | #define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a |
1046 | #define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c |
1047 | #define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e |
1048 | #define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0 |
1049 | #define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2 |
1050 | #define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4 |
1051 | #define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6 |
1052 | #define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8 |
1053 | #define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa |
1054 | #define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac |
1055 | #define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae |
1056 | #define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0 |
1057 | #define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2 |
1058 | #define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095 |
1059 | #define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097 |
1060 | #define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099 |
1061 | #define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b |
1062 | #define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d |
1063 | #define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f |
1064 | #define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1 |
1065 | #define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3 |
1066 | #define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5 |
1067 | #define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7 |
1068 | #define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9 |
1069 | #define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab |
1070 | #define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad |
1071 | #define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af |
1072 | #define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1 |
1073 | #define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3 |
1074 | #define mmPA_SC_VPORT_ZMIN_0 0xa0b4 |
1075 | #define mmPA_SC_VPORT_ZMIN_1 0xa0b6 |
1076 | #define mmPA_SC_VPORT_ZMIN_2 0xa0b8 |
1077 | #define mmPA_SC_VPORT_ZMIN_3 0xa0ba |
1078 | #define mmPA_SC_VPORT_ZMIN_4 0xa0bc |
1079 | #define mmPA_SC_VPORT_ZMIN_5 0xa0be |
1080 | #define mmPA_SC_VPORT_ZMIN_6 0xa0c0 |
1081 | #define mmPA_SC_VPORT_ZMIN_7 0xa0c2 |
1082 | #define mmPA_SC_VPORT_ZMIN_8 0xa0c4 |
1083 | #define mmPA_SC_VPORT_ZMIN_9 0xa0c6 |
1084 | #define mmPA_SC_VPORT_ZMIN_10 0xa0c8 |
1085 | #define mmPA_SC_VPORT_ZMIN_11 0xa0ca |
1086 | #define mmPA_SC_VPORT_ZMIN_12 0xa0cc |
1087 | #define mmPA_SC_VPORT_ZMIN_13 0xa0ce |
1088 | #define mmPA_SC_VPORT_ZMIN_14 0xa0d0 |
1089 | #define mmPA_SC_VPORT_ZMIN_15 0xa0d2 |
1090 | #define mmPA_SC_VPORT_ZMAX_0 0xa0b5 |
1091 | #define mmPA_SC_VPORT_ZMAX_1 0xa0b7 |
1092 | #define mmPA_SC_VPORT_ZMAX_2 0xa0b9 |
1093 | #define mmPA_SC_VPORT_ZMAX_3 0xa0bb |
1094 | #define mmPA_SC_VPORT_ZMAX_4 0xa0bd |
1095 | #define mmPA_SC_VPORT_ZMAX_5 0xa0bf |
1096 | #define mmPA_SC_VPORT_ZMAX_6 0xa0c1 |
1097 | #define mmPA_SC_VPORT_ZMAX_7 0xa0c3 |
1098 | #define mmPA_SC_VPORT_ZMAX_8 0xa0c5 |
1099 | #define mmPA_SC_VPORT_ZMAX_9 0xa0c7 |
1100 | #define mmPA_SC_VPORT_ZMAX_10 0xa0c9 |
1101 | #define mmPA_SC_VPORT_ZMAX_11 0xa0cb |
1102 | #define mmPA_SC_VPORT_ZMAX_12 0xa0cd |
1103 | #define mmPA_SC_VPORT_ZMAX_13 0xa0cf |
1104 | #define mmPA_SC_VPORT_ZMAX_14 0xa0d1 |
1105 | #define mmPA_SC_VPORT_ZMAX_15 0xa0d3 |
1106 | #define mmPA_SC_ENHANCE 0x22fc |
1107 | #define mmPA_SC_FIFO_SIZE 0x22f3 |
1108 | #define mmPA_SC_IF_FIFO_SIZE 0x22f5 |
1109 | #define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9 |
1110 | #define mmPA_SC_LINE_STIPPLE_STATE 0xc281 |
1111 | #define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284 |
1112 | #define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285 |
1113 | #define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286 |
1114 | #define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b |
1115 | #define mmPA_SC_PERFCOUNTER0_SELECT 0xd940 |
1116 | #define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941 |
1117 | #define mmPA_SC_PERFCOUNTER1_SELECT 0xd942 |
1118 | #define mmPA_SC_PERFCOUNTER2_SELECT 0xd943 |
1119 | #define mmPA_SC_PERFCOUNTER3_SELECT 0xd944 |
1120 | #define mmPA_SC_PERFCOUNTER4_SELECT 0xd945 |
1121 | #define mmPA_SC_PERFCOUNTER5_SELECT 0xd946 |
1122 | #define mmPA_SC_PERFCOUNTER6_SELECT 0xd947 |
1123 | #define mmPA_SC_PERFCOUNTER7_SELECT 0xd948 |
1124 | #define mmPA_SC_PERFCOUNTER0_LO 0xd140 |
1125 | #define mmPA_SC_PERFCOUNTER0_HI 0xd141 |
1126 | #define mmPA_SC_PERFCOUNTER1_LO 0xd142 |
1127 | #define mmPA_SC_PERFCOUNTER1_HI 0xd143 |
1128 | #define mmPA_SC_PERFCOUNTER2_LO 0xd144 |
1129 | #define mmPA_SC_PERFCOUNTER2_HI 0xd145 |
1130 | #define mmPA_SC_PERFCOUNTER3_LO 0xd146 |
1131 | #define mmPA_SC_PERFCOUNTER3_HI 0xd147 |
1132 | #define mmPA_SC_PERFCOUNTER4_LO 0xd148 |
1133 | #define mmPA_SC_PERFCOUNTER4_HI 0xd149 |
1134 | #define mmPA_SC_PERFCOUNTER5_LO 0xd14a |
1135 | #define mmPA_SC_PERFCOUNTER5_HI 0xd14b |
1136 | #define mmPA_SC_PERFCOUNTER6_LO 0xd14c |
1137 | #define mmPA_SC_PERFCOUNTER6_HI 0xd14d |
1138 | #define mmPA_SC_PERFCOUNTER7_LO 0xd14e |
1139 | #define mmPA_SC_PERFCOUNTER7_HI 0xd14f |
1140 | #define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0 |
1141 | #define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1 |
1142 | #define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2 |
1143 | #define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3 |
1144 | #define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4 |
1145 | #define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8 |
1146 | #define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9 |
1147 | #define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa |
1148 | #define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab |
1149 | #define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac |
1150 | #define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0 |
1151 | #define mmPA_SC_TRAP_SCREEN_H 0xc2b1 |
1152 | #define mmPA_SC_TRAP_SCREEN_V 0xc2b2 |
1153 | #define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3 |
1154 | #define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4 |
1155 | #define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0 |
1156 | #define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1 |
1157 | #define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2 |
1158 | #define mmPA_CL_CNTL_STATUS 0x2284 |
1159 | #define mmPA_SU_CNTL_STATUS 0x2294 |
1160 | #define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 |
1161 | #define mmCGTT_PA_CLK_CTRL 0xf088 |
1162 | #define mmCGTT_SC_CLK_CTRL 0xf089 |
1163 | #define mmPA_SU_DEBUG_CNTL 0x2280 |
1164 | #define mmPA_SU_DEBUG_DATA 0x2281 |
1165 | #define mmPA_SC_DEBUG_CNTL 0x22f6 |
1166 | #define mmPA_SC_DEBUG_DATA 0x22f7 |
1167 | #define ixCLIPPER_DEBUG_REG00 0x0 |
1168 | #define ixCLIPPER_DEBUG_REG01 0x1 |
1169 | #define ixCLIPPER_DEBUG_REG02 0x2 |
1170 | #define ixCLIPPER_DEBUG_REG03 0x3 |
1171 | #define ixCLIPPER_DEBUG_REG04 0x4 |
1172 | #define ixCLIPPER_DEBUG_REG05 0x5 |
1173 | #define ixCLIPPER_DEBUG_REG06 0x6 |
1174 | #define ixCLIPPER_DEBUG_REG07 0x7 |
1175 | #define ixCLIPPER_DEBUG_REG08 0x8 |
1176 | #define ixCLIPPER_DEBUG_REG09 0x9 |
1177 | #define ixCLIPPER_DEBUG_REG10 0xa |
1178 | #define ixCLIPPER_DEBUG_REG11 0xb |
1179 | #define ixCLIPPER_DEBUG_REG12 0xc |
1180 | #define ixCLIPPER_DEBUG_REG13 0xd |
1181 | #define ixCLIPPER_DEBUG_REG14 0xe |
1182 | #define ixCLIPPER_DEBUG_REG15 0xf |
1183 | #define ixCLIPPER_DEBUG_REG16 0x10 |
1184 | #define ixCLIPPER_DEBUG_REG17 0x11 |
1185 | #define ixCLIPPER_DEBUG_REG18 0x12 |
1186 | #define ixCLIPPER_DEBUG_REG19 0x13 |
1187 | #define ixSXIFCCG_DEBUG_REG0 0x14 |
1188 | #define ixSXIFCCG_DEBUG_REG1 0x15 |
1189 | #define ixSXIFCCG_DEBUG_REG2 0x16 |
1190 | #define ixSXIFCCG_DEBUG_REG3 0x17 |
1191 | #define ixSETUP_DEBUG_REG0 0x18 |
1192 | #define ixSETUP_DEBUG_REG1 0x19 |
1193 | #define ixSETUP_DEBUG_REG2 0x1a |
1194 | #define ixSETUP_DEBUG_REG3 0x1b |
1195 | #define ixSETUP_DEBUG_REG4 0x1c |
1196 | #define ixSETUP_DEBUG_REG5 0x1d |
1197 | #define ixPA_SC_DEBUG_REG0 0x0 |
1198 | #define ixPA_SC_DEBUG_REG1 0x1 |
1199 | #define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00 |
1200 | #define mmCOMPUTE_DIM_X 0x2e01 |
1201 | #define mmCOMPUTE_DIM_Y 0x2e02 |
1202 | #define mmCOMPUTE_DIM_Z 0x2e03 |
1203 | #define mmCOMPUTE_START_X 0x2e04 |
1204 | #define mmCOMPUTE_START_Y 0x2e05 |
1205 | #define mmCOMPUTE_START_Z 0x2e06 |
1206 | #define mmCOMPUTE_NUM_THREAD_X 0x2e07 |
1207 | #define mmCOMPUTE_NUM_THREAD_Y 0x2e08 |
1208 | #define mmCOMPUTE_NUM_THREAD_Z 0x2e09 |
1209 | #define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a |
1210 | #define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b |
1211 | #define mmCOMPUTE_PGM_LO 0x2e0c |
1212 | #define mmCOMPUTE_PGM_HI 0x2e0d |
1213 | #define mmCOMPUTE_TBA_LO 0x2e0e |
1214 | #define mmCOMPUTE_TBA_HI 0x2e0f |
1215 | #define mmCOMPUTE_TMA_LO 0x2e10 |
1216 | #define mmCOMPUTE_TMA_HI 0x2e11 |
1217 | #define mmCOMPUTE_PGM_RSRC1 0x2e12 |
1218 | #define mmCOMPUTE_PGM_RSRC2 0x2e13 |
1219 | #define mmCOMPUTE_VMID 0x2e14 |
1220 | #define mmCOMPUTE_RESOURCE_LIMITS 0x2e15 |
1221 | #define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16 |
1222 | #define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17 |
1223 | #define mmCOMPUTE_TMPRING_SIZE 0x2e18 |
1224 | #define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19 |
1225 | #define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a |
1226 | #define mmCOMPUTE_RESTART_X 0x2e1b |
1227 | #define mmCOMPUTE_RESTART_Y 0x2e1c |
1228 | #define mmCOMPUTE_RESTART_Z 0x2e1d |
1229 | #define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e |
1230 | #define mmCOMPUTE_MISC_RESERVED 0x2e1f |
1231 | #define mmCOMPUTE_USER_DATA_0 0x2e40 |
1232 | #define mmCOMPUTE_USER_DATA_1 0x2e41 |
1233 | #define mmCOMPUTE_USER_DATA_2 0x2e42 |
1234 | #define mmCOMPUTE_USER_DATA_3 0x2e43 |
1235 | #define mmCOMPUTE_USER_DATA_4 0x2e44 |
1236 | #define mmCOMPUTE_USER_DATA_5 0x2e45 |
1237 | #define mmCOMPUTE_USER_DATA_6 0x2e46 |
1238 | #define mmCOMPUTE_USER_DATA_7 0x2e47 |
1239 | #define mmCOMPUTE_USER_DATA_8 0x2e48 |
1240 | #define mmCOMPUTE_USER_DATA_9 0x2e49 |
1241 | #define mmCOMPUTE_USER_DATA_10 0x2e4a |
1242 | #define mmCOMPUTE_USER_DATA_11 0x2e4b |
1243 | #define mmCOMPUTE_USER_DATA_12 0x2e4c |
1244 | #define mmCOMPUTE_USER_DATA_13 0x2e4d |
1245 | #define mmCOMPUTE_USER_DATA_14 0x2e4e |
1246 | #define mmCOMPUTE_USER_DATA_15 0x2e4f |
1247 | #define mmCSPRIV_CONNECT 0x0 |
1248 | #define mmCSPRIV_THREAD_TRACE_TG0 0x1e |
1249 | #define mmCSPRIV_THREAD_TRACE_TG1 0x1e |
1250 | #define mmCSPRIV_THREAD_TRACE_TG2 0x1e |
1251 | #define mmCSPRIV_THREAD_TRACE_TG3 0x1e |
1252 | #define mmCSPRIV_THREAD_TRACE_EVENT 0x1f |
1253 | #define mmRLC_CNTL 0x30c0 |
1254 | #define mmRLC_DEBUG_SELECT 0x30c1 |
1255 | #define mmRLC_DEBUG 0x30c2 |
1256 | #define mmRLC_MC_CNTL 0x30c3 |
1257 | #define mmRLC_STAT 0x30c4 |
1258 | #define mmRLC_SAFE_MODE 0x313a |
1259 | #define mmRLC_SOFT_RESET_GPU 0x30c5 |
1260 | #define mmRLC_MEM_SLP_CNTL 0x30c6 |
1261 | #define mmRLC_PERFMON_CNTL 0xdcc0 |
1262 | #define mmRLC_PERFCOUNTER0_SELECT 0xdcc1 |
1263 | #define mmRLC_PERFCOUNTER1_SELECT 0xdcc2 |
1264 | #define mmRLC_PERFCOUNTER0_LO 0xd480 |
1265 | #define mmRLC_PERFCOUNTER1_LO 0xd482 |
1266 | #define mmRLC_PERFCOUNTER0_HI 0xd481 |
1267 | #define mmRLC_PERFCOUNTER1_HI 0xd483 |
1268 | #define mmCGTT_RLC_CLK_CTRL 0xf0b8 |
1269 | #define mmRLC_LB_CNTL 0x30d9 |
1270 | #define mmRLC_LB_CNTR_MAX 0x30d2 |
1271 | #define mmRLC_LB_CNTR_INIT 0x30db |
1272 | #define mmRLC_LOAD_BALANCE_CNTR 0x30dc |
1273 | #define mmRLC_SAVE_AND_RESTORE_BASE 0x30dd |
1274 | #define mmRLC_JUMP_TABLE_RESTORE 0x30de |
1275 | #define mmRLC_DRIVER_CPDMA_STATUS 0x30de |
1276 | #define mmRLC_PG_DELAY_2 0x30df |
1277 | #define mmRLC_GPM_DEBUG_SELECT 0x30e0 |
1278 | #define mmRLC_GPM_DEBUG 0x30e1 |
1279 | #define mmRLC_GPM_UCODE_ADDR 0x30e2 |
1280 | #define mmRLC_GPM_UCODE_DATA 0x30e3 |
1281 | #define mmRLC_GPU_CLOCK_COUNT_LSB 0x30e4 |
1282 | #define mmRLC_GPU_CLOCK_COUNT_MSB 0x30e5 |
1283 | #define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30e6 |
1284 | #define mmRLC_UCODE_CNTL 0x30e7 |
1285 | #define mmRLC_GPM_STAT 0x3100 |
1286 | #define mmRLC_GPU_CLOCK_32_RES_SEL 0x3101 |
1287 | #define mmRLC_GPU_CLOCK_32 0x3102 |
1288 | #define mmRLC_PG_CNTL 0x3103 |
1289 | #define mmRLC_GPM_THREAD_PRIORITY 0x3104 |
1290 | #define mmRLC_GPM_THREAD_ENABLE 0x3105 |
1291 | #define mmRLC_GPM_VMID_THREAD0 0x3106 |
1292 | #define mmRLC_GPM_VMID_THREAD1 0x3107 |
1293 | #define mmRLC_CGTT_MGCG_OVERRIDE 0x3108 |
1294 | #define mmRLC_CGCG_CGLS_CTRL 0x3109 |
1295 | #define mmRLC_CGCG_RAMP_CTRL 0x310a |
1296 | #define mmRLC_DYN_PG_STATUS 0x310b |
1297 | #define mmRLC_DYN_PG_REQUEST 0x310c |
1298 | #define mmRLC_PG_DELAY 0x310d |
1299 | #define mmRLC_CU_STATUS 0x310e |
1300 | #define mmRLC_LB_INIT_CU_MASK 0x310f |
1301 | #define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3110 |
1302 | #define mmRLC_LB_PARAMS 0x3111 |
1303 | #define mmRLC_THREAD1_DELAY 0x3112 |
1304 | #define mmRLC_PG_ALWAYS_ON_CU_MASK 0x3113 |
1305 | #define mmRLC_MAX_PG_CU 0x3114 |
1306 | #define mmRLC_AUTO_PG_CTRL 0x3115 |
1307 | #define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x3116 |
1308 | #define mmRLC_SMU_PG_CTRL 0x3117 |
1309 | #define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3118 |
1310 | #define mmRLC_SERDES_RD_MASTER_INDEX 0x3119 |
1311 | #define mmRLC_SERDES_RD_DATA_0 0x311a |
1312 | #define mmRLC_SERDES_RD_DATA_1 0x311b |
1313 | #define mmRLC_SERDES_RD_DATA_2 0x311c |
1314 | #define mmRLC_SERDES_WR_CU_MASTER_MASK 0x311d |
1315 | #define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x311e |
1316 | #define mmRLC_SERDES_WR_CTRL 0x311f |
1317 | #define mmRLC_SERDES_WR_DATA 0x3120 |
1318 | #define mmRLC_SERDES_CU_MASTER_BUSY 0x3121 |
1319 | #define mmRLC_SERDES_NONCU_MASTER_BUSY 0x3122 |
1320 | #define mmRLC_GPM_GENERAL_0 0x3123 |
1321 | #define mmRLC_GPM_GENERAL_1 0x3124 |
1322 | #define mmRLC_GPM_GENERAL_2 0x3125 |
1323 | #define mmRLC_GPM_GENERAL_3 0x3126 |
1324 | #define mmRLC_GPM_GENERAL_4 0x3127 |
1325 | #define mmRLC_GPM_GENERAL_5 0x3128 |
1326 | #define mmRLC_GPM_GENERAL_6 0x3129 |
1327 | #define mmRLC_GPM_GENERAL_7 0x312a |
1328 | #define mmRLC_GPM_CU_PD_TIMEOUT 0x312b |
1329 | #define mmRLC_GPM_SCRATCH_ADDR 0x312c |
1330 | #define mmRLC_GPM_SCRATCH_DATA 0x312d |
1331 | #define mmRLC_STATIC_PG_STATUS 0x312e |
1332 | #define mmRLC_GPM_PERF_COUNT_0 0x312f |
1333 | #define mmRLC_GPM_PERF_COUNT_1 0x3130 |
1334 | #define mmRLC_GPR_REG1 0x3139 |
1335 | #define mmRLC_GPR_REG2 0x313a |
1336 | #define mmRLC_SPM_VMID 0x3131 |
1337 | #define mmRLC_SPM_INT_CNTL 0x3132 |
1338 | #define mmRLC_SPM_INT_STATUS 0x3133 |
1339 | #define mmRLC_SPM_DEBUG_SELECT 0x3134 |
1340 | #define mmRLC_SPM_DEBUG 0x3135 |
1341 | #define mmRLC_GPM_LOG_ADDR 0x3136 |
1342 | #define mmRLC_GPM_LOG_SIZE 0x3137 |
1343 | #define mmRLC_GPM_LOG_CONT 0x3138 |
1344 | #define mmRLC_SPM_PERFMON_CNTL 0xdc80 |
1345 | #define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81 |
1346 | #define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82 |
1347 | #define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83 |
1348 | #define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84 |
1349 | #define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85 |
1350 | #define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86 |
1351 | #define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87 |
1352 | #define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88 |
1353 | #define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89 |
1354 | #define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a |
1355 | #define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b |
1356 | #define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c |
1357 | #define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d |
1358 | #define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e |
1359 | #define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90 |
1360 | #define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91 |
1361 | #define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92 |
1362 | #define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93 |
1363 | #define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94 |
1364 | #define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95 |
1365 | #define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96 |
1366 | #define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97 |
1367 | #define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98 |
1368 | #define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY 0xdc99 |
1369 | #define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a |
1370 | #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b |
1371 | #define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c |
1372 | #define mmRLC_SPM_RING_RDPTR 0xdc9d |
1373 | #define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e |
1374 | #define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY 0xdc9f |
1375 | #define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY 0xdca0 |
1376 | #define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY 0xdca1 |
1377 | #define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY 0xdca2 |
1378 | #define mmSPI_PS_INPUT_CNTL_0 0xa191 |
1379 | #define mmSPI_PS_INPUT_CNTL_1 0xa192 |
1380 | #define mmSPI_PS_INPUT_CNTL_2 0xa193 |
1381 | #define mmSPI_PS_INPUT_CNTL_3 0xa194 |
1382 | #define mmSPI_PS_INPUT_CNTL_4 0xa195 |
1383 | #define mmSPI_PS_INPUT_CNTL_5 0xa196 |
1384 | #define mmSPI_PS_INPUT_CNTL_6 0xa197 |
1385 | #define mmSPI_PS_INPUT_CNTL_7 0xa198 |
1386 | #define mmSPI_PS_INPUT_CNTL_8 0xa199 |
1387 | #define mmSPI_PS_INPUT_CNTL_9 0xa19a |
1388 | #define mmSPI_PS_INPUT_CNTL_10 0xa19b |
1389 | #define mmSPI_PS_INPUT_CNTL_11 0xa19c |
1390 | #define mmSPI_PS_INPUT_CNTL_12 0xa19d |
1391 | #define mmSPI_PS_INPUT_CNTL_13 0xa19e |
1392 | #define mmSPI_PS_INPUT_CNTL_14 0xa19f |
1393 | #define mmSPI_PS_INPUT_CNTL_15 0xa1a0 |
1394 | #define mmSPI_PS_INPUT_CNTL_16 0xa1a1 |
1395 | #define mmSPI_PS_INPUT_CNTL_17 0xa1a2 |
1396 | #define mmSPI_PS_INPUT_CNTL_18 0xa1a3 |
1397 | #define mmSPI_PS_INPUT_CNTL_19 0xa1a4 |
1398 | #define mmSPI_PS_INPUT_CNTL_20 0xa1a5 |
1399 | #define mmSPI_PS_INPUT_CNTL_21 0xa1a6 |
1400 | #define mmSPI_PS_INPUT_CNTL_22 0xa1a7 |
1401 | #define mmSPI_PS_INPUT_CNTL_23 0xa1a8 |
1402 | #define mmSPI_PS_INPUT_CNTL_24 0xa1a9 |
1403 | #define mmSPI_PS_INPUT_CNTL_25 0xa1aa |
1404 | #define mmSPI_PS_INPUT_CNTL_26 0xa1ab |
1405 | #define mmSPI_PS_INPUT_CNTL_27 0xa1ac |
1406 | #define mmSPI_PS_INPUT_CNTL_28 0xa1ad |
1407 | #define mmSPI_PS_INPUT_CNTL_29 0xa1ae |
1408 | #define mmSPI_PS_INPUT_CNTL_30 0xa1af |
1409 | #define mmSPI_PS_INPUT_CNTL_31 0xa1b0 |
1410 | #define mmSPI_VS_OUT_CONFIG 0xa1b1 |
1411 | #define mmSPI_PS_INPUT_ENA 0xa1b3 |
1412 | #define mmSPI_PS_INPUT_ADDR 0xa1b4 |
1413 | #define mmSPI_INTERP_CONTROL_0 0xa1b5 |
1414 | #define mmSPI_PS_IN_CONTROL 0xa1b6 |
1415 | #define mmSPI_BARYC_CNTL 0xa1b8 |
1416 | #define mmSPI_TMPRING_SIZE 0xa1ba |
1417 | #define mmSPI_SHADER_POS_FORMAT 0xa1c3 |
1418 | #define mmSPI_SHADER_Z_FORMAT 0xa1c4 |
1419 | #define mmSPI_SHADER_COL_FORMAT 0xa1c5 |
1420 | #define mmSPI_ARB_PRIORITY 0x31c0 |
1421 | #define mmSPI_ARB_CYCLES_0 0x31c1 |
1422 | #define mmSPI_ARB_CYCLES_1 0x31c2 |
1423 | #define mmSPI_CDBG_SYS_GFX 0x31c3 |
1424 | #define mmSPI_CDBG_SYS_HP3D 0x31c4 |
1425 | #define mmSPI_CDBG_SYS_CS0 0x31c5 |
1426 | #define mmSPI_CDBG_SYS_CS1 0x31c6 |
1427 | #define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 |
1428 | #define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8 |
1429 | #define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9 |
1430 | #define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca |
1431 | #define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb |
1432 | #define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc |
1433 | #define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd |
1434 | #define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce |
1435 | #define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf |
1436 | #define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0 |
1437 | #define mmSPI_GDBG_WAVE_CNTL 0x31d1 |
1438 | #define mmSPI_GDBG_TRAP_CONFIG 0x31d2 |
1439 | #define mmSPI_GDBG_TRAP_MASK 0x31d3 |
1440 | #define mmSPI_GDBG_TBA_LO 0x31d4 |
1441 | #define mmSPI_GDBG_TBA_HI 0x31d5 |
1442 | #define mmSPI_GDBG_TMA_LO 0x31d6 |
1443 | #define mmSPI_GDBG_TMA_HI 0x31d7 |
1444 | #define mmSPI_GDBG_TRAP_DATA0 0x31d8 |
1445 | #define mmSPI_GDBG_TRAP_DATA1 0x31d9 |
1446 | #define mmSPI_RESET_DEBUG 0x31da |
1447 | #define mmSPI_COMPUTE_QUEUE_RESET 0x31db |
1448 | #define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc |
1449 | #define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd |
1450 | #define mmSPI_RESOURCE_RESERVE_CU_2 0x31de |
1451 | #define mmSPI_RESOURCE_RESERVE_CU_3 0x31df |
1452 | #define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0 |
1453 | #define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1 |
1454 | #define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2 |
1455 | #define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3 |
1456 | #define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4 |
1457 | #define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5 |
1458 | #define mmSPI_RESOURCE_RESERVE_CU_10 0x31f0 |
1459 | #define mmSPI_RESOURCE_RESERVE_CU_11 0x31f1 |
1460 | #define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6 |
1461 | #define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7 |
1462 | #define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8 |
1463 | #define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9 |
1464 | #define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea |
1465 | #define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb |
1466 | #define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec |
1467 | #define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed |
1468 | #define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee |
1469 | #define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef |
1470 | #define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x31f2 |
1471 | #define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x31f3 |
1472 | #define mmSPI_PS_MAX_WAVE_ID 0x243a |
1473 | #define mmSPI_CONFIG_CNTL 0x2440 |
1474 | #define mmSPI_DEBUG_CNTL 0x2441 |
1475 | #define mmSPI_DEBUG_READ 0x2442 |
1476 | #define mmSPI_PERFCOUNTER0_SELECT 0xd980 |
1477 | #define mmSPI_PERFCOUNTER1_SELECT 0xd981 |
1478 | #define mmSPI_PERFCOUNTER2_SELECT 0xd982 |
1479 | #define mmSPI_PERFCOUNTER3_SELECT 0xd983 |
1480 | #define mmSPI_PERFCOUNTER0_SELECT1 0xd984 |
1481 | #define mmSPI_PERFCOUNTER1_SELECT1 0xd985 |
1482 | #define mmSPI_PERFCOUNTER2_SELECT1 0xd986 |
1483 | #define mmSPI_PERFCOUNTER3_SELECT1 0xd987 |
1484 | #define mmSPI_PERFCOUNTER4_SELECT 0xd988 |
1485 | #define mmSPI_PERFCOUNTER5_SELECT 0xd989 |
1486 | #define mmSPI_PERFCOUNTER_BINS 0xd98a |
1487 | #define mmSPI_PERFCOUNTER0_HI 0xd180 |
1488 | #define mmSPI_PERFCOUNTER0_LO 0xd181 |
1489 | #define mmSPI_PERFCOUNTER1_HI 0xd182 |
1490 | #define mmSPI_PERFCOUNTER1_LO 0xd183 |
1491 | #define mmSPI_PERFCOUNTER2_HI 0xd184 |
1492 | #define mmSPI_PERFCOUNTER2_LO 0xd185 |
1493 | #define mmSPI_PERFCOUNTER3_HI 0xd186 |
1494 | #define mmSPI_PERFCOUNTER3_LO 0xd187 |
1495 | #define mmSPI_PERFCOUNTER4_HI 0xd188 |
1496 | #define mmSPI_PERFCOUNTER4_LO 0xd189 |
1497 | #define mmSPI_PERFCOUNTER5_HI 0xd18a |
1498 | #define mmSPI_PERFCOUNTER5_LO 0xd18b |
1499 | #define mmSPI_CONFIG_CNTL_1 0x244f |
1500 | #define mmSPI_DEBUG_BUSY 0x2450 |
1501 | #define mmCGTS_SM_CTRL_REG 0xf000 |
1502 | #define mmCGTS_RD_CTRL_REG 0xf001 |
1503 | #define mmCGTS_RD_REG 0xf002 |
1504 | #define mmCGTS_TCC_DISABLE 0xf003 |
1505 | #define mmCGTS_USER_TCC_DISABLE 0xf004 |
1506 | #define mmCGTS_CU0_SP0_CTRL_REG 0xf008 |
1507 | #define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009 |
1508 | #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a |
1509 | #define mmCGTS_CU0_SP1_CTRL_REG 0xf00b |
1510 | #define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c |
1511 | #define mmCGTS_CU1_SP0_CTRL_REG 0xf00d |
1512 | #define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e |
1513 | #define mmCGTS_CU1_TA_CTRL_REG 0xf00f |
1514 | #define mmCGTS_CU1_SP1_CTRL_REG 0xf010 |
1515 | #define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011 |
1516 | #define mmCGTS_CU2_SP0_CTRL_REG 0xf012 |
1517 | #define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013 |
1518 | #define mmCGTS_CU2_TA_CTRL_REG 0xf014 |
1519 | #define mmCGTS_CU2_SP1_CTRL_REG 0xf015 |
1520 | #define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016 |
1521 | #define mmCGTS_CU3_SP0_CTRL_REG 0xf017 |
1522 | #define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018 |
1523 | #define mmCGTS_CU3_TA_CTRL_REG 0xf019 |
1524 | #define mmCGTS_CU3_SP1_CTRL_REG 0xf01a |
1525 | #define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b |
1526 | #define mmCGTS_CU4_SP0_CTRL_REG 0xf01c |
1527 | #define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d |
1528 | #define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e |
1529 | #define mmCGTS_CU4_SP1_CTRL_REG 0xf01f |
1530 | #define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020 |
1531 | #define mmCGTS_CU5_SP0_CTRL_REG 0xf021 |
1532 | #define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022 |
1533 | #define mmCGTS_CU5_TA_CTRL_REG 0xf023 |
1534 | #define mmCGTS_CU5_SP1_CTRL_REG 0xf024 |
1535 | #define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025 |
1536 | #define mmCGTS_CU6_SP0_CTRL_REG 0xf026 |
1537 | #define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027 |
1538 | #define mmCGTS_CU6_TA_CTRL_REG 0xf028 |
1539 | #define mmCGTS_CU6_SP1_CTRL_REG 0xf029 |
1540 | #define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a |
1541 | #define mmCGTS_CU7_SP0_CTRL_REG 0xf02b |
1542 | #define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c |
1543 | #define mmCGTS_CU7_TA_CTRL_REG 0xf02d |
1544 | #define mmCGTS_CU7_SP1_CTRL_REG 0xf02e |
1545 | #define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f |
1546 | #define mmCGTS_CU8_SP0_CTRL_REG 0xf030 |
1547 | #define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031 |
1548 | #define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032 |
1549 | #define mmCGTS_CU8_SP1_CTRL_REG 0xf033 |
1550 | #define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034 |
1551 | #define mmCGTS_CU9_SP0_CTRL_REG 0xf035 |
1552 | #define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036 |
1553 | #define mmCGTS_CU9_TA_CTRL_REG 0xf037 |
1554 | #define mmCGTS_CU9_SP1_CTRL_REG 0xf038 |
1555 | #define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039 |
1556 | #define mmCGTS_CU10_SP0_CTRL_REG 0xf03a |
1557 | #define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b |
1558 | #define mmCGTS_CU10_TA_CTRL_REG 0xf03c |
1559 | #define mmCGTS_CU10_SP1_CTRL_REG 0xf03d |
1560 | #define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e |
1561 | #define mmCGTS_CU11_SP0_CTRL_REG 0xf03f |
1562 | #define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040 |
1563 | #define mmCGTS_CU11_TA_CTRL_REG 0xf041 |
1564 | #define mmCGTS_CU11_SP1_CTRL_REG 0xf042 |
1565 | #define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043 |
1566 | #define mmCGTS_CU12_SP0_CTRL_REG 0xf044 |
1567 | #define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045 |
1568 | #define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046 |
1569 | #define mmCGTS_CU12_SP1_CTRL_REG 0xf047 |
1570 | #define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048 |
1571 | #define mmCGTS_CU13_SP0_CTRL_REG 0xf049 |
1572 | #define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a |
1573 | #define mmCGTS_CU13_TA_CTRL_REG 0xf04b |
1574 | #define mmCGTS_CU13_SP1_CTRL_REG 0xf04c |
1575 | #define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d |
1576 | #define mmCGTS_CU14_SP0_CTRL_REG 0xf04e |
1577 | #define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f |
1578 | #define mmCGTS_CU14_TA_CTRL_REG 0xf050 |
1579 | #define mmCGTS_CU14_SP1_CTRL_REG 0xf051 |
1580 | #define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052 |
1581 | #define mmCGTS_CU15_SP0_CTRL_REG 0xf053 |
1582 | #define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 |
1583 | #define mmCGTS_CU15_TA_CTRL_REG 0xf055 |
1584 | #define mmCGTS_CU15_SP1_CTRL_REG 0xf056 |
1585 | #define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057 |
1586 | #define mmCGTT_SPI_CLK_CTRL 0xf080 |
1587 | #define mmCGTT_PC_CLK_CTRL 0xf081 |
1588 | #define mmCGTT_BCI_CLK_CTRL 0xf082 |
1589 | #define mmSPI_WF_LIFETIME_CNTL 0x24aa |
1590 | #define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab |
1591 | #define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac |
1592 | #define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad |
1593 | #define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae |
1594 | #define mmSPI_WF_LIFETIME_LIMIT_4 0x24af |
1595 | #define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0 |
1596 | #define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1 |
1597 | #define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2 |
1598 | #define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3 |
1599 | #define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4 |
1600 | #define mmSPI_WF_LIFETIME_STATUS_0 0x24b5 |
1601 | #define mmSPI_WF_LIFETIME_STATUS_1 0x24b6 |
1602 | #define mmSPI_WF_LIFETIME_STATUS_2 0x24b7 |
1603 | #define mmSPI_WF_LIFETIME_STATUS_3 0x24b8 |
1604 | #define mmSPI_WF_LIFETIME_STATUS_4 0x24b9 |
1605 | #define mmSPI_WF_LIFETIME_STATUS_5 0x24ba |
1606 | #define mmSPI_WF_LIFETIME_STATUS_6 0x24bb |
1607 | #define mmSPI_WF_LIFETIME_STATUS_7 0x24bc |
1608 | #define mmSPI_WF_LIFETIME_STATUS_8 0x24bd |
1609 | #define mmSPI_WF_LIFETIME_STATUS_9 0x24be |
1610 | #define mmSPI_WF_LIFETIME_STATUS_10 0x24bf |
1611 | #define mmSPI_WF_LIFETIME_STATUS_11 0x24c0 |
1612 | #define mmSPI_WF_LIFETIME_STATUS_12 0x24c1 |
1613 | #define mmSPI_WF_LIFETIME_STATUS_13 0x24c2 |
1614 | #define mmSPI_WF_LIFETIME_STATUS_14 0x24c3 |
1615 | #define mmSPI_WF_LIFETIME_STATUS_15 0x24c4 |
1616 | #define mmSPI_WF_LIFETIME_STATUS_16 0x24c5 |
1617 | #define mmSPI_WF_LIFETIME_STATUS_17 0x24c6 |
1618 | #define mmSPI_WF_LIFETIME_STATUS_18 0x24c7 |
1619 | #define mmSPI_WF_LIFETIME_STATUS_19 0x24c8 |
1620 | #define mmSPI_WF_LIFETIME_STATUS_20 0x24c9 |
1621 | #define mmSPI_WF_LIFETIME_DEBUG 0x24ca |
1622 | #define mmSPI_SLAVE_DEBUG_BUSY 0x24d3 |
1623 | #define mmSPI_LB_CTR_CTRL 0x24d4 |
1624 | #define mmSPI_LB_CU_MASK 0x24d5 |
1625 | #define mmSPI_LB_DATA_REG 0x24d6 |
1626 | #define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7 |
1627 | #define mmSPI_GDS_CREDITS 0x24d8 |
1628 | #define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9 |
1629 | #define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da |
1630 | #define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db |
1631 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc |
1632 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd |
1633 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de |
1634 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df |
1635 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0 |
1636 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1 |
1637 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2 |
1638 | #define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3 |
1639 | #define mmBCI_DEBUG_READ 0x24eb |
1640 | #define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec |
1641 | #define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed |
1642 | #define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee |
1643 | #define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef |
1644 | #define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0 |
1645 | #define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1 |
1646 | #define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2 |
1647 | #define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3 |
1648 | #define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4 |
1649 | #define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5 |
1650 | #define mmSPI_SHADER_TBA_LO_PS 0x2c00 |
1651 | #define mmSPI_SHADER_TBA_HI_PS 0x2c01 |
1652 | #define mmSPI_SHADER_TMA_LO_PS 0x2c02 |
1653 | #define mmSPI_SHADER_TMA_HI_PS 0x2c03 |
1654 | #define mmSPI_SHADER_PGM_LO_PS 0x2c08 |
1655 | #define mmSPI_SHADER_PGM_HI_PS 0x2c09 |
1656 | #define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a |
1657 | #define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b |
1658 | #define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07 |
1659 | #define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c |
1660 | #define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d |
1661 | #define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e |
1662 | #define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f |
1663 | #define mmSPI_SHADER_USER_DATA_PS_4 0x2c10 |
1664 | #define mmSPI_SHADER_USER_DATA_PS_5 0x2c11 |
1665 | #define mmSPI_SHADER_USER_DATA_PS_6 0x2c12 |
1666 | #define mmSPI_SHADER_USER_DATA_PS_7 0x2c13 |
1667 | #define mmSPI_SHADER_USER_DATA_PS_8 0x2c14 |
1668 | #define mmSPI_SHADER_USER_DATA_PS_9 0x2c15 |
1669 | #define mmSPI_SHADER_USER_DATA_PS_10 0x2c16 |
1670 | #define mmSPI_SHADER_USER_DATA_PS_11 0x2c17 |
1671 | #define mmSPI_SHADER_USER_DATA_PS_12 0x2c18 |
1672 | #define mmSPI_SHADER_USER_DATA_PS_13 0x2c19 |
1673 | #define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a |
1674 | #define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b |
1675 | #define mmSPI_SHADER_TBA_LO_VS 0x2c40 |
1676 | #define mmSPI_SHADER_TBA_HI_VS 0x2c41 |
1677 | #define mmSPI_SHADER_TMA_LO_VS 0x2c42 |
1678 | #define mmSPI_SHADER_TMA_HI_VS 0x2c43 |
1679 | #define mmSPI_SHADER_PGM_LO_VS 0x2c48 |
1680 | #define mmSPI_SHADER_PGM_HI_VS 0x2c49 |
1681 | #define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a |
1682 | #define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b |
1683 | #define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46 |
1684 | #define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47 |
1685 | #define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c |
1686 | #define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d |
1687 | #define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e |
1688 | #define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f |
1689 | #define mmSPI_SHADER_USER_DATA_VS_4 0x2c50 |
1690 | #define mmSPI_SHADER_USER_DATA_VS_5 0x2c51 |
1691 | #define mmSPI_SHADER_USER_DATA_VS_6 0x2c52 |
1692 | #define mmSPI_SHADER_USER_DATA_VS_7 0x2c53 |
1693 | #define mmSPI_SHADER_USER_DATA_VS_8 0x2c54 |
1694 | #define mmSPI_SHADER_USER_DATA_VS_9 0x2c55 |
1695 | #define mmSPI_SHADER_USER_DATA_VS_10 0x2c56 |
1696 | #define mmSPI_SHADER_USER_DATA_VS_11 0x2c57 |
1697 | #define mmSPI_SHADER_USER_DATA_VS_12 0x2c58 |
1698 | #define mmSPI_SHADER_USER_DATA_VS_13 0x2c59 |
1699 | #define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a |
1700 | #define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b |
1701 | #define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c |
1702 | #define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d |
1703 | #define mmSPI_SHADER_TBA_LO_GS 0x2c80 |
1704 | #define mmSPI_SHADER_TBA_HI_GS 0x2c81 |
1705 | #define mmSPI_SHADER_TMA_LO_GS 0x2c82 |
1706 | #define mmSPI_SHADER_TMA_HI_GS 0x2c83 |
1707 | #define mmSPI_SHADER_PGM_LO_GS 0x2c88 |
1708 | #define mmSPI_SHADER_PGM_HI_GS 0x2c89 |
1709 | #define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a |
1710 | #define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b |
1711 | #define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87 |
1712 | #define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c |
1713 | #define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d |
1714 | #define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e |
1715 | #define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f |
1716 | #define mmSPI_SHADER_USER_DATA_GS_4 0x2c90 |
1717 | #define mmSPI_SHADER_USER_DATA_GS_5 0x2c91 |
1718 | #define mmSPI_SHADER_USER_DATA_GS_6 0x2c92 |
1719 | #define mmSPI_SHADER_USER_DATA_GS_7 0x2c93 |
1720 | #define mmSPI_SHADER_USER_DATA_GS_8 0x2c94 |
1721 | #define mmSPI_SHADER_USER_DATA_GS_9 0x2c95 |
1722 | #define mmSPI_SHADER_USER_DATA_GS_10 0x2c96 |
1723 | #define mmSPI_SHADER_USER_DATA_GS_11 0x2c97 |
1724 | #define mmSPI_SHADER_USER_DATA_GS_12 0x2c98 |
1725 | #define mmSPI_SHADER_USER_DATA_GS_13 0x2c99 |
1726 | #define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a |
1727 | #define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b |
1728 | #define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc |
1729 | #define mmSPI_SHADER_TBA_LO_ES 0x2cc0 |
1730 | #define mmSPI_SHADER_TBA_HI_ES 0x2cc1 |
1731 | #define mmSPI_SHADER_TMA_LO_ES 0x2cc2 |
1732 | #define mmSPI_SHADER_TMA_HI_ES 0x2cc3 |
1733 | #define mmSPI_SHADER_PGM_LO_ES 0x2cc8 |
1734 | #define mmSPI_SHADER_PGM_HI_ES 0x2cc9 |
1735 | #define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca |
1736 | #define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb |
1737 | #define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7 |
1738 | #define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc |
1739 | #define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd |
1740 | #define mmSPI_SHADER_USER_DATA_ES_2 0x2cce |
1741 | #define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf |
1742 | #define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0 |
1743 | #define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1 |
1744 | #define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2 |
1745 | #define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3 |
1746 | #define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4 |
1747 | #define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5 |
1748 | #define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6 |
1749 | #define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7 |
1750 | #define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8 |
1751 | #define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9 |
1752 | #define mmSPI_SHADER_USER_DATA_ES_14 0x2cda |
1753 | #define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb |
1754 | #define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd |
1755 | #define mmSPI_SHADER_TBA_LO_HS 0x2d00 |
1756 | #define mmSPI_SHADER_TBA_HI_HS 0x2d01 |
1757 | #define mmSPI_SHADER_TMA_LO_HS 0x2d02 |
1758 | #define mmSPI_SHADER_TMA_HI_HS 0x2d03 |
1759 | #define mmSPI_SHADER_PGM_LO_HS 0x2d08 |
1760 | #define mmSPI_SHADER_PGM_HI_HS 0x2d09 |
1761 | #define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a |
1762 | #define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b |
1763 | #define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07 |
1764 | #define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c |
1765 | #define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d |
1766 | #define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e |
1767 | #define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f |
1768 | #define mmSPI_SHADER_USER_DATA_HS_4 0x2d10 |
1769 | #define mmSPI_SHADER_USER_DATA_HS_5 0x2d11 |
1770 | #define mmSPI_SHADER_USER_DATA_HS_6 0x2d12 |
1771 | #define mmSPI_SHADER_USER_DATA_HS_7 0x2d13 |
1772 | #define mmSPI_SHADER_USER_DATA_HS_8 0x2d14 |
1773 | #define mmSPI_SHADER_USER_DATA_HS_9 0x2d15 |
1774 | #define mmSPI_SHADER_USER_DATA_HS_10 0x2d16 |
1775 | #define mmSPI_SHADER_USER_DATA_HS_11 0x2d17 |
1776 | #define mmSPI_SHADER_USER_DATA_HS_12 0x2d18 |
1777 | #define mmSPI_SHADER_USER_DATA_HS_13 0x2d19 |
1778 | #define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a |
1779 | #define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b |
1780 | #define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d |
1781 | #define mmSPI_SHADER_TBA_LO_LS 0x2d40 |
1782 | #define mmSPI_SHADER_TBA_HI_LS 0x2d41 |
1783 | #define mmSPI_SHADER_TMA_LO_LS 0x2d42 |
1784 | #define mmSPI_SHADER_TMA_HI_LS 0x2d43 |
1785 | #define mmSPI_SHADER_PGM_LO_LS 0x2d48 |
1786 | #define mmSPI_SHADER_PGM_HI_LS 0x2d49 |
1787 | #define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a |
1788 | #define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b |
1789 | #define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47 |
1790 | #define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c |
1791 | #define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d |
1792 | #define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e |
1793 | #define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f |
1794 | #define mmSPI_SHADER_USER_DATA_LS_4 0x2d50 |
1795 | #define mmSPI_SHADER_USER_DATA_LS_5 0x2d51 |
1796 | #define mmSPI_SHADER_USER_DATA_LS_6 0x2d52 |
1797 | #define mmSPI_SHADER_USER_DATA_LS_7 0x2d53 |
1798 | #define mmSPI_SHADER_USER_DATA_LS_8 0x2d54 |
1799 | #define mmSPI_SHADER_USER_DATA_LS_9 0x2d55 |
1800 | #define mmSPI_SHADER_USER_DATA_LS_10 0x2d56 |
1801 | #define mmSPI_SHADER_USER_DATA_LS_11 0x2d57 |
1802 | #define mmSPI_SHADER_USER_DATA_LS_12 0x2d58 |
1803 | #define mmSPI_SHADER_USER_DATA_LS_13 0x2d59 |
1804 | #define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a |
1805 | #define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b |
1806 | #define mmSQ_CONFIG 0x2300 |
1807 | #define mmSQC_CONFIG 0x2301 |
1808 | #define mmSQC_CACHES 0xc348 |
1809 | #define mmSQ_RANDOM_WAVE_PRI 0x2303 |
1810 | #define mmSQ_REG_CREDITS 0x2304 |
1811 | #define mmSQ_FIFO_SIZES 0x2305 |
1812 | #define mmSQ_INTERRUPT_AUTO_MASK 0x2314 |
1813 | #define mmSQ_INTERRUPT_MSG_CTRL 0x2315 |
1814 | #define mmSQ_PERFCOUNTER_CTRL 0xd9e0 |
1815 | #define mmSQ_PERFCOUNTER_MASK 0xd9e1 |
1816 | #define mmSQ_PERFCOUNTER_CTRL2 0xd9e2 |
1817 | #define mmCC_SQC_BANK_DISABLE 0x2307 |
1818 | #define mmUSER_SQC_BANK_DISABLE 0x2308 |
1819 | #define mmSQ_PERFCOUNTER0_LO 0xd1c0 |
1820 | #define mmSQ_PERFCOUNTER1_LO 0xd1c2 |
1821 | #define mmSQ_PERFCOUNTER2_LO 0xd1c4 |
1822 | #define mmSQ_PERFCOUNTER3_LO 0xd1c6 |
1823 | #define mmSQ_PERFCOUNTER4_LO 0xd1c8 |
1824 | #define mmSQ_PERFCOUNTER5_LO 0xd1ca |
1825 | #define mmSQ_PERFCOUNTER6_LO 0xd1cc |
1826 | #define mmSQ_PERFCOUNTER7_LO 0xd1ce |
1827 | #define mmSQ_PERFCOUNTER8_LO 0xd1d0 |
1828 | #define mmSQ_PERFCOUNTER9_LO 0xd1d2 |
1829 | #define mmSQ_PERFCOUNTER10_LO 0xd1d4 |
1830 | #define mmSQ_PERFCOUNTER11_LO 0xd1d6 |
1831 | #define mmSQ_PERFCOUNTER12_LO 0xd1d8 |
1832 | #define mmSQ_PERFCOUNTER13_LO 0xd1da |
1833 | #define mmSQ_PERFCOUNTER14_LO 0xd1dc |
1834 | #define mmSQ_PERFCOUNTER15_LO 0xd1de |
1835 | #define mmSQ_PERFCOUNTER0_HI 0xd1c1 |
1836 | #define mmSQ_PERFCOUNTER1_HI 0xd1c3 |
1837 | #define mmSQ_PERFCOUNTER2_HI 0xd1c5 |
1838 | #define mmSQ_PERFCOUNTER3_HI 0xd1c7 |
1839 | #define mmSQ_PERFCOUNTER4_HI 0xd1c9 |
1840 | #define mmSQ_PERFCOUNTER5_HI 0xd1cb |
1841 | #define mmSQ_PERFCOUNTER6_HI 0xd1cd |
1842 | #define mmSQ_PERFCOUNTER7_HI 0xd1cf |
1843 | #define mmSQ_PERFCOUNTER8_HI 0xd1d1 |
1844 | #define mmSQ_PERFCOUNTER9_HI 0xd1d3 |
1845 | #define mmSQ_PERFCOUNTER10_HI 0xd1d5 |
1846 | #define mmSQ_PERFCOUNTER11_HI 0xd1d7 |
1847 | #define mmSQ_PERFCOUNTER12_HI 0xd1d9 |
1848 | #define mmSQ_PERFCOUNTER13_HI 0xd1db |
1849 | #define mmSQ_PERFCOUNTER14_HI 0xd1dd |
1850 | #define mmSQ_PERFCOUNTER15_HI 0xd1df |
1851 | #define mmSQ_PERFCOUNTER0_SELECT 0xd9c0 |
1852 | #define mmSQ_PERFCOUNTER1_SELECT 0xd9c1 |
1853 | #define mmSQ_PERFCOUNTER2_SELECT 0xd9c2 |
1854 | #define mmSQ_PERFCOUNTER3_SELECT 0xd9c3 |
1855 | #define mmSQ_PERFCOUNTER4_SELECT 0xd9c4 |
1856 | #define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 |
1857 | #define mmSQ_PERFCOUNTER6_SELECT 0xd9c6 |
1858 | #define mmSQ_PERFCOUNTER7_SELECT 0xd9c7 |
1859 | #define mmSQ_PERFCOUNTER8_SELECT 0xd9c8 |
1860 | #define mmSQ_PERFCOUNTER9_SELECT 0xd9c9 |
1861 | #define mmSQ_PERFCOUNTER10_SELECT 0xd9ca |
1862 | #define mmSQ_PERFCOUNTER11_SELECT 0xd9cb |
1863 | #define mmSQ_PERFCOUNTER12_SELECT 0xd9cc |
1864 | #define mmSQ_PERFCOUNTER13_SELECT 0xd9cd |
1865 | #define mmSQ_PERFCOUNTER14_SELECT 0xd9ce |
1866 | #define mmSQ_PERFCOUNTER15_SELECT 0xd9cf |
1867 | #define mmCGTT_SQ_CLK_CTRL 0xf08c |
1868 | #define mmCGTT_SQG_CLK_CTRL 0xf08d |
1869 | #define mmSQ_ALU_CLK_CTRL 0xf08e |
1870 | #define mmSQ_TEX_CLK_CTRL 0xf08f |
1871 | #define mmSQ_LDS_CLK_CTRL 0xf090 |
1872 | #define mmSQ_POWER_THROTTLE 0xf091 |
1873 | #define mmSQ_POWER_THROTTLE2 0xf092 |
1874 | #define mmSQ_TIME_HI 0x237c |
1875 | #define mmSQ_TIME_LO 0x237d |
1876 | #define mmSQ_THREAD_TRACE_BASE 0x2380 |
1877 | #define mmSQ_THREAD_TRACE_BASE2 0x2385 |
1878 | #define mmSQ_THREAD_TRACE_SIZE 0x2381 |
1879 | #define mmSQ_THREAD_TRACE_MASK 0x2382 |
1880 | #define mmSQ_THREAD_TRACE_USERDATA_0 0xc340 |
1881 | #define mmSQ_THREAD_TRACE_USERDATA_1 0xc341 |
1882 | #define mmSQ_THREAD_TRACE_USERDATA_2 0xc342 |
1883 | #define mmSQ_THREAD_TRACE_USERDATA_3 0xc343 |
1884 | #define mmSQ_THREAD_TRACE_MODE 0x238e |
1885 | #define mmSQ_THREAD_TRACE_CTRL 0x238f |
1886 | #define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383 |
1887 | #define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2386 |
1888 | #define mmSQ_THREAD_TRACE_PERF_MASK 0x2384 |
1889 | #define mmSQ_THREAD_TRACE_WPTR 0x238c |
1890 | #define mmSQ_THREAD_TRACE_STATUS 0x238d |
1891 | #define mmSQ_THREAD_TRACE_CNTR 0x2390 |
1892 | #define mmSQ_THREAD_TRACE_HIWATER 0x2392 |
1893 | #define mmSQ_LB_CTR_CTRL 0x2398 |
1894 | #define mmSQ_LB_DATA_ALU_CYCLES 0x2399 |
1895 | #define mmSQ_LB_DATA_TEX_CYCLES 0x239a |
1896 | #define mmSQ_LB_DATA_ALU_STALLS 0x239b |
1897 | #define mmSQ_LB_DATA_TEX_STALLS 0x239c |
1898 | #define mmSQC_SECDED_CNT 0x23a0 |
1899 | #define mmSQ_SEC_CNT 0x23a1 |
1900 | #define mmSQ_DED_CNT 0x23a2 |
1901 | #define mmSQ_DED_INFO 0x23a3 |
1902 | #define mmSQ_BUF_RSRC_WORD0 0x23c0 |
1903 | #define mmSQ_BUF_RSRC_WORD1 0x23c1 |
1904 | #define mmSQ_BUF_RSRC_WORD2 0x23c2 |
1905 | #define mmSQ_BUF_RSRC_WORD3 0x23c3 |
1906 | #define mmSQ_IMG_RSRC_WORD0 0x23c4 |
1907 | #define mmSQ_IMG_RSRC_WORD1 0x23c5 |
1908 | #define mmSQ_IMG_RSRC_WORD2 0x23c6 |
1909 | #define mmSQ_IMG_RSRC_WORD3 0x23c7 |
1910 | #define mmSQ_IMG_RSRC_WORD4 0x23c8 |
1911 | #define mmSQ_IMG_RSRC_WORD5 0x23c9 |
1912 | #define mmSQ_IMG_RSRC_WORD6 0x23ca |
1913 | #define mmSQ_IMG_RSRC_WORD7 0x23cb |
1914 | #define mmSQ_IMG_SAMP_WORD0 0x23cc |
1915 | #define mmSQ_IMG_SAMP_WORD1 0x23cd |
1916 | #define mmSQ_IMG_SAMP_WORD2 0x23ce |
1917 | #define mmSQ_IMG_SAMP_WORD3 0x23cf |
1918 | #define mmSQ_FLAT_SCRATCH_WORD0 0x23d0 |
1919 | #define mmSQ_FLAT_SCRATCH_WORD1 0x23d1 |
1920 | #define mmSQ_IND_INDEX 0x2378 |
1921 | #define mmSQ_IND_CMD 0x237a |
1922 | #define mmSQ_CMD 0x237b |
1923 | #define mmSQ_IND_DATA 0x2379 |
1924 | #define mmSQ_REG_TIMESTAMP 0x2374 |
1925 | #define mmSQ_CMD_TIMESTAMP 0x2375 |
1926 | #define mmSQ_HV_VMID_CTRL 0xf840 |
1927 | #define ixSQ_WAVE_INST_DW0 0x1a |
1928 | #define ixSQ_WAVE_INST_DW1 0x1b |
1929 | #define ixSQ_WAVE_PC_LO 0x18 |
1930 | #define ixSQ_WAVE_PC_HI 0x19 |
1931 | #define ixSQ_WAVE_IB_DBG0 0x1c |
1932 | #define ixSQ_WAVE_EXEC_LO 0x27e |
1933 | #define ixSQ_WAVE_EXEC_HI 0x27f |
1934 | #define ixSQ_WAVE_STATUS 0x12 |
1935 | #define ixSQ_WAVE_MODE 0x11 |
1936 | #define ixSQ_WAVE_TRAPSTS 0x13 |
1937 | #define ixSQ_WAVE_HW_ID 0x14 |
1938 | #define ixSQ_WAVE_GPR_ALLOC 0x15 |
1939 | #define ixSQ_WAVE_LDS_ALLOC 0x16 |
1940 | #define ixSQ_WAVE_IB_STS 0x17 |
1941 | #define ixSQ_WAVE_M0 0x27c |
1942 | #define ixSQ_WAVE_TBA_LO 0x26c |
1943 | #define ixSQ_WAVE_TBA_HI 0x26d |
1944 | #define ixSQ_WAVE_TMA_LO 0x26e |
1945 | #define ixSQ_WAVE_TMA_HI 0x26f |
1946 | #define ixSQ_WAVE_TTMP0 0x270 |
1947 | #define ixSQ_WAVE_TTMP1 0x271 |
1948 | #define ixSQ_WAVE_TTMP2 0x272 |
1949 | #define ixSQ_WAVE_TTMP3 0x273 |
1950 | #define ixSQ_WAVE_TTMP4 0x274 |
1951 | #define ixSQ_WAVE_TTMP5 0x275 |
1952 | #define ixSQ_WAVE_TTMP6 0x276 |
1953 | #define ixSQ_WAVE_TTMP7 0x277 |
1954 | #define ixSQ_WAVE_TTMP8 0x278 |
1955 | #define ixSQ_WAVE_TTMP9 0x279 |
1956 | #define ixSQ_WAVE_TTMP10 0x27a |
1957 | #define ixSQ_WAVE_TTMP11 0x27b |
1958 | #define mmSQ_DEBUG_STS_GLOBAL 0x2309 |
1959 | #define mmSQ_DEBUG_STS_GLOBAL2 0x2310 |
1960 | #define mmSQ_DEBUG_STS_GLOBAL3 0x2311 |
1961 | #define ixSQ_DEBUG_STS_LOCAL 0x8 |
1962 | #define ixSQ_DEBUG_CTRL_LOCAL 0x9 |
1963 | #define mmSH_MEM_BASES 0x230a |
1964 | #define mmSH_MEM_APE1_BASE 0x230b |
1965 | #define mmSH_MEM_APE1_LIMIT 0x230c |
1966 | #define mmSH_MEM_CONFIG 0x230d |
1967 | #define mmSQC_POLICY 0x230e |
1968 | #define mmSQC_VOLATILE 0x230f |
1969 | #define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0 |
1970 | #define mmSQ_THREAD_TRACE_WORD_INST 0x23b0 |
1971 | #define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0 |
1972 | #define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1 |
1973 | #define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0 |
1974 | #define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1 |
1975 | #define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0 |
1976 | #define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1 |
1977 | #define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0 |
1978 | #define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0 |
1979 | #define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0 |
1980 | #define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0 |
1981 | #define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0 |
1982 | #define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0 |
1983 | #define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0 |
1984 | #define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0 |
1985 | #define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0 |
1986 | #define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0 |
1987 | #define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1 |
1988 | #define ixSQ_INTERRUPT_WORD_CMN 0x20c0 |
1989 | #define ixSQ_INTERRUPT_WORD_AUTO 0x20c0 |
1990 | #define ixSQ_INTERRUPT_WORD_WAVE 0x20c0 |
1991 | #define mmSQ_SOP2 0x237f |
1992 | #define mmSQ_VOP1 0x237f |
1993 | #define mmSQ_MTBUF_1 0x237f |
1994 | #define mmSQ_EXP_1 0x237f |
1995 | #define mmSQ_MUBUF_1 0x237f |
1996 | #define mmSQ_INST 0x237f |
1997 | #define mmSQ_EXP_0 0x237f |
1998 | #define mmSQ_MUBUF_0 0x237f |
1999 | #define mmSQ_VOP3_0 0x237f |
2000 | #define mmSQ_VOP2 0x237f |
2001 | #define mmSQ_MTBUF_0 0x237f |
2002 | #define mmSQ_SOPP 0x237f |
2003 | #define mmSQ_FLAT_0 0x237f |
2004 | #define mmSQ_VOP3_0_SDST_ENC 0x237f |
2005 | #define mmSQ_MIMG_1 0x237f |
2006 | #define mmSQ_SMRD 0x237f |
2007 | #define mmSQ_SOP1 0x237f |
2008 | #define mmSQ_SOPC 0x237f |
2009 | #define mmSQ_FLAT_1 0x237f |
2010 | #define mmSQ_DS_1 0x237f |
2011 | #define mmSQ_VOP3_1 0x237f |
2012 | #define mmSQ_MIMG_0 0x237f |
2013 | #define mmSQ_SOPK 0x237f |
2014 | #define mmSQ_DS_0 0x237f |
2015 | #define mmSQ_VOPC 0x237f |
2016 | #define mmSQ_VINTRP 0x237f |
2017 | #define mmCGTT_SX_CLK_CTRL0 0xf094 |
2018 | #define mmCGTT_SX_CLK_CTRL1 0xf095 |
2019 | #define mmCGTT_SX_CLK_CTRL2 0xf096 |
2020 | #define mmCGTT_SX_CLK_CTRL3 0xf097 |
2021 | #define mmCGTT_SX_CLK_CTRL4 0xf098 |
2022 | #define mmSX_DEBUG_BUSY 0x2414 |
2023 | #define mmSX_DEBUG_BUSY_2 0x2415 |
2024 | #define mmSX_DEBUG_BUSY_3 0x2416 |
2025 | #define mmSX_DEBUG_BUSY_4 0x2417 |
2026 | #define mmSX_DEBUG_1 0x2418 |
2027 | #define mmSX_PERFCOUNTER0_SELECT 0xda40 |
2028 | #define mmSX_PERFCOUNTER1_SELECT 0xda41 |
2029 | #define mmSX_PERFCOUNTER2_SELECT 0xda42 |
2030 | #define mmSX_PERFCOUNTER3_SELECT 0xda43 |
2031 | #define mmSX_PERFCOUNTER0_SELECT1 0xda44 |
2032 | #define mmSX_PERFCOUNTER1_SELECT1 0xda45 |
2033 | #define mmSX_PERFCOUNTER0_LO 0xd240 |
2034 | #define mmSX_PERFCOUNTER0_HI 0xd241 |
2035 | #define mmSX_PERFCOUNTER1_LO 0xd242 |
2036 | #define mmSX_PERFCOUNTER1_HI 0xd243 |
2037 | #define mmSX_PERFCOUNTER2_LO 0xd244 |
2038 | #define mmSX_PERFCOUNTER2_HI 0xd245 |
2039 | #define mmSX_PERFCOUNTER3_LO 0xd246 |
2040 | #define mmSX_PERFCOUNTER3_HI 0xd247 |
2041 | #define mmTCC_CTRL 0x2b80 |
2042 | #define mmTCC_EDC_COUNTER 0x2b82 |
2043 | #define mmTCC_REDUNDANCY 0x2b83 |
2044 | #define mmTCC_CGTT_SCLK_CTRL 0xf0ac |
2045 | #define mmTCA_CGTT_SCLK_CTRL 0xf0ad |
2046 | #define mmTCS_CGTT_SCLK_CTRL 0xf0ae |
2047 | #define mmTCC_PERFCOUNTER0_SELECT 0xdb80 |
2048 | #define mmTCC_PERFCOUNTER1_SELECT 0xdb82 |
2049 | #define mmTCC_PERFCOUNTER0_SELECT1 0xdb81 |
2050 | #define mmTCC_PERFCOUNTER1_SELECT1 0xdb83 |
2051 | #define mmTCC_PERFCOUNTER2_SELECT 0xdb84 |
2052 | #define mmTCC_PERFCOUNTER3_SELECT 0xdb85 |
2053 | #define mmTCC_PERFCOUNTER0_LO 0xd380 |
2054 | #define mmTCC_PERFCOUNTER1_LO 0xd382 |
2055 | #define mmTCC_PERFCOUNTER2_LO 0xd384 |
2056 | #define mmTCC_PERFCOUNTER3_LO 0xd386 |
2057 | #define mmTCC_PERFCOUNTER0_HI 0xd381 |
2058 | #define mmTCC_PERFCOUNTER1_HI 0xd383 |
2059 | #define mmTCC_PERFCOUNTER2_HI 0xd385 |
2060 | #define mmTCC_PERFCOUNTER3_HI 0xd387 |
2061 | #define mmTCA_CTRL 0x2bc0 |
2062 | #define mmTCA_PERFCOUNTER0_SELECT 0xdb90 |
2063 | #define mmTCA_PERFCOUNTER1_SELECT 0xdb92 |
2064 | #define mmTCA_PERFCOUNTER0_SELECT1 0xdb91 |
2065 | #define mmTCA_PERFCOUNTER1_SELECT1 0xdb93 |
2066 | #define mmTCA_PERFCOUNTER2_SELECT 0xdb94 |
2067 | #define mmTCA_PERFCOUNTER3_SELECT 0xdb95 |
2068 | #define mmTCA_PERFCOUNTER0_LO 0xd390 |
2069 | #define mmTCA_PERFCOUNTER1_LO 0xd392 |
2070 | #define mmTCA_PERFCOUNTER2_LO 0xd394 |
2071 | #define mmTCA_PERFCOUNTER3_LO 0xd396 |
2072 | #define mmTCA_PERFCOUNTER0_HI 0xd391 |
2073 | #define mmTCA_PERFCOUNTER1_HI 0xd393 |
2074 | #define mmTCA_PERFCOUNTER2_HI 0xd395 |
2075 | #define mmTCA_PERFCOUNTER3_HI 0xd397 |
2076 | #define mmTCS_CTRL 0x2be0 |
2077 | #define mmTCS_PERFCOUNTER0_SELECT 0xdba0 |
2078 | #define mmTCS_PERFCOUNTER0_SELECT1 0xdba1 |
2079 | #define mmTCS_PERFCOUNTER1_SELECT 0xdba2 |
2080 | #define mmTCS_PERFCOUNTER2_SELECT 0xdba3 |
2081 | #define mmTCS_PERFCOUNTER3_SELECT 0xdba4 |
2082 | #define mmTCS_PERFCOUNTER0_LO 0xd3a0 |
2083 | #define mmTCS_PERFCOUNTER1_LO 0xd3a2 |
2084 | #define mmTCS_PERFCOUNTER2_LO 0xd3a4 |
2085 | #define mmTCS_PERFCOUNTER3_LO 0xd3a6 |
2086 | #define mmTCS_PERFCOUNTER0_HI 0xd3a1 |
2087 | #define mmTCS_PERFCOUNTER1_HI 0xd3a3 |
2088 | #define mmTCS_PERFCOUNTER2_HI 0xd3a5 |
2089 | #define mmTCS_PERFCOUNTER3_HI 0xd3a7 |
2090 | #define mmTA_BC_BASE_ADDR 0xa020 |
2091 | #define mmTA_BC_BASE_ADDR_HI 0xa021 |
2092 | #define mmTD_CNTL 0x2525 |
2093 | #define mmTD_STATUS 0x2526 |
2094 | #define mmTD_DEBUG_INDEX 0x2528 |
2095 | #define mmTD_DEBUG_DATA 0x2529 |
2096 | #define mmTD_PERFCOUNTER0_SELECT 0xdb00 |
2097 | #define mmTD_PERFCOUNTER1_SELECT 0xdb02 |
2098 | #define mmTD_PERFCOUNTER0_SELECT1 0xdb01 |
2099 | #define mmTD_PERFCOUNTER0_LO 0xd300 |
2100 | #define mmTD_PERFCOUNTER1_LO 0xd302 |
2101 | #define mmTD_PERFCOUNTER0_HI 0xd301 |
2102 | #define mmTD_PERFCOUNTER1_HI 0xd303 |
2103 | #define mmTD_SCRATCH 0x2533 |
2104 | #define mmTA_CNTL 0x2541 |
2105 | #define mmTA_CNTL_AUX 0x2542 |
2106 | #define mmTA_RESERVED_010C 0x2543 |
2107 | #define mmTA_CS_BC_BASE_ADDR 0xc380 |
2108 | #define mmTA_CS_BC_BASE_ADDR_HI 0xc381 |
2109 | #define mmTA_STATUS 0x2548 |
2110 | #define mmTA_DEBUG_INDEX 0x254c |
2111 | #define mmTA_DEBUG_DATA 0x254d |
2112 | #define mmTA_PERFCOUNTER0_SELECT 0xdac0 |
2113 | #define mmTA_PERFCOUNTER1_SELECT 0xdac2 |
2114 | #define mmTA_PERFCOUNTER0_SELECT1 0xdac1 |
2115 | #define mmTA_PERFCOUNTER0_LO 0xd2c0 |
2116 | #define mmTA_PERFCOUNTER1_LO 0xd2c2 |
2117 | #define mmTA_PERFCOUNTER0_HI 0xd2c1 |
2118 | #define mmTA_PERFCOUNTER1_HI 0xd2c3 |
2119 | #define mmTA_SCRATCH 0x2564 |
2120 | #define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580 |
2121 | #define mmSH_STATIC_MEM_CONFIG 0x2581 |
2122 | #define mmTCP_INVALIDATE 0x2b00 |
2123 | #define mmTCP_STATUS 0x2b01 |
2124 | #define mmTCP_CNTL 0x2b02 |
2125 | #define mmTCP_CHAN_STEER_LO 0x2b03 |
2126 | #define mmTCP_CHAN_STEER_HI 0x2b04 |
2127 | #define mmTCP_ADDR_CONFIG 0x2b05 |
2128 | #define mmTCP_CREDIT 0x2b06 |
2129 | #define mmTCP_PERFCOUNTER0_SELECT 0xdb40 |
2130 | #define mmTCP_PERFCOUNTER1_SELECT 0xdb42 |
2131 | #define mmTCP_PERFCOUNTER0_SELECT1 0xdb41 |
2132 | #define mmTCP_PERFCOUNTER1_SELECT1 0xdb43 |
2133 | #define mmTCP_PERFCOUNTER2_SELECT 0xdb44 |
2134 | #define mmTCP_PERFCOUNTER3_SELECT 0xdb45 |
2135 | #define mmTCP_PERFCOUNTER0_LO 0xd340 |
2136 | #define mmTCP_PERFCOUNTER1_LO 0xd342 |
2137 | #define mmTCP_PERFCOUNTER2_LO 0xd344 |
2138 | #define mmTCP_PERFCOUNTER3_LO 0xd346 |
2139 | #define mmTCP_PERFCOUNTER0_HI 0xd341 |
2140 | #define mmTCP_PERFCOUNTER1_HI 0xd343 |
2141 | #define mmTCP_PERFCOUNTER2_HI 0xd345 |
2142 | #define mmTCP_PERFCOUNTER3_HI 0xd347 |
2143 | #define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16 |
2144 | #define mmTCP_EDC_COUNTER 0x2b17 |
2145 | #define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a |
2146 | #define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b |
2147 | #define mmTC_CFG_L1_STORE_POLICY 0x2b1c |
2148 | #define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d |
2149 | #define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e |
2150 | #define mmTC_CFG_L2_STORE_POLICY0 0x2b1f |
2151 | #define mmTC_CFG_L2_STORE_POLICY1 0x2b20 |
2152 | #define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21 |
2153 | #define mmTC_CFG_L1_VOLATILE 0x2b22 |
2154 | #define mmTC_CFG_L2_VOLATILE 0x2b23 |
2155 | #define mmTCP_WATCH0_ADDR_H 0x32a0 |
2156 | #define mmTCP_WATCH1_ADDR_H 0x32a3 |
2157 | #define mmTCP_WATCH2_ADDR_H 0x32a6 |
2158 | #define mmTCP_WATCH3_ADDR_H 0x32a9 |
2159 | #define mmTCP_WATCH0_ADDR_L 0x32a1 |
2160 | #define mmTCP_WATCH1_ADDR_L 0x32a4 |
2161 | #define mmTCP_WATCH2_ADDR_L 0x32a7 |
2162 | #define mmTCP_WATCH3_ADDR_L 0x32aa |
2163 | #define mmTCP_WATCH0_CNTL 0x32a2 |
2164 | #define mmTCP_WATCH1_CNTL 0x32a5 |
2165 | #define mmTCP_WATCH2_CNTL 0x32a8 |
2166 | #define mmTCP_WATCH3_CNTL 0x32ab |
2167 | #define mmTD_CGTT_CTRL 0xf09c |
2168 | #define mmTA_CGTT_CTRL 0xf09d |
2169 | #define mmCGTT_TCP_CLK_CTRL 0xf09e |
2170 | #define mmCGTT_TCI_CLK_CTRL 0xf09f |
2171 | #define mmTCI_STATUS 0x2b61 |
2172 | #define mmTCI_CNTL_1 0x2b62 |
2173 | #define mmTCI_CNTL_2 0x2b63 |
2174 | #define mmGDS_CONFIG 0x25c0 |
2175 | #define mmGDS_CNTL_STATUS 0x25c1 |
2176 | #define mmGDS_ENHANCE2 0x25c2 |
2177 | #define mmGDS_PROTECTION_FAULT 0x25c3 |
2178 | #define mmGDS_VM_PROTECTION_FAULT 0x25c4 |
2179 | #define mmGDS_SECDED_CNT 0x25c5 |
2180 | #define mmGDS_GRBM_SECDED_CNT 0x25c6 |
2181 | #define mmGDS_OA_DED 0x25c7 |
2182 | #define mmGDS_DEBUG_CNTL 0x25c8 |
2183 | #define mmGDS_DEBUG_DATA 0x25c9 |
2184 | #define mmCGTT_GDS_CLK_CTRL 0xf0a0 |
2185 | #define mmGDS_RD_ADDR 0xc400 |
2186 | #define mmGDS_RD_DATA 0xc401 |
2187 | #define mmGDS_RD_BURST_ADDR 0xc402 |
2188 | #define mmGDS_RD_BURST_COUNT 0xc403 |
2189 | #define mmGDS_RD_BURST_DATA 0xc404 |
2190 | #define mmGDS_WR_ADDR 0xc405 |
2191 | #define mmGDS_WR_DATA 0xc406 |
2192 | #define mmGDS_WR_BURST_ADDR 0xc407 |
2193 | #define mmGDS_WR_BURST_DATA 0xc408 |
2194 | #define mmGDS_WRITE_COMPLETE 0xc409 |
2195 | #define mmGDS_ATOM_CNTL 0xc40a |
2196 | #define mmGDS_ATOM_COMPLETE 0xc40b |
2197 | #define mmGDS_ATOM_BASE 0xc40c |
2198 | #define mmGDS_ATOM_SIZE 0xc40d |
2199 | #define mmGDS_ATOM_OFFSET0 0xc40e |
2200 | #define mmGDS_ATOM_OFFSET1 0xc40f |
2201 | #define mmGDS_ATOM_DST 0xc410 |
2202 | #define mmGDS_ATOM_OP 0xc411 |
2203 | #define mmGDS_ATOM_SRC0 0xc412 |
2204 | #define mmGDS_ATOM_SRC0_U 0xc413 |
2205 | #define mmGDS_ATOM_SRC1 0xc414 |
2206 | #define mmGDS_ATOM_SRC1_U 0xc415 |
2207 | #define mmGDS_ATOM_READ0 0xc416 |
2208 | #define mmGDS_ATOM_READ0_U 0xc417 |
2209 | #define mmGDS_ATOM_READ1 0xc418 |
2210 | #define mmGDS_ATOM_READ1_U 0xc419 |
2211 | #define mmGDS_GWS_RESOURCE_CNTL 0xc41a |
2212 | #define mmGDS_GWS_RESOURCE 0xc41b |
2213 | #define mmGDS_GWS_RESOURCE_CNT 0xc41c |
2214 | #define mmGDS_OA_CNTL 0xc41d |
2215 | #define mmGDS_OA_COUNTER 0xc41e |
2216 | #define mmGDS_OA_ADDRESS 0xc41f |
2217 | #define mmGDS_OA_INCDEC 0xc420 |
2218 | #define mmGDS_OA_RING_SIZE 0xc421 |
2219 | #define ixGDS_DEBUG_REG0 0x0 |
2220 | #define ixGDS_DEBUG_REG1 0x1 |
2221 | #define ixGDS_DEBUG_REG2 0x2 |
2222 | #define ixGDS_DEBUG_REG3 0x3 |
2223 | #define ixGDS_DEBUG_REG4 0x4 |
2224 | #define ixGDS_DEBUG_REG5 0x5 |
2225 | #define ixGDS_DEBUG_REG6 0x6 |
2226 | #define mmGDS_PERFCOUNTER0_SELECT 0xda80 |
2227 | #define mmGDS_PERFCOUNTER1_SELECT 0xda81 |
2228 | #define mmGDS_PERFCOUNTER2_SELECT 0xda82 |
2229 | #define mmGDS_PERFCOUNTER3_SELECT 0xda83 |
2230 | #define mmGDS_PERFCOUNTER0_LO 0xd280 |
2231 | #define mmGDS_PERFCOUNTER1_LO 0xd282 |
2232 | #define mmGDS_PERFCOUNTER2_LO 0xd284 |
2233 | #define mmGDS_PERFCOUNTER3_LO 0xd286 |
2234 | #define mmGDS_PERFCOUNTER0_HI 0xd281 |
2235 | #define mmGDS_PERFCOUNTER1_HI 0xd283 |
2236 | #define mmGDS_PERFCOUNTER2_HI 0xd285 |
2237 | #define mmGDS_PERFCOUNTER3_HI 0xd287 |
2238 | #define mmGDS_PERFCOUNTER0_SELECT1 0xda84 |
2239 | #define mmGDS_VMID0_BASE 0x3300 |
2240 | #define mmGDS_VMID1_BASE 0x3302 |
2241 | #define mmGDS_VMID2_BASE 0x3304 |
2242 | #define mmGDS_VMID3_BASE 0x3306 |
2243 | #define mmGDS_VMID4_BASE 0x3308 |
2244 | #define mmGDS_VMID5_BASE 0x330a |
2245 | #define mmGDS_VMID6_BASE 0x330c |
2246 | #define mmGDS_VMID7_BASE 0x330e |
2247 | #define mmGDS_VMID8_BASE 0x3310 |
2248 | #define mmGDS_VMID9_BASE 0x3312 |
2249 | #define mmGDS_VMID10_BASE 0x3314 |
2250 | #define mmGDS_VMID11_BASE 0x3316 |
2251 | #define mmGDS_VMID12_BASE 0x3318 |
2252 | #define mmGDS_VMID13_BASE 0x331a |
2253 | #define mmGDS_VMID14_BASE 0x331c |
2254 | #define mmGDS_VMID15_BASE 0x331e |
2255 | #define mmGDS_VMID0_SIZE 0x3301 |
2256 | #define mmGDS_VMID1_SIZE 0x3303 |
2257 | #define mmGDS_VMID2_SIZE 0x3305 |
2258 | #define mmGDS_VMID3_SIZE 0x3307 |
2259 | #define mmGDS_VMID4_SIZE 0x3309 |
2260 | #define mmGDS_VMID5_SIZE 0x330b |
2261 | #define mmGDS_VMID6_SIZE 0x330d |
2262 | #define mmGDS_VMID7_SIZE 0x330f |
2263 | #define mmGDS_VMID8_SIZE 0x3311 |
2264 | #define mmGDS_VMID9_SIZE 0x3313 |
2265 | #define mmGDS_VMID10_SIZE 0x3315 |
2266 | #define mmGDS_VMID11_SIZE 0x3317 |
2267 | #define mmGDS_VMID12_SIZE 0x3319 |
2268 | #define mmGDS_VMID13_SIZE 0x331b |
2269 | #define mmGDS_VMID14_SIZE 0x331d |
2270 | #define mmGDS_VMID15_SIZE 0x331f |
2271 | #define mmGDS_GWS_VMID0 0x3320 |
2272 | #define mmGDS_GWS_VMID1 0x3321 |
2273 | #define mmGDS_GWS_VMID2 0x3322 |
2274 | #define mmGDS_GWS_VMID3 0x3323 |
2275 | #define mmGDS_GWS_VMID4 0x3324 |
2276 | #define mmGDS_GWS_VMID5 0x3325 |
2277 | #define mmGDS_GWS_VMID6 0x3326 |
2278 | #define mmGDS_GWS_VMID7 0x3327 |
2279 | #define mmGDS_GWS_VMID8 0x3328 |
2280 | #define mmGDS_GWS_VMID9 0x3329 |
2281 | #define mmGDS_GWS_VMID10 0x332a |
2282 | #define mmGDS_GWS_VMID11 0x332b |
2283 | #define mmGDS_GWS_VMID12 0x332c |
2284 | #define mmGDS_GWS_VMID13 0x332d |
2285 | #define mmGDS_GWS_VMID14 0x332e |
2286 | #define mmGDS_GWS_VMID15 0x332f |
2287 | #define mmGDS_OA_VMID0 0x3330 |
2288 | #define mmGDS_OA_VMID1 0x3331 |
2289 | #define mmGDS_OA_VMID2 0x3332 |
2290 | #define mmGDS_OA_VMID3 0x3333 |
2291 | #define mmGDS_OA_VMID4 0x3334 |
2292 | #define mmGDS_OA_VMID5 0x3335 |
2293 | #define mmGDS_OA_VMID6 0x3336 |
2294 | #define mmGDS_OA_VMID7 0x3337 |
2295 | #define mmGDS_OA_VMID8 0x3338 |
2296 | #define mmGDS_OA_VMID9 0x3339 |
2297 | #define mmGDS_OA_VMID10 0x333a |
2298 | #define mmGDS_OA_VMID11 0x333b |
2299 | #define mmGDS_OA_VMID12 0x333c |
2300 | #define mmGDS_OA_VMID13 0x333d |
2301 | #define mmGDS_OA_VMID14 0x333e |
2302 | #define mmGDS_OA_VMID15 0x333f |
2303 | #define mmGDS_GWS_RESET0 0x3344 |
2304 | #define mmGDS_GWS_RESET1 0x3345 |
2305 | #define mmGDS_GWS_RESOURCE_RESET 0x3346 |
2306 | #define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348 |
2307 | #define mmGDS_OA_RESET_MASK 0x3349 |
2308 | #define mmGDS_OA_RESET 0x334a |
2309 | #define mmGDS_ENHANCE 0x334b |
2310 | #define mmGDS_OA_CGPG_RESTORE 0x334c |
2311 | #define mmCS_COPY_STATE 0xa1f3 |
2312 | #define mmGFX_COPY_STATE 0xa1f4 |
2313 | #define mmVGT_DRAW_INITIATOR 0xa1fc |
2314 | #define mmVGT_EVENT_INITIATOR 0xa2a4 |
2315 | #define mmVGT_EVENT_ADDRESS_REG 0xa1fe |
2316 | #define mmVGT_DMA_BASE_HI 0xa1f9 |
2317 | #define mmVGT_DMA_BASE 0xa1fa |
2318 | #define mmVGT_DMA_INDEX_TYPE 0xa29f |
2319 | #define mmVGT_DMA_NUM_INSTANCES 0xa2a2 |
2320 | #define mmIA_ENHANCE 0xa29c |
2321 | #define mmVGT_DMA_SIZE 0xa29d |
2322 | #define mmVGT_DMA_MAX_SIZE 0xa29e |
2323 | #define mmVGT_DMA_PRIMITIVE_TYPE 0x2271 |
2324 | #define mmVGT_DMA_CONTROL 0x2272 |
2325 | #define mmVGT_IMMED_DATA 0xa1fd |
2326 | #define mmVGT_INDEX_TYPE 0xc243 |
2327 | #define mmVGT_NUM_INDICES 0xc24c |
2328 | #define mmVGT_NUM_INSTANCES 0xc24d |
2329 | #define mmVGT_PRIMITIVE_TYPE 0xc242 |
2330 | #define mmVGT_PRIMITIVEID_EN 0xa2a1 |
2331 | #define mmVGT_PRIMITIVEID_RESET 0xa2a3 |
2332 | #define mmVGT_VTX_CNT_EN 0xa2ae |
2333 | #define mmVGT_REUSE_OFF 0xa2ad |
2334 | #define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8 |
2335 | #define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9 |
2336 | #define mmVGT_MAX_VTX_INDX 0xa100 |
2337 | #define mmVGT_MIN_VTX_INDX 0xa101 |
2338 | #define mmVGT_INDX_OFFSET 0xa102 |
2339 | #define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316 |
2340 | #define mmVGT_OUT_DEALLOC_CNTL 0xa317 |
2341 | #define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103 |
2342 | #define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5 |
2343 | #define mmVGT_ENHANCE 0xa294 |
2344 | #define mmVGT_OUTPUT_PATH_CNTL 0xa284 |
2345 | #define mmVGT_HOS_CNTL 0xa285 |
2346 | #define mmVGT_HOS_MAX_TESS_LEVEL 0xa286 |
2347 | #define mmVGT_HOS_MIN_TESS_LEVEL 0xa287 |
2348 | #define mmVGT_HOS_REUSE_DEPTH 0xa288 |
2349 | #define mmVGT_GROUP_PRIM_TYPE 0xa289 |
2350 | #define mmVGT_GROUP_FIRST_DECR 0xa28a |
2351 | #define mmVGT_GROUP_DECR 0xa28b |
2352 | #define mmVGT_GROUP_VECT_0_CNTL 0xa28c |
2353 | #define mmVGT_GROUP_VECT_1_CNTL 0xa28d |
2354 | #define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e |
2355 | #define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f |
2356 | #define mmVGT_VTX_VECT_EJECT_REG 0x222c |
2357 | #define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d |
2358 | #define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e |
2359 | #define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f |
2360 | #define mmVGT_LAST_COPY_STATE 0x2230 |
2361 | #define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f |
2362 | #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 |
2363 | #define mmVGT_GS_MODE 0xa290 |
2364 | #define mmVGT_GS_ONCHIP_CNTL 0xa291 |
2365 | #define mmVGT_GS_OUT_PRIM_TYPE 0xa29b |
2366 | #define mmVGT_CACHE_INVALIDATION 0x2231 |
2367 | #define mmVGT_RESET_DEBUG 0x2232 |
2368 | #define mmVGT_STRMOUT_DELAY 0x2233 |
2369 | #define mmVGT_FIFO_DEPTHS 0x2234 |
2370 | #define mmVGT_GS_PER_ES 0xa295 |
2371 | #define mmVGT_ES_PER_GS 0xa296 |
2372 | #define mmVGT_GS_PER_VS 0xa297 |
2373 | #define mmVGT_GS_VERTEX_REUSE 0x2235 |
2374 | #define mmVGT_MC_LAT_CNTL 0x2236 |
2375 | #define mmIA_CNTL_STATUS 0x2237 |
2376 | #define mmVGT_STRMOUT_CONFIG 0xa2e5 |
2377 | #define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4 |
2378 | #define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8 |
2379 | #define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc |
2380 | #define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0 |
2381 | #define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7 |
2382 | #define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb |
2383 | #define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf |
2384 | #define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3 |
2385 | #define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5 |
2386 | #define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9 |
2387 | #define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd |
2388 | #define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1 |
2389 | #define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6 |
2390 | #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244 |
2391 | #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245 |
2392 | #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246 |
2393 | #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247 |
2394 | #define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca |
2395 | #define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb |
2396 | #define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc |
2397 | #define mmVGT_GS_MAX_VERT_OUT 0xa2ce |
2398 | #define mmIA_VMID_OVERRIDE 0x2260 |
2399 | #define mmVGT_SHADER_STAGES_EN 0xa2d5 |
2400 | #define mmVGT_DISPATCH_DRAW_INDEX 0xa2dd |
2401 | #define mmVGT_LS_HS_CONFIG 0xa2d6 |
2402 | #define mmVGT_DMA_LS_HS_CONFIG 0x2273 |
2403 | #define mmVGT_TF_PARAM 0xa2db |
2404 | #define mmVGT_TF_RING_SIZE 0xc24e |
2405 | #define mmVGT_SYS_CONFIG 0x2263 |
2406 | #define mmVGT_HS_OFFCHIP_PARAM 0xc24f |
2407 | #define mmVGT_TF_MEMORY_BASE 0xc250 |
2408 | #define mmVGT_GS_INSTANCE_CNT 0xa2e4 |
2409 | #define mmIA_MULTI_VGT_PARAM 0xa2aa |
2410 | #define mmVGT_VS_MAX_WAVE_ID 0x2268 |
2411 | #define mmVGT_ESGS_RING_SIZE 0xc240 |
2412 | #define mmVGT_GSVS_RING_SIZE 0xc241 |
2413 | #define mmVGT_GSVS_RING_OFFSET_1 0xa298 |
2414 | #define mmVGT_GSVS_RING_OFFSET_2 0xa299 |
2415 | #define mmVGT_GSVS_RING_OFFSET_3 0xa29a |
2416 | #define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab |
2417 | #define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac |
2418 | #define mmVGT_GS_VERT_ITEMSIZE 0xa2d7 |
2419 | #define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8 |
2420 | #define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9 |
2421 | #define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da |
2422 | #define mmWD_CNTL_STATUS 0x223f |
2423 | #define mmWD_ENHANCE 0xa2a0 |
2424 | #define mmGFX_PIPE_CONTROL 0x226d |
2425 | #define mmGFX_PIPE_PRIORITY 0xf87f |
2426 | #define mmCGTT_VGT_CLK_CTRL 0xf084 |
2427 | #define mmCGTT_IA_CLK_CTRL 0xf085 |
2428 | #define mmCGTT_WD_CLK_CTRL 0xf086 |
2429 | #define mmVGT_DEBUG_CNTL 0x2238 |
2430 | #define mmVGT_DEBUG_DATA 0x2239 |
2431 | #define mmIA_DEBUG_CNTL 0x223a |
2432 | #define mmIA_DEBUG_DATA 0x223b |
2433 | #define mmVGT_CNTL_STATUS 0x223c |
2434 | #define mmWD_DEBUG_CNTL 0x223d |
2435 | #define mmWD_DEBUG_DATA 0x223e |
2436 | #define mmCC_GC_PRIM_CONFIG 0x2240 |
2437 | #define mmGC_USER_PRIM_CONFIG 0x2241 |
2438 | #define ixWD_DEBUG_REG0 0x0 |
2439 | #define ixWD_DEBUG_REG1 0x1 |
2440 | #define ixWD_DEBUG_REG2 0x2 |
2441 | #define ixWD_DEBUG_REG3 0x3 |
2442 | #define ixWD_DEBUG_REG4 0x4 |
2443 | #define ixWD_DEBUG_REG5 0x5 |
2444 | #define ixIA_DEBUG_REG0 0x0 |
2445 | #define ixIA_DEBUG_REG1 0x1 |
2446 | #define ixIA_DEBUG_REG2 0x2 |
2447 | #define ixIA_DEBUG_REG3 0x3 |
2448 | #define ixIA_DEBUG_REG4 0x4 |
2449 | #define ixIA_DEBUG_REG5 0x5 |
2450 | #define ixIA_DEBUG_REG6 0x6 |
2451 | #define ixIA_DEBUG_REG7 0x7 |
2452 | #define ixIA_DEBUG_REG8 0x8 |
2453 | #define ixIA_DEBUG_REG9 0x9 |
2454 | #define ixVGT_DEBUG_REG0 0x0 |
2455 | #define ixVGT_DEBUG_REG1 0x1 |
2456 | #define ixVGT_DEBUG_REG2 0x1e |
2457 | #define ixVGT_DEBUG_REG3 0x1f |
2458 | #define ixVGT_DEBUG_REG4 0x20 |
2459 | #define ixVGT_DEBUG_REG5 0x21 |
2460 | #define ixVGT_DEBUG_REG6 0x22 |
2461 | #define ixVGT_DEBUG_REG7 0x23 |
2462 | #define ixVGT_DEBUG_REG8 0x8 |
2463 | #define ixVGT_DEBUG_REG9 0x9 |
2464 | #define ixVGT_DEBUG_REG10 0xa |
2465 | #define ixVGT_DEBUG_REG11 0xb |
2466 | #define ixVGT_DEBUG_REG12 0xc |
2467 | #define ixVGT_DEBUG_REG13 0xd |
2468 | #define ixVGT_DEBUG_REG14 0xe |
2469 | #define ixVGT_DEBUG_REG15 0xf |
2470 | #define ixVGT_DEBUG_REG16 0x10 |
2471 | #define ixVGT_DEBUG_REG17 0x11 |
2472 | #define ixVGT_DEBUG_REG18 0x7 |
2473 | #define ixVGT_DEBUG_REG19 0x13 |
2474 | #define ixVGT_DEBUG_REG20 0x14 |
2475 | #define ixVGT_DEBUG_REG21 0x15 |
2476 | #define ixVGT_DEBUG_REG22 0x16 |
2477 | #define ixVGT_DEBUG_REG23 0x17 |
2478 | #define ixVGT_DEBUG_REG24 0x18 |
2479 | #define ixVGT_DEBUG_REG25 0x19 |
2480 | #define ixVGT_DEBUG_REG26 0x24 |
2481 | #define ixVGT_DEBUG_REG27 0x1b |
2482 | #define ixVGT_DEBUG_REG28 0x1c |
2483 | #define ixVGT_DEBUG_REG29 0x1d |
2484 | #define ixVGT_DEBUG_REG30 0x25 |
2485 | #define ixVGT_DEBUG_REG31 0x26 |
2486 | #define ixVGT_DEBUG_REG32 0x27 |
2487 | #define ixVGT_DEBUG_REG33 0x28 |
2488 | #define ixVGT_DEBUG_REG34 0x29 |
2489 | #define ixVGT_DEBUG_REG35 0x2a |
2490 | #define mmVGT_PERFCOUNTER_SEID_MASK 0xd894 |
2491 | #define mmVGT_PERFCOUNTER0_SELECT 0xd88c |
2492 | #define mmVGT_PERFCOUNTER1_SELECT 0xd88d |
2493 | #define mmVGT_PERFCOUNTER2_SELECT 0xd88e |
2494 | #define mmVGT_PERFCOUNTER3_SELECT 0xd88f |
2495 | #define mmVGT_PERFCOUNTER0_SELECT1 0xd890 |
2496 | #define mmVGT_PERFCOUNTER1_SELECT1 0xd891 |
2497 | #define mmVGT_PERFCOUNTER0_LO 0xd090 |
2498 | #define mmVGT_PERFCOUNTER1_LO 0xd092 |
2499 | #define mmVGT_PERFCOUNTER2_LO 0xd094 |
2500 | #define mmVGT_PERFCOUNTER3_LO 0xd096 |
2501 | #define mmVGT_PERFCOUNTER0_HI 0xd091 |
2502 | #define mmVGT_PERFCOUNTER1_HI 0xd093 |
2503 | #define mmVGT_PERFCOUNTER2_HI 0xd095 |
2504 | #define mmVGT_PERFCOUNTER3_HI 0xd097 |
2505 | #define mmIA_PERFCOUNTER0_SELECT 0xd884 |
2506 | #define mmIA_PERFCOUNTER1_SELECT 0xd885 |
2507 | #define mmIA_PERFCOUNTER2_SELECT 0xd886 |
2508 | #define mmIA_PERFCOUNTER3_SELECT 0xd887 |
2509 | #define mmIA_PERFCOUNTER0_SELECT1 0xd888 |
2510 | #define mmIA_PERFCOUNTER0_LO 0xd088 |
2511 | #define mmIA_PERFCOUNTER1_LO 0xd08a |
2512 | #define mmIA_PERFCOUNTER2_LO 0xd08c |
2513 | #define mmIA_PERFCOUNTER3_LO 0xd08e |
2514 | #define mmIA_PERFCOUNTER0_HI 0xd089 |
2515 | #define mmIA_PERFCOUNTER1_HI 0xd08b |
2516 | #define mmIA_PERFCOUNTER2_HI 0xd08d |
2517 | #define mmIA_PERFCOUNTER3_HI 0xd08f |
2518 | #define mmWD_PERFCOUNTER0_SELECT 0xd880 |
2519 | #define mmWD_PERFCOUNTER1_SELECT 0xd881 |
2520 | #define mmWD_PERFCOUNTER2_SELECT 0xd882 |
2521 | #define mmWD_PERFCOUNTER3_SELECT 0xd883 |
2522 | #define mmWD_PERFCOUNTER0_LO 0xd080 |
2523 | #define mmWD_PERFCOUNTER1_LO 0xd082 |
2524 | #define mmWD_PERFCOUNTER2_LO 0xd084 |
2525 | #define mmWD_PERFCOUNTER3_LO 0xd086 |
2526 | #define mmWD_PERFCOUNTER0_HI 0xd081 |
2527 | #define mmWD_PERFCOUNTER1_HI 0xd083 |
2528 | #define mmWD_PERFCOUNTER2_HI 0xd085 |
2529 | #define mmWD_PERFCOUNTER3_HI 0xd087 |
2530 | #define mmDIDT_IND_INDEX 0x3280 |
2531 | #define mmDIDT_IND_DATA 0x3281 |
2532 | #define ixDIDT_SQ_CTRL0 0x0 |
2533 | #define ixDIDT_SQ_CTRL1 0x1 |
2534 | #define ixDIDT_SQ_CTRL2 0x2 |
2535 | #define ixDIDT_SQ_WEIGHT0_3 0x10 |
2536 | #define ixDIDT_SQ_WEIGHT4_7 0x11 |
2537 | #define ixDIDT_SQ_WEIGHT8_11 0x12 |
2538 | #define ixDIDT_DB_CTRL0 0x20 |
2539 | #define ixDIDT_DB_CTRL1 0x21 |
2540 | #define ixDIDT_DB_CTRL2 0x22 |
2541 | #define ixDIDT_DB_WEIGHT0_3 0x30 |
2542 | #define ixDIDT_DB_WEIGHT4_7 0x31 |
2543 | #define ixDIDT_DB_WEIGHT8_11 0x32 |
2544 | #define ixDIDT_TD_CTRL0 0x40 |
2545 | #define ixDIDT_TD_CTRL1 0x41 |
2546 | #define ixDIDT_TD_CTRL2 0x42 |
2547 | #define ixDIDT_TD_WEIGHT0_3 0x50 |
2548 | #define ixDIDT_TD_WEIGHT4_7 0x51 |
2549 | #define ixDIDT_TD_WEIGHT8_11 0x52 |
2550 | #define ixDIDT_TCP_CTRL0 0x60 |
2551 | #define ixDIDT_TCP_CTRL1 0x61 |
2552 | #define ixDIDT_TCP_CTRL2 0x62 |
2553 | #define ixDIDT_TCP_WEIGHT0_3 0x70 |
2554 | #define ixDIDT_TCP_WEIGHT4_7 0x71 |
2555 | #define ixDIDT_TCP_WEIGHT8_11 0x72 |
2556 | |
2557 | #endif /* GFX_7_2_D_H */ |
2558 | |