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1/*
2 * GFX_8_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef GFX_8_0_ENUM_H
25#define GFX_8_0_ENUM_H
26
27typedef enum SurfaceNumber {
28 NUMBER_UNORM = 0x0,
29 NUMBER_SNORM = 0x1,
30 NUMBER_USCALED = 0x2,
31 NUMBER_SSCALED = 0x3,
32 NUMBER_UINT = 0x4,
33 NUMBER_SINT = 0x5,
34 NUMBER_SRGB = 0x6,
35 NUMBER_FLOAT = 0x7,
36} SurfaceNumber;
37typedef enum SurfaceSwap {
38 SWAP_STD = 0x0,
39 SWAP_ALT = 0x1,
40 SWAP_STD_REV = 0x2,
41 SWAP_ALT_REV = 0x3,
42} SurfaceSwap;
43typedef enum CBMode {
44 CB_DISABLE = 0x0,
45 CB_NORMAL = 0x1,
46 CB_ELIMINATE_FAST_CLEAR = 0x2,
47 CB_RESOLVE = 0x3,
48 CB_DECOMPRESS = 0x4,
49 CB_FMASK_DECOMPRESS = 0x5,
50 CB_DCC_DECOMPRESS = 0x6,
51} CBMode;
52typedef enum RoundMode {
53 ROUND_BY_HALF = 0x0,
54 ROUND_TRUNCATE = 0x1,
55} RoundMode;
56typedef enum SourceFormat {
57 EXPORT_4C_32BPC = 0x0,
58 EXPORT_4C_16BPC = 0x1,
59 EXPORT_2C_32BPC_GR = 0x2,
60 EXPORT_2C_32BPC_AR = 0x3,
61} SourceFormat;
62typedef enum BlendOp {
63 BLEND_ZERO = 0x0,
64 BLEND_ONE = 0x1,
65 BLEND_SRC_COLOR = 0x2,
66 BLEND_ONE_MINUS_SRC_COLOR = 0x3,
67 BLEND_SRC_ALPHA = 0x4,
68 BLEND_ONE_MINUS_SRC_ALPHA = 0x5,
69 BLEND_DST_ALPHA = 0x6,
70 BLEND_ONE_MINUS_DST_ALPHA = 0x7,
71 BLEND_DST_COLOR = 0x8,
72 BLEND_ONE_MINUS_DST_COLOR = 0x9,
73 BLEND_SRC_ALPHA_SATURATE = 0xa,
74 BLEND_BOTH_SRC_ALPHA = 0xb,
75 BLEND_BOTH_INV_SRC_ALPHA = 0xc,
76 BLEND_CONSTANT_COLOR = 0xd,
77 BLEND_ONE_MINUS_CONSTANT_COLOR = 0xe,
78 BLEND_SRC1_COLOR = 0xf,
79 BLEND_INV_SRC1_COLOR = 0x10,
80 BLEND_SRC1_ALPHA = 0x11,
81 BLEND_INV_SRC1_ALPHA = 0x12,
82 BLEND_CONSTANT_ALPHA = 0x13,
83 BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14,
84} BlendOp;
85typedef enum CombFunc {
86 COMB_DST_PLUS_SRC = 0x0,
87 COMB_SRC_MINUS_DST = 0x1,
88 COMB_MIN_DST_SRC = 0x2,
89 COMB_MAX_DST_SRC = 0x3,
90 COMB_DST_MINUS_SRC = 0x4,
91} CombFunc;
92typedef enum BlendOpt {
93 FORCE_OPT_AUTO = 0x0,
94 FORCE_OPT_DISABLE = 0x1,
95 FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2,
96 FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x3,
97 FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x4,
98 FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5,
99 FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x6,
100 FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x7,
101} BlendOpt;
102typedef enum CmaskCode {
103 CMASK_CLR00_F0 = 0x0,
104 CMASK_CLR00_F1 = 0x1,
105 CMASK_CLR00_F2 = 0x2,
106 CMASK_CLR00_FX = 0x3,
107 CMASK_CLR01_F0 = 0x4,
108 CMASK_CLR01_F1 = 0x5,
109 CMASK_CLR01_F2 = 0x6,
110 CMASK_CLR01_FX = 0x7,
111 CMASK_CLR10_F0 = 0x8,
112 CMASK_CLR10_F1 = 0x9,
113 CMASK_CLR10_F2 = 0xa,
114 CMASK_CLR10_FX = 0xb,
115 CMASK_CLR11_F0 = 0xc,
116 CMASK_CLR11_F1 = 0xd,
117 CMASK_CLR11_F2 = 0xe,
118 CMASK_CLR11_FX = 0xf,
119} CmaskCode;
120typedef enum CmaskAddr {
121 CMASK_ADDR_TILED = 0x0,
122 CMASK_ADDR_LINEAR = 0x1,
123 CMASK_ADDR_COMPATIBLE = 0x2,
124} CmaskAddr;
125typedef enum CBPerfSel {
126 CB_PERF_SEL_NONE = 0x0,
127 CB_PERF_SEL_BUSY = 0x1,
128 CB_PERF_SEL_CORE_SCLK_VLD = 0x2,
129 CB_PERF_SEL_REG_SCLK0_VLD = 0x3,
130 CB_PERF_SEL_REG_SCLK1_VLD = 0x4,
131 CB_PERF_SEL_DRAWN_QUAD = 0x5,
132 CB_PERF_SEL_DRAWN_PIXEL = 0x6,
133 CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x7,
134 CB_PERF_SEL_DRAWN_TILE = 0x8,
135 CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x9,
136 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa,
137 CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0xb,
138 CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0xc,
139 CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0xd,
140 CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0xe,
141 CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0xf,
142 CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x10,
143 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x11,
144 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x12,
145 CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x13,
146 CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x14,
147 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x15,
148 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x16,
149 CB_PERF_SEL_LQUAD_NO_TILE = 0x17,
150 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x18,
151 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x19,
152 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x1a,
153 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x1b,
154 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x1c,
155 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d,
156 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e,
157 CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x1f,
158 CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x20,
159 CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21,
160 CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x22,
161 CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x23,
162 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x24,
163 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x25,
164 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x26,
165 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x27,
166 CB_PERF_SEL_FOP_IN_VALID_READY = 0x28,
167 CB_PERF_SEL_FOP_IN_VALID_READYB = 0x29,
168 CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x2a,
169 CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x2b,
170 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x2c,
171 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x2d,
172 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x2e,
173 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x2f,
174 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x30,
175 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x31,
176 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x32,
177 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x33,
178 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x34,
179 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x35,
180 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x36,
181 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x37,
182 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x38,
183 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x39,
184 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x3a,
185 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x3b,
186 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x3c,
187 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x3d,
188 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x3e,
189 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x3f,
190 CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x40,
191 CB_PERF_SEL_CM_CACHE_HIT = 0x41,
192 CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x42,
193 CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x43,
194 CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x44,
195 CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45,
196 CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46,
197 CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47,
198 CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x48,
199 CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x49,
200 CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x4a,
201 CB_PERF_SEL_CM_CACHE_STALL = 0x4b,
202 CB_PERF_SEL_CM_CACHE_FLUSH = 0x4c,
203 CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x4d,
204 CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x4e,
205 CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x4f,
206 CB_PERF_SEL_FC_CACHE_HIT = 0x50,
207 CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x51,
208 CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x52,
209 CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x53,
210 CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54,
211 CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55,
212 CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56,
213 CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x57,
214 CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x58,
215 CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x59,
216 CB_PERF_SEL_FC_CACHE_STALL = 0x5a,
217 CB_PERF_SEL_FC_CACHE_FLUSH = 0x5b,
218 CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x5c,
219 CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x5d,
220 CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x5e,
221 CB_PERF_SEL_CC_CACHE_HIT = 0x5f,
222 CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x60,
223 CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x61,
224 CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x62,
225 CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63,
226 CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64,
227 CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65,
228 CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x66,
229 CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x67,
230 CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x68,
231 CB_PERF_SEL_CC_CACHE_STALL = 0x69,
232 CB_PERF_SEL_CC_CACHE_FLUSH = 0x6a,
233 CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x6b,
234 CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x6c,
235 CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x6d,
236 CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x6e,
237 CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x6f,
238 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x70,
239 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x71,
240 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x72,
241 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x73,
242 CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x74,
243 CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x75,
244 CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x76,
245 CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x77,
246 CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x78,
247 CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x79,
248 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x7a,
249 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x7b,
250 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x7c,
251 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x7d,
252 CB_PERF_SEL_CM_MC_READ_REQUEST = 0x7e,
253 CB_PERF_SEL_FC_MC_READ_REQUEST = 0x7f,
254 CB_PERF_SEL_CC_MC_READ_REQUEST = 0x80,
255 CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x81,
256 CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x82,
257 CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x83,
258 CB_PERF_SEL_CM_TQ_FULL = 0x84,
259 CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x85,
260 CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x86,
261 CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x87,
262 CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x88,
263 CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x89,
264 CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x8a,
265 CB_PERF_SEL_CC_SF_FULL = 0x8b,
266 CB_PERF_SEL_CC_RB_FULL = 0x8c,
267 CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x8d,
268 CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x8e,
269 CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x8f,
270 CB_PERF_SEL_EVENT = 0x90,
271 CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x91,
272 CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x92,
273 CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x93,
274 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x94,
275 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x95,
276 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x96,
277 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x97,
278 CB_PERF_SEL_CC_SURFACE_SYNC = 0x98,
279 CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x99,
280 CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x9a,
281 CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x9b,
282 CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x9c,
283 CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x9d,
284 CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x9e,
285 CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x9f,
286 CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0xa0,
287 CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0xa1,
288 CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0xa2,
289 CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0xa3,
290 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0xa4,
291 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0xa5,
292 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0xa6,
293 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0xa7,
294 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0xa8,
295 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0xa9,
296 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0xaa,
297 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0xab,
298 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0xac,
299 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0xad,
300 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0xae,
301 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0xaf,
302 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0xb0,
303 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0xb1,
304 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0xb2,
305 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0xb3,
306 CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0xb4,
307 CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0xb5,
308 CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0xb6,
309 CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0xb7,
310 CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0xb8,
311 CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0xb9,
312 CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0xba,
313 CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0xbb,
314 CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0xbc,
315 CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0xbd,
316 CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0xbe,
317 CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0xbf,
318 CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0xc0,
319 CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0xc1,
320 CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0xc2,
321 CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0xc3,
322 CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0xc4,
323 CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0xc5,
324 CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0xc6,
325 CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0xc7,
326 CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0xc8,
327 CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0xc9,
328 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0xca,
329 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0xcb,
330 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0xcc,
331 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0xcd,
332 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0xce,
333 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0xcf,
334 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0xd0,
335 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0xd1,
336 CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0xd2,
337 CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0xd3,
338 CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0xd4,
339 CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd5,
340 CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd6,
341 CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0xd7,
342 CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0xd8,
343 CB_PERF_SEL_DRAWN_BUSY = 0xd9,
344 CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0xda,
345 CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0xdb,
346 CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0xdc,
347 CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0xdd,
348 CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xde,
349 CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0xdf,
350 CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0xe0,
351 CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0xe1,
352 CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe2,
353 CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0xe3,
354 CB_PERF_SEL_FC_DOC_IS_STALLED = 0xe4,
355 CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0xe5,
356 CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0xe6,
357 CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0xe7,
358 CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0xe8,
359 CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0xe9,
360 CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0xea,
361 CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0xeb,
362 CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0xec,
363 CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0xed,
364 CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0xee,
365 CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0xef,
366 CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0xf0,
367 CB_PERF_SEL_FC_DCC_CACHE_HIT = 0xf1,
368 CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0xf2,
369 CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0xf3,
370 CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0xf4,
371 CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0xf5,
372 CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL= 0xf6,
373 CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0xf7,
374 CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0xf8,
375 CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0xf9,
376 CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0xfa,
377 CB_PERF_SEL_FC_DCC_CACHE_STALL = 0xfb,
378 CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0xfc,
379 CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0xfd,
380 CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0xfe,
381 CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0xff,
382 CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x100,
383 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x101,
384 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x102,
385 CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x103,
386 CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x104,
387 CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x105,
388 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x106,
389 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x107,
390 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x108,
391 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x109,
392 CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x10a,
393 CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x10b,
394 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2= 0x10c,
395 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x10d,
396 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1= 0x10e,
397 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1= 0x10f,
398 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2= 0x110,
399 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111,
400 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112,
401 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x113,
402 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1= 0x114,
403 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115,
404 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2= 0x116,
405 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117,
406 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x118,
407 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1= 0x119,
408 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x11a,
409 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2= 0x11b,
410 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3= 0x11c,
411 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4= 0x11d,
412 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1= 0x11e,
413 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x11f,
414 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3= 0x120,
415 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4= 0x121,
416 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122,
417 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2= 0x123,
418 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x124,
419 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125,
420 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126,
421 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2= 0x127,
422 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3= 0x128,
423 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1= 0x129,
424 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2= 0x12a,
425 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3= 0x12b,
426 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4= 0x12c,
427 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1= 0x12d,
428 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2= 0x12e,
429 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3= 0x12f,
430 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4= 0x130,
431 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131,
432 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132,
433 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133,
434 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4= 0x134,
435 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135,
436 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136,
437 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3= 0x137,
438 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1= 0x138,
439 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1= 0x139,
440 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1= 0x13a,
441 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1= 0x13b,
442 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1= 0x13c,
443 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1= 0x13d,
444 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1= 0x13e,
445 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1= 0x13f,
446 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2= 0x140,
447 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141,
448 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2= 0x142,
449 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2= 0x143,
450 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2= 0x144,
451 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145,
452 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2= 0x146,
453 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1= 0x147,
454 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1= 0x148,
455 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1= 0x149,
456 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1= 0x14a,
457 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2= 0x14b,
458 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2= 0x14c,
459 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2= 0x14d,
460 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2= 0x14e,
461 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x14f,
462 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2= 0x150,
463 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2= 0x151,
464 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x152,
465 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1= 0x153,
466 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1= 0x154,
467 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1= 0x155,
468 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1= 0x156,
469 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2= 0x157,
470 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3= 0x158,
471 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4= 0x159,
472 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5= 0x15a,
473 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6= 0x15b,
474 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x15c,
475 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x15d,
476 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1= 0x15e,
477 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2= 0x15f,
478 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3= 0x160,
479 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4= 0x161,
480 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5= 0x162,
481 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x163,
482 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x164,
483 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1= 0x165,
484 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1= 0x166,
485 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1= 0x167,
486 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1= 0x168,
487 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1= 0x169,
488 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1= 0x16a,
489 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x16b,
490 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x16c,
491 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2= 0x16d,
492 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2= 0x16e,
493 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2= 0x16f,
494 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2= 0x170,
495 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2= 0x171,
496 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x172,
497 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x173,
498 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x174,
499 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x175,
500 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x176,
501 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x177,
502 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x178,
503 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x179,
504 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x17a,
505 CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x17b,
506 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x17c,
507 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x17d,
508 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x17e,
509 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x17f,
510 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x180,
511 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x181,
512 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x182,
513 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x183,
514 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x184,
515 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x185,
516 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x186,
517 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x187,
518 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x188,
519 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x189,
520 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x18a,
521 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x18b,
522} CBPerfSel;
523typedef enum CBPerfOpFilterSel {
524 CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x0,
525 CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x1,
526 CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2,
527 CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x3,
528 CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x4,
529 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5,
530} CBPerfOpFilterSel;
531typedef enum CBPerfClearFilterSel {
532 CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x0,
533 CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x1,
534} CBPerfClearFilterSel;
535typedef enum CP_RING_ID {
536 RINGID0 = 0x0,
537 RINGID1 = 0x1,
538 RINGID2 = 0x2,
539 RINGID3 = 0x3,
540} CP_RING_ID;
541typedef enum CP_PIPE_ID {
542 PIPE_ID0 = 0x0,
543 PIPE_ID1 = 0x1,
544 PIPE_ID2 = 0x2,
545 PIPE_ID3 = 0x3,
546} CP_PIPE_ID;
547typedef enum CP_ME_ID {
548 ME_ID0 = 0x0,
549 ME_ID1 = 0x1,
550 ME_ID2 = 0x2,
551 ME_ID3 = 0x3,
552} CP_ME_ID;
553typedef enum SPM_PERFMON_STATE {
554 STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x0,
555 STRM_PERFMON_STATE_START_COUNTING = 0x1,
556 STRM_PERFMON_STATE_STOP_COUNTING = 0x2,
557 STRM_PERFMON_STATE_RESERVED_3 = 0x3,
558 STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4,
559 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
560} SPM_PERFMON_STATE;
561typedef enum CP_PERFMON_STATE {
562 CP_PERFMON_STATE_DISABLE_AND_RESET = 0x0,
563 CP_PERFMON_STATE_START_COUNTING = 0x1,
564 CP_PERFMON_STATE_STOP_COUNTING = 0x2,
565 CP_PERFMON_STATE_RESERVED_3 = 0x3,
566 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4,
567 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
568} CP_PERFMON_STATE;
569typedef enum CP_PERFMON_ENABLE_MODE {
570 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x0,
571 CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x1,
572 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2,
573 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x3,
574} CP_PERFMON_ENABLE_MODE;
575typedef enum CPG_PERFCOUNT_SEL {
576 CPG_PERF_SEL_ALWAYS_COUNT = 0x0,
577 CPG_PERF_SEL_RBIU_FIFO_FULL = 0x1,
578 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2,
579 CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x3,
580 CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x4,
581 CPG_PERF_SEL_ME_PARSER_BUSY = 0x5,
582 CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x6,
583 CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x7,
584 CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x8,
585 CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x9,
586 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa,
587 CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0xb,
588 CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0xc,
589 CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0xd,
590 CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0xe,
591 CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0xf,
592 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x10,
593 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x11,
594 CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x12,
595 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x13,
596 CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x14,
597 CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x15,
598 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x16,
599 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x17,
600 CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x18,
601 CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x19,
602 CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x1a,
603 CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x1b,
604 CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x1c,
605 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d,
606 CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x1e,
607 CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x1f,
608 CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x20,
609 CPG_PERF_SEL_REGISTER_CLK_VALID = 0x21,
610 CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x22,
611 CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x23,
612 CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x24,
613 CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x25,
614 CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x26,
615 CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x27,
616 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x28,
617 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x29,
618 CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x2a,
619 CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x2b,
620 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x2c,
621 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x2d,
622 CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x2e,
623 CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x2f,
624 CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x30,
625} CPG_PERFCOUNT_SEL;
626typedef enum CPF_PERFCOUNT_SEL {
627 CPF_PERF_SEL_ALWAYS_COUNT = 0x0,
628 CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x1,
629 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2,
630 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x3,
631 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x4,
632 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x5,
633 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x6,
634 CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x7,
635 CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x8,
636 CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x9,
637 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa,
638 CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0xb,
639 CPF_PERF_SEL_GRBM_DWORDS_SENT = 0xc,
640 CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0xd,
641 CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0xe,
642 CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0xf,
643 CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x10,
644 CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x11,
645 CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x12,
646 CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x13,
647} CPF_PERFCOUNT_SEL;
648typedef enum CPC_PERFCOUNT_SEL {
649 CPC_PERF_SEL_ALWAYS_COUNT = 0x0,
650 CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x1,
651 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2,
652 CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x3,
653 CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x4,
654 CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x5,
655 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x6,
656 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x7,
657 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x8,
658 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x9,
659 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa,
660 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0xb,
661 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0xc,
662 CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0xd,
663 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0xe,
664 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0xf,
665 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x10,
666 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x11,
667 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x12,
668 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x13,
669 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x14,
670 CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x15,
671 CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x16,
672 CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x17,
673 CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x18,
674} CPC_PERFCOUNT_SEL;
675typedef enum CP_ALPHA_TAG_RAM_SEL {
676 CPG_TAG_RAM = 0x0,
677 CPC_TAG_RAM = 0x1,
678 CPF_TAG_RAM = 0x2,
679 RSV_TAG_RAM = 0x3,
680} CP_ALPHA_TAG_RAM_SEL;
681#define SEM_ECC_ERROR 0x0
682#define SEM_RESERVED 0x1
683#define SEM_FAILED 0x2
684#define SEM_PASSED 0x3
685#define IQ_QUEUE_SLEEP 0x0
686#define IQ_OFFLOAD_RETRY 0x1
687#define IQ_SCH_WAVE_MSG 0x2
688#define IQ_SEM_REARM 0x3
689#define IQ_DEQUEUE_RETRY 0x4
690#define IQ_INTR_TYPE_PQ 0x0
691#define IQ_INTR_TYPE_IB 0x1
692#define IQ_INTR_TYPE_MQD 0x2
693#define VMID_SZ 0x4
694#define CONFIG_SPACE_START 0x2000
695#define CONFIG_SPACE_END 0x9fff
696#define CONFIG_SPACE1_START 0x2000
697#define CONFIG_SPACE1_END 0x2bff
698#define CONFIG_SPACE2_START 0x3000
699#define CONFIG_SPACE2_END 0x9fff
700#define UCONFIG_SPACE_START 0xc000
701#define UCONFIG_SPACE_END 0xffff
702#define PERSISTENT_SPACE_START 0x2c00
703#define PERSISTENT_SPACE_END 0x2fff
704#define CONTEXT_SPACE_START 0xa000
705#define CONTEXT_SPACE_END 0xbfff
706typedef enum ForceControl {
707 FORCE_OFF = 0x0,
708 FORCE_ENABLE = 0x1,
709 FORCE_DISABLE = 0x2,
710 FORCE_RESERVED = 0x3,
711} ForceControl;
712typedef enum ZSamplePosition {
713 Z_SAMPLE_CENTER = 0x0,
714 Z_SAMPLE_CENTROID = 0x1,
715} ZSamplePosition;
716typedef enum ZOrder {
717 LATE_Z = 0x0,
718 EARLY_Z_THEN_LATE_Z = 0x1,
719 RE_Z = 0x2,
720 EARLY_Z_THEN_RE_Z = 0x3,
721} ZOrder;
722typedef enum ZpassControl {
723 ZPASS_DISABLE = 0x0,
724 ZPASS_SAMPLES = 0x1,
725 ZPASS_PIXELS = 0x2,
726} ZpassControl;
727typedef enum ZModeForce {
728 NO_FORCE = 0x0,
729 FORCE_EARLY_Z = 0x1,
730 FORCE_LATE_Z = 0x2,
731 FORCE_RE_Z = 0x3,
732} ZModeForce;
733typedef enum ZLimitSumm {
734 FORCE_SUMM_OFF = 0x0,
735 FORCE_SUMM_MINZ = 0x1,
736 FORCE_SUMM_MAXZ = 0x2,
737 FORCE_SUMM_BOTH = 0x3,
738} ZLimitSumm;
739typedef enum CompareFrag {
740 FRAG_NEVER = 0x0,
741 FRAG_LESS = 0x1,
742 FRAG_EQUAL = 0x2,
743 FRAG_LEQUAL = 0x3,
744 FRAG_GREATER = 0x4,
745 FRAG_NOTEQUAL = 0x5,
746 FRAG_GEQUAL = 0x6,
747 FRAG_ALWAYS = 0x7,
748} CompareFrag;
749typedef enum StencilOp {
750 STENCIL_KEEP = 0x0,
751 STENCIL_ZERO = 0x1,
752 STENCIL_ONES = 0x2,
753 STENCIL_REPLACE_TEST = 0x3,
754 STENCIL_REPLACE_OP = 0x4,
755 STENCIL_ADD_CLAMP = 0x5,
756 STENCIL_SUB_CLAMP = 0x6,
757 STENCIL_INVERT = 0x7,
758 STENCIL_ADD_WRAP = 0x8,
759 STENCIL_SUB_WRAP = 0x9,
760 STENCIL_AND = 0xa,
761 STENCIL_OR = 0xb,
762 STENCIL_XOR = 0xc,
763 STENCIL_NAND = 0xd,
764 STENCIL_NOR = 0xe,
765 STENCIL_XNOR = 0xf,
766} StencilOp;
767typedef enum ConservativeZExport {
768 EXPORT_ANY_Z = 0x0,
769 EXPORT_LESS_THAN_Z = 0x1,
770 EXPORT_GREATER_THAN_Z = 0x2,
771 EXPORT_RESERVED = 0x3,
772} ConservativeZExport;
773typedef enum DbPSLControl {
774 PSLC_AUTO = 0x0,
775 PSLC_ON_HANG_ONLY = 0x1,
776 PSLC_ASAP = 0x2,
777 PSLC_COUNTDOWN = 0x3,
778} DbPSLControl;
779typedef enum PerfCounter_Vals {
780 DB_PERF_SEL_SC_DB_tile_sends = 0x0,
781 DB_PERF_SEL_SC_DB_tile_busy = 0x1,
782 DB_PERF_SEL_SC_DB_tile_stalls = 0x2,
783 DB_PERF_SEL_SC_DB_tile_events = 0x3,
784 DB_PERF_SEL_SC_DB_tile_tiles = 0x4,
785 DB_PERF_SEL_SC_DB_tile_covered = 0x5,
786 DB_PERF_SEL_hiz_tc_read_starved = 0x6,
787 DB_PERF_SEL_hiz_tc_write_stall = 0x7,
788 DB_PERF_SEL_hiz_qtiles_culled = 0x8,
789 DB_PERF_SEL_his_qtiles_culled = 0x9,
790 DB_PERF_SEL_DB_SC_tile_sends = 0xa,
791 DB_PERF_SEL_DB_SC_tile_busy = 0xb,
792 DB_PERF_SEL_DB_SC_tile_stalls = 0xc,
793 DB_PERF_SEL_DB_SC_tile_df_stalls = 0xd,
794 DB_PERF_SEL_DB_SC_tile_tiles = 0xe,
795 DB_PERF_SEL_DB_SC_tile_culled = 0xf,
796 DB_PERF_SEL_DB_SC_tile_hier_kill = 0x10,
797 DB_PERF_SEL_DB_SC_tile_fast_ops = 0x11,
798 DB_PERF_SEL_DB_SC_tile_no_ops = 0x12,
799 DB_PERF_SEL_DB_SC_tile_tile_rate = 0x13,
800 DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x14,
801 DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x15,
802 DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x16,
803 DB_PERF_SEL_SC_DB_quad_sends = 0x17,
804 DB_PERF_SEL_SC_DB_quad_busy = 0x18,
805 DB_PERF_SEL_SC_DB_quad_squads = 0x19,
806 DB_PERF_SEL_SC_DB_quad_tiles = 0x1a,
807 DB_PERF_SEL_SC_DB_quad_pixels = 0x1b,
808 DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x1c,
809 DB_PERF_SEL_DB_SC_quad_sends = 0x1d,
810 DB_PERF_SEL_DB_SC_quad_busy = 0x1e,
811 DB_PERF_SEL_DB_SC_quad_stalls = 0x1f,
812 DB_PERF_SEL_DB_SC_quad_tiles = 0x20,
813 DB_PERF_SEL_DB_SC_quad_lit_quad = 0x21,
814 DB_PERF_SEL_DB_CB_tile_sends = 0x22,
815 DB_PERF_SEL_DB_CB_tile_busy = 0x23,
816 DB_PERF_SEL_DB_CB_tile_stalls = 0x24,
817 DB_PERF_SEL_SX_DB_quad_sends = 0x25,
818 DB_PERF_SEL_SX_DB_quad_busy = 0x26,
819 DB_PERF_SEL_SX_DB_quad_stalls = 0x27,
820 DB_PERF_SEL_SX_DB_quad_quads = 0x28,
821 DB_PERF_SEL_SX_DB_quad_pixels = 0x29,
822 DB_PERF_SEL_SX_DB_quad_exports = 0x2a,
823 DB_PERF_SEL_SH_quads_outstanding_sum = 0x2b,
824 DB_PERF_SEL_DB_CB_lquad_sends = 0x2c,
825 DB_PERF_SEL_DB_CB_lquad_busy = 0x2d,
826 DB_PERF_SEL_DB_CB_lquad_stalls = 0x2e,
827 DB_PERF_SEL_DB_CB_lquad_quads = 0x2f,
828 DB_PERF_SEL_tile_rd_sends = 0x30,
829 DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x31,
830 DB_PERF_SEL_quad_rd_sends = 0x32,
831 DB_PERF_SEL_quad_rd_busy = 0x33,
832 DB_PERF_SEL_quad_rd_mi_stall = 0x34,
833 DB_PERF_SEL_quad_rd_rw_collision = 0x35,
834 DB_PERF_SEL_quad_rd_tag_stall = 0x36,
835 DB_PERF_SEL_quad_rd_32byte_reqs = 0x37,
836 DB_PERF_SEL_quad_rd_panic = 0x38,
837 DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x39,
838 DB_PERF_SEL_quad_rdret_sends = 0x3a,
839 DB_PERF_SEL_quad_rdret_busy = 0x3b,
840 DB_PERF_SEL_tile_wr_sends = 0x3c,
841 DB_PERF_SEL_tile_wr_acks = 0x3d,
842 DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x3e,
843 DB_PERF_SEL_quad_wr_sends = 0x3f,
844 DB_PERF_SEL_quad_wr_busy = 0x40,
845 DB_PERF_SEL_quad_wr_mi_stall = 0x41,
846 DB_PERF_SEL_quad_wr_coherency_stall = 0x42,
847 DB_PERF_SEL_quad_wr_acks = 0x43,
848 DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x44,
849 DB_PERF_SEL_Tile_Cache_misses = 0x45,
850 DB_PERF_SEL_Tile_Cache_hits = 0x46,
851 DB_PERF_SEL_Tile_Cache_flushes = 0x47,
852 DB_PERF_SEL_Tile_Cache_surface_stall = 0x48,
853 DB_PERF_SEL_Tile_Cache_starves = 0x49,
854 DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x4a,
855 DB_PERF_SEL_tcp_dispatcher_reads = 0x4b,
856 DB_PERF_SEL_tcp_prefetcher_reads = 0x4c,
857 DB_PERF_SEL_tcp_preloader_reads = 0x4d,
858 DB_PERF_SEL_tcp_dispatcher_flushes = 0x4e,
859 DB_PERF_SEL_tcp_prefetcher_flushes = 0x4f,
860 DB_PERF_SEL_tcp_preloader_flushes = 0x50,
861 DB_PERF_SEL_Depth_Tile_Cache_sends = 0x51,
862 DB_PERF_SEL_Depth_Tile_Cache_busy = 0x52,
863 DB_PERF_SEL_Depth_Tile_Cache_starves = 0x53,
864 DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x54,
865 DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x55,
866 DB_PERF_SEL_Depth_Tile_Cache_misses = 0x56,
867 DB_PERF_SEL_Depth_Tile_Cache_hits = 0x57,
868 DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x58,
869 DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x59,
870 DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x5a,
871 DB_PERF_SEL_Depth_Tile_Cache_event = 0x5b,
872 DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x5c,
873 DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x5d,
874 DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x5e,
875 DB_PERF_SEL_Stencil_Cache_misses = 0x5f,
876 DB_PERF_SEL_Stencil_Cache_hits = 0x60,
877 DB_PERF_SEL_Stencil_Cache_flushes = 0x61,
878 DB_PERF_SEL_Stencil_Cache_starves = 0x62,
879 DB_PERF_SEL_Stencil_Cache_frees = 0x63,
880 DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x64,
881 DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x65,
882 DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x66,
883 DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x67,
884 DB_PERF_SEL_Z_Cache_pmask_misses = 0x68,
885 DB_PERF_SEL_Z_Cache_pmask_hits = 0x69,
886 DB_PERF_SEL_Z_Cache_pmask_flushes = 0x6a,
887 DB_PERF_SEL_Z_Cache_pmask_starves = 0x6b,
888 DB_PERF_SEL_Z_Cache_frees = 0x6c,
889 DB_PERF_SEL_Plane_Cache_misses = 0x6d,
890 DB_PERF_SEL_Plane_Cache_hits = 0x6e,
891 DB_PERF_SEL_Plane_Cache_flushes = 0x6f,
892 DB_PERF_SEL_Plane_Cache_starves = 0x70,
893 DB_PERF_SEL_Plane_Cache_frees = 0x71,
894 DB_PERF_SEL_flush_expanded_stencil = 0x72,
895 DB_PERF_SEL_flush_compressed_stencil = 0x73,
896 DB_PERF_SEL_flush_single_stencil = 0x74,
897 DB_PERF_SEL_planes_flushed = 0x75,
898 DB_PERF_SEL_flush_1plane = 0x76,
899 DB_PERF_SEL_flush_2plane = 0x77,
900 DB_PERF_SEL_flush_3plane = 0x78,
901 DB_PERF_SEL_flush_4plane = 0x79,
902 DB_PERF_SEL_flush_5plane = 0x7a,
903 DB_PERF_SEL_flush_6plane = 0x7b,
904 DB_PERF_SEL_flush_7plane = 0x7c,
905 DB_PERF_SEL_flush_8plane = 0x7d,
906 DB_PERF_SEL_flush_9plane = 0x7e,
907 DB_PERF_SEL_flush_10plane = 0x7f,
908 DB_PERF_SEL_flush_11plane = 0x80,
909 DB_PERF_SEL_flush_12plane = 0x81,
910 DB_PERF_SEL_flush_13plane = 0x82,
911 DB_PERF_SEL_flush_14plane = 0x83,
912 DB_PERF_SEL_flush_15plane = 0x84,
913 DB_PERF_SEL_flush_16plane = 0x85,
914 DB_PERF_SEL_flush_expanded_z = 0x86,
915 DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x87,
916 DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x88,
917 DB_PERF_SEL_dk_tile_sends = 0x89,
918 DB_PERF_SEL_dk_tile_busy = 0x8a,
919 DB_PERF_SEL_dk_tile_quad_starves = 0x8b,
920 DB_PERF_SEL_dk_tile_stalls = 0x8c,
921 DB_PERF_SEL_dk_squad_sends = 0x8d,
922 DB_PERF_SEL_dk_squad_busy = 0x8e,
923 DB_PERF_SEL_dk_squad_stalls = 0x8f,
924 DB_PERF_SEL_Op_Pipe_Busy = 0x90,
925 DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x91,
926 DB_PERF_SEL_qc_busy = 0x92,
927 DB_PERF_SEL_qc_xfc = 0x93,
928 DB_PERF_SEL_qc_conflicts = 0x94,
929 DB_PERF_SEL_qc_full_stall = 0x95,
930 DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x96,
931 DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x97,
932 DB_PERF_SEL_tsc_insert_summarize_stall = 0x98,
933 DB_PERF_SEL_tl_busy = 0x99,
934 DB_PERF_SEL_tl_dtc_read_starved = 0x9a,
935 DB_PERF_SEL_tl_z_fetch_stall = 0x9b,
936 DB_PERF_SEL_tl_stencil_stall = 0x9c,
937 DB_PERF_SEL_tl_z_decompress_stall = 0x9d,
938 DB_PERF_SEL_tl_stencil_locked_stall = 0x9e,
939 DB_PERF_SEL_tl_events = 0x9f,
940 DB_PERF_SEL_tl_summarize_squads = 0xa0,
941 DB_PERF_SEL_tl_flush_expand_squads = 0xa1,
942 DB_PERF_SEL_tl_expand_squads = 0xa2,
943 DB_PERF_SEL_tl_preZ_squads = 0xa3,
944 DB_PERF_SEL_tl_postZ_squads = 0xa4,
945 DB_PERF_SEL_tl_preZ_noop_squads = 0xa5,
946 DB_PERF_SEL_tl_postZ_noop_squads = 0xa6,
947 DB_PERF_SEL_tl_tile_ops = 0xa7,
948 DB_PERF_SEL_tl_in_xfc = 0xa8,
949 DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0xa9,
950 DB_PERF_SEL_tl_in_fast_z_stall = 0xaa,
951 DB_PERF_SEL_tl_out_xfc = 0xab,
952 DB_PERF_SEL_tl_out_squads = 0xac,
953 DB_PERF_SEL_zf_plane_multicycle = 0xad,
954 DB_PERF_SEL_PostZ_Samples_passing_Z = 0xae,
955 DB_PERF_SEL_PostZ_Samples_failing_Z = 0xaf,
956 DB_PERF_SEL_PostZ_Samples_failing_S = 0xb0,
957 DB_PERF_SEL_PreZ_Samples_passing_Z = 0xb1,
958 DB_PERF_SEL_PreZ_Samples_failing_Z = 0xb2,
959 DB_PERF_SEL_PreZ_Samples_failing_S = 0xb3,
960 DB_PERF_SEL_ts_tc_update_stall = 0xb4,
961 DB_PERF_SEL_sc_kick_start = 0xb5,
962 DB_PERF_SEL_sc_kick_end = 0xb6,
963 DB_PERF_SEL_clock_reg_active = 0xb7,
964 DB_PERF_SEL_clock_main_active = 0xb8,
965 DB_PERF_SEL_clock_mem_export_active = 0xb9,
966 DB_PERF_SEL_esr_ps_out_busy = 0xba,
967 DB_PERF_SEL_esr_ps_lqf_busy = 0xbb,
968 DB_PERF_SEL_esr_ps_lqf_stall = 0xbc,
969 DB_PERF_SEL_etr_out_send = 0xbd,
970 DB_PERF_SEL_etr_out_busy = 0xbe,
971 DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0xbf,
972 DB_PERF_SEL_etr_out_cb_tile_stall = 0xc0,
973 DB_PERF_SEL_etr_out_esr_stall = 0xc1,
974 DB_PERF_SEL_esr_ps_sqq_busy = 0xc2,
975 DB_PERF_SEL_esr_ps_sqq_stall = 0xc3,
976 DB_PERF_SEL_esr_eot_fwd_busy = 0xc4,
977 DB_PERF_SEL_esr_eot_fwd_holding_squad = 0xc5,
978 DB_PERF_SEL_esr_eot_fwd_forward = 0xc6,
979 DB_PERF_SEL_esr_sqq_zi_busy = 0xc7,
980 DB_PERF_SEL_esr_sqq_zi_stall = 0xc8,
981 DB_PERF_SEL_postzl_sq_pt_busy = 0xc9,
982 DB_PERF_SEL_postzl_sq_pt_stall = 0xca,
983 DB_PERF_SEL_postzl_se_busy = 0xcb,
984 DB_PERF_SEL_postzl_se_stall = 0xcc,
985 DB_PERF_SEL_postzl_partial_launch = 0xcd,
986 DB_PERF_SEL_postzl_full_launch = 0xce,
987 DB_PERF_SEL_postzl_partial_waiting = 0xcf,
988 DB_PERF_SEL_postzl_tile_mem_stall = 0xd0,
989 DB_PERF_SEL_postzl_tile_init_stall = 0xd1,
990 DB_PEFF_SEL_prezl_tile_mem_stall = 0xd2,
991 DB_PERF_SEL_prezl_tile_init_stall = 0xd3,
992 DB_PERF_SEL_dtt_sm_clash_stall = 0xd4,
993 DB_PERF_SEL_dtt_sm_slot_stall = 0xd5,
994 DB_PERF_SEL_dtt_sm_miss_stall = 0xd6,
995 DB_PERF_SEL_mi_rdreq_busy = 0xd7,
996 DB_PERF_SEL_mi_rdreq_stall = 0xd8,
997 DB_PERF_SEL_mi_wrreq_busy = 0xd9,
998 DB_PERF_SEL_mi_wrreq_stall = 0xda,
999 DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0xdb,
1000 DB_PERF_SEL_dkg_tile_rate_tile = 0xdc,
1001 DB_PERF_SEL_prezl_src_in_sends = 0xdd,
1002 DB_PERF_SEL_prezl_src_in_stall = 0xde,
1003 DB_PERF_SEL_prezl_src_in_squads = 0xdf,
1004 DB_PERF_SEL_prezl_src_in_squads_unrolled = 0xe0,
1005 DB_PERF_SEL_prezl_src_in_tile_rate = 0xe1,
1006 DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0xe2,
1007 DB_PERF_SEL_prezl_src_out_stall = 0xe3,
1008 DB_PERF_SEL_postzl_src_in_sends = 0xe4,
1009 DB_PERF_SEL_postzl_src_in_stall = 0xe5,
1010 DB_PERF_SEL_postzl_src_in_squads = 0xe6,
1011 DB_PERF_SEL_postzl_src_in_squads_unrolled = 0xe7,
1012 DB_PERF_SEL_postzl_src_in_tile_rate = 0xe8,
1013 DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0xe9,
1014 DB_PERF_SEL_postzl_src_out_stall = 0xea,
1015 DB_PERF_SEL_esr_ps_src_in_sends = 0xeb,
1016 DB_PERF_SEL_esr_ps_src_in_stall = 0xec,
1017 DB_PERF_SEL_esr_ps_src_in_squads = 0xed,
1018 DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0xee,
1019 DB_PERF_SEL_esr_ps_src_in_tile_rate = 0xef,
1020 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0xf0,
1021 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1,
1022 DB_PERF_SEL_esr_ps_src_out_stall = 0xf2,
1023 DB_PERF_SEL_depth_bounds_qtiles_culled = 0xf3,
1024 DB_PERF_SEL_PreZ_Samples_failing_DB = 0xf4,
1025 DB_PERF_SEL_PostZ_Samples_failing_DB = 0xf5,
1026 DB_PERF_SEL_flush_compressed = 0xf6,
1027 DB_PERF_SEL_flush_plane_le4 = 0xf7,
1028 DB_PERF_SEL_tiles_z_fully_summarized = 0xf8,
1029 DB_PERF_SEL_tiles_stencil_fully_summarized = 0xf9,
1030 DB_PERF_SEL_tiles_z_clear_on_expclear = 0xfa,
1031 DB_PERF_SEL_tiles_s_clear_on_expclear = 0xfb,
1032 DB_PERF_SEL_tiles_decomp_on_expclear = 0xfc,
1033 DB_PERF_SEL_tiles_compressed_to_decompressed = 0xfd,
1034 DB_PERF_SEL_Op_Pipe_Prez_Busy = 0xfe,
1035 DB_PERF_SEL_Op_Pipe_Postz_Busy = 0xff,
1036 DB_PERF_SEL_di_dt_stall = 0x100,
1037} PerfCounter_Vals;
1038typedef enum RingCounterControl {
1039 COUNTER_RING_SPLIT = 0x0,
1040 COUNTER_RING_0 = 0x1,
1041 COUNTER_RING_1 = 0x2,
1042} RingCounterControl;
1043typedef enum PixelPipeCounterId {
1044 PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x0,
1045 PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x1,
1046 PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2,
1047 PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x3,
1048 PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x4,
1049 PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x5,
1050 PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x6,
1051 PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x7,
1052} PixelPipeCounterId;
1053typedef enum PixelPipeStride {
1054 PIXEL_PIPE_STRIDE_32_BITS = 0x0,
1055 PIXEL_PIPE_STRIDE_64_BITS = 0x1,
1056 PIXEL_PIPE_STRIDE_128_BITS = 0x2,
1057 PIXEL_PIPE_STRIDE_256_BITS = 0x3,
1058} PixelPipeStride;
1059typedef enum GB_EDC_DED_MODE {
1060 GB_EDC_DED_MODE_LOG = 0x0,
1061 GB_EDC_DED_MODE_HALT = 0x1,
1062 GB_EDC_DED_MODE_INT_HALT = 0x2,
1063} GB_EDC_DED_MODE;
1064#define GB_TILING_CONFIG_TABLE_SIZE 0x20
1065#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x10
1066typedef enum GRBM_PERF_SEL {
1067 GRBM_PERF_SEL_COUNT = 0x0,
1068 GRBM_PERF_SEL_USER_DEFINED = 0x1,
1069 GRBM_PERF_SEL_GUI_ACTIVE = 0x2,
1070 GRBM_PERF_SEL_CP_BUSY = 0x3,
1071 GRBM_PERF_SEL_CP_COHER_BUSY = 0x4,
1072 GRBM_PERF_SEL_CP_DMA_BUSY = 0x5,
1073 GRBM_PERF_SEL_CB_BUSY = 0x6,
1074 GRBM_PERF_SEL_DB_BUSY = 0x7,
1075 GRBM_PERF_SEL_PA_BUSY = 0x8,
1076 GRBM_PERF_SEL_SC_BUSY = 0x9,
1077 GRBM_PERF_SEL_RESERVED_6 = 0xa,
1078 GRBM_PERF_SEL_SPI_BUSY = 0xb,
1079 GRBM_PERF_SEL_SX_BUSY = 0xc,
1080 GRBM_PERF_SEL_TA_BUSY = 0xd,
1081 GRBM_PERF_SEL_CB_CLEAN = 0xe,
1082 GRBM_PERF_SEL_DB_CLEAN = 0xf,
1083 GRBM_PERF_SEL_RESERVED_5 = 0x10,
1084 GRBM_PERF_SEL_VGT_BUSY = 0x11,
1085 GRBM_PERF_SEL_RESERVED_4 = 0x12,
1086 GRBM_PERF_SEL_RESERVED_3 = 0x13,
1087 GRBM_PERF_SEL_RESERVED_2 = 0x14,
1088 GRBM_PERF_SEL_RESERVED_1 = 0x15,
1089 GRBM_PERF_SEL_RESERVED_0 = 0x16,
1090 GRBM_PERF_SEL_IA_BUSY = 0x17,
1091 GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x18,
1092 GRBM_PERF_SEL_GDS_BUSY = 0x19,
1093 GRBM_PERF_SEL_BCI_BUSY = 0x1a,
1094 GRBM_PERF_SEL_RLC_BUSY = 0x1b,
1095 GRBM_PERF_SEL_TC_BUSY = 0x1c,
1096 GRBM_PERF_SEL_CPG_BUSY = 0x1d,
1097 GRBM_PERF_SEL_CPC_BUSY = 0x1e,
1098 GRBM_PERF_SEL_CPF_BUSY = 0x1f,
1099 GRBM_PERF_SEL_WD_BUSY = 0x20,
1100 GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x21,
1101} GRBM_PERF_SEL;
1102typedef enum GRBM_SE0_PERF_SEL {
1103 GRBM_SE0_PERF_SEL_COUNT = 0x0,
1104 GRBM_SE0_PERF_SEL_USER_DEFINED = 0x1,
1105 GRBM_SE0_PERF_SEL_CB_BUSY = 0x2,
1106 GRBM_SE0_PERF_SEL_DB_BUSY = 0x3,
1107 GRBM_SE0_PERF_SEL_SC_BUSY = 0x4,
1108 GRBM_SE0_PERF_SEL_RESERVED_1 = 0x5,
1109 GRBM_SE0_PERF_SEL_SPI_BUSY = 0x6,
1110 GRBM_SE0_PERF_SEL_SX_BUSY = 0x7,
1111 GRBM_SE0_PERF_SEL_TA_BUSY = 0x8,
1112 GRBM_SE0_PERF_SEL_CB_CLEAN = 0x9,
1113 GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa,
1114 GRBM_SE0_PERF_SEL_RESERVED_0 = 0xb,
1115 GRBM_SE0_PERF_SEL_PA_BUSY = 0xc,
1116 GRBM_SE0_PERF_SEL_VGT_BUSY = 0xd,
1117 GRBM_SE0_PERF_SEL_BCI_BUSY = 0xe,
1118} GRBM_SE0_PERF_SEL;
1119typedef enum GRBM_SE1_PERF_SEL {
1120 GRBM_SE1_PERF_SEL_COUNT = 0x0,
1121 GRBM_SE1_PERF_SEL_USER_DEFINED = 0x1,
1122 GRBM_SE1_PERF_SEL_CB_BUSY = 0x2,
1123 GRBM_SE1_PERF_SEL_DB_BUSY = 0x3,
1124 GRBM_SE1_PERF_SEL_SC_BUSY = 0x4,
1125 GRBM_SE1_PERF_SEL_RESERVED_1 = 0x5,
1126 GRBM_SE1_PERF_SEL_SPI_BUSY = 0x6,
1127 GRBM_SE1_PERF_SEL_SX_BUSY = 0x7,
1128 GRBM_SE1_PERF_SEL_TA_BUSY = 0x8,
1129 GRBM_SE1_PERF_SEL_CB_CLEAN = 0x9,
1130 GRBM_SE1_PERF_SEL_DB_CLEAN = 0xa,
1131 GRBM_SE1_PERF_SEL_RESERVED_0 = 0xb,
1132 GRBM_SE1_PERF_SEL_PA_BUSY = 0xc,
1133 GRBM_SE1_PERF_SEL_VGT_BUSY = 0xd,
1134 GRBM_SE1_PERF_SEL_BCI_BUSY = 0xe,
1135} GRBM_SE1_PERF_SEL;
1136typedef enum GRBM_SE2_PERF_SEL {
1137 GRBM_SE2_PERF_SEL_COUNT = 0x0,
1138 GRBM_SE2_PERF_SEL_USER_DEFINED = 0x1,
1139 GRBM_SE2_PERF_SEL_CB_BUSY = 0x2,
1140 GRBM_SE2_PERF_SEL_DB_BUSY = 0x3,
1141 GRBM_SE2_PERF_SEL_SC_BUSY = 0x4,
1142 GRBM_SE2_PERF_SEL_RESERVED_1 = 0x5,
1143 GRBM_SE2_PERF_SEL_SPI_BUSY = 0x6,
1144 GRBM_SE2_PERF_SEL_SX_BUSY = 0x7,
1145 GRBM_SE2_PERF_SEL_TA_BUSY = 0x8,
1146 GRBM_SE2_PERF_SEL_CB_CLEAN = 0x9,
1147 GRBM_SE2_PERF_SEL_DB_CLEAN = 0xa,
1148 GRBM_SE2_PERF_SEL_RESERVED_0 = 0xb,
1149 GRBM_SE2_PERF_SEL_PA_BUSY = 0xc,
1150 GRBM_SE2_PERF_SEL_VGT_BUSY = 0xd,
1151 GRBM_SE2_PERF_SEL_BCI_BUSY = 0xe,
1152} GRBM_SE2_PERF_SEL;
1153typedef enum GRBM_SE3_PERF_SEL {
1154 GRBM_SE3_PERF_SEL_COUNT = 0x0,
1155 GRBM_SE3_PERF_SEL_USER_DEFINED = 0x1,
1156 GRBM_SE3_PERF_SEL_CB_BUSY = 0x2,
1157 GRBM_SE3_PERF_SEL_DB_BUSY = 0x3,
1158 GRBM_SE3_PERF_SEL_SC_BUSY = 0x4,
1159 GRBM_SE3_PERF_SEL_RESERVED_1 = 0x5,
1160 GRBM_SE3_PERF_SEL_SPI_BUSY = 0x6,
1161 GRBM_SE3_PERF_SEL_SX_BUSY = 0x7,
1162 GRBM_SE3_PERF_SEL_TA_BUSY = 0x8,
1163 GRBM_SE3_PERF_SEL_CB_CLEAN = 0x9,
1164 GRBM_SE3_PERF_SEL_DB_CLEAN = 0xa,
1165 GRBM_SE3_PERF_SEL_RESERVED_0 = 0xb,
1166 GRBM_SE3_PERF_SEL_PA_BUSY = 0xc,
1167 GRBM_SE3_PERF_SEL_VGT_BUSY = 0xd,
1168 GRBM_SE3_PERF_SEL_BCI_BUSY = 0xe,
1169} GRBM_SE3_PERF_SEL;
1170typedef enum SU_PERFCNT_SEL {
1171 PERF_PAPC_PASX_REQ = 0x0,
1172 PERF_PAPC_PASX_DISABLE_PIPE = 0x1,
1173 PERF_PAPC_PASX_FIRST_VECTOR = 0x2,
1174 PERF_PAPC_PASX_SECOND_VECTOR = 0x3,
1175 PERF_PAPC_PASX_FIRST_DEAD = 0x4,
1176 PERF_PAPC_PASX_SECOND_DEAD = 0x5,
1177 PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x6,
1178 PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x7,
1179 PERF_PAPC_PA_INPUT_PRIM = 0x8,
1180 PERF_PAPC_PA_INPUT_NULL_PRIM = 0x9,
1181 PERF_PAPC_PA_INPUT_EVENT_FLAG = 0xa,
1182 PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0xb,
1183 PERF_PAPC_PA_INPUT_END_OF_PACKET = 0xc,
1184 PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0xd,
1185 PERF_PAPC_CLPR_CULL_PRIM = 0xe,
1186 PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0xf,
1187 PERF_PAPC_CLPR_VV_CULL_PRIM = 0x10,
1188 PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x11,
1189 PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x12,
1190 PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x13,
1191 PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x14,
1192 PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x15,
1193 PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x16,
1194 PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x17,
1195 PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x18,
1196 PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x19,
1197 PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x1a,
1198 PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x1b,
1199 PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x1c,
1200 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d,
1201 PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x1e,
1202 PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x1f,
1203 PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x20,
1204 PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x21,
1205 PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x22,
1206 PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x23,
1207 PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x24,
1208 PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x25,
1209 PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x26,
1210 PERF_PAPC_CLSM_NULL_PRIM = 0x27,
1211 PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x28,
1212 PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x29,
1213 PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x2a,
1214 PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x2b,
1215 PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x2c,
1216 PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x2d,
1217 PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x2e,
1218 PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x2f,
1219 PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x30,
1220 PERF_PAPC_SU_INPUT_PRIM = 0x31,
1221 PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x32,
1222 PERF_PAPC_SU_INPUT_NULL_PRIM = 0x33,
1223 PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x34,
1224 PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x35,
1225 PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x36,
1226 PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x37,
1227 PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x38,
1228 PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x39,
1229 PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x3a,
1230 PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x3b,
1231 PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x3c,
1232 PERF_PAPC_SU_OUTPUT_PRIM = 0x3d,
1233 PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x3e,
1234 PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x3f,
1235 PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x40,
1236 PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x41,
1237 PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x42,
1238 PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x43,
1239 PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x44,
1240 PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x45,
1241 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x46,
1242 PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x47,
1243 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x48,
1244 PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x49,
1245 PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x4a,
1246 PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x4b,
1247 PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x4c,
1248 PERF_PAPC_PASX_REQ_IDLE = 0x4d,
1249 PERF_PAPC_PASX_REQ_BUSY = 0x4e,
1250 PERF_PAPC_PASX_REQ_STALLED = 0x4f,
1251 PERF_PAPC_PASX_REC_IDLE = 0x50,
1252 PERF_PAPC_PASX_REC_BUSY = 0x51,
1253 PERF_PAPC_PASX_REC_STARVED_SX = 0x52,
1254 PERF_PAPC_PASX_REC_STALLED = 0x53,
1255 PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x54,
1256 PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x55,
1257 PERF_PAPC_CCGSM_IDLE = 0x56,
1258 PERF_PAPC_CCGSM_BUSY = 0x57,
1259 PERF_PAPC_CCGSM_STALLED = 0x58,
1260 PERF_PAPC_CLPRIM_IDLE = 0x59,
1261 PERF_PAPC_CLPRIM_BUSY = 0x5a,
1262 PERF_PAPC_CLPRIM_STALLED = 0x5b,
1263 PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x5c,
1264 PERF_PAPC_CLIPSM_IDLE = 0x5d,
1265 PERF_PAPC_CLIPSM_BUSY = 0x5e,
1266 PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x5f,
1267 PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x60,
1268 PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x61,
1269 PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x62,
1270 PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x63,
1271 PERF_PAPC_CLIPGA_IDLE = 0x64,
1272 PERF_PAPC_CLIPGA_BUSY = 0x65,
1273 PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x66,
1274 PERF_PAPC_CLIPGA_STALLED = 0x67,
1275 PERF_PAPC_CLIP_IDLE = 0x68,
1276 PERF_PAPC_CLIP_BUSY = 0x69,
1277 PERF_PAPC_SU_IDLE = 0x6a,
1278 PERF_PAPC_SU_BUSY = 0x6b,
1279 PERF_PAPC_SU_STARVED_CLIP = 0x6c,
1280 PERF_PAPC_SU_STALLED_SC = 0x6d,
1281 PERF_PAPC_CL_DYN_SCLK_VLD = 0x6e,
1282 PERF_PAPC_SU_DYN_SCLK_VLD = 0x6f,
1283 PERF_PAPC_PA_REG_SCLK_VLD = 0x70,
1284 PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x71,
1285 PERF_PAPC_PASX_SE0_REQ = 0x72,
1286 PERF_PAPC_PASX_SE1_REQ = 0x73,
1287 PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x74,
1288 PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x75,
1289 PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x76,
1290 PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x77,
1291 PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x78,
1292 PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x79,
1293 PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x7a,
1294 PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x7b,
1295 PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x7c,
1296 PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x7d,
1297 PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x7e,
1298 PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x7f,
1299 PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x80,
1300 PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x81,
1301 PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x82,
1302 PERF_PAPC_SU_SE0_STALLED_SC = 0x83,
1303 PERF_PAPC_SU_SE1_STALLED_SC = 0x84,
1304 PERF_PAPC_SU_SE01_STALLED_SC = 0x85,
1305 PERF_PAPC_CLSM_CLIPPING_PRIM = 0x86,
1306 PERF_PAPC_SU_CULLED_PRIM = 0x87,
1307 PERF_PAPC_SU_OUTPUT_EOPG = 0x88,
1308 PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x89,
1309 PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x8a,
1310 PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x8b,
1311 PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x8c,
1312 PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x8d,
1313 PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x8e,
1314 PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x8f,
1315 PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x90,
1316 PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x91,
1317 PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x92,
1318 PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x93,
1319 PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x94,
1320 PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x95,
1321 PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x96,
1322 PERF_PAPC_SU_SE2_STALLED_SC = 0x97,
1323 PERF_PAPC_SU_SE3_STALLED_SC = 0x98,
1324} SU_PERFCNT_SEL;
1325typedef enum SC_PERFCNT_SEL {
1326 SC_SRPS_WINDOW_VALID = 0x0,
1327 SC_PSSW_WINDOW_VALID = 0x1,
1328 SC_TPQZ_WINDOW_VALID = 0x2,
1329 SC_QZQP_WINDOW_VALID = 0x3,
1330 SC_TRPK_WINDOW_VALID = 0x4,
1331 SC_SRPS_WINDOW_VALID_BUSY = 0x5,
1332 SC_PSSW_WINDOW_VALID_BUSY = 0x6,
1333 SC_TPQZ_WINDOW_VALID_BUSY = 0x7,
1334 SC_QZQP_WINDOW_VALID_BUSY = 0x8,
1335 SC_TRPK_WINDOW_VALID_BUSY = 0x9,
1336 SC_STARVED_BY_PA = 0xa,
1337 SC_STALLED_BY_PRIMFIFO = 0xb,
1338 SC_STALLED_BY_DB_TILE = 0xc,
1339 SC_STARVED_BY_DB_TILE = 0xd,
1340 SC_STALLED_BY_TILEORDERFIFO = 0xe,
1341 SC_STALLED_BY_TILEFIFO = 0xf,
1342 SC_STALLED_BY_DB_QUAD = 0x10,
1343 SC_STARVED_BY_DB_QUAD = 0x11,
1344 SC_STALLED_BY_QUADFIFO = 0x12,
1345 SC_STALLED_BY_BCI = 0x13,
1346 SC_STALLED_BY_SPI = 0x14,
1347 SC_SCISSOR_DISCARD = 0x15,
1348 SC_BB_DISCARD = 0x16,
1349 SC_SUPERTILE_COUNT = 0x17,
1350 SC_SUPERTILE_PER_PRIM_H0 = 0x18,
1351 SC_SUPERTILE_PER_PRIM_H1 = 0x19,
1352 SC_SUPERTILE_PER_PRIM_H2 = 0x1a,
1353 SC_SUPERTILE_PER_PRIM_H3 = 0x1b,
1354 SC_SUPERTILE_PER_PRIM_H4 = 0x1c,
1355 SC_SUPERTILE_PER_PRIM_H5 = 0x1d,
1356 SC_SUPERTILE_PER_PRIM_H6 = 0x1e,
1357 SC_SUPERTILE_PER_PRIM_H7 = 0x1f,
1358 SC_SUPERTILE_PER_PRIM_H8 = 0x20,
1359 SC_SUPERTILE_PER_PRIM_H9 = 0x21,
1360 SC_SUPERTILE_PER_PRIM_H10 = 0x22,
1361 SC_SUPERTILE_PER_PRIM_H11 = 0x23,
1362 SC_SUPERTILE_PER_PRIM_H12 = 0x24,
1363 SC_SUPERTILE_PER_PRIM_H13 = 0x25,
1364 SC_SUPERTILE_PER_PRIM_H14 = 0x26,
1365 SC_SUPERTILE_PER_PRIM_H15 = 0x27,
1366 SC_SUPERTILE_PER_PRIM_H16 = 0x28,
1367 SC_TILE_PER_PRIM_H0 = 0x29,
1368 SC_TILE_PER_PRIM_H1 = 0x2a,
1369 SC_TILE_PER_PRIM_H2 = 0x2b,
1370 SC_TILE_PER_PRIM_H3 = 0x2c,
1371 SC_TILE_PER_PRIM_H4 = 0x2d,
1372 SC_TILE_PER_PRIM_H5 = 0x2e,
1373 SC_TILE_PER_PRIM_H6 = 0x2f,
1374 SC_TILE_PER_PRIM_H7 = 0x30,
1375 SC_TILE_PER_PRIM_H8 = 0x31,
1376 SC_TILE_PER_PRIM_H9 = 0x32,
1377 SC_TILE_PER_PRIM_H10 = 0x33,
1378 SC_TILE_PER_PRIM_H11 = 0x34,
1379 SC_TILE_PER_PRIM_H12 = 0x35,
1380 SC_TILE_PER_PRIM_H13 = 0x36,
1381 SC_TILE_PER_PRIM_H14 = 0x37,
1382 SC_TILE_PER_PRIM_H15 = 0x38,
1383 SC_TILE_PER_PRIM_H16 = 0x39,
1384 SC_TILE_PER_SUPERTILE_H0 = 0x3a,
1385 SC_TILE_PER_SUPERTILE_H1 = 0x3b,
1386 SC_TILE_PER_SUPERTILE_H2 = 0x3c,
1387 SC_TILE_PER_SUPERTILE_H3 = 0x3d,
1388 SC_TILE_PER_SUPERTILE_H4 = 0x3e,
1389 SC_TILE_PER_SUPERTILE_H5 = 0x3f,
1390 SC_TILE_PER_SUPERTILE_H6 = 0x40,
1391 SC_TILE_PER_SUPERTILE_H7 = 0x41,
1392 SC_TILE_PER_SUPERTILE_H8 = 0x42,
1393 SC_TILE_PER_SUPERTILE_H9 = 0x43,
1394 SC_TILE_PER_SUPERTILE_H10 = 0x44,
1395 SC_TILE_PER_SUPERTILE_H11 = 0x45,
1396 SC_TILE_PER_SUPERTILE_H12 = 0x46,
1397 SC_TILE_PER_SUPERTILE_H13 = 0x47,
1398 SC_TILE_PER_SUPERTILE_H14 = 0x48,
1399 SC_TILE_PER_SUPERTILE_H15 = 0x49,
1400 SC_TILE_PER_SUPERTILE_H16 = 0x4a,
1401 SC_TILE_PICKED_H1 = 0x4b,
1402 SC_TILE_PICKED_H2 = 0x4c,
1403 SC_TILE_PICKED_H3 = 0x4d,
1404 SC_TILE_PICKED_H4 = 0x4e,
1405 SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x4f,
1406 SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x50,
1407 SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x51,
1408 SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x52,
1409 SC_QZ0_TILE_COUNT = 0x53,
1410 SC_QZ1_TILE_COUNT = 0x54,
1411 SC_QZ2_TILE_COUNT = 0x55,
1412 SC_QZ3_TILE_COUNT = 0x56,
1413 SC_QZ0_TILE_COVERED_COUNT = 0x57,
1414 SC_QZ1_TILE_COVERED_COUNT = 0x58,
1415 SC_QZ2_TILE_COVERED_COUNT = 0x59,
1416 SC_QZ3_TILE_COVERED_COUNT = 0x5a,
1417 SC_QZ0_TILE_NOT_COVERED_COUNT = 0x5b,
1418 SC_QZ1_TILE_NOT_COVERED_COUNT = 0x5c,
1419 SC_QZ2_TILE_NOT_COVERED_COUNT = 0x5d,
1420 SC_QZ3_TILE_NOT_COVERED_COUNT = 0x5e,
1421 SC_QZ0_QUAD_PER_TILE_H0 = 0x5f,
1422 SC_QZ0_QUAD_PER_TILE_H1 = 0x60,
1423 SC_QZ0_QUAD_PER_TILE_H2 = 0x61,
1424 SC_QZ0_QUAD_PER_TILE_H3 = 0x62,
1425 SC_QZ0_QUAD_PER_TILE_H4 = 0x63,
1426 SC_QZ0_QUAD_PER_TILE_H5 = 0x64,
1427 SC_QZ0_QUAD_PER_TILE_H6 = 0x65,
1428 SC_QZ0_QUAD_PER_TILE_H7 = 0x66,
1429 SC_QZ0_QUAD_PER_TILE_H8 = 0x67,
1430 SC_QZ0_QUAD_PER_TILE_H9 = 0x68,
1431 SC_QZ0_QUAD_PER_TILE_H10 = 0x69,
1432 SC_QZ0_QUAD_PER_TILE_H11 = 0x6a,
1433 SC_QZ0_QUAD_PER_TILE_H12 = 0x6b,
1434 SC_QZ0_QUAD_PER_TILE_H13 = 0x6c,
1435 SC_QZ0_QUAD_PER_TILE_H14 = 0x6d,
1436 SC_QZ0_QUAD_PER_TILE_H15 = 0x6e,
1437 SC_QZ0_QUAD_PER_TILE_H16 = 0x6f,
1438 SC_QZ1_QUAD_PER_TILE_H0 = 0x70,
1439 SC_QZ1_QUAD_PER_TILE_H1 = 0x71,
1440 SC_QZ1_QUAD_PER_TILE_H2 = 0x72,
1441 SC_QZ1_QUAD_PER_TILE_H3 = 0x73,
1442 SC_QZ1_QUAD_PER_TILE_H4 = 0x74,
1443 SC_QZ1_QUAD_PER_TILE_H5 = 0x75,
1444 SC_QZ1_QUAD_PER_TILE_H6 = 0x76,
1445 SC_QZ1_QUAD_PER_TILE_H7 = 0x77,
1446 SC_QZ1_QUAD_PER_TILE_H8 = 0x78,
1447 SC_QZ1_QUAD_PER_TILE_H9 = 0x79,
1448 SC_QZ1_QUAD_PER_TILE_H10 = 0x7a,
1449 SC_QZ1_QUAD_PER_TILE_H11 = 0x7b,
1450 SC_QZ1_QUAD_PER_TILE_H12 = 0x7c,
1451 SC_QZ1_QUAD_PER_TILE_H13 = 0x7d,
1452 SC_QZ1_QUAD_PER_TILE_H14 = 0x7e,
1453 SC_QZ1_QUAD_PER_TILE_H15 = 0x7f,
1454 SC_QZ1_QUAD_PER_TILE_H16 = 0x80,
1455 SC_QZ2_QUAD_PER_TILE_H0 = 0x81,
1456 SC_QZ2_QUAD_PER_TILE_H1 = 0x82,
1457 SC_QZ2_QUAD_PER_TILE_H2 = 0x83,
1458 SC_QZ2_QUAD_PER_TILE_H3 = 0x84,
1459 SC_QZ2_QUAD_PER_TILE_H4 = 0x85,
1460 SC_QZ2_QUAD_PER_TILE_H5 = 0x86,
1461 SC_QZ2_QUAD_PER_TILE_H6 = 0x87,
1462 SC_QZ2_QUAD_PER_TILE_H7 = 0x88,
1463 SC_QZ2_QUAD_PER_TILE_H8 = 0x89,
1464 SC_QZ2_QUAD_PER_TILE_H9 = 0x8a,
1465 SC_QZ2_QUAD_PER_TILE_H10 = 0x8b,
1466 SC_QZ2_QUAD_PER_TILE_H11 = 0x8c,
1467 SC_QZ2_QUAD_PER_TILE_H12 = 0x8d,
1468 SC_QZ2_QUAD_PER_TILE_H13 = 0x8e,
1469 SC_QZ2_QUAD_PER_TILE_H14 = 0x8f,
1470 SC_QZ2_QUAD_PER_TILE_H15 = 0x90,
1471 SC_QZ2_QUAD_PER_TILE_H16 = 0x91,
1472 SC_QZ3_QUAD_PER_TILE_H0 = 0x92,
1473 SC_QZ3_QUAD_PER_TILE_H1 = 0x93,
1474 SC_QZ3_QUAD_PER_TILE_H2 = 0x94,
1475 SC_QZ3_QUAD_PER_TILE_H3 = 0x95,
1476 SC_QZ3_QUAD_PER_TILE_H4 = 0x96,
1477 SC_QZ3_QUAD_PER_TILE_H5 = 0x97,
1478 SC_QZ3_QUAD_PER_TILE_H6 = 0x98,
1479 SC_QZ3_QUAD_PER_TILE_H7 = 0x99,
1480 SC_QZ3_QUAD_PER_TILE_H8 = 0x9a,
1481 SC_QZ3_QUAD_PER_TILE_H9 = 0x9b,
1482 SC_QZ3_QUAD_PER_TILE_H10 = 0x9c,
1483 SC_QZ3_QUAD_PER_TILE_H11 = 0x9d,
1484 SC_QZ3_QUAD_PER_TILE_H12 = 0x9e,
1485 SC_QZ3_QUAD_PER_TILE_H13 = 0x9f,
1486 SC_QZ3_QUAD_PER_TILE_H14 = 0xa0,
1487 SC_QZ3_QUAD_PER_TILE_H15 = 0xa1,
1488 SC_QZ3_QUAD_PER_TILE_H16 = 0xa2,
1489 SC_QZ0_QUAD_COUNT = 0xa3,
1490 SC_QZ1_QUAD_COUNT = 0xa4,
1491 SC_QZ2_QUAD_COUNT = 0xa5,
1492 SC_QZ3_QUAD_COUNT = 0xa6,
1493 SC_P0_HIZ_TILE_COUNT = 0xa7,
1494 SC_P1_HIZ_TILE_COUNT = 0xa8,
1495 SC_P2_HIZ_TILE_COUNT = 0xa9,
1496 SC_P3_HIZ_TILE_COUNT = 0xaa,
1497 SC_P0_HIZ_QUAD_PER_TILE_H0 = 0xab,
1498 SC_P0_HIZ_QUAD_PER_TILE_H1 = 0xac,
1499 SC_P0_HIZ_QUAD_PER_TILE_H2 = 0xad,
1500 SC_P0_HIZ_QUAD_PER_TILE_H3 = 0xae,
1501 SC_P0_HIZ_QUAD_PER_TILE_H4 = 0xaf,
1502 SC_P0_HIZ_QUAD_PER_TILE_H5 = 0xb0,
1503 SC_P0_HIZ_QUAD_PER_TILE_H6 = 0xb1,
1504 SC_P0_HIZ_QUAD_PER_TILE_H7 = 0xb2,
1505 SC_P0_HIZ_QUAD_PER_TILE_H8 = 0xb3,
1506 SC_P0_HIZ_QUAD_PER_TILE_H9 = 0xb4,
1507 SC_P0_HIZ_QUAD_PER_TILE_H10 = 0xb5,
1508 SC_P0_HIZ_QUAD_PER_TILE_H11 = 0xb6,
1509 SC_P0_HIZ_QUAD_PER_TILE_H12 = 0xb7,
1510 SC_P0_HIZ_QUAD_PER_TILE_H13 = 0xb8,
1511 SC_P0_HIZ_QUAD_PER_TILE_H14 = 0xb9,
1512 SC_P0_HIZ_QUAD_PER_TILE_H15 = 0xba,
1513 SC_P0_HIZ_QUAD_PER_TILE_H16 = 0xbb,
1514 SC_P1_HIZ_QUAD_PER_TILE_H0 = 0xbc,
1515 SC_P1_HIZ_QUAD_PER_TILE_H1 = 0xbd,
1516 SC_P1_HIZ_QUAD_PER_TILE_H2 = 0xbe,
1517 SC_P1_HIZ_QUAD_PER_TILE_H3 = 0xbf,
1518 SC_P1_HIZ_QUAD_PER_TILE_H4 = 0xc0,
1519 SC_P1_HIZ_QUAD_PER_TILE_H5 = 0xc1,
1520 SC_P1_HIZ_QUAD_PER_TILE_H6 = 0xc2,
1521 SC_P1_HIZ_QUAD_PER_TILE_H7 = 0xc3,
1522 SC_P1_HIZ_QUAD_PER_TILE_H8 = 0xc4,
1523 SC_P1_HIZ_QUAD_PER_TILE_H9 = 0xc5,
1524 SC_P1_HIZ_QUAD_PER_TILE_H10 = 0xc6,
1525 SC_P1_HIZ_QUAD_PER_TILE_H11 = 0xc7,
1526 SC_P1_HIZ_QUAD_PER_TILE_H12 = 0xc8,
1527 SC_P1_HIZ_QUAD_PER_TILE_H13 = 0xc9,
1528 SC_P1_HIZ_QUAD_PER_TILE_H14 = 0xca,
1529 SC_P1_HIZ_QUAD_PER_TILE_H15 = 0xcb,
1530 SC_P1_HIZ_QUAD_PER_TILE_H16 = 0xcc,
1531 SC_P2_HIZ_QUAD_PER_TILE_H0 = 0xcd,
1532 SC_P2_HIZ_QUAD_PER_TILE_H1 = 0xce,
1533 SC_P2_HIZ_QUAD_PER_TILE_H2 = 0xcf,
1534 SC_P2_HIZ_QUAD_PER_TILE_H3 = 0xd0,
1535 SC_P2_HIZ_QUAD_PER_TILE_H4 = 0xd1,
1536 SC_P2_HIZ_QUAD_PER_TILE_H5 = 0xd2,
1537 SC_P2_HIZ_QUAD_PER_TILE_H6 = 0xd3,
1538 SC_P2_HIZ_QUAD_PER_TILE_H7 = 0xd4,
1539 SC_P2_HIZ_QUAD_PER_TILE_H8 = 0xd5,
1540 SC_P2_HIZ_QUAD_PER_TILE_H9 = 0xd6,
1541 SC_P2_HIZ_QUAD_PER_TILE_H10 = 0xd7,
1542 SC_P2_HIZ_QUAD_PER_TILE_H11 = 0xd8,
1543 SC_P2_HIZ_QUAD_PER_TILE_H12 = 0xd9,
1544 SC_P2_HIZ_QUAD_PER_TILE_H13 = 0xda,
1545 SC_P2_HIZ_QUAD_PER_TILE_H14 = 0xdb,
1546 SC_P2_HIZ_QUAD_PER_TILE_H15 = 0xdc,
1547 SC_P2_HIZ_QUAD_PER_TILE_H16 = 0xdd,
1548 SC_P3_HIZ_QUAD_PER_TILE_H0 = 0xde,
1549 SC_P3_HIZ_QUAD_PER_TILE_H1 = 0xdf,
1550 SC_P3_HIZ_QUAD_PER_TILE_H2 = 0xe0,
1551 SC_P3_HIZ_QUAD_PER_TILE_H3 = 0xe1,
1552 SC_P3_HIZ_QUAD_PER_TILE_H4 = 0xe2,
1553 SC_P3_HIZ_QUAD_PER_TILE_H5 = 0xe3,
1554 SC_P3_HIZ_QUAD_PER_TILE_H6 = 0xe4,
1555 SC_P3_HIZ_QUAD_PER_TILE_H7 = 0xe5,
1556 SC_P3_HIZ_QUAD_PER_TILE_H8 = 0xe6,
1557 SC_P3_HIZ_QUAD_PER_TILE_H9 = 0xe7,
1558 SC_P3_HIZ_QUAD_PER_TILE_H10 = 0xe8,
1559 SC_P3_HIZ_QUAD_PER_TILE_H11 = 0xe9,
1560 SC_P3_HIZ_QUAD_PER_TILE_H12 = 0xea,
1561 SC_P3_HIZ_QUAD_PER_TILE_H13 = 0xeb,
1562 SC_P3_HIZ_QUAD_PER_TILE_H14 = 0xec,
1563 SC_P3_HIZ_QUAD_PER_TILE_H15 = 0xed,
1564 SC_P3_HIZ_QUAD_PER_TILE_H16 = 0xee,
1565 SC_P0_HIZ_QUAD_COUNT = 0xef,
1566 SC_P1_HIZ_QUAD_COUNT = 0xf0,
1567 SC_P2_HIZ_QUAD_COUNT = 0xf1,
1568 SC_P3_HIZ_QUAD_COUNT = 0xf2,
1569 SC_P0_DETAIL_QUAD_COUNT = 0xf3,
1570 SC_P1_DETAIL_QUAD_COUNT = 0xf4,
1571 SC_P2_DETAIL_QUAD_COUNT = 0xf5,
1572 SC_P3_DETAIL_QUAD_COUNT = 0xf6,
1573 SC_P0_DETAIL_QUAD_WITH_1_PIX = 0xf7,
1574 SC_P0_DETAIL_QUAD_WITH_2_PIX = 0xf8,
1575 SC_P0_DETAIL_QUAD_WITH_3_PIX = 0xf9,
1576 SC_P0_DETAIL_QUAD_WITH_4_PIX = 0xfa,
1577 SC_P1_DETAIL_QUAD_WITH_1_PIX = 0xfb,
1578 SC_P1_DETAIL_QUAD_WITH_2_PIX = 0xfc,
1579 SC_P1_DETAIL_QUAD_WITH_3_PIX = 0xfd,
1580 SC_P1_DETAIL_QUAD_WITH_4_PIX = 0xfe,
1581 SC_P2_DETAIL_QUAD_WITH_1_PIX = 0xff,
1582 SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x100,
1583 SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x101,
1584 SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x102,
1585 SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x103,
1586 SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x104,
1587 SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105,
1588 SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x106,
1589 SC_EARLYZ_QUAD_COUNT = 0x107,
1590 SC_EARLYZ_QUAD_WITH_1_PIX = 0x108,
1591 SC_EARLYZ_QUAD_WITH_2_PIX = 0x109,
1592 SC_EARLYZ_QUAD_WITH_3_PIX = 0x10a,
1593 SC_EARLYZ_QUAD_WITH_4_PIX = 0x10b,
1594 SC_PKR_QUAD_PER_ROW_H1 = 0x10c,
1595 SC_PKR_QUAD_PER_ROW_H2 = 0x10d,
1596 SC_PKR_QUAD_PER_ROW_H3 = 0x10e,
1597 SC_PKR_QUAD_PER_ROW_H4 = 0x10f,
1598 SC_PKR_END_OF_VECTOR = 0x110,
1599 SC_PKR_CONTROL_XFER = 0x111,
1600 SC_PKR_DBHANG_FORCE_EOV = 0x112,
1601 SC_REG_SCLK_BUSY = 0x113,
1602 SC_GRP0_DYN_SCLK_BUSY = 0x114,
1603 SC_GRP1_DYN_SCLK_BUSY = 0x115,
1604 SC_GRP2_DYN_SCLK_BUSY = 0x116,
1605 SC_GRP3_DYN_SCLK_BUSY = 0x117,
1606 SC_GRP4_DYN_SCLK_BUSY = 0x118,
1607 SC_PA0_SC_DATA_FIFO_RD = 0x119,
1608 SC_PA0_SC_DATA_FIFO_WE = 0x11a,
1609 SC_PA1_SC_DATA_FIFO_RD = 0x11b,
1610 SC_PA1_SC_DATA_FIFO_WE = 0x11c,
1611 SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x11d,
1612 SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x11e,
1613 SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x11f,
1614 SC_PS_ARB_STALLED_FROM_BELOW = 0x120,
1615 SC_PS_ARB_STARVED_FROM_ABOVE = 0x121,
1616 SC_PS_ARB_SC_BUSY = 0x122,
1617 SC_PS_ARB_PA_SC_BUSY = 0x123,
1618 SC_PA2_SC_DATA_FIFO_RD = 0x124,
1619 SC_PA2_SC_DATA_FIFO_WE = 0x125,
1620 SC_PA3_SC_DATA_FIFO_RD = 0x126,
1621 SC_PA3_SC_DATA_FIFO_WE = 0x127,
1622 SC_PA_SC_DEALLOC_0_0_WE = 0x128,
1623 SC_PA_SC_DEALLOC_0_1_WE = 0x129,
1624 SC_PA_SC_DEALLOC_1_0_WE = 0x12a,
1625 SC_PA_SC_DEALLOC_1_1_WE = 0x12b,
1626 SC_PA_SC_DEALLOC_2_0_WE = 0x12c,
1627 SC_PA_SC_DEALLOC_2_1_WE = 0x12d,
1628 SC_PA_SC_DEALLOC_3_0_WE = 0x12e,
1629 SC_PA_SC_DEALLOC_3_1_WE = 0x12f,
1630 SC_PA0_SC_EOP_WE = 0x130,
1631 SC_PA0_SC_EOPG_WE = 0x131,
1632 SC_PA0_SC_EVENT_WE = 0x132,
1633 SC_PA1_SC_EOP_WE = 0x133,
1634 SC_PA1_SC_EOPG_WE = 0x134,
1635 SC_PA1_SC_EVENT_WE = 0x135,
1636 SC_PA2_SC_EOP_WE = 0x136,
1637 SC_PA2_SC_EOPG_WE = 0x137,
1638 SC_PA2_SC_EVENT_WE = 0x138,
1639 SC_PA3_SC_EOP_WE = 0x139,
1640 SC_PA3_SC_EOPG_WE = 0x13a,
1641 SC_PA3_SC_EVENT_WE = 0x13b,
1642 SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x13c,
1643 SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x13d,
1644 SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x13e,
1645 SC_PS_ARB_EOP_POP_SYNC_POP = 0x13f,
1646 SC_PS_ARB_EVENT_SYNC_POP = 0x140,
1647 SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141,
1648 SC_PA0_SC_FPOV_WE = 0x142,
1649 SC_PA1_SC_FPOV_WE = 0x143,
1650 SC_PA2_SC_FPOV_WE = 0x144,
1651 SC_PA3_SC_FPOV_WE = 0x145,
1652 SC_PA0_SC_LPOV_WE = 0x146,
1653 SC_PA1_SC_LPOV_WE = 0x147,
1654 SC_PA2_SC_LPOV_WE = 0x148,
1655 SC_PA3_SC_LPOV_WE = 0x149,
1656 SC_SC_SPI_DEALLOC_0_0 = 0x14a,
1657 SC_SC_SPI_DEALLOC_0_1 = 0x14b,
1658 SC_SC_SPI_DEALLOC_0_2 = 0x14c,
1659 SC_SC_SPI_DEALLOC_1_0 = 0x14d,
1660 SC_SC_SPI_DEALLOC_1_1 = 0x14e,
1661 SC_SC_SPI_DEALLOC_1_2 = 0x14f,
1662 SC_SC_SPI_DEALLOC_2_0 = 0x150,
1663 SC_SC_SPI_DEALLOC_2_1 = 0x151,
1664 SC_SC_SPI_DEALLOC_2_2 = 0x152,
1665 SC_SC_SPI_DEALLOC_3_0 = 0x153,
1666 SC_SC_SPI_DEALLOC_3_1 = 0x154,
1667 SC_SC_SPI_DEALLOC_3_2 = 0x155,
1668 SC_SC_SPI_FPOV_0 = 0x156,
1669 SC_SC_SPI_FPOV_1 = 0x157,
1670 SC_SC_SPI_FPOV_2 = 0x158,
1671 SC_SC_SPI_FPOV_3 = 0x159,
1672 SC_SC_SPI_EVENT = 0x15a,
1673 SC_PS_TS_EVENT_FIFO_PUSH = 0x15b,
1674 SC_PS_TS_EVENT_FIFO_POP = 0x15c,
1675 SC_PS_CTX_DONE_FIFO_PUSH = 0x15d,
1676 SC_PS_CTX_DONE_FIFO_POP = 0x15e,
1677 SC_MULTICYCLE_BUBBLE_FREEZE = 0x15f,
1678 SC_EOP_SYNC_WINDOW = 0x160,
1679 SC_PA0_SC_NULL_WE = 0x161,
1680 SC_PA0_SC_NULL_DEALLOC_WE = 0x162,
1681 SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x163,
1682 SC_PA0_SC_DATA_FIFO_EOP_RD = 0x164,
1683 SC_PA0_SC_DEALLOC_0_RD = 0x165,
1684 SC_PA0_SC_DEALLOC_1_RD = 0x166,
1685 SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x167,
1686 SC_PA1_SC_DATA_FIFO_EOP_RD = 0x168,
1687 SC_PA1_SC_DEALLOC_0_RD = 0x169,
1688 SC_PA1_SC_DEALLOC_1_RD = 0x16a,
1689 SC_PA1_SC_NULL_WE = 0x16b,
1690 SC_PA1_SC_NULL_DEALLOC_WE = 0x16c,
1691 SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x16d,
1692 SC_PA2_SC_DATA_FIFO_EOP_RD = 0x16e,
1693 SC_PA2_SC_DEALLOC_0_RD = 0x16f,
1694 SC_PA2_SC_DEALLOC_1_RD = 0x170,
1695 SC_PA2_SC_NULL_WE = 0x171,
1696 SC_PA2_SC_NULL_DEALLOC_WE = 0x172,
1697 SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x173,
1698 SC_PA3_SC_DATA_FIFO_EOP_RD = 0x174,
1699 SC_PA3_SC_DEALLOC_0_RD = 0x175,
1700 SC_PA3_SC_DEALLOC_1_RD = 0x176,
1701 SC_PA3_SC_NULL_WE = 0x177,
1702 SC_PA3_SC_NULL_DEALLOC_WE = 0x178,
1703 SC_PS_PA0_SC_FIFO_EMPTY = 0x179,
1704 SC_PS_PA0_SC_FIFO_FULL = 0x17a,
1705 SC_PA0_PS_DATA_SEND = 0x17b,
1706 SC_PS_PA1_SC_FIFO_EMPTY = 0x17c,
1707 SC_PS_PA1_SC_FIFO_FULL = 0x17d,
1708 SC_PA1_PS_DATA_SEND = 0x17e,
1709 SC_PS_PA2_SC_FIFO_EMPTY = 0x17f,
1710 SC_PS_PA2_SC_FIFO_FULL = 0x180,
1711 SC_PA2_PS_DATA_SEND = 0x181,
1712 SC_PS_PA3_SC_FIFO_EMPTY = 0x182,
1713 SC_PS_PA3_SC_FIFO_FULL = 0x183,
1714 SC_PA3_PS_DATA_SEND = 0x184,
1715 SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x185,
1716 SC_BUSY_CNT_NOT_ZERO = 0x186,
1717 SC_BM_BUSY = 0x187,
1718 SC_BACKEND_BUSY = 0x188,
1719 SC_SCF_SCB_INTERFACE_BUSY = 0x189,
1720 SC_SCB_BUSY = 0x18a,
1721 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x18b,
1722 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x18c,
1723} SC_PERFCNT_SEL;
1724typedef enum SePairXsel {
1725 RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x0,
1726 RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x1,
1727 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2,
1728 RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x3,
1729} SePairXsel;
1730typedef enum SePairYsel {
1731 RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x0,
1732 RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x1,
1733 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2,
1734 RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x3,
1735} SePairYsel;
1736typedef enum SePairMap {
1737 RASTER_CONFIG_SE_PAIR_MAP_0 = 0x0,
1738 RASTER_CONFIG_SE_PAIR_MAP_1 = 0x1,
1739 RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2,
1740 RASTER_CONFIG_SE_PAIR_MAP_3 = 0x3,
1741} SePairMap;
1742typedef enum SeXsel {
1743 RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x0,
1744 RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x1,
1745 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2,
1746 RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x3,
1747} SeXsel;
1748typedef enum SeYsel {
1749 RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x0,
1750 RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x1,
1751 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2,
1752 RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x3,
1753} SeYsel;
1754typedef enum SeMap {
1755 RASTER_CONFIG_SE_MAP_0 = 0x0,
1756 RASTER_CONFIG_SE_MAP_1 = 0x1,
1757 RASTER_CONFIG_SE_MAP_2 = 0x2,
1758 RASTER_CONFIG_SE_MAP_3 = 0x3,
1759} SeMap;
1760typedef enum ScXsel {
1761 RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x0,
1762 RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x1,
1763 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2,
1764 RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x3,
1765} ScXsel;
1766typedef enum ScYsel {
1767 RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x0,
1768 RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x1,
1769 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2,
1770 RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x3,
1771} ScYsel;
1772typedef enum ScMap {
1773 RASTER_CONFIG_SC_MAP_0 = 0x0,
1774 RASTER_CONFIG_SC_MAP_1 = 0x1,
1775 RASTER_CONFIG_SC_MAP_2 = 0x2,
1776 RASTER_CONFIG_SC_MAP_3 = 0x3,
1777} ScMap;
1778typedef enum PkrXsel2 {
1779 RASTER_CONFIG_PKR_XSEL2_0 = 0x0,
1780 RASTER_CONFIG_PKR_XSEL2_1 = 0x1,
1781 RASTER_CONFIG_PKR_XSEL2_2 = 0x2,
1782 RASTER_CONFIG_PKR_XSEL2_3 = 0x3,
1783} PkrXsel2;
1784typedef enum PkrXsel {
1785 RASTER_CONFIG_PKR_XSEL_0 = 0x0,
1786 RASTER_CONFIG_PKR_XSEL_1 = 0x1,
1787 RASTER_CONFIG_PKR_XSEL_2 = 0x2,
1788 RASTER_CONFIG_PKR_XSEL_3 = 0x3,
1789} PkrXsel;
1790typedef enum PkrYsel {
1791 RASTER_CONFIG_PKR_YSEL_0 = 0x0,
1792 RASTER_CONFIG_PKR_YSEL_1 = 0x1,
1793 RASTER_CONFIG_PKR_YSEL_2 = 0x2,
1794 RASTER_CONFIG_PKR_YSEL_3 = 0x3,
1795} PkrYsel;
1796typedef enum PkrMap {
1797 RASTER_CONFIG_PKR_MAP_0 = 0x0,
1798 RASTER_CONFIG_PKR_MAP_1 = 0x1,
1799 RASTER_CONFIG_PKR_MAP_2 = 0x2,
1800 RASTER_CONFIG_PKR_MAP_3 = 0x3,
1801} PkrMap;
1802typedef enum RbXsel {
1803 RASTER_CONFIG_RB_XSEL_0 = 0x0,
1804 RASTER_CONFIG_RB_XSEL_1 = 0x1,
1805} RbXsel;
1806typedef enum RbYsel {
1807 RASTER_CONFIG_RB_YSEL_0 = 0x0,
1808 RASTER_CONFIG_RB_YSEL_1 = 0x1,
1809} RbYsel;
1810typedef enum RbXsel2 {
1811 RASTER_CONFIG_RB_XSEL2_0 = 0x0,
1812 RASTER_CONFIG_RB_XSEL2_1 = 0x1,
1813 RASTER_CONFIG_RB_XSEL2_2 = 0x2,
1814 RASTER_CONFIG_RB_XSEL2_3 = 0x3,
1815} RbXsel2;
1816typedef enum RbMap {
1817 RASTER_CONFIG_RB_MAP_0 = 0x0,
1818 RASTER_CONFIG_RB_MAP_1 = 0x1,
1819 RASTER_CONFIG_RB_MAP_2 = 0x2,
1820 RASTER_CONFIG_RB_MAP_3 = 0x3,
1821} RbMap;
1822typedef enum CSDATA_TYPE {
1823 CSDATA_TYPE_TG = 0x0,
1824 CSDATA_TYPE_STATE = 0x1,
1825 CSDATA_TYPE_EVENT = 0x2,
1826 CSDATA_TYPE_PRIVATE = 0x3,
1827} CSDATA_TYPE;
1828#define CSDATA_TYPE_WIDTH 0x2
1829#define CSDATA_ADDR_WIDTH 0x7
1830#define CSDATA_DATA_WIDTH 0x20
1831typedef enum SPI_SAMPLE_CNTL {
1832 CENTROIDS_ONLY = 0x0,
1833 CENTERS_ONLY = 0x1,
1834 CENTROIDS_AND_CENTERS = 0x2,
1835 UNDEF = 0x3,
1836} SPI_SAMPLE_CNTL;
1837typedef enum SPI_FOG_MODE {
1838 SPI_FOG_NONE = 0x0,
1839 SPI_FOG_EXP = 0x1,
1840 SPI_FOG_EXP2 = 0x2,
1841 SPI_FOG_LINEAR = 0x3,
1842} SPI_FOG_MODE;
1843typedef enum SPI_PNT_SPRITE_OVERRIDE {
1844 SPI_PNT_SPRITE_SEL_0 = 0x0,
1845 SPI_PNT_SPRITE_SEL_1 = 0x1,
1846 SPI_PNT_SPRITE_SEL_S = 0x2,
1847 SPI_PNT_SPRITE_SEL_T = 0x3,
1848 SPI_PNT_SPRITE_SEL_NONE = 0x4,
1849} SPI_PNT_SPRITE_OVERRIDE;
1850typedef enum SPI_PERFCNT_SEL {
1851 SPI_PERF_VS_WINDOW_VALID = 0x0,
1852 SPI_PERF_VS_BUSY = 0x1,
1853 SPI_PERF_VS_FIRST_WAVE = 0x2,
1854 SPI_PERF_VS_LAST_WAVE = 0x3,
1855 SPI_PERF_VS_LSHS_DEALLOC = 0x4,
1856 SPI_PERF_VS_PC_STALL = 0x5,
1857 SPI_PERF_VS_POS0_STALL = 0x6,
1858 SPI_PERF_VS_POS1_STALL = 0x7,
1859 SPI_PERF_VS_CRAWLER_STALL = 0x8,
1860 SPI_PERF_VS_EVENT_WAVE = 0x9,
1861 SPI_PERF_VS_WAVE = 0xa,
1862 SPI_PERF_VS_PERS_UPD_FULL0 = 0xb,
1863 SPI_PERF_VS_PERS_UPD_FULL1 = 0xc,
1864 SPI_PERF_VS_LATE_ALLOC_FULL = 0xd,
1865 SPI_PERF_VS_FIRST_SUBGRP = 0xe,
1866 SPI_PERF_VS_LAST_SUBGRP = 0xf,
1867 SPI_PERF_GS_WINDOW_VALID = 0x10,
1868 SPI_PERF_GS_BUSY = 0x11,
1869 SPI_PERF_GS_CRAWLER_STALL = 0x12,
1870 SPI_PERF_GS_EVENT_WAVE = 0x13,
1871 SPI_PERF_GS_WAVE = 0x14,
1872 SPI_PERF_GS_PERS_UPD_FULL0 = 0x15,
1873 SPI_PERF_GS_PERS_UPD_FULL1 = 0x16,
1874 SPI_PERF_GS_FIRST_SUBGRP = 0x17,
1875 SPI_PERF_GS_LAST_SUBGRP = 0x18,
1876 SPI_PERF_ES_WINDOW_VALID = 0x19,
1877 SPI_PERF_ES_BUSY = 0x1a,
1878 SPI_PERF_ES_CRAWLER_STALL = 0x1b,
1879 SPI_PERF_ES_FIRST_WAVE = 0x1c,
1880 SPI_PERF_ES_LAST_WAVE = 0x1d,
1881 SPI_PERF_ES_LSHS_DEALLOC = 0x1e,
1882 SPI_PERF_ES_EVENT_WAVE = 0x1f,
1883 SPI_PERF_ES_WAVE = 0x20,
1884 SPI_PERF_ES_PERS_UPD_FULL0 = 0x21,
1885 SPI_PERF_ES_PERS_UPD_FULL1 = 0x22,
1886 SPI_PERF_ES_FIRST_SUBGRP = 0x23,
1887 SPI_PERF_ES_LAST_SUBGRP = 0x24,
1888 SPI_PERF_HS_WINDOW_VALID = 0x25,
1889 SPI_PERF_HS_BUSY = 0x26,
1890 SPI_PERF_HS_CRAWLER_STALL = 0x27,
1891 SPI_PERF_HS_FIRST_WAVE = 0x28,
1892 SPI_PERF_HS_LAST_WAVE = 0x29,
1893 SPI_PERF_HS_LSHS_DEALLOC = 0x2a,
1894 SPI_PERF_HS_EVENT_WAVE = 0x2b,
1895 SPI_PERF_HS_WAVE = 0x2c,
1896 SPI_PERF_HS_PERS_UPD_FULL0 = 0x2d,
1897 SPI_PERF_HS_PERS_UPD_FULL1 = 0x2e,
1898 SPI_PERF_LS_WINDOW_VALID = 0x2f,
1899 SPI_PERF_LS_BUSY = 0x30,
1900 SPI_PERF_LS_CRAWLER_STALL = 0x31,
1901 SPI_PERF_LS_FIRST_WAVE = 0x32,
1902 SPI_PERF_LS_LAST_WAVE = 0x33,
1903 SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x34,
1904 SPI_PERF_LS_EVENT_WAVE = 0x35,
1905 SPI_PERF_LS_WAVE = 0x36,
1906 SPI_PERF_LS_PERS_UPD_FULL0 = 0x37,
1907 SPI_PERF_LS_PERS_UPD_FULL1 = 0x38,
1908 SPI_PERF_CSG_WINDOW_VALID = 0x39,
1909 SPI_PERF_CSG_BUSY = 0x3a,
1910 SPI_PERF_CSG_NUM_THREADGROUPS = 0x3b,
1911 SPI_PERF_CSG_CRAWLER_STALL = 0x3c,
1912 SPI_PERF_CSG_EVENT_WAVE = 0x3d,
1913 SPI_PERF_CSG_WAVE = 0x3e,
1914 SPI_PERF_CSN_WINDOW_VALID = 0x3f,
1915 SPI_PERF_CSN_BUSY = 0x40,
1916 SPI_PERF_CSN_NUM_THREADGROUPS = 0x41,
1917 SPI_PERF_CSN_CRAWLER_STALL = 0x42,
1918 SPI_PERF_CSN_EVENT_WAVE = 0x43,
1919 SPI_PERF_CSN_WAVE = 0x44,
1920 SPI_PERF_PS_CTL_WINDOW_VALID = 0x45,
1921 SPI_PERF_PS_CTL_BUSY = 0x46,
1922 SPI_PERF_PS_CTL_ACTIVE = 0x47,
1923 SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x48,
1924 SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x49,
1925 SPI_PERF_PS_CTL_EVENT_WAVE = 0x4a,
1926 SPI_PERF_PS_CTL_WAVE = 0x4b,
1927 SPI_PERF_PS_CTL_OPT_WAVE = 0x4c,
1928 SPI_PERF_PS_CTL_PASS_BIN0 = 0x4d,
1929 SPI_PERF_PS_CTL_PASS_BIN1 = 0x4e,
1930 SPI_PERF_PS_CTL_FPOS_BIN2 = 0x4f,
1931 SPI_PERF_PS_CTL_PRIM_BIN0 = 0x50,
1932 SPI_PERF_PS_CTL_PRIM_BIN1 = 0x51,
1933 SPI_PERF_PS_CTL_CNF_BIN2 = 0x52,
1934 SPI_PERF_PS_CTL_CNF_BIN3 = 0x53,
1935 SPI_PERF_PS_CTL_CRAWLER_STALL = 0x54,
1936 SPI_PERF_PS_CTL_LDS_RES_FULL = 0x55,
1937 SPI_PERF_PS_PERS_UPD_FULL0 = 0x56,
1938 SPI_PERF_PS_PERS_UPD_FULL1 = 0x57,
1939 SPI_PERF_PIX_ALLOC_PEND_CNT = 0x58,
1940 SPI_PERF_PIX_ALLOC_SCB_STALL = 0x59,
1941 SPI_PERF_PIX_ALLOC_DB0_STALL = 0x5a,
1942 SPI_PERF_PIX_ALLOC_DB1_STALL = 0x5b,
1943 SPI_PERF_PIX_ALLOC_DB2_STALL = 0x5c,
1944 SPI_PERF_PIX_ALLOC_DB3_STALL = 0x5d,
1945 SPI_PERF_LDS0_PC_VALID = 0x5e,
1946 SPI_PERF_LDS1_PC_VALID = 0x5f,
1947 SPI_PERF_RA_PIPE_REQ_BIN2 = 0x60,
1948 SPI_PERF_RA_TASK_REQ_BIN3 = 0x61,
1949 SPI_PERF_RA_WR_CTL_FULL = 0x62,
1950 SPI_PERF_RA_REQ_NO_ALLOC = 0x63,
1951 SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x64,
1952 SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x65,
1953 SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x66,
1954 SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x67,
1955 SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x68,
1956 SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x69,
1957 SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x6a,
1958 SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x6b,
1959 SPI_PERF_RA_RES_STALL_PS = 0x6c,
1960 SPI_PERF_RA_RES_STALL_VS = 0x6d,
1961 SPI_PERF_RA_RES_STALL_GS = 0x6e,
1962 SPI_PERF_RA_RES_STALL_ES = 0x6f,
1963 SPI_PERF_RA_RES_STALL_HS = 0x70,
1964 SPI_PERF_RA_RES_STALL_LS = 0x71,
1965 SPI_PERF_RA_RES_STALL_CSG = 0x72,
1966 SPI_PERF_RA_RES_STALL_CSN = 0x73,
1967 SPI_PERF_RA_TMP_STALL_PS = 0x74,
1968 SPI_PERF_RA_TMP_STALL_VS = 0x75,
1969 SPI_PERF_RA_TMP_STALL_GS = 0x76,
1970 SPI_PERF_RA_TMP_STALL_ES = 0x77,
1971 SPI_PERF_RA_TMP_STALL_HS = 0x78,
1972 SPI_PERF_RA_TMP_STALL_LS = 0x79,
1973 SPI_PERF_RA_TMP_STALL_CSG = 0x7a,
1974 SPI_PERF_RA_TMP_STALL_CSN = 0x7b,
1975 SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x7c,
1976 SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x7d,
1977 SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x7e,
1978 SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x7f,
1979 SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x80,
1980 SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x81,
1981 SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x82,
1982 SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x83,
1983 SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x84,
1984 SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x85,
1985 SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x86,
1986 SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x87,
1987 SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x88,
1988 SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x89,
1989 SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x8a,
1990 SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x8b,
1991 SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x8c,
1992 SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x8d,
1993 SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x8e,
1994 SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x8f,
1995 SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x90,
1996 SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x91,
1997 SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x92,
1998 SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x93,
1999 SPI_PERF_RA_LDS_CU_FULL_PS = 0x94,
2000 SPI_PERF_RA_LDS_CU_FULL_LS = 0x95,
2001 SPI_PERF_RA_LDS_CU_FULL_ES = 0x96,
2002 SPI_PERF_RA_LDS_CU_FULL_CSG = 0x97,
2003 SPI_PERF_RA_LDS_CU_FULL_CSN = 0x98,
2004 SPI_PERF_RA_BAR_CU_FULL_HS = 0x99,
2005 SPI_PERF_RA_BAR_CU_FULL_CSG = 0x9a,
2006 SPI_PERF_RA_BAR_CU_FULL_CSN = 0x9b,
2007 SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x9c,
2008 SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x9d,
2009 SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x9e,
2010 SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x9f,
2011 SPI_PERF_RA_WVLIM_STALL_PS = 0xa0,
2012 SPI_PERF_RA_WVLIM_STALL_VS = 0xa1,
2013 SPI_PERF_RA_WVLIM_STALL_GS = 0xa2,
2014 SPI_PERF_RA_WVLIM_STALL_ES = 0xa3,
2015 SPI_PERF_RA_WVLIM_STALL_HS = 0xa4,
2016 SPI_PERF_RA_WVLIM_STALL_LS = 0xa5,
2017 SPI_PERF_RA_WVLIM_STALL_CSG = 0xa6,
2018 SPI_PERF_RA_WVLIM_STALL_CSN = 0xa7,
2019 SPI_PERF_RA_PS_LOCK_NA = 0xa8,
2020 SPI_PERF_RA_VS_LOCK = 0xa9,
2021 SPI_PERF_RA_GS_LOCK = 0xaa,
2022 SPI_PERF_RA_ES_LOCK = 0xab,
2023 SPI_PERF_RA_HS_LOCK = 0xac,
2024 SPI_PERF_RA_LS_LOCK = 0xad,
2025 SPI_PERF_RA_CSG_LOCK = 0xae,
2026 SPI_PERF_RA_CSN_LOCK = 0xaf,
2027 SPI_PERF_RA_RSV_UPD = 0xb0,
2028 SPI_PERF_EXP_ARB_COL_CNT = 0xb1,
2029 SPI_PERF_EXP_ARB_PAR_CNT = 0xb2,
2030 SPI_PERF_EXP_ARB_POS_CNT = 0xb3,
2031 SPI_PERF_EXP_ARB_GDS_CNT = 0xb4,
2032 SPI_PERF_CLKGATE_BUSY_STALL = 0xb5,
2033 SPI_PERF_CLKGATE_ACTIVE_STALL = 0xb6,
2034 SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0xb7,
2035 SPI_PERF_CLKGATE_CGTT_DYN_ON = 0xb8,
2036 SPI_PERF_CLKGATE_CGTT_REG_ON = 0xb9,
2037 SPI_PERF_NUM_VS_POS_EXPORTS = 0xba,
2038 SPI_PERF_NUM_VS_PARAM_EXPORTS = 0xbb,
2039 SPI_PERF_NUM_PS_COL_EXPORTS = 0xbc,
2040 SPI_PERF_ES_GRP_FIFO_FULL = 0xbd,
2041 SPI_PERF_GS_GRP_FIFO_FULL = 0xbe,
2042 SPI_PERF_HS_GRP_FIFO_FULL = 0xbf,
2043 SPI_PERF_LS_GRP_FIFO_FULL = 0xc0,
2044 SPI_PERF_VS_ALLOC_CNT = 0xc1,
2045 SPI_PERF_VS_LATE_ALLOC_ACCUM = 0xc2,
2046 SPI_PERF_PC_ALLOC_CNT = 0xc3,
2047 SPI_PERF_PC_ALLOC_ACCUM = 0xc4,
2048} SPI_PERFCNT_SEL;
2049typedef enum SPI_SHADER_FORMAT {
2050 SPI_SHADER_NONE = 0x0,
2051 SPI_SHADER_1COMP = 0x1,
2052 SPI_SHADER_2COMP = 0x2,
2053 SPI_SHADER_4COMPRESS = 0x3,
2054 SPI_SHADER_4COMP = 0x4,
2055} SPI_SHADER_FORMAT;
2056typedef enum SPI_SHADER_EX_FORMAT {
2057 SPI_SHADER_ZERO = 0x0,
2058 SPI_SHADER_32_R = 0x1,
2059 SPI_SHADER_32_GR = 0x2,
2060 SPI_SHADER_32_AR = 0x3,
2061 SPI_SHADER_FP16_ABGR = 0x4,
2062 SPI_SHADER_UNORM16_ABGR = 0x5,
2063 SPI_SHADER_SNORM16_ABGR = 0x6,
2064 SPI_SHADER_UINT16_ABGR = 0x7,
2065 SPI_SHADER_SINT16_ABGR = 0x8,
2066 SPI_SHADER_32_ABGR = 0x9,
2067} SPI_SHADER_EX_FORMAT;
2068typedef enum CLKGATE_SM_MODE {
2069 ON_SEQ = 0x0,
2070 OFF_SEQ = 0x1,
2071 PROG_SEQ = 0x2,
2072 READ_SEQ = 0x3,
2073 SM_MODE_RESERVED = 0x4,
2074} CLKGATE_SM_MODE;
2075typedef enum CLKGATE_BASE_MODE {
2076 MULT_8 = 0x0,
2077 MULT_16 = 0x1,
2078} CLKGATE_BASE_MODE;
2079typedef enum SQ_TEX_CLAMP {
2080 SQ_TEX_WRAP = 0x0,
2081 SQ_TEX_MIRROR = 0x1,
2082 SQ_TEX_CLAMP_LAST_TEXEL = 0x2,
2083 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x3,
2084 SQ_TEX_CLAMP_HALF_BORDER = 0x4,
2085 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x5,
2086 SQ_TEX_CLAMP_BORDER = 0x6,
2087 SQ_TEX_MIRROR_ONCE_BORDER = 0x7,
2088} SQ_TEX_CLAMP;
2089typedef enum SQ_TEX_XY_FILTER {
2090 SQ_TEX_XY_FILTER_POINT = 0x0,
2091 SQ_TEX_XY_FILTER_BILINEAR = 0x1,
2092 SQ_TEX_XY_FILTER_ANISO_POINT = 0x2,
2093 SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x3,
2094} SQ_TEX_XY_FILTER;
2095typedef enum SQ_TEX_Z_FILTER {
2096 SQ_TEX_Z_FILTER_NONE = 0x0,
2097 SQ_TEX_Z_FILTER_POINT = 0x1,
2098 SQ_TEX_Z_FILTER_LINEAR = 0x2,
2099} SQ_TEX_Z_FILTER;
2100typedef enum SQ_TEX_MIP_FILTER {
2101 SQ_TEX_MIP_FILTER_NONE = 0x0,
2102 SQ_TEX_MIP_FILTER_POINT = 0x1,
2103 SQ_TEX_MIP_FILTER_LINEAR = 0x2,
2104 SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x3,
2105} SQ_TEX_MIP_FILTER;
2106typedef enum SQ_TEX_ANISO_RATIO {
2107 SQ_TEX_ANISO_RATIO_1 = 0x0,
2108 SQ_TEX_ANISO_RATIO_2 = 0x1,
2109 SQ_TEX_ANISO_RATIO_4 = 0x2,
2110 SQ_TEX_ANISO_RATIO_8 = 0x3,
2111 SQ_TEX_ANISO_RATIO_16 = 0x4,
2112} SQ_TEX_ANISO_RATIO;
2113typedef enum SQ_TEX_DEPTH_COMPARE {
2114 SQ_TEX_DEPTH_COMPARE_NEVER = 0x0,
2115 SQ_TEX_DEPTH_COMPARE_LESS = 0x1,
2116 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2,
2117 SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x3,
2118 SQ_TEX_DEPTH_COMPARE_GREATER = 0x4,
2119 SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x5,
2120 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x6,
2121 SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x7,
2122} SQ_TEX_DEPTH_COMPARE;
2123typedef enum SQ_TEX_BORDER_COLOR {
2124 SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x0,
2125 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x1,
2126 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2,
2127 SQ_TEX_BORDER_COLOR_REGISTER = 0x3,
2128} SQ_TEX_BORDER_COLOR;
2129typedef enum SQ_RSRC_BUF_TYPE {
2130 SQ_RSRC_BUF = 0x0,
2131 SQ_RSRC_BUF_RSVD_1 = 0x1,
2132 SQ_RSRC_BUF_RSVD_2 = 0x2,
2133 SQ_RSRC_BUF_RSVD_3 = 0x3,
2134} SQ_RSRC_BUF_TYPE;
2135typedef enum SQ_RSRC_IMG_TYPE {
2136 SQ_RSRC_IMG_RSVD_0 = 0x0,
2137 SQ_RSRC_IMG_RSVD_1 = 0x1,
2138 SQ_RSRC_IMG_RSVD_2 = 0x2,
2139 SQ_RSRC_IMG_RSVD_3 = 0x3,
2140 SQ_RSRC_IMG_RSVD_4 = 0x4,
2141 SQ_RSRC_IMG_RSVD_5 = 0x5,
2142 SQ_RSRC_IMG_RSVD_6 = 0x6,
2143 SQ_RSRC_IMG_RSVD_7 = 0x7,
2144 SQ_RSRC_IMG_1D = 0x8,
2145 SQ_RSRC_IMG_2D = 0x9,
2146 SQ_RSRC_IMG_3D = 0xa,
2147 SQ_RSRC_IMG_CUBE = 0xb,
2148 SQ_RSRC_IMG_1D_ARRAY = 0xc,
2149 SQ_RSRC_IMG_2D_ARRAY = 0xd,
2150 SQ_RSRC_IMG_2D_MSAA = 0xe,
2151 SQ_RSRC_IMG_2D_MSAA_ARRAY = 0xf,
2152} SQ_RSRC_IMG_TYPE;
2153typedef enum SQ_RSRC_FLAT_TYPE {
2154 SQ_RSRC_FLAT_RSVD_0 = 0x0,
2155 SQ_RSRC_FLAT = 0x1,
2156 SQ_RSRC_FLAT_RSVD_2 = 0x2,
2157 SQ_RSRC_FLAT_RSVD_3 = 0x3,
2158} SQ_RSRC_FLAT_TYPE;
2159typedef enum SQ_IMG_FILTER_TYPE {
2160 SQ_IMG_FILTER_MODE_BLEND = 0x0,
2161 SQ_IMG_FILTER_MODE_MIN = 0x1,
2162 SQ_IMG_FILTER_MODE_MAX = 0x2,
2163} SQ_IMG_FILTER_TYPE;
2164typedef enum SQ_SEL_XYZW01 {
2165 SQ_SEL_0 = 0x0,
2166 SQ_SEL_1 = 0x1,
2167 SQ_SEL_RESERVED_0 = 0x2,
2168 SQ_SEL_RESERVED_1 = 0x3,
2169 SQ_SEL_X = 0x4,
2170 SQ_SEL_Y = 0x5,
2171 SQ_SEL_Z = 0x6,
2172 SQ_SEL_W = 0x7,
2173} SQ_SEL_XYZW01;
2174typedef enum SQ_WAVE_TYPE {
2175 SQ_WAVE_TYPE_PS = 0x0,
2176 SQ_WAVE_TYPE_VS = 0x1,
2177 SQ_WAVE_TYPE_GS = 0x2,
2178 SQ_WAVE_TYPE_ES = 0x3,
2179 SQ_WAVE_TYPE_HS = 0x4,
2180 SQ_WAVE_TYPE_LS = 0x5,
2181 SQ_WAVE_TYPE_CS = 0x6,
2182 SQ_WAVE_TYPE_PS1 = 0x7,
2183} SQ_WAVE_TYPE;
2184typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
2185 SQ_THREAD_TRACE_TOKEN_MISC = 0x0,
2186 SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x1,
2187 SQ_THREAD_TRACE_TOKEN_REG = 0x2,
2188 SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x3,
2189 SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x4,
2190 SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x5,
2191 SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x6,
2192 SQ_THREAD_TRACE_TOKEN_EVENT = 0x7,
2193 SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x8,
2194 SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x9,
2195 SQ_THREAD_TRACE_TOKEN_INST = 0xa,
2196 SQ_THREAD_TRACE_TOKEN_INST_PC = 0xb,
2197 SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0xc,
2198 SQ_THREAD_TRACE_TOKEN_ISSUE = 0xd,
2199 SQ_THREAD_TRACE_TOKEN_PERF = 0xe,
2200 SQ_THREAD_TRACE_TOKEN_REG_CS = 0xf,
2201} SQ_THREAD_TRACE_TOKEN_TYPE;
2202typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
2203 SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x0,
2204 SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x1,
2205 SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2,
2206 SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x3,
2207 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x4,
2208 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x5,
2209 SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x6,
2210 SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x7,
2211} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
2212typedef enum SQ_THREAD_TRACE_INST_TYPE {
2213 SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x0,
2214 SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x1,
2215 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2,
2216 SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x3,
2217 SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x4,
2218 SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x5,
2219 SQ_THREAD_TRACE_INST_TYPE_LDS = 0x6,
2220 SQ_THREAD_TRACE_INST_TYPE_PC = 0x7,
2221 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x8,
2222 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x9,
2223 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0xa,
2224 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0xb,
2225 SQ_THREAD_TRACE_INST_TYPE_JUMP = 0xc,
2226 SQ_THREAD_TRACE_INST_TYPE_NEXT = 0xd,
2227 SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0xe,
2228 SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0xf,
2229 SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x10,
2230 SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x11,
2231 SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x12,
2232 SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x13,
2233 SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x14,
2234 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x15,
2235 SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x16,
2236 SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x17,
2237 SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x18,
2238} SQ_THREAD_TRACE_INST_TYPE;
2239typedef enum SQ_THREAD_TRACE_REG_TYPE {
2240 SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x0,
2241 SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x1,
2242 SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2,
2243 SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x3,
2244 SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x4,
2245 SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x5,
2246 SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x6,
2247 SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x7,
2248} SQ_THREAD_TRACE_REG_TYPE;
2249typedef enum SQ_THREAD_TRACE_REG_OP {
2250 SQ_THREAD_TRACE_REG_OP_READ = 0x0,
2251 SQ_THREAD_TRACE_REG_OP_WRITE = 0x1,
2252} SQ_THREAD_TRACE_REG_OP;
2253typedef enum SQ_THREAD_TRACE_MODE_SEL {
2254 SQ_THREAD_TRACE_MODE_OFF = 0x0,
2255 SQ_THREAD_TRACE_MODE_ON = 0x1,
2256} SQ_THREAD_TRACE_MODE_SEL;
2257typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
2258 SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x0,
2259 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x1,
2260 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2,
2261} SQ_THREAD_TRACE_CAPTURE_MODE;
2262typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
2263 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x0,
2264 SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x1,
2265 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2,
2266} SQ_THREAD_TRACE_VM_ID_MASK;
2267typedef enum SQ_THREAD_TRACE_WAVE_MASK {
2268 SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x0,
2269 SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x1,
2270} SQ_THREAD_TRACE_WAVE_MASK;
2271typedef enum SQ_THREAD_TRACE_ISSUE {
2272 SQ_THREAD_TRACE_ISSUE_NULL = 0x0,
2273 SQ_THREAD_TRACE_ISSUE_STALL = 0x1,
2274 SQ_THREAD_TRACE_ISSUE_INST = 0x2,
2275 SQ_THREAD_TRACE_ISSUE_IMMED = 0x3,
2276} SQ_THREAD_TRACE_ISSUE;
2277typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
2278 SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x0,
2279 SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x1,
2280 SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2,
2281 SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x3,
2282} SQ_THREAD_TRACE_ISSUE_MASK;
2283typedef enum SQ_PERF_SEL {
2284 SQ_PERF_SEL_NONE = 0x0,
2285 SQ_PERF_SEL_ACCUM_PREV = 0x1,
2286 SQ_PERF_SEL_CYCLES = 0x2,
2287 SQ_PERF_SEL_BUSY_CYCLES = 0x3,
2288 SQ_PERF_SEL_WAVES = 0x4,
2289 SQ_PERF_SEL_LEVEL_WAVES = 0x5,
2290 SQ_PERF_SEL_WAVES_EQ_64 = 0x6,
2291 SQ_PERF_SEL_WAVES_LT_64 = 0x7,
2292 SQ_PERF_SEL_WAVES_LT_48 = 0x8,
2293 SQ_PERF_SEL_WAVES_LT_32 = 0x9,
2294 SQ_PERF_SEL_WAVES_LT_16 = 0xa,
2295 SQ_PERF_SEL_WAVES_CU = 0xb,
2296 SQ_PERF_SEL_LEVEL_WAVES_CU = 0xc,
2297 SQ_PERF_SEL_BUSY_CU_CYCLES = 0xd,
2298 SQ_PERF_SEL_ITEMS = 0xe,
2299 SQ_PERF_SEL_QUADS = 0xf,
2300 SQ_PERF_SEL_EVENTS = 0x10,
2301 SQ_PERF_SEL_SURF_SYNCS = 0x11,
2302 SQ_PERF_SEL_TTRACE_REQS = 0x12,
2303 SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x13,
2304 SQ_PERF_SEL_TTRACE_STALL = 0x14,
2305 SQ_PERF_SEL_MSG_CNTR = 0x15,
2306 SQ_PERF_SEL_MSG_PERF = 0x16,
2307 SQ_PERF_SEL_MSG_GSCNT = 0x17,
2308 SQ_PERF_SEL_MSG_INTERRUPT = 0x18,
2309 SQ_PERF_SEL_INSTS = 0x19,
2310 SQ_PERF_SEL_INSTS_VALU = 0x1a,
2311 SQ_PERF_SEL_INSTS_VMEM_WR = 0x1b,
2312 SQ_PERF_SEL_INSTS_VMEM_RD = 0x1c,
2313 SQ_PERF_SEL_INSTS_VMEM = 0x1d,
2314 SQ_PERF_SEL_INSTS_SALU = 0x1e,
2315 SQ_PERF_SEL_INSTS_SMEM = 0x1f,
2316 SQ_PERF_SEL_INSTS_FLAT = 0x20,
2317 SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x21,
2318 SQ_PERF_SEL_INSTS_LDS = 0x22,
2319 SQ_PERF_SEL_INSTS_GDS = 0x23,
2320 SQ_PERF_SEL_INSTS_EXP = 0x24,
2321 SQ_PERF_SEL_INSTS_EXP_GDS = 0x25,
2322 SQ_PERF_SEL_INSTS_BRANCH = 0x26,
2323 SQ_PERF_SEL_INSTS_SENDMSG = 0x27,
2324 SQ_PERF_SEL_INSTS_VSKIPPED = 0x28,
2325 SQ_PERF_SEL_INST_LEVEL_VMEM = 0x29,
2326 SQ_PERF_SEL_INST_LEVEL_SMEM = 0x2a,
2327 SQ_PERF_SEL_INST_LEVEL_LDS = 0x2b,
2328 SQ_PERF_SEL_INST_LEVEL_GDS = 0x2c,
2329 SQ_PERF_SEL_INST_LEVEL_EXP = 0x2d,
2330 SQ_PERF_SEL_WAVE_CYCLES = 0x2e,
2331 SQ_PERF_SEL_WAVE_READY = 0x2f,
2332 SQ_PERF_SEL_WAIT_CNT_VM = 0x30,
2333 SQ_PERF_SEL_WAIT_CNT_LGKM = 0x31,
2334 SQ_PERF_SEL_WAIT_CNT_EXP = 0x32,
2335 SQ_PERF_SEL_WAIT_CNT_ANY = 0x33,
2336 SQ_PERF_SEL_WAIT_BARRIER = 0x34,
2337 SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x35,
2338 SQ_PERF_SEL_WAIT_SLEEP = 0x36,
2339 SQ_PERF_SEL_WAIT_OTHER = 0x37,
2340 SQ_PERF_SEL_WAIT_ANY = 0x38,
2341 SQ_PERF_SEL_WAIT_TTRACE = 0x39,
2342 SQ_PERF_SEL_WAIT_IFETCH = 0x3a,
2343 SQ_PERF_SEL_WAIT_INST_VMEM = 0x3b,
2344 SQ_PERF_SEL_WAIT_INST_SCA = 0x3c,
2345 SQ_PERF_SEL_WAIT_INST_LDS = 0x3d,
2346 SQ_PERF_SEL_WAIT_INST_VALU = 0x3e,
2347 SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x3f,
2348 SQ_PERF_SEL_WAIT_INST_MISC = 0x40,
2349 SQ_PERF_SEL_WAIT_INST_FLAT = 0x41,
2350 SQ_PERF_SEL_ACTIVE_INST_ANY = 0x42,
2351 SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x43,
2352 SQ_PERF_SEL_ACTIVE_INST_LDS = 0x44,
2353 SQ_PERF_SEL_ACTIVE_INST_VALU = 0x45,
2354 SQ_PERF_SEL_ACTIVE_INST_SCA = 0x46,
2355 SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x47,
2356 SQ_PERF_SEL_ACTIVE_INST_MISC = 0x48,
2357 SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x49,
2358 SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x4a,
2359 SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x4b,
2360 SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x4c,
2361 SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x4d,
2362 SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x4e,
2363 SQ_PERF_SEL_INST_CYCLES_VMEM = 0x4f,
2364 SQ_PERF_SEL_INST_CYCLES_LDS = 0x50,
2365 SQ_PERF_SEL_INST_CYCLES_VALU = 0x51,
2366 SQ_PERF_SEL_INST_CYCLES_EXP = 0x52,
2367 SQ_PERF_SEL_INST_CYCLES_GDS = 0x53,
2368 SQ_PERF_SEL_INST_CYCLES_SCA = 0x54,
2369 SQ_PERF_SEL_INST_CYCLES_SMEM = 0x55,
2370 SQ_PERF_SEL_INST_CYCLES_SALU = 0x56,
2371 SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x57,
2372 SQ_PERF_SEL_INST_CYCLES_MISC = 0x58,
2373 SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x59,
2374 SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x5a,
2375 SQ_PERF_SEL_IFETCH = 0x5b,
2376 SQ_PERF_SEL_IFETCH_LEVEL = 0x5c,
2377 SQ_PERF_SEL_CBRANCH_FORK = 0x5d,
2378 SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x5e,
2379 SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x5f,
2380 SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x60,
2381 SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x61,
2382 SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x62,
2383 SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x63,
2384 SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x64,
2385 SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x65,
2386 SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x66,
2387 SQ_PERF_SEL_VALU_DEP_STALL = 0x67,
2388 SQ_PERF_SEL_VALU_STARVE = 0x68,
2389 SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x69,
2390 SQ_PERF_SEL_LDS_BACK2BACK_STALL = 0x6a,
2391 SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x6b,
2392 SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x6c,
2393 SQ_PERF_SEL_VMEM_BACK2BACK_STALL = 0x6d,
2394 SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x6e,
2395 SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x6f,
2396 SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x70,
2397 SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL = 0x71,
2398 SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x72,
2399 SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x73,
2400 SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x74,
2401 SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x75,
2402 SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x76,
2403 SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x77,
2404 SQ_PERF_SEL_SRC_CD_BUSY = 0x78,
2405 SQ_PERF_SEL_PT_POWER_STALL = 0x79,
2406 SQ_PERF_SEL_USER0 = 0x7a,
2407 SQ_PERF_SEL_USER1 = 0x7b,
2408 SQ_PERF_SEL_USER2 = 0x7c,
2409 SQ_PERF_SEL_USER3 = 0x7d,
2410 SQ_PERF_SEL_USER4 = 0x7e,
2411 SQ_PERF_SEL_USER5 = 0x7f,
2412 SQ_PERF_SEL_USER6 = 0x80,
2413 SQ_PERF_SEL_USER7 = 0x81,
2414 SQ_PERF_SEL_USER8 = 0x82,
2415 SQ_PERF_SEL_USER9 = 0x83,
2416 SQ_PERF_SEL_USER10 = 0x84,
2417 SQ_PERF_SEL_USER11 = 0x85,
2418 SQ_PERF_SEL_USER12 = 0x86,
2419 SQ_PERF_SEL_USER13 = 0x87,
2420 SQ_PERF_SEL_USER14 = 0x88,
2421 SQ_PERF_SEL_USER15 = 0x89,
2422 SQ_PERF_SEL_USER_LEVEL0 = 0x8a,
2423 SQ_PERF_SEL_USER_LEVEL1 = 0x8b,
2424 SQ_PERF_SEL_USER_LEVEL2 = 0x8c,
2425 SQ_PERF_SEL_USER_LEVEL3 = 0x8d,
2426 SQ_PERF_SEL_USER_LEVEL4 = 0x8e,
2427 SQ_PERF_SEL_USER_LEVEL5 = 0x8f,
2428 SQ_PERF_SEL_USER_LEVEL6 = 0x90,
2429 SQ_PERF_SEL_USER_LEVEL7 = 0x91,
2430 SQ_PERF_SEL_USER_LEVEL8 = 0x92,
2431 SQ_PERF_SEL_USER_LEVEL9 = 0x93,
2432 SQ_PERF_SEL_USER_LEVEL10 = 0x94,
2433 SQ_PERF_SEL_USER_LEVEL11 = 0x95,
2434 SQ_PERF_SEL_USER_LEVEL12 = 0x96,
2435 SQ_PERF_SEL_USER_LEVEL13 = 0x97,
2436 SQ_PERF_SEL_USER_LEVEL14 = 0x98,
2437 SQ_PERF_SEL_USER_LEVEL15 = 0x99,
2438 SQ_PERF_SEL_POWER_VALU = 0x9a,
2439 SQ_PERF_SEL_POWER_VALU0 = 0x9b,
2440 SQ_PERF_SEL_POWER_VALU1 = 0x9c,
2441 SQ_PERF_SEL_POWER_VALU2 = 0x9d,
2442 SQ_PERF_SEL_POWER_GPR_RD = 0x9e,
2443 SQ_PERF_SEL_POWER_GPR_WR = 0x9f,
2444 SQ_PERF_SEL_POWER_LDS_BUSY = 0xa0,
2445 SQ_PERF_SEL_POWER_ALU_BUSY = 0xa1,
2446 SQ_PERF_SEL_POWER_TEX_BUSY = 0xa2,
2447 SQ_PERF_SEL_ACCUM_PREV_HIRES = 0xa3,
2448 SQ_PERF_SEL_WAVES_RESTORED = 0xa4,
2449 SQ_PERF_SEL_WAVES_SAVED = 0xa5,
2450 SQ_PERF_SEL_DUMMY_LAST = 0xa7,
2451 SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0xa8,
2452 SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0xa9,
2453 SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0xaa,
2454 SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0xab,
2455 SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0xac,
2456 SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0xad,
2457 SQC_PERF_SEL_TC_REQ = 0xae,
2458 SQC_PERF_SEL_TC_INST_REQ = 0xaf,
2459 SQC_PERF_SEL_TC_DATA_READ_REQ = 0xb0,
2460 SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0xb1,
2461 SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0xb2,
2462 SQC_PERF_SEL_TC_STALL = 0xb3,
2463 SQC_PERF_SEL_TC_STARVE = 0xb4,
2464 SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0xb5,
2465 SQC_PERF_SEL_ICACHE_REQ = 0xb6,
2466 SQC_PERF_SEL_ICACHE_HITS = 0xb7,
2467 SQC_PERF_SEL_ICACHE_MISSES = 0xb8,
2468 SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0xb9,
2469 SQC_PERF_SEL_ICACHE_INVAL_INST = 0xba,
2470 SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0xbb,
2471 SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0xbc,
2472 SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0xbd,
2473 SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0xbe,
2474 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xbf,
2475 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0xc0,
2476 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0xc1,
2477 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc2,
2478 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xc3,
2479 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0xc4,
2480 SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xc5,
2481 SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0xc6,
2482 SQC_PERF_SEL_DCACHE_REQ = 0xc7,
2483 SQC_PERF_SEL_DCACHE_HITS = 0xc8,
2484 SQC_PERF_SEL_DCACHE_MISSES = 0xc9,
2485 SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0xca,
2486 SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0xcb,
2487 SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0xcc,
2488 SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0xcd,
2489 SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0xce,
2490 SQC_PERF_SEL_DCACHE_ATOMIC = 0xcf,
2491 SQC_PERF_SEL_DCACHE_VOLATILE = 0xd0,
2492 SQC_PERF_SEL_DCACHE_INVAL_INST = 0xd1,
2493 SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0xd2,
2494 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0xd3,
2495 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0xd4,
2496 SQC_PERF_SEL_DCACHE_WB_INST = 0xd5,
2497 SQC_PERF_SEL_DCACHE_WB_ASYNC = 0xd6,
2498 SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0xd7,
2499 SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0xd8,
2500 SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0xd9,
2501 SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0xda,
2502 SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0xdb,
2503 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0xdc,
2504 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0xdd,
2505 SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0xde,
2506 SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0xdf,
2507 SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE= 0xe0,
2508 SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0xe1,
2509 SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0xe2,
2510 SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0xe3,
2511 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xe4,
2512 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xe5,
2513 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0xe6,
2514 SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xe7,
2515 SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0xe8,
2516 SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0xe9,
2517 SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0xea,
2518 SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0xeb,
2519 SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0xec,
2520 SQC_PERF_SEL_DCACHE_REQ_TIME = 0xed,
2521 SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0xee,
2522 SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0xef,
2523 SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0xf0,
2524 SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0xf1,
2525 SQC_PERF_SEL_SQ_DCACHE_REQS = 0xf2,
2526 SQC_PERF_SEL_DCACHE_FLAT_REQ = 0xf3,
2527 SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0xf4,
2528 SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0xf5,
2529 SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0xf6,
2530 SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0xf7,
2531 SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0xf8,
2532 SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0xf9,
2533 SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0xfa,
2534 SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0xfb,
2535 SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0xfc,
2536 SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0xfd,
2537 SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0xfe,
2538 SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0xff,
2539 SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x100,
2540 SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x101,
2541 SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x102,
2542 SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x103,
2543 SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x104,
2544 SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x105,
2545 SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x106,
2546 SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x107,
2547 SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x108,
2548 SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x109,
2549 SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x10a,
2550 SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x10b,
2551 SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x10c,
2552 SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x10d,
2553 SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x10e,
2554 SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x10f,
2555 SQC_PERF_SEL_DUMMY_LAST = 0x110,
2556 SQ_PERF_SEL_INSTS_SMEM_NORM = 0x111,
2557 SQ_PERF_SEL_ATC_INSTS_VMEM = 0x112,
2558 SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 0x113,
2559 SQ_PERF_SEL_ATC_XNACK_FIRST = 0x114,
2560 SQ_PERF_SEL_ATC_XNACK_ALL = 0x115,
2561 SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 0x116,
2562 SQ_PERF_SEL_ATC_INSTS_SMEM = 0x117,
2563 SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 0x118,
2564 SQ_PERF_SEL_IFETCH_XNACK = 0x119,
2565 SQ_PERF_SEL_TLB_SHOOTDOWN = 0x11a,
2566 SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x11b,
2567 SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x11c,
2568 SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x11d,
2569 SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x11e,
2570 SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x11f,
2571 SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x120,
2572 SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x121,
2573 SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x122,
2574 SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 0x123,
2575 SQ_PERF_SEL_DUMMY_LAST1 = 0x12a,
2576} SQ_PERF_SEL;
2577typedef enum SQ_CAC_POWER_SEL {
2578 SQ_CAC_POWER_VALU = 0x0,
2579 SQ_CAC_POWER_VALU0 = 0x1,
2580 SQ_CAC_POWER_VALU1 = 0x2,
2581 SQ_CAC_POWER_VALU2 = 0x3,
2582 SQ_CAC_POWER_GPR_RD = 0x4,
2583 SQ_CAC_POWER_GPR_WR = 0x5,
2584 SQ_CAC_POWER_LDS_BUSY = 0x6,
2585 SQ_CAC_POWER_ALU_BUSY = 0x7,
2586 SQ_CAC_POWER_TEX_BUSY = 0x8,
2587} SQ_CAC_POWER_SEL;
2588typedef enum SQ_IND_CMD_CMD {
2589 SQ_IND_CMD_CMD_NULL = 0x0,
2590 SQ_IND_CMD_CMD_SETHALT = 0x1,
2591 SQ_IND_CMD_CMD_SAVECTX = 0x2,
2592 SQ_IND_CMD_CMD_KILL = 0x3,
2593 SQ_IND_CMD_CMD_DEBUG = 0x4,
2594 SQ_IND_CMD_CMD_TRAP = 0x5,
2595 SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x6,
2596} SQ_IND_CMD_CMD;
2597typedef enum SQ_IND_CMD_MODE {
2598 SQ_IND_CMD_MODE_SINGLE = 0x0,
2599 SQ_IND_CMD_MODE_BROADCAST = 0x1,
2600 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2,
2601 SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x3,
2602 SQ_IND_CMD_MODE_BROADCAST_ME = 0x4,
2603} SQ_IND_CMD_MODE;
2604typedef enum SQ_EDC_INFO_SOURCE {
2605 SQ_EDC_INFO_SOURCE_INVALID = 0x0,
2606 SQ_EDC_INFO_SOURCE_INST = 0x1,
2607 SQ_EDC_INFO_SOURCE_SGPR = 0x2,
2608 SQ_EDC_INFO_SOURCE_VGPR = 0x3,
2609 SQ_EDC_INFO_SOURCE_LDS = 0x4,
2610 SQ_EDC_INFO_SOURCE_GDS = 0x5,
2611 SQ_EDC_INFO_SOURCE_TA = 0x6,
2612} SQ_EDC_INFO_SOURCE;
2613typedef enum SQ_ROUND_MODE {
2614 SQ_ROUND_NEAREST_EVEN = 0x0,
2615 SQ_ROUND_PLUS_INFINITY = 0x1,
2616 SQ_ROUND_MINUS_INFINITY = 0x2,
2617 SQ_ROUND_TO_ZERO = 0x3,
2618} SQ_ROUND_MODE;
2619typedef enum SQ_INTERRUPT_WORD_ENCODING {
2620 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
2621 SQ_INTERRUPT_WORD_ENCODING_INST = 0x1,
2622 SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2,
2623} SQ_INTERRUPT_WORD_ENCODING;
2624typedef enum ENUM_SQ_EXPORT_RAT_INST {
2625 SQ_EXPORT_RAT_INST_NOP = 0x0,
2626 SQ_EXPORT_RAT_INST_STORE_TYPED = 0x1,
2627 SQ_EXPORT_RAT_INST_STORE_RAW = 0x2,
2628 SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x3,
2629 SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x4,
2630 SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x5,
2631 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x6,
2632 SQ_EXPORT_RAT_INST_ADD = 0x7,
2633 SQ_EXPORT_RAT_INST_SUB = 0x8,
2634 SQ_EXPORT_RAT_INST_RSUB = 0x9,
2635 SQ_EXPORT_RAT_INST_MIN_INT = 0xa,
2636 SQ_EXPORT_RAT_INST_MIN_UINT = 0xb,
2637 SQ_EXPORT_RAT_INST_MAX_INT = 0xc,
2638 SQ_EXPORT_RAT_INST_MAX_UINT = 0xd,
2639 SQ_EXPORT_RAT_INST_AND = 0xe,
2640 SQ_EXPORT_RAT_INST_OR = 0xf,
2641 SQ_EXPORT_RAT_INST_XOR = 0x10,
2642 SQ_EXPORT_RAT_INST_MSKOR = 0x11,
2643 SQ_EXPORT_RAT_INST_INC_UINT = 0x12,
2644 SQ_EXPORT_RAT_INST_DEC_UINT = 0x13,
2645 SQ_EXPORT_RAT_INST_STORE_DWORD = 0x14,
2646 SQ_EXPORT_RAT_INST_STORE_SHORT = 0x15,
2647 SQ_EXPORT_RAT_INST_STORE_BYTE = 0x16,
2648 SQ_EXPORT_RAT_INST_NOP_RTN = 0x20,
2649 SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22,
2650 SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23,
2651 SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24,
2652 SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25,
2653 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26,
2654 SQ_EXPORT_RAT_INST_ADD_RTN = 0x27,
2655 SQ_EXPORT_RAT_INST_SUB_RTN = 0x28,
2656 SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29,
2657 SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a,
2658 SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b,
2659 SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c,
2660 SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d,
2661 SQ_EXPORT_RAT_INST_AND_RTN = 0x2e,
2662 SQ_EXPORT_RAT_INST_OR_RTN = 0x2f,
2663 SQ_EXPORT_RAT_INST_XOR_RTN = 0x30,
2664 SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31,
2665 SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32,
2666 SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33,
2667} ENUM_SQ_EXPORT_RAT_INST;
2668typedef enum SQ_IBUF_ST {
2669 SQ_IBUF_IB_IDLE = 0x0,
2670 SQ_IBUF_IB_INI_WAIT_GNT = 0x1,
2671 SQ_IBUF_IB_INI_WAIT_DRET = 0x2,
2672 SQ_IBUF_IB_LE_4DW = 0x3,
2673 SQ_IBUF_IB_WAIT_DRET = 0x4,
2674 SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x5,
2675 SQ_IBUF_IB_DRET = 0x6,
2676 SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x7,
2677} SQ_IBUF_ST;
2678typedef enum SQ_INST_STR_ST {
2679 SQ_INST_STR_IB_WAVE_NORML = 0x0,
2680 SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x1,
2681 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2,
2682 SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x3,
2683 SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x4,
2684 SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x5,
2685 SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x6,
2686 SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x7,
2687} SQ_INST_STR_ST;
2688typedef enum SQ_WAVE_IB_ECC_ST {
2689 SQ_WAVE_IB_ECC_CLEAN = 0x0,
2690 SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x1,
2691 SQ_WAVE_IB_ECC_ERR_HALT = 0x2,
2692 SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x3,
2693} SQ_WAVE_IB_ECC_ST;
2694typedef enum SH_MEM_ADDRESS_MODE {
2695 SH_MEM_ADDRESS_MODE_GPUVM64 = 0x0,
2696 SH_MEM_ADDRESS_MODE_GPUVM32 = 0x1,
2697 SH_MEM_ADDRESS_MODE_HSA64 = 0x2,
2698 SH_MEM_ADDRESS_MODE_HSA32 = 0x3,
2699} SH_MEM_ADDRESS_MODE;
2700typedef enum SH_MEM_ALIGNMENT_MODE {
2701 SH_MEM_ALIGNMENT_MODE_DWORD = 0x0,
2702 SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x1,
2703 SH_MEM_ALIGNMENT_MODE_STRICT = 0x2,
2704 SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x3,
2705} SH_MEM_ALIGNMENT_MODE;
2706typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
2707 SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x18,
2708 SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x19,
2709} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
2710#define SQ_WAVE_TYPE_PS0 0x0
2711#define SQIND_GLOBAL_REGS_OFFSET 0x0
2712#define SQIND_GLOBAL_REGS_SIZE 0x8
2713#define SQIND_LOCAL_REGS_OFFSET 0x8
2714#define SQIND_LOCAL_REGS_SIZE 0x8
2715#define SQIND_WAVE_HWREGS_OFFSET 0x10
2716#define SQIND_WAVE_HWREGS_SIZE 0x1f0
2717#define SQIND_WAVE_SGPRS_OFFSET 0x200
2718#define SQIND_WAVE_SGPRS_SIZE 0x200
2719#define SQ_GFXDEC_BEGIN 0xa000
2720#define SQ_GFXDEC_END 0xc000
2721#define SQ_GFXDEC_STATE_ID_SHIFT 0xa
2722#define SQDEC_BEGIN 0x2300
2723#define SQDEC_END 0x23ff
2724#define SQPERFSDEC_BEGIN 0xd9c0
2725#define SQPERFSDEC_END 0xda40
2726#define SQPERFDDEC_BEGIN 0xd1c0
2727#define SQPERFDDEC_END 0xd240
2728#define SQGFXUDEC_BEGIN 0xc330
2729#define SQGFXUDEC_END 0xc380
2730#define SQPWRDEC_BEGIN 0xf08c
2731#define SQPWRDEC_END 0xf094
2732#define SQ_DISPATCHER_GFX_MIN 0x10
2733#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x8
2734#define SQ_MAX_PGM_SGPRS 0x68
2735#define SQ_MAX_PGM_VGPRS 0x100
2736#define SQ_THREAD_TRACE_TIME_UNIT 0x4
2737#define SQ_EX_MODE_EXCP_VALU_BASE 0x0
2738#define SQ_EX_MODE_EXCP_VALU_SIZE 0x7
2739#define SQ_EX_MODE_EXCP_INVALID 0x0
2740#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x1
2741#define SQ_EX_MODE_EXCP_DIV0 0x2
2742#define SQ_EX_MODE_EXCP_OVERFLOW 0x3
2743#define SQ_EX_MODE_EXCP_UNDERFLOW 0x4
2744#define SQ_EX_MODE_EXCP_INEXACT 0x5
2745#define SQ_EX_MODE_EXCP_INT_DIV0 0x6
2746#define SQ_EX_MODE_EXCP_ADDR_WATCH 0x7
2747#define SQ_EX_MODE_EXCP_MEM_VIOL 0x8
2748#define INST_ID_PRIV_START 0x80000000
2749#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0
2750#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1
2751#define INST_ID_HW_TRAP 0xfffffff2
2752#define INST_ID_KILL_SEQ 0xfffffff3
2753#define INST_ID_SPI_WREXEC 0xfffffff4
2754#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe
2755#define SQ_ENC_SOP1_BITS 0xbe800000
2756#define SQ_ENC_SOP1_MASK 0xff800000
2757#define SQ_ENC_SOP1_FIELD 0x17d
2758#define SQ_ENC_SOPC_BITS 0xbf000000
2759#define SQ_ENC_SOPC_MASK 0xff800000
2760#define SQ_ENC_SOPC_FIELD 0x17e
2761#define SQ_ENC_SOPP_BITS 0xbf800000
2762#define SQ_ENC_SOPP_MASK 0xff800000
2763#define SQ_ENC_SOPP_FIELD 0x17f
2764#define SQ_ENC_SOPK_BITS 0xb0000000
2765#define SQ_ENC_SOPK_MASK 0xf0000000
2766#define SQ_ENC_SOPK_FIELD 0xb
2767#define SQ_ENC_SOP2_BITS 0x80000000
2768#define SQ_ENC_SOP2_MASK 0xc0000000
2769#define SQ_ENC_SOP2_FIELD 0x2
2770#define SQ_ENC_SMEM_BITS 0xc0000000
2771#define SQ_ENC_SMEM_MASK 0xfc000000
2772#define SQ_ENC_SMEM_FIELD 0x30
2773#define SQ_ENC_VOP1_BITS 0x7e000000
2774#define SQ_ENC_VOP1_MASK 0xfe000000
2775#define SQ_ENC_VOP1_FIELD 0x3f
2776#define SQ_ENC_VOPC_BITS 0x7c000000
2777#define SQ_ENC_VOPC_MASK 0xfe000000
2778#define SQ_ENC_VOPC_FIELD 0x3e
2779#define SQ_ENC_VOP2_BITS 0x0
2780#define SQ_ENC_VOP2_MASK 0x80000000
2781#define SQ_ENC_VOP2_FIELD 0x0
2782#define SQ_ENC_VINTRP_BITS 0xd4000000
2783#define SQ_ENC_VINTRP_MASK 0xfc000000
2784#define SQ_ENC_VINTRP_FIELD 0x35
2785#define SQ_ENC_VOP3_BITS 0xd0000000
2786#define SQ_ENC_VOP3_MASK 0xfc000000
2787#define SQ_ENC_VOP3_FIELD 0x34
2788#define SQ_ENC_DS_BITS 0xd8000000
2789#define SQ_ENC_DS_MASK 0xfc000000
2790#define SQ_ENC_DS_FIELD 0x36
2791#define SQ_ENC_MUBUF_BITS 0xe0000000
2792#define SQ_ENC_MUBUF_MASK 0xfc000000
2793#define SQ_ENC_MUBUF_FIELD 0x38
2794#define SQ_ENC_MTBUF_BITS 0xe8000000
2795#define SQ_ENC_MTBUF_MASK 0xfc000000
2796#define SQ_ENC_MTBUF_FIELD 0x3a
2797#define SQ_ENC_MIMG_BITS 0xf0000000
2798#define SQ_ENC_MIMG_MASK 0xfc000000
2799#define SQ_ENC_MIMG_FIELD 0x3c
2800#define SQ_ENC_EXP_BITS 0xc4000000
2801#define SQ_ENC_EXP_MASK 0xfc000000
2802#define SQ_ENC_EXP_FIELD 0x31
2803#define SQ_ENC_FLAT_BITS 0xdc000000
2804#define SQ_ENC_FLAT_MASK 0xfc000000
2805#define SQ_ENC_FLAT_FIELD 0x37
2806#define SQ_V_OP3_INTRP_OFFSET 0x274
2807#define SQ_WAITCNT_VM_SHIFT 0x0
2808#define SQ_SENDMSG_STREAMID_SIZE 0x2
2809#define SQ_V_OPC_COUNT 0x100
2810#define SQ_V_OP3_INTRP_COUNT 0xc
2811#define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x100
2812#define SQ_HWREG_OFFSET_SIZE 0x5
2813#define SQ_HWREG_OFFSET_SHIFT 0x6
2814#define SQ_V_OP3_3IN_OFFSET 0x1c0
2815#define SQ_NUM_ATTR 0x21
2816#define SQ_NUM_VGPR 0x100
2817#define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x4
2818#define SQ_SENDMSG_MSG_SIZE 0x4
2819#define SQ_NUM_TTMP 0xc
2820#define SQ_HWREG_ID_SIZE 0x6
2821#define SQ_SENDMSG_GSOP_SIZE 0x2
2822#define SQ_NUM_SGPR 0x66
2823#define SQ_EXP_NUM_MRT 0x8
2824#define SQ_SENDMSG_SYSTEM_SIZE 0x3
2825#define SQ_WAITCNT_LGKM_SHIFT 0x8
2826#define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x40
2827#define SQ_V_OP3_3IN_COUNT 0xb0
2828#define SQ_V_INTRP_COUNT 0x4
2829#define SQ_WAITCNT_EXP_SIZE 0x3
2830#define SQ_SENDMSG_SYSTEM_SHIFT 0x4
2831#define SQ_EXP_NUM_GDS 0x5
2832#define SQ_HWREG_SIZE_SHIFT 0xb
2833#define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x0
2834#define SQ_V_OP3_2IN_COUNT 0x80
2835#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x270
2836#define SQ_SENDMSG_MSG_SHIFT 0x0
2837#define SQ_WAITCNT_EXP_SHIFT 0x4
2838#define SQ_WAITCNT_VM_SIZE 0x4
2839#define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x140
2840#define SQ_SENDMSG_GSOP_SHIFT 0x4
2841#define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x80
2842#define SQ_SRC_VGPR_BIT 0x100
2843#define SQ_V_OP2_COUNT 0x40
2844#define SQ_EXP_NUM_PARAM 0x20
2845#define SQ_V_OP1_COUNT 0x80
2846#define SQ_SENDMSG_STREAMID_SHIFT 0x8
2847#define SQ_V_OP3_2IN_OFFSET 0x280
2848#define SQ_WAITCNT_LGKM_SIZE 0x4
2849#define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x100
2850#define SQ_EXP_NUM_POS 0x4
2851#define SQ_HWREG_SIZE_SIZE 0x5
2852#define SQ_HWREG_ID_SHIFT 0x0
2853#define SQ_S_MOV_B32 0x0
2854#define SQ_S_MOV_B64 0x1
2855#define SQ_S_CMOV_B32 0x2
2856#define SQ_S_CMOV_B64 0x3
2857#define SQ_S_NOT_B32 0x4
2858#define SQ_S_NOT_B64 0x5
2859#define SQ_S_WQM_B32 0x6
2860#define SQ_S_WQM_B64 0x7
2861#define SQ_S_BREV_B32 0x8
2862#define SQ_S_BREV_B64 0x9
2863#define SQ_S_BCNT0_I32_B32 0xa
2864#define SQ_S_BCNT0_I32_B64 0xb
2865#define SQ_S_BCNT1_I32_B32 0xc
2866#define SQ_S_BCNT1_I32_B64 0xd
2867#define SQ_S_FF0_I32_B32 0xe
2868#define SQ_S_FF0_I32_B64 0xf
2869#define SQ_S_FF1_I32_B32 0x10
2870#define SQ_S_FF1_I32_B64 0x11
2871#define SQ_S_FLBIT_I32_B32 0x12
2872#define SQ_S_FLBIT_I32_B64 0x13
2873#define SQ_S_FLBIT_I32 0x14
2874#define SQ_S_FLBIT_I32_I64 0x15
2875#define SQ_S_SEXT_I32_I8 0x16
2876#define SQ_S_SEXT_I32_I16 0x17
2877#define SQ_S_BITSET0_B32 0x18
2878#define SQ_S_BITSET0_B64 0x19
2879#define SQ_S_BITSET1_B32 0x1a
2880#define SQ_S_BITSET1_B64 0x1b
2881#define SQ_S_GETPC_B64 0x1c
2882#define SQ_S_SETPC_B64 0x1d
2883#define SQ_S_SWAPPC_B64 0x1e
2884#define SQ_S_RFE_B64 0x1f
2885#define SQ_S_AND_SAVEEXEC_B64 0x20
2886#define SQ_S_OR_SAVEEXEC_B64 0x21
2887#define SQ_S_XOR_SAVEEXEC_B64 0x22
2888#define SQ_S_ANDN2_SAVEEXEC_B64 0x23
2889#define SQ_S_ORN2_SAVEEXEC_B64 0x24
2890#define SQ_S_NAND_SAVEEXEC_B64 0x25
2891#define SQ_S_NOR_SAVEEXEC_B64 0x26
2892#define SQ_S_XNOR_SAVEEXEC_B64 0x27
2893#define SQ_S_QUADMASK_B32 0x28
2894#define SQ_S_QUADMASK_B64 0x29
2895#define SQ_S_MOVRELS_B32 0x2a
2896#define SQ_S_MOVRELS_B64 0x2b
2897#define SQ_S_MOVRELD_B32 0x2c
2898#define SQ_S_MOVRELD_B64 0x2d
2899#define SQ_S_CBRANCH_JOIN 0x2e
2900#define SQ_S_MOV_REGRD_B32 0x2f
2901#define SQ_S_ABS_I32 0x30
2902#define SQ_S_MOV_FED_B32 0x31
2903#define SQ_S_SET_GPR_IDX_IDX 0x32
2904#define SQ_ATTR0 0x0
2905#define SQ_S_MOVK_I32 0x0
2906#define SQ_S_CMOVK_I32 0x1
2907#define SQ_S_CMPK_EQ_I32 0x2
2908#define SQ_S_CMPK_LG_I32 0x3
2909#define SQ_S_CMPK_GT_I32 0x4
2910#define SQ_S_CMPK_GE_I32 0x5
2911#define SQ_S_CMPK_LT_I32 0x6
2912#define SQ_S_CMPK_LE_I32 0x7
2913#define SQ_S_CMPK_EQ_U32 0x8
2914#define SQ_S_CMPK_LG_U32 0x9
2915#define SQ_S_CMPK_GT_U32 0xa
2916#define SQ_S_CMPK_GE_U32 0xb
2917#define SQ_S_CMPK_LT_U32 0xc
2918#define SQ_S_CMPK_LE_U32 0xd
2919#define SQ_S_ADDK_I32 0xe
2920#define SQ_S_MULK_I32 0xf
2921#define SQ_S_CBRANCH_I_FORK 0x10
2922#define SQ_S_GETREG_B32 0x11
2923#define SQ_S_SETREG_B32 0x12
2924#define SQ_S_GETREG_REGRD_B32 0x13
2925#define SQ_S_SETREG_IMM32_B32 0x14
2926#define SQ_TBA_LO 0x6c
2927#define SQ_TBA_HI 0x6d
2928#define SQ_TMA_LO 0x6e
2929#define SQ_TMA_HI 0x6f
2930#define SQ_TTMP0 0x70
2931#define SQ_TTMP1 0x71
2932#define SQ_TTMP2 0x72
2933#define SQ_TTMP3 0x73
2934#define SQ_TTMP4 0x74
2935#define SQ_TTMP5 0x75
2936#define SQ_TTMP6 0x76
2937#define SQ_TTMP7 0x77
2938#define SQ_TTMP8 0x78
2939#define SQ_TTMP9 0x79
2940#define SQ_TTMP10 0x7a
2941#define SQ_TTMP11 0x7b
2942#define SQ_VGPR0 0x0
2943#define SQ_EXP 0x0
2944#define SQ_EXP_MRT0 0x0
2945#define SQ_EXP_MRTZ 0x8
2946#define SQ_EXP_NULL 0x9
2947#define SQ_EXP_POS0 0xc
2948#define SQ_EXP_PARAM0 0x20
2949#define SQ_CNT1 0x0
2950#define SQ_CNT2 0x1
2951#define SQ_CNT3 0x2
2952#define SQ_CNT4 0x3
2953#define SQ_S_LOAD_DWORD 0x0
2954#define SQ_S_LOAD_DWORDX2 0x1
2955#define SQ_S_LOAD_DWORDX4 0x2
2956#define SQ_S_LOAD_DWORDX8 0x3
2957#define SQ_S_LOAD_DWORDX16 0x4
2958#define SQ_S_BUFFER_LOAD_DWORD 0x8
2959#define SQ_S_BUFFER_LOAD_DWORDX2 0x9
2960#define SQ_S_BUFFER_LOAD_DWORDX4 0xa
2961#define SQ_S_BUFFER_LOAD_DWORDX8 0xb
2962#define SQ_S_BUFFER_LOAD_DWORDX16 0xc
2963#define SQ_S_STORE_DWORD 0x10
2964#define SQ_S_STORE_DWORDX2 0x11
2965#define SQ_S_STORE_DWORDX4 0x12
2966#define SQ_S_BUFFER_STORE_DWORD 0x18
2967#define SQ_S_BUFFER_STORE_DWORDX2 0x19
2968#define SQ_S_BUFFER_STORE_DWORDX4 0x1a
2969#define SQ_S_DCACHE_INV 0x20
2970#define SQ_S_DCACHE_WB 0x21
2971#define SQ_S_DCACHE_INV_VOL 0x22
2972#define SQ_S_DCACHE_WB_VOL 0x23
2973#define SQ_S_MEMTIME 0x24
2974#define SQ_S_MEMREALTIME 0x25
2975#define SQ_S_ATC_PROBE 0x26
2976#define SQ_S_ATC_PROBE_BUFFER 0x27
2977#define SQ_S_BUFFER_ATOMIC_SWAP 0x40
2978#define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x41
2979#define SQ_S_BUFFER_ATOMIC_ADD 0x42
2980#define SQ_S_BUFFER_ATOMIC_SUB 0x43
2981#define SQ_S_BUFFER_ATOMIC_SMIN 0x44
2982#define SQ_S_BUFFER_ATOMIC_UMIN 0x45
2983#define SQ_S_BUFFER_ATOMIC_SMAX 0x46
2984#define SQ_S_BUFFER_ATOMIC_UMAX 0x47
2985#define SQ_S_BUFFER_ATOMIC_AND 0x48
2986#define SQ_S_BUFFER_ATOMIC_OR 0x49
2987#define SQ_S_BUFFER_ATOMIC_XOR 0x4a
2988#define SQ_S_BUFFER_ATOMIC_INC 0x4b
2989#define SQ_S_BUFFER_ATOMIC_DEC 0x4c
2990#define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x60
2991#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x61
2992#define SQ_S_BUFFER_ATOMIC_ADD_X2 0x62
2993#define SQ_S_BUFFER_ATOMIC_SUB_X2 0x63
2994#define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x64
2995#define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x65
2996#define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x66
2997#define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x67
2998#define SQ_S_BUFFER_ATOMIC_AND_X2 0x68
2999#define SQ_S_BUFFER_ATOMIC_OR_X2 0x69
3000#define SQ_S_BUFFER_ATOMIC_XOR_X2 0x6a
3001#define SQ_S_BUFFER_ATOMIC_INC_X2 0x6b
3002#define SQ_S_BUFFER_ATOMIC_DEC_X2 0x6c
3003#define SQ_F 0x0
3004#define SQ_LT 0x1
3005#define SQ_EQ 0x2
3006#define SQ_LE 0x3
3007#define SQ_GT 0x4
3008#define SQ_LG 0x5
3009#define SQ_GE 0x6
3010#define SQ_O 0x7
3011#define SQ_U 0x8
3012#define SQ_NGE 0x9
3013#define SQ_NLG 0xa
3014#define SQ_NGT 0xb
3015#define SQ_NLE 0xc
3016#define SQ_NEQ 0xd
3017#define SQ_NLT 0xe
3018#define SQ_TRU 0xf
3019#define SQ_V_CMP_CLASS_F32 0x10
3020#define SQ_V_CMPX_CLASS_F32 0x11
3021#define SQ_V_CMP_CLASS_F64 0x12
3022#define SQ_V_CMPX_CLASS_F64 0x13
3023#define SQ_V_CMP_CLASS_F16 0x14
3024#define SQ_V_CMPX_CLASS_F16 0x15
3025#define SQ_V_CMP_F_F16 0x20
3026#define SQ_V_CMP_LT_F16 0x21
3027#define SQ_V_CMP_EQ_F16 0x22
3028#define SQ_V_CMP_LE_F16 0x23
3029#define SQ_V_CMP_GT_F16 0x24
3030#define SQ_V_CMP_LG_F16 0x25
3031#define SQ_V_CMP_GE_F16 0x26
3032#define SQ_V_CMP_O_F16 0x27
3033#define SQ_V_CMP_U_F16 0x28
3034#define SQ_V_CMP_NGE_F16 0x29
3035#define SQ_V_CMP_NLG_F16 0x2a
3036#define SQ_V_CMP_NGT_F16 0x2b
3037#define SQ_V_CMP_NLE_F16 0x2c
3038#define SQ_V_CMP_NEQ_F16 0x2d
3039#define SQ_V_CMP_NLT_F16 0x2e
3040#define SQ_V_CMP_TRU_F16 0x2f
3041#define SQ_V_CMPX_F_F16 0x30
3042#define SQ_V_CMPX_LT_F16 0x31
3043#define SQ_V_CMPX_EQ_F16 0x32
3044#define SQ_V_CMPX_LE_F16 0x33
3045#define SQ_V_CMPX_GT_F16 0x34
3046#define SQ_V_CMPX_LG_F16 0x35
3047#define SQ_V_CMPX_GE_F16 0x36
3048#define SQ_V_CMPX_O_F16 0x37
3049#define SQ_V_CMPX_U_F16 0x38
3050#define SQ_V_CMPX_NGE_F16 0x39
3051#define SQ_V_CMPX_NLG_F16 0x3a
3052#define SQ_V_CMPX_NGT_F16 0x3b
3053#define SQ_V_CMPX_NLE_F16 0x3c
3054#define SQ_V_CMPX_NEQ_F16 0x3d
3055#define SQ_V_CMPX_NLT_F16 0x3e
3056#define SQ_V_CMPX_TRU_F16 0x3f
3057#define SQ_V_CMP_F_F32 0x40
3058#define SQ_V_CMP_LT_F32 0x41
3059#define SQ_V_CMP_EQ_F32 0x42
3060#define SQ_V_CMP_LE_F32 0x43
3061#define SQ_V_CMP_GT_F32 0x44
3062#define SQ_V_CMP_LG_F32 0x45
3063#define SQ_V_CMP_GE_F32 0x46
3064#define SQ_V_CMP_O_F32 0x47
3065#define SQ_V_CMP_U_F32 0x48
3066#define SQ_V_CMP_NGE_F32 0x49
3067#define SQ_V_CMP_NLG_F32 0x4a
3068#define SQ_V_CMP_NGT_F32 0x4b
3069#define SQ_V_CMP_NLE_F32 0x4c
3070#define SQ_V_CMP_NEQ_F32 0x4d
3071#define SQ_V_CMP_NLT_F32 0x4e
3072#define SQ_V_CMP_TRU_F32 0x4f
3073#define SQ_V_CMPX_F_F32 0x50
3074#define SQ_V_CMPX_LT_F32 0x51
3075#define SQ_V_CMPX_EQ_F32 0x52
3076#define SQ_V_CMPX_LE_F32 0x53
3077#define SQ_V_CMPX_GT_F32 0x54
3078#define SQ_V_CMPX_LG_F32 0x55
3079#define SQ_V_CMPX_GE_F32 0x56
3080#define SQ_V_CMPX_O_F32 0x57
3081#define SQ_V_CMPX_U_F32 0x58
3082#define SQ_V_CMPX_NGE_F32 0x59
3083#define SQ_V_CMPX_NLG_F32 0x5a
3084#define SQ_V_CMPX_NGT_F32 0x5b
3085#define SQ_V_CMPX_NLE_F32 0x5c
3086#define SQ_V_CMPX_NEQ_F32 0x5d
3087#define SQ_V_CMPX_NLT_F32 0x5e
3088#define SQ_V_CMPX_TRU_F32 0x5f
3089#define SQ_V_CMP_F_F64 0x60
3090#define SQ_V_CMP_LT_F64 0x61
3091#define SQ_V_CMP_EQ_F64 0x62
3092#define SQ_V_CMP_LE_F64 0x63
3093#define SQ_V_CMP_GT_F64 0x64
3094#define SQ_V_CMP_LG_F64 0x65
3095#define SQ_V_CMP_GE_F64 0x66
3096#define SQ_V_CMP_O_F64 0x67
3097#define SQ_V_CMP_U_F64 0x68
3098#define SQ_V_CMP_NGE_F64 0x69
3099#define SQ_V_CMP_NLG_F64 0x6a
3100#define SQ_V_CMP_NGT_F64 0x6b
3101#define SQ_V_CMP_NLE_F64 0x6c
3102#define SQ_V_CMP_NEQ_F64 0x6d
3103#define SQ_V_CMP_NLT_F64 0x6e
3104#define SQ_V_CMP_TRU_F64 0x6f
3105#define SQ_V_CMPX_F_F64 0x70
3106#define SQ_V_CMPX_LT_F64 0x71
3107#define SQ_V_CMPX_EQ_F64 0x72
3108#define SQ_V_CMPX_LE_F64 0x73
3109#define SQ_V_CMPX_GT_F64 0x74
3110#define SQ_V_CMPX_LG_F64 0x75
3111#define SQ_V_CMPX_GE_F64 0x76
3112#define SQ_V_CMPX_O_F64 0x77
3113#define SQ_V_CMPX_U_F64 0x78
3114#define SQ_V_CMPX_NGE_F64 0x79
3115#define SQ_V_CMPX_NLG_F64 0x7a
3116#define SQ_V_CMPX_NGT_F64 0x7b
3117#define SQ_V_CMPX_NLE_F64 0x7c
3118#define SQ_V_CMPX_NEQ_F64 0x7d
3119#define SQ_V_CMPX_NLT_F64 0x7e
3120#define SQ_V_CMPX_TRU_F64 0x7f
3121#define SQ_V_CMP_F_I16 0xa0
3122#define SQ_V_CMP_LT_I16 0xa1
3123#define SQ_V_CMP_EQ_I16 0xa2
3124#define SQ_V_CMP_LE_I16 0xa3
3125#define SQ_V_CMP_GT_I16 0xa4
3126#define SQ_V_CMP_NE_I16 0xa5
3127#define SQ_V_CMP_GE_I16 0xa6
3128#define SQ_V_CMP_T_I16 0xa7
3129#define SQ_V_CMP_F_U16 0xa8
3130#define SQ_V_CMP_LT_U16 0xa9
3131#define SQ_V_CMP_EQ_U16 0xaa
3132#define SQ_V_CMP_LE_U16 0xab
3133#define SQ_V_CMP_GT_U16 0xac
3134#define SQ_V_CMP_NE_U16 0xad
3135#define SQ_V_CMP_GE_U16 0xae
3136#define SQ_V_CMP_T_U16 0xaf
3137#define SQ_V_CMPX_F_I16 0xb0
3138#define SQ_V_CMPX_LT_I16 0xb1
3139#define SQ_V_CMPX_EQ_I16 0xb2
3140#define SQ_V_CMPX_LE_I16 0xb3
3141#define SQ_V_CMPX_GT_I16 0xb4
3142#define SQ_V_CMPX_NE_I16 0xb5
3143#define SQ_V_CMPX_GE_I16 0xb6
3144#define SQ_V_CMPX_T_I16 0xb7
3145#define SQ_V_CMPX_F_U16 0xb8
3146#define SQ_V_CMPX_LT_U16 0xb9
3147#define SQ_V_CMPX_EQ_U16 0xba
3148#define SQ_V_CMPX_LE_U16 0xbb
3149#define SQ_V_CMPX_GT_U16 0xbc
3150#define SQ_V_CMPX_NE_U16 0xbd
3151#define SQ_V_CMPX_GE_U16 0xbe
3152#define SQ_V_CMPX_T_U16 0xbf
3153#define SQ_V_CMP_F_I32 0xc0
3154#define SQ_V_CMP_LT_I32 0xc1
3155#define SQ_V_CMP_EQ_I32 0xc2
3156#define SQ_V_CMP_LE_I32 0xc3
3157#define SQ_V_CMP_GT_I32 0xc4
3158#define SQ_V_CMP_NE_I32 0xc5
3159#define SQ_V_CMP_GE_I32 0xc6
3160#define SQ_V_CMP_T_I32 0xc7
3161#define SQ_V_CMP_F_U32 0xc8
3162#define SQ_V_CMP_LT_U32 0xc9
3163#define SQ_V_CMP_EQ_U32 0xca
3164#define SQ_V_CMP_LE_U32 0xcb
3165#define SQ_V_CMP_GT_U32 0xcc
3166#define SQ_V_CMP_NE_U32 0xcd
3167#define SQ_V_CMP_GE_U32 0xce
3168#define SQ_V_CMP_T_U32 0xcf
3169#define SQ_V_CMPX_F_I32 0xd0
3170#define SQ_V_CMPX_LT_I32 0xd1
3171#define SQ_V_CMPX_EQ_I32 0xd2
3172#define SQ_V_CMPX_LE_I32 0xd3
3173#define SQ_V_CMPX_GT_I32 0xd4
3174#define SQ_V_CMPX_NE_I32 0xd5
3175#define SQ_V_CMPX_GE_I32 0xd6
3176#define SQ_V_CMPX_T_I32 0xd7
3177#define SQ_V_CMPX_F_U32 0xd8
3178#define SQ_V_CMPX_LT_U32 0xd9
3179#define SQ_V_CMPX_EQ_U32 0xda
3180#define SQ_V_CMPX_LE_U32 0xdb
3181#define SQ_V_CMPX_GT_U32 0xdc
3182#define SQ_V_CMPX_NE_U32 0xdd
3183#define SQ_V_CMPX_GE_U32 0xde
3184#define SQ_V_CMPX_T_U32 0xdf
3185#define SQ_V_CMP_F_I64 0xe0
3186#define SQ_V_CMP_LT_I64 0xe1
3187#define SQ_V_CMP_EQ_I64 0xe2
3188#define SQ_V_CMP_LE_I64 0xe3
3189#define SQ_V_CMP_GT_I64 0xe4
3190#define SQ_V_CMP_NE_I64 0xe5
3191#define SQ_V_CMP_GE_I64 0xe6
3192#define SQ_V_CMP_T_I64 0xe7
3193#define SQ_V_CMP_F_U64 0xe8
3194#define SQ_V_CMP_LT_U64 0xe9
3195#define SQ_V_CMP_EQ_U64 0xea
3196#define SQ_V_CMP_LE_U64 0xeb
3197#define SQ_V_CMP_GT_U64 0xec
3198#define SQ_V_CMP_NE_U64 0xed
3199#define SQ_V_CMP_GE_U64 0xee
3200#define SQ_V_CMP_T_U64 0xef
3201#define SQ_V_CMPX_F_I64 0xf0
3202#define SQ_V_CMPX_LT_I64 0xf1
3203#define SQ_V_CMPX_EQ_I64 0xf2
3204#define SQ_V_CMPX_LE_I64 0xf3
3205#define SQ_V_CMPX_GT_I64 0xf4
3206#define SQ_V_CMPX_NE_I64 0xf5
3207#define SQ_V_CMPX_GE_I64 0xf6
3208#define SQ_V_CMPX_T_I64 0xf7
3209#define SQ_V_CMPX_F_U64 0xf8
3210#define SQ_V_CMPX_LT_U64 0xf9
3211#define SQ_V_CMPX_EQ_U64 0xfa
3212#define SQ_V_CMPX_LE_U64 0xfb
3213#define SQ_V_CMPX_GT_U64 0xfc
3214#define SQ_V_CMPX_NE_U64 0xfd
3215#define SQ_V_CMPX_GE_U64 0xfe
3216#define SQ_V_CMPX_T_U64 0xff
3217#define SQ_L1 0x1
3218#define SQ_L2 0x2
3219#define SQ_L3 0x3
3220#define SQ_L4 0x4
3221#define SQ_L5 0x5
3222#define SQ_L6 0x6
3223#define SQ_L7 0x7
3224#define SQ_L8 0x8
3225#define SQ_L9 0x9
3226#define SQ_L10 0xa
3227#define SQ_L11 0xb
3228#define SQ_L12 0xc
3229#define SQ_L13 0xd
3230#define SQ_L14 0xe
3231#define SQ_L15 0xf
3232#define SQ_SGPR0 0x0
3233#define SQ_SDWA_UNUSED_PAD 0x0
3234#define SQ_SDWA_UNUSED_SEXT 0x1
3235#define SQ_SDWA_UNUSED_PRESERVE 0x2
3236#define SQ_F 0x0
3237#define SQ_LT 0x1
3238#define SQ_EQ 0x2
3239#define SQ_LE 0x3
3240#define SQ_GT 0x4
3241#define SQ_NE 0x5
3242#define SQ_GE 0x6
3243#define SQ_T 0x7
3244#define SQ_SRC_64_INT 0xc0
3245#define SQ_SRC_M_1_INT 0xc1
3246#define SQ_SRC_M_2_INT 0xc2
3247#define SQ_SRC_M_3_INT 0xc3
3248#define SQ_SRC_M_4_INT 0xc4
3249#define SQ_SRC_M_5_INT 0xc5
3250#define SQ_SRC_M_6_INT 0xc6
3251#define SQ_SRC_M_7_INT 0xc7
3252#define SQ_SRC_M_8_INT 0xc8
3253#define SQ_SRC_M_9_INT 0xc9
3254#define SQ_SRC_M_10_INT 0xca
3255#define SQ_SRC_M_11_INT 0xcb
3256#define SQ_SRC_M_12_INT 0xcc
3257#define SQ_SRC_M_13_INT 0xcd
3258#define SQ_SRC_M_14_INT 0xce
3259#define SQ_SRC_M_15_INT 0xcf
3260#define SQ_SRC_M_16_INT 0xd0
3261#define SQ_SRC_0_5 0xf0
3262#define SQ_SRC_M_0_5 0xf1
3263#define SQ_SRC_1 0xf2
3264#define SQ_SRC_M_1 0xf3
3265#define SQ_SRC_2 0xf4
3266#define SQ_SRC_M_2 0xf5
3267#define SQ_SRC_4 0xf6
3268#define SQ_SRC_M_4 0xf7
3269#define SQ_SRC_INV_2PI 0xf8
3270#define SQ_SRC_0 0x80
3271#define SQ_SRC_1_INT 0x81
3272#define SQ_SRC_2_INT 0x82
3273#define SQ_SRC_3_INT 0x83
3274#define SQ_SRC_4_INT 0x84
3275#define SQ_SRC_5_INT 0x85
3276#define SQ_SRC_6_INT 0x86
3277#define SQ_SRC_7_INT 0x87
3278#define SQ_SRC_8_INT 0x88
3279#define SQ_SRC_9_INT 0x89
3280#define SQ_SRC_10_INT 0x8a
3281#define SQ_SRC_11_INT 0x8b
3282#define SQ_SRC_12_INT 0x8c
3283#define SQ_SRC_13_INT 0x8d
3284#define SQ_SRC_14_INT 0x8e
3285#define SQ_SRC_15_INT 0x8f
3286#define SQ_SRC_16_INT 0x90
3287#define SQ_SRC_17_INT 0x91
3288#define SQ_SRC_18_INT 0x92
3289#define SQ_SRC_19_INT 0x93
3290#define SQ_SRC_20_INT 0x94
3291#define SQ_SRC_21_INT 0x95
3292#define SQ_SRC_22_INT 0x96
3293#define SQ_SRC_23_INT 0x97
3294#define SQ_SRC_24_INT 0x98
3295#define SQ_SRC_25_INT 0x99
3296#define SQ_SRC_26_INT 0x9a
3297#define SQ_SRC_27_INT 0x9b
3298#define SQ_SRC_28_INT 0x9c
3299#define SQ_SRC_29_INT 0x9d
3300#define SQ_SRC_30_INT 0x9e
3301#define SQ_SRC_31_INT 0x9f
3302#define SQ_SRC_32_INT 0xa0
3303#define SQ_SRC_33_INT 0xa1
3304#define SQ_SRC_34_INT 0xa2
3305#define SQ_SRC_35_INT 0xa3
3306#define SQ_SRC_36_INT 0xa4
3307#define SQ_SRC_37_INT 0xa5
3308#define SQ_SRC_38_INT 0xa6
3309#define SQ_SRC_39_INT 0xa7
3310#define SQ_SRC_40_INT 0xa8
3311#define SQ_SRC_41_INT 0xa9
3312#define SQ_SRC_42_INT 0xaa
3313#define SQ_SRC_43_INT 0xab
3314#define SQ_SRC_44_INT 0xac
3315#define SQ_SRC_45_INT 0xad
3316#define SQ_SRC_46_INT 0xae
3317#define SQ_SRC_47_INT 0xaf
3318#define SQ_SRC_48_INT 0xb0
3319#define SQ_SRC_49_INT 0xb1
3320#define SQ_SRC_50_INT 0xb2
3321#define SQ_SRC_51_INT 0xb3
3322#define SQ_SRC_52_INT 0xb4
3323#define SQ_SRC_53_INT 0xb5
3324#define SQ_SRC_54_INT 0xb6
3325#define SQ_SRC_55_INT 0xb7
3326#define SQ_SRC_56_INT 0xb8
3327#define SQ_SRC_57_INT 0xb9
3328#define SQ_SRC_58_INT 0xba
3329#define SQ_SRC_59_INT 0xbb
3330#define SQ_SRC_60_INT 0xbc
3331#define SQ_SRC_61_INT 0xbd
3332#define SQ_SRC_62_INT 0xbe
3333#define SQ_SRC_63_INT 0xbf
3334#define SQ_DS_ADD_U32 0x0
3335#define SQ_DS_SUB_U32 0x1
3336#define SQ_DS_RSUB_U32 0x2
3337#define SQ_DS_INC_U32 0x3
3338#define SQ_DS_DEC_U32 0x4
3339#define SQ_DS_MIN_I32 0x5
3340#define SQ_DS_MAX_I32 0x6
3341#define SQ_DS_MIN_U32 0x7
3342#define SQ_DS_MAX_U32 0x8
3343#define SQ_DS_AND_B32 0x9
3344#define SQ_DS_OR_B32 0xa
3345#define SQ_DS_XOR_B32 0xb
3346#define SQ_DS_MSKOR_B32 0xc
3347#define SQ_DS_WRITE_B32 0xd
3348#define SQ_DS_WRITE2_B32 0xe
3349#define SQ_DS_WRITE2ST64_B32 0xf
3350#define SQ_DS_CMPST_B32 0x10
3351#define SQ_DS_CMPST_F32 0x11
3352#define SQ_DS_MIN_F32 0x12
3353#define SQ_DS_MAX_F32 0x13
3354#define SQ_DS_NOP 0x14
3355#define SQ_DS_ADD_F32 0x15
3356#define SQ_DS_WRITE_B8 0x1e
3357#define SQ_DS_WRITE_B16 0x1f
3358#define SQ_DS_ADD_RTN_U32 0x20
3359#define SQ_DS_SUB_RTN_U32 0x21
3360#define SQ_DS_RSUB_RTN_U32 0x22
3361#define SQ_DS_INC_RTN_U32 0x23
3362#define SQ_DS_DEC_RTN_U32 0x24
3363#define SQ_DS_MIN_RTN_I32 0x25
3364#define SQ_DS_MAX_RTN_I32 0x26
3365#define SQ_DS_MIN_RTN_U32 0x27
3366#define SQ_DS_MAX_RTN_U32 0x28
3367#define SQ_DS_AND_RTN_B32 0x29
3368#define SQ_DS_OR_RTN_B32 0x2a
3369#define SQ_DS_XOR_RTN_B32 0x2b
3370#define SQ_DS_MSKOR_RTN_B32 0x2c
3371#define SQ_DS_WRXCHG_RTN_B32 0x2d
3372#define SQ_DS_WRXCHG2_RTN_B32 0x2e
3373#define SQ_DS_WRXCHG2ST64_RTN_B32 0x2f
3374#define SQ_DS_CMPST_RTN_B32 0x30
3375#define SQ_DS_CMPST_RTN_F32 0x31
3376#define SQ_DS_MIN_RTN_F32 0x32
3377#define SQ_DS_MAX_RTN_F32 0x33
3378#define SQ_DS_WRAP_RTN_B32 0x34
3379#define SQ_DS_ADD_RTN_F32 0x35
3380#define SQ_DS_READ_B32 0x36
3381#define SQ_DS_READ2_B32 0x37
3382#define SQ_DS_READ2ST64_B32 0x38
3383#define SQ_DS_READ_I8 0x39
3384#define SQ_DS_READ_U8 0x3a
3385#define SQ_DS_READ_I16 0x3b
3386#define SQ_DS_READ_U16 0x3c
3387#define SQ_DS_SWIZZLE_B32 0x3d
3388#define SQ_DS_PERMUTE_B32 0x3e
3389#define SQ_DS_BPERMUTE_B32 0x3f
3390#define SQ_DS_ADD_U64 0x40
3391#define SQ_DS_SUB_U64 0x41
3392#define SQ_DS_RSUB_U64 0x42
3393#define SQ_DS_INC_U64 0x43
3394#define SQ_DS_DEC_U64 0x44
3395#define SQ_DS_MIN_I64 0x45
3396#define SQ_DS_MAX_I64 0x46
3397#define SQ_DS_MIN_U64 0x47
3398#define SQ_DS_MAX_U64 0x48
3399#define SQ_DS_AND_B64 0x49
3400#define SQ_DS_OR_B64 0x4a
3401#define SQ_DS_XOR_B64 0x4b
3402#define SQ_DS_MSKOR_B64 0x4c
3403#define SQ_DS_WRITE_B64 0x4d
3404#define SQ_DS_WRITE2_B64 0x4e
3405#define SQ_DS_WRITE2ST64_B64 0x4f
3406#define SQ_DS_CMPST_B64 0x50
3407#define SQ_DS_CMPST_F64 0x51
3408#define SQ_DS_MIN_F64 0x52
3409#define SQ_DS_MAX_F64 0x53
3410#define SQ_DS_ADD_RTN_U64 0x60
3411#define SQ_DS_SUB_RTN_U64 0x61
3412#define SQ_DS_RSUB_RTN_U64 0x62
3413#define SQ_DS_INC_RTN_U64 0x63
3414#define SQ_DS_DEC_RTN_U64 0x64
3415#define SQ_DS_MIN_RTN_I64 0x65
3416#define SQ_DS_MAX_RTN_I64 0x66
3417#define SQ_DS_MIN_RTN_U64 0x67
3418#define SQ_DS_MAX_RTN_U64 0x68
3419#define SQ_DS_AND_RTN_B64 0x69
3420#define SQ_DS_OR_RTN_B64 0x6a
3421#define SQ_DS_XOR_RTN_B64 0x6b
3422#define SQ_DS_MSKOR_RTN_B64 0x6c
3423#define SQ_DS_WRXCHG_RTN_B64 0x6d
3424#define SQ_DS_WRXCHG2_RTN_B64 0x6e
3425#define SQ_DS_WRXCHG2ST64_RTN_B64 0x6f
3426#define SQ_DS_CMPST_RTN_B64 0x70
3427#define SQ_DS_CMPST_RTN_F64 0x71
3428#define SQ_DS_MIN_RTN_F64 0x72
3429#define SQ_DS_MAX_RTN_F64 0x73
3430#define SQ_DS_READ_B64 0x76
3431#define SQ_DS_READ2_B64 0x77
3432#define SQ_DS_READ2ST64_B64 0x78
3433#define SQ_DS_CONDXCHG32_RTN_B64 0x7e
3434#define SQ_DS_ADD_SRC2_U32 0x80
3435#define SQ_DS_SUB_SRC2_U32 0x81
3436#define SQ_DS_RSUB_SRC2_U32 0x82
3437#define SQ_DS_INC_SRC2_U32 0x83
3438#define SQ_DS_DEC_SRC2_U32 0x84
3439#define SQ_DS_MIN_SRC2_I32 0x85
3440#define SQ_DS_MAX_SRC2_I32 0x86
3441#define SQ_DS_MIN_SRC2_U32 0x87
3442#define SQ_DS_MAX_SRC2_U32 0x88
3443#define SQ_DS_AND_SRC2_B32 0x89
3444#define SQ_DS_OR_SRC2_B32 0x8a
3445#define SQ_DS_XOR_SRC2_B32 0x8b
3446#define SQ_DS_WRITE_SRC2_B32 0x8d
3447#define SQ_DS_MIN_SRC2_F32 0x92
3448#define SQ_DS_MAX_SRC2_F32 0x93
3449#define SQ_DS_ADD_SRC2_F32 0x95
3450#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x98
3451#define SQ_DS_GWS_INIT 0x99
3452#define SQ_DS_GWS_SEMA_V 0x9a
3453#define SQ_DS_GWS_SEMA_BR 0x9b
3454#define SQ_DS_GWS_SEMA_P 0x9c
3455#define SQ_DS_GWS_BARRIER 0x9d
3456#define SQ_DS_CONSUME 0xbd
3457#define SQ_DS_APPEND 0xbe
3458#define SQ_DS_ORDERED_COUNT 0xbf
3459#define SQ_DS_ADD_SRC2_U64 0xc0
3460#define SQ_DS_SUB_SRC2_U64 0xc1
3461#define SQ_DS_RSUB_SRC2_U64 0xc2
3462#define SQ_DS_INC_SRC2_U64 0xc3
3463#define SQ_DS_DEC_SRC2_U64 0xc4
3464#define SQ_DS_MIN_SRC2_I64 0xc5
3465#define SQ_DS_MAX_SRC2_I64 0xc6
3466#define SQ_DS_MIN_SRC2_U64 0xc7
3467#define SQ_DS_MAX_SRC2_U64 0xc8
3468#define SQ_DS_AND_SRC2_B64 0xc9
3469#define SQ_DS_OR_SRC2_B64 0xca
3470#define SQ_DS_XOR_SRC2_B64 0xcb
3471#define SQ_DS_WRITE_SRC2_B64 0xcd
3472#define SQ_DS_MIN_SRC2_F64 0xd2
3473#define SQ_DS_MAX_SRC2_F64 0xd3
3474#define SQ_DS_WRITE_B96 0xde
3475#define SQ_DS_WRITE_B128 0xdf
3476#define SQ_DS_CONDXCHG32_RTN_B128 0xfd
3477#define SQ_DS_READ_B96 0xfe
3478#define SQ_DS_READ_B128 0xff
3479#define SQ_BUFFER_LOAD_FORMAT_X 0x0
3480#define SQ_BUFFER_LOAD_FORMAT_XY 0x1
3481#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2
3482#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x3
3483#define SQ_BUFFER_STORE_FORMAT_X 0x4
3484#define SQ_BUFFER_STORE_FORMAT_XY 0x5
3485#define SQ_BUFFER_STORE_FORMAT_XYZ 0x6
3486#define SQ_BUFFER_STORE_FORMAT_XYZW 0x7
3487#define SQ_BUFFER_LOAD_FORMAT_D16_X 0x8
3488#define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x9
3489#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0xa
3490#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0xb
3491#define SQ_BUFFER_STORE_FORMAT_D16_X 0xc
3492#define SQ_BUFFER_STORE_FORMAT_D16_XY 0xd
3493#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0xe
3494#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0xf
3495#define SQ_BUFFER_LOAD_UBYTE 0x10
3496#define SQ_BUFFER_LOAD_SBYTE 0x11
3497#define SQ_BUFFER_LOAD_USHORT 0x12
3498#define SQ_BUFFER_LOAD_SSHORT 0x13
3499#define SQ_BUFFER_LOAD_DWORD 0x14
3500#define SQ_BUFFER_LOAD_DWORDX2 0x15
3501#define SQ_BUFFER_LOAD_DWORDX3 0x16
3502#define SQ_BUFFER_LOAD_DWORDX4 0x17
3503#define SQ_BUFFER_STORE_BYTE 0x18
3504#define SQ_BUFFER_STORE_SHORT 0x1a
3505#define SQ_BUFFER_STORE_DWORD 0x1c
3506#define SQ_BUFFER_STORE_DWORDX2 0x1d
3507#define SQ_BUFFER_STORE_DWORDX3 0x1e
3508#define SQ_BUFFER_STORE_DWORDX4 0x1f
3509#define SQ_BUFFER_STORE_LDS_DWORD 0x3d
3510#define SQ_BUFFER_WBINVL1 0x3e
3511#define SQ_BUFFER_WBINVL1_VOL 0x3f
3512#define SQ_BUFFER_ATOMIC_SWAP 0x40
3513#define SQ_BUFFER_ATOMIC_CMPSWAP 0x41
3514#define SQ_BUFFER_ATOMIC_ADD 0x42
3515#define SQ_BUFFER_ATOMIC_SUB 0x43
3516#define SQ_BUFFER_ATOMIC_SMIN 0x44
3517#define SQ_BUFFER_ATOMIC_UMIN 0x45
3518#define SQ_BUFFER_ATOMIC_SMAX 0x46
3519#define SQ_BUFFER_ATOMIC_UMAX 0x47
3520#define SQ_BUFFER_ATOMIC_AND 0x48
3521#define SQ_BUFFER_ATOMIC_OR 0x49
3522#define SQ_BUFFER_ATOMIC_XOR 0x4a
3523#define SQ_BUFFER_ATOMIC_INC 0x4b
3524#define SQ_BUFFER_ATOMIC_DEC 0x4c
3525#define SQ_BUFFER_ATOMIC_SWAP_X2 0x60
3526#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x61
3527#define SQ_BUFFER_ATOMIC_ADD_X2 0x62
3528#define SQ_BUFFER_ATOMIC_SUB_X2 0x63
3529#define SQ_BUFFER_ATOMIC_SMIN_X2 0x64
3530#define SQ_BUFFER_ATOMIC_UMIN_X2 0x65
3531#define SQ_BUFFER_ATOMIC_SMAX_X2 0x66
3532#define SQ_BUFFER_ATOMIC_UMAX_X2 0x67
3533#define SQ_BUFFER_ATOMIC_AND_X2 0x68
3534#define SQ_BUFFER_ATOMIC_OR_X2 0x69
3535#define SQ_BUFFER_ATOMIC_XOR_X2 0x6a
3536#define SQ_BUFFER_ATOMIC_INC_X2 0x6b
3537#define SQ_BUFFER_ATOMIC_DEC_X2 0x6c
3538#define SQ_EXEC_LO 0x7e
3539#define SQ_EXEC_HI 0x7f
3540#define SQ_SRC_SCC 0xfd
3541#define SQ_OMOD_OFF 0x0
3542#define SQ_OMOD_M2 0x1
3543#define SQ_OMOD_M4 0x2
3544#define SQ_OMOD_D2 0x3
3545#define SQ_DPP_QUAD_PERM 0x0
3546#define SQ_DPP_ROW_SL1 0x101
3547#define SQ_DPP_ROW_SL2 0x102
3548#define SQ_DPP_ROW_SL3 0x103
3549#define SQ_DPP_ROW_SL4 0x104
3550#define SQ_DPP_ROW_SL5 0x105
3551#define SQ_DPP_ROW_SL6 0x106
3552#define SQ_DPP_ROW_SL7 0x107
3553#define SQ_DPP_ROW_SL8 0x108
3554#define SQ_DPP_ROW_SL9 0x109
3555#define SQ_DPP_ROW_SL10 0x10a
3556#define SQ_DPP_ROW_SL11 0x10b
3557#define SQ_DPP_ROW_SL12 0x10c
3558#define SQ_DPP_ROW_SL13 0x10d
3559#define SQ_DPP_ROW_SL14 0x10e
3560#define SQ_DPP_ROW_SL15 0x10f
3561#define SQ_DPP_ROW_SR1 0x111
3562#define SQ_DPP_ROW_SR2 0x112
3563#define SQ_DPP_ROW_SR3 0x113
3564#define SQ_DPP_ROW_SR4 0x114
3565#define SQ_DPP_ROW_SR5 0x115
3566#define SQ_DPP_ROW_SR6 0x116
3567#define SQ_DPP_ROW_SR7 0x117
3568#define SQ_DPP_ROW_SR8 0x118
3569#define SQ_DPP_ROW_SR9 0x119
3570#define SQ_DPP_ROW_SR10 0x11a
3571#define SQ_DPP_ROW_SR11 0x11b
3572#define SQ_DPP_ROW_SR12 0x11c
3573#define SQ_DPP_ROW_SR13 0x11d
3574#define SQ_DPP_ROW_SR14 0x11e
3575#define SQ_DPP_ROW_SR15 0x11f
3576#define SQ_DPP_ROW_RR1 0x121
3577#define SQ_DPP_ROW_RR2 0x122
3578#define SQ_DPP_ROW_RR3 0x123
3579#define SQ_DPP_ROW_RR4 0x124
3580#define SQ_DPP_ROW_RR5 0x125
3581#define SQ_DPP_ROW_RR6 0x126
3582#define SQ_DPP_ROW_RR7 0x127
3583#define SQ_DPP_ROW_RR8 0x128
3584#define SQ_DPP_ROW_RR9 0x129
3585#define SQ_DPP_ROW_RR10 0x12a
3586#define SQ_DPP_ROW_RR11 0x12b
3587#define SQ_DPP_ROW_RR12 0x12c
3588#define SQ_DPP_ROW_RR13 0x12d
3589#define SQ_DPP_ROW_RR14 0x12e
3590#define SQ_DPP_ROW_RR15 0x12f
3591#define SQ_DPP_WF_SL1 0x130
3592#define SQ_DPP_WF_RL1 0x134
3593#define SQ_DPP_WF_SR1 0x138
3594#define SQ_DPP_WF_RR1 0x13c
3595#define SQ_DPP_ROW_MIRROR 0x140
3596#define SQ_DPP_ROW_HALF_MIRROR 0x141
3597#define SQ_DPP_ROW_BCAST15 0x142
3598#define SQ_DPP_ROW_BCAST31 0x143
3599#define SQ_EXP_GDS0 0x18
3600#define SQ_GS_OP_NOP 0x0
3601#define SQ_GS_OP_CUT 0x1
3602#define SQ_GS_OP_EMIT 0x2
3603#define SQ_GS_OP_EMIT_CUT 0x3
3604#define SQ_IMAGE_LOAD 0x0
3605#define SQ_IMAGE_LOAD_MIP 0x1
3606#define SQ_IMAGE_LOAD_PCK 0x2
3607#define SQ_IMAGE_LOAD_PCK_SGN 0x3
3608#define SQ_IMAGE_LOAD_MIP_PCK 0x4
3609#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x5
3610#define SQ_IMAGE_STORE 0x8
3611#define SQ_IMAGE_STORE_MIP 0x9
3612#define SQ_IMAGE_STORE_PCK 0xa
3613#define SQ_IMAGE_STORE_MIP_PCK 0xb
3614#define SQ_IMAGE_GET_RESINFO 0xe
3615#define SQ_IMAGE_ATOMIC_SWAP 0x10
3616#define SQ_IMAGE_ATOMIC_CMPSWAP 0x11
3617#define SQ_IMAGE_ATOMIC_ADD 0x12
3618#define SQ_IMAGE_ATOMIC_SUB 0x13
3619#define SQ_IMAGE_ATOMIC_SMIN 0x14
3620#define SQ_IMAGE_ATOMIC_UMIN 0x15
3621#define SQ_IMAGE_ATOMIC_SMAX 0x16
3622#define SQ_IMAGE_ATOMIC_UMAX 0x17
3623#define SQ_IMAGE_ATOMIC_AND 0x18
3624#define SQ_IMAGE_ATOMIC_OR 0x19
3625#define SQ_IMAGE_ATOMIC_XOR 0x1a
3626#define SQ_IMAGE_ATOMIC_INC 0x1b
3627#define SQ_IMAGE_ATOMIC_DEC 0x1c
3628#define SQ_IMAGE_SAMPLE 0x20
3629#define SQ_IMAGE_SAMPLE_CL 0x21
3630#define SQ_IMAGE_SAMPLE_D 0x22
3631#define SQ_IMAGE_SAMPLE_D_CL 0x23
3632#define SQ_IMAGE_SAMPLE_L 0x24
3633#define SQ_IMAGE_SAMPLE_B 0x25
3634#define SQ_IMAGE_SAMPLE_B_CL 0x26
3635#define SQ_IMAGE_SAMPLE_LZ 0x27
3636#define SQ_IMAGE_SAMPLE_C 0x28
3637#define SQ_IMAGE_SAMPLE_C_CL 0x29
3638#define SQ_IMAGE_SAMPLE_C_D 0x2a
3639#define SQ_IMAGE_SAMPLE_C_D_CL 0x2b
3640#define SQ_IMAGE_SAMPLE_C_L 0x2c
3641#define SQ_IMAGE_SAMPLE_C_B 0x2d
3642#define SQ_IMAGE_SAMPLE_C_B_CL 0x2e
3643#define SQ_IMAGE_SAMPLE_C_LZ 0x2f
3644#define SQ_IMAGE_SAMPLE_O 0x30
3645#define SQ_IMAGE_SAMPLE_CL_O 0x31
3646#define SQ_IMAGE_SAMPLE_D_O 0x32
3647#define SQ_IMAGE_SAMPLE_D_CL_O 0x33
3648#define SQ_IMAGE_SAMPLE_L_O 0x34
3649#define SQ_IMAGE_SAMPLE_B_O 0x35
3650#define SQ_IMAGE_SAMPLE_B_CL_O 0x36
3651#define SQ_IMAGE_SAMPLE_LZ_O 0x37
3652#define SQ_IMAGE_SAMPLE_C_O 0x38
3653#define SQ_IMAGE_SAMPLE_C_CL_O 0x39
3654#define SQ_IMAGE_SAMPLE_C_D_O 0x3a
3655#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x3b
3656#define SQ_IMAGE_SAMPLE_C_L_O 0x3c
3657#define SQ_IMAGE_SAMPLE_C_B_O 0x3d
3658#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x3e
3659#define SQ_IMAGE_SAMPLE_C_LZ_O 0x3f
3660#define SQ_IMAGE_GATHER4 0x40
3661#define SQ_IMAGE_GATHER4_CL 0x41
3662#define SQ_IMAGE_GATHER4_L 0x44
3663#define SQ_IMAGE_GATHER4_B 0x45
3664#define SQ_IMAGE_GATHER4_B_CL 0x46
3665#define SQ_IMAGE_GATHER4_LZ 0x47
3666#define SQ_IMAGE_GATHER4_C 0x48
3667#define SQ_IMAGE_GATHER4_C_CL 0x49
3668#define SQ_IMAGE_GATHER4_C_L 0x4c
3669#define SQ_IMAGE_GATHER4_C_B 0x4d
3670#define SQ_IMAGE_GATHER4_C_B_CL 0x4e
3671#define SQ_IMAGE_GATHER4_C_LZ 0x4f
3672#define SQ_IMAGE_GATHER4_O 0x50
3673#define SQ_IMAGE_GATHER4_CL_O 0x51
3674#define SQ_IMAGE_GATHER4_L_O 0x54
3675#define SQ_IMAGE_GATHER4_B_O 0x55
3676#define SQ_IMAGE_GATHER4_B_CL_O 0x56
3677#define SQ_IMAGE_GATHER4_LZ_O 0x57
3678#define SQ_IMAGE_GATHER4_C_O 0x58
3679#define SQ_IMAGE_GATHER4_C_CL_O 0x59
3680#define SQ_IMAGE_GATHER4_C_L_O 0x5c
3681#define SQ_IMAGE_GATHER4_C_B_O 0x5d
3682#define SQ_IMAGE_GATHER4_C_B_CL_O 0x5e
3683#define SQ_IMAGE_GATHER4_C_LZ_O 0x5f
3684#define SQ_IMAGE_GET_LOD 0x60
3685#define SQ_IMAGE_SAMPLE_CD 0x68
3686#define SQ_IMAGE_SAMPLE_CD_CL 0x69
3687#define SQ_IMAGE_SAMPLE_C_CD 0x6a
3688#define SQ_IMAGE_SAMPLE_C_CD_CL 0x6b
3689#define SQ_IMAGE_SAMPLE_CD_O 0x6c
3690#define SQ_IMAGE_SAMPLE_CD_CL_O 0x6d
3691#define SQ_IMAGE_SAMPLE_C_CD_O 0x6e
3692#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6f
3693#define SQ_IMAGE_RSRC256 0x7e
3694#define SQ_IMAGE_SAMPLER 0x7f
3695#define SQ_SRC_VCCZ 0xfb
3696#define SQ_SRC_VGPR0 0x100
3697#define SQ_SDWA_BYTE_0 0x0
3698#define SQ_SDWA_BYTE_1 0x1
3699#define SQ_SDWA_BYTE_2 0x2
3700#define SQ_SDWA_BYTE_3 0x3
3701#define SQ_SDWA_WORD_0 0x4
3702#define SQ_SDWA_WORD_1 0x5
3703#define SQ_SDWA_DWORD 0x6
3704#define SQ_XNACK_MASK_LO 0x68
3705#define SQ_XNACK_MASK_HI 0x69
3706#define SQ_TBUFFER_LOAD_FORMAT_X 0x0
3707#define SQ_TBUFFER_LOAD_FORMAT_XY 0x1
3708#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2
3709#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x3
3710#define SQ_TBUFFER_STORE_FORMAT_X 0x4
3711#define SQ_TBUFFER_STORE_FORMAT_XY 0x5
3712#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x6
3713#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x7
3714#define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x8
3715#define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x9
3716#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0xa
3717#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0xb
3718#define SQ_TBUFFER_STORE_FORMAT_D16_X 0xc
3719#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0xd
3720#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0xe
3721#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0xf
3722#define SQ_CHAN_X 0x0
3723#define SQ_CHAN_Y 0x1
3724#define SQ_CHAN_Z 0x2
3725#define SQ_CHAN_W 0x3
3726#define SQ_V_NOP 0x0
3727#define SQ_V_MOV_B32 0x1
3728#define SQ_V_READFIRSTLANE_B32 0x2
3729#define SQ_V_CVT_I32_F64 0x3
3730#define SQ_V_CVT_F64_I32 0x4
3731#define SQ_V_CVT_F32_I32 0x5
3732#define SQ_V_CVT_F32_U32 0x6
3733#define SQ_V_CVT_U32_F32 0x7
3734#define SQ_V_CVT_I32_F32 0x8
3735#define SQ_V_MOV_FED_B32 0x9
3736#define SQ_V_CVT_F16_F32 0xa
3737#define SQ_V_CVT_F32_F16 0xb
3738#define SQ_V_CVT_RPI_I32_F32 0xc
3739#define SQ_V_CVT_FLR_I32_F32 0xd
3740#define SQ_V_CVT_OFF_F32_I4 0xe
3741#define SQ_V_CVT_F32_F64 0xf
3742#define SQ_V_CVT_F64_F32 0x10
3743#define SQ_V_CVT_F32_UBYTE0 0x11
3744#define SQ_V_CVT_F32_UBYTE1 0x12
3745#define SQ_V_CVT_F32_UBYTE2 0x13
3746#define SQ_V_CVT_F32_UBYTE3 0x14
3747#define SQ_V_CVT_U32_F64 0x15
3748#define SQ_V_CVT_F64_U32 0x16
3749#define SQ_V_TRUNC_F64 0x17
3750#define SQ_V_CEIL_F64 0x18
3751#define SQ_V_RNDNE_F64 0x19
3752#define SQ_V_FLOOR_F64 0x1a
3753#define SQ_V_FRACT_F32 0x1b
3754#define SQ_V_TRUNC_F32 0x1c
3755#define SQ_V_CEIL_F32 0x1d
3756#define SQ_V_RNDNE_F32 0x1e
3757#define SQ_V_FLOOR_F32 0x1f
3758#define SQ_V_EXP_F32 0x20
3759#define SQ_V_LOG_F32 0x21
3760#define SQ_V_RCP_F32 0x22
3761#define SQ_V_RCP_IFLAG_F32 0x23
3762#define SQ_V_RSQ_F32 0x24
3763#define SQ_V_RCP_F64 0x25
3764#define SQ_V_RSQ_F64 0x26
3765#define SQ_V_SQRT_F32 0x27
3766#define SQ_V_SQRT_F64 0x28
3767#define SQ_V_SIN_F32 0x29
3768#define SQ_V_COS_F32 0x2a
3769#define SQ_V_NOT_B32 0x2b
3770#define SQ_V_BFREV_B32 0x2c
3771#define SQ_V_FFBH_U32 0x2d
3772#define SQ_V_FFBL_B32 0x2e
3773#define SQ_V_FFBH_I32 0x2f
3774#define SQ_V_FREXP_EXP_I32_F64 0x30
3775#define SQ_V_FREXP_MANT_F64 0x31
3776#define SQ_V_FRACT_F64 0x32
3777#define SQ_V_FREXP_EXP_I32_F32 0x33
3778#define SQ_V_FREXP_MANT_F32 0x34
3779#define SQ_V_CLREXCP 0x35
3780#define SQ_V_MOVRELD_B32 0x36
3781#define SQ_V_MOVRELS_B32 0x37
3782#define SQ_V_MOVRELSD_B32 0x38
3783#define SQ_V_CVT_F16_U16 0x39
3784#define SQ_V_CVT_F16_I16 0x3a
3785#define SQ_V_CVT_U16_F16 0x3b
3786#define SQ_V_CVT_I16_F16 0x3c
3787#define SQ_V_RCP_F16 0x3d
3788#define SQ_V_SQRT_F16 0x3e
3789#define SQ_V_RSQ_F16 0x3f
3790#define SQ_V_LOG_F16 0x40
3791#define SQ_V_EXP_F16 0x41
3792#define SQ_V_FREXP_MANT_F16 0x42
3793#define SQ_V_FREXP_EXP_I16_F16 0x43
3794#define SQ_V_FLOOR_F16 0x44
3795#define SQ_V_CEIL_F16 0x45
3796#define SQ_V_TRUNC_F16 0x46
3797#define SQ_V_RNDNE_F16 0x47
3798#define SQ_V_FRACT_F16 0x48
3799#define SQ_V_SIN_F16 0x49
3800#define SQ_V_COS_F16 0x4a
3801#define SQ_V_EXP_LEGACY_F32 0x4b
3802#define SQ_V_LOG_LEGACY_F32 0x4c
3803#define SQ_SRC_SDWA 0xf9
3804#define SQ_V_OPC_OFFSET 0x0
3805#define SQ_V_OP2_OFFSET 0x100
3806#define SQ_V_OP1_OFFSET 0x140
3807#define SQ_V_INTRP_OFFSET 0x270
3808#define SQ_V_INTERP_P1_F32 0x0
3809#define SQ_V_INTERP_P2_F32 0x1
3810#define SQ_V_INTERP_MOV_F32 0x2
3811#define SQ_S_NOP 0x0
3812#define SQ_S_ENDPGM 0x1
3813#define SQ_S_BRANCH 0x2
3814#define SQ_S_WAKEUP 0x3
3815#define SQ_S_CBRANCH_SCC0 0x4
3816#define SQ_S_CBRANCH_SCC1 0x5
3817#define SQ_S_CBRANCH_VCCZ 0x6
3818#define SQ_S_CBRANCH_VCCNZ 0x7
3819#define SQ_S_CBRANCH_EXECZ 0x8
3820#define SQ_S_CBRANCH_EXECNZ 0x9
3821#define SQ_S_BARRIER 0xa
3822#define SQ_S_SETKILL 0xb
3823#define SQ_S_WAITCNT 0xc
3824#define SQ_S_SETHALT 0xd
3825#define SQ_S_SLEEP 0xe
3826#define SQ_S_SETPRIO 0xf
3827#define SQ_S_SENDMSG 0x10
3828#define SQ_S_SENDMSGHALT 0x11
3829#define SQ_S_TRAP 0x12
3830#define SQ_S_ICACHE_INV 0x13
3831#define SQ_S_INCPERFLEVEL 0x14
3832#define SQ_S_DECPERFLEVEL 0x15
3833#define SQ_S_TTRACEDATA 0x16
3834#define SQ_S_CBRANCH_CDBGSYS 0x17
3835#define SQ_S_CBRANCH_CDBGUSER 0x18
3836#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19
3837#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1a
3838#define SQ_S_ENDPGM_SAVED 0x1b
3839#define SQ_S_SET_GPR_IDX_OFF 0x1c
3840#define SQ_S_SET_GPR_IDX_MODE 0x1d
3841#define SQ_SRC_DPP 0xfa
3842#define SQ_SRC_LITERAL 0xff
3843#define SQ_VCC_LO 0x6a
3844#define SQ_VCC_HI 0x6b
3845#define SQ_PARAM_P10 0x0
3846#define SQ_PARAM_P20 0x1
3847#define SQ_PARAM_P0 0x2
3848#define SQ_SRC_LDS_DIRECT 0xfe
3849#define SQ_V_CNDMASK_B32 0x0
3850#define SQ_V_ADD_F32 0x1
3851#define SQ_V_SUB_F32 0x2
3852#define SQ_V_SUBREV_F32 0x3
3853#define SQ_V_MUL_LEGACY_F32 0x4
3854#define SQ_V_MUL_F32 0x5
3855#define SQ_V_MUL_I32_I24 0x6
3856#define SQ_V_MUL_HI_I32_I24 0x7
3857#define SQ_V_MUL_U32_U24 0x8
3858#define SQ_V_MUL_HI_U32_U24 0x9
3859#define SQ_V_MIN_F32 0xa
3860#define SQ_V_MAX_F32 0xb
3861#define SQ_V_MIN_I32 0xc
3862#define SQ_V_MAX_I32 0xd
3863#define SQ_V_MIN_U32 0xe
3864#define SQ_V_MAX_U32 0xf
3865#define SQ_V_LSHRREV_B32 0x10
3866#define SQ_V_ASHRREV_I32 0x11
3867#define SQ_V_LSHLREV_B32 0x12
3868#define SQ_V_AND_B32 0x13
3869#define SQ_V_OR_B32 0x14
3870#define SQ_V_XOR_B32 0x15
3871#define SQ_V_MAC_F32 0x16
3872#define SQ_V_MADMK_F32 0x17
3873#define SQ_V_MADAK_F32 0x18
3874#define SQ_V_ADD_U32 0x19
3875#define SQ_V_SUB_U32 0x1a
3876#define SQ_V_SUBREV_U32 0x1b
3877#define SQ_V_ADDC_U32 0x1c
3878#define SQ_V_SUBB_U32 0x1d
3879#define SQ_V_SUBBREV_U32 0x1e
3880#define SQ_V_ADD_F16 0x1f
3881#define SQ_V_SUB_F16 0x20
3882#define SQ_V_SUBREV_F16 0x21
3883#define SQ_V_MUL_F16 0x22
3884#define SQ_V_MAC_F16 0x23
3885#define SQ_V_MADMK_F16 0x24
3886#define SQ_V_MADAK_F16 0x25
3887#define SQ_V_ADD_U16 0x26
3888#define SQ_V_SUB_U16 0x27
3889#define SQ_V_SUBREV_U16 0x28
3890#define SQ_V_MUL_LO_U16 0x29
3891#define SQ_V_LSHLREV_B16 0x2a
3892#define SQ_V_LSHRREV_B16 0x2b
3893#define SQ_V_ASHRREV_I16 0x2c
3894#define SQ_V_MAX_F16 0x2d
3895#define SQ_V_MIN_F16 0x2e
3896#define SQ_V_MAX_U16 0x2f
3897#define SQ_V_MAX_I16 0x30
3898#define SQ_V_MIN_U16 0x31
3899#define SQ_V_MIN_I16 0x32
3900#define SQ_V_LDEXP_F16 0x33
3901#define SQ_FLAT_LOAD_UBYTE 0x10
3902#define SQ_FLAT_LOAD_SBYTE 0x11
3903#define SQ_FLAT_LOAD_USHORT 0x12
3904#define SQ_FLAT_LOAD_SSHORT 0x13
3905#define SQ_FLAT_LOAD_DWORD 0x14
3906#define SQ_FLAT_LOAD_DWORDX2 0x15
3907#define SQ_FLAT_LOAD_DWORDX3 0x16
3908#define SQ_FLAT_LOAD_DWORDX4 0x17
3909#define SQ_FLAT_STORE_BYTE 0x18
3910#define SQ_FLAT_STORE_SHORT 0x1a
3911#define SQ_FLAT_STORE_DWORD 0x1c
3912#define SQ_FLAT_STORE_DWORDX2 0x1d
3913#define SQ_FLAT_STORE_DWORDX3 0x1e
3914#define SQ_FLAT_STORE_DWORDX4 0x1f
3915#define SQ_FLAT_ATOMIC_SWAP 0x40
3916#define SQ_FLAT_ATOMIC_CMPSWAP 0x41
3917#define SQ_FLAT_ATOMIC_ADD 0x42
3918#define SQ_FLAT_ATOMIC_SUB 0x43
3919#define SQ_FLAT_ATOMIC_SMIN 0x44
3920#define SQ_FLAT_ATOMIC_UMIN 0x45
3921#define SQ_FLAT_ATOMIC_SMAX 0x46
3922#define SQ_FLAT_ATOMIC_UMAX 0x47
3923#define SQ_FLAT_ATOMIC_AND 0x48
3924#define SQ_FLAT_ATOMIC_OR 0x49
3925#define SQ_FLAT_ATOMIC_XOR 0x4a
3926#define SQ_FLAT_ATOMIC_INC 0x4b
3927#define SQ_FLAT_ATOMIC_DEC 0x4c
3928#define SQ_FLAT_ATOMIC_SWAP_X2 0x60
3929#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x61
3930#define SQ_FLAT_ATOMIC_ADD_X2 0x62
3931#define SQ_FLAT_ATOMIC_SUB_X2 0x63
3932#define SQ_FLAT_ATOMIC_SMIN_X2 0x64
3933#define SQ_FLAT_ATOMIC_UMIN_X2 0x65
3934#define SQ_FLAT_ATOMIC_SMAX_X2 0x66
3935#define SQ_FLAT_ATOMIC_UMAX_X2 0x67
3936#define SQ_FLAT_ATOMIC_AND_X2 0x68
3937#define SQ_FLAT_ATOMIC_OR_X2 0x69
3938#define SQ_FLAT_ATOMIC_XOR_X2 0x6a
3939#define SQ_FLAT_ATOMIC_INC_X2 0x6b
3940#define SQ_FLAT_ATOMIC_DEC_X2 0x6c
3941#define SQ_S_CMP_EQ_I32 0x0
3942#define SQ_S_CMP_LG_I32 0x1
3943#define SQ_S_CMP_GT_I32 0x2
3944#define SQ_S_CMP_GE_I32 0x3
3945#define SQ_S_CMP_LT_I32 0x4
3946#define SQ_S_CMP_LE_I32 0x5
3947#define SQ_S_CMP_EQ_U32 0x6
3948#define SQ_S_CMP_LG_U32 0x7
3949#define SQ_S_CMP_GT_U32 0x8
3950#define SQ_S_CMP_GE_U32 0x9
3951#define SQ_S_CMP_LT_U32 0xa
3952#define SQ_S_CMP_LE_U32 0xb
3953#define SQ_S_BITCMP0_B32 0xc
3954#define SQ_S_BITCMP1_B32 0xd
3955#define SQ_S_BITCMP0_B64 0xe
3956#define SQ_S_BITCMP1_B64 0xf
3957#define SQ_S_SETVSKIP 0x10
3958#define SQ_S_SET_GPR_IDX_ON 0x11
3959#define SQ_S_CMP_EQ_U64 0x12
3960#define SQ_S_CMP_LG_U64 0x13
3961#define SQ_M0 0x7c
3962#define SQ_V_MAD_LEGACY_F32 0x1c0
3963#define SQ_V_MAD_F32 0x1c1
3964#define SQ_V_MAD_I32_I24 0x1c2
3965#define SQ_V_MAD_U32_U24 0x1c3
3966#define SQ_V_CUBEID_F32 0x1c4
3967#define SQ_V_CUBESC_F32 0x1c5
3968#define SQ_V_CUBETC_F32 0x1c6
3969#define SQ_V_CUBEMA_F32 0x1c7
3970#define SQ_V_BFE_U32 0x1c8
3971#define SQ_V_BFE_I32 0x1c9
3972#define SQ_V_BFI_B32 0x1ca
3973#define SQ_V_FMA_F32 0x1cb
3974#define SQ_V_FMA_F64 0x1cc
3975#define SQ_V_LERP_U8 0x1cd
3976#define SQ_V_ALIGNBIT_B32 0x1ce
3977#define SQ_V_ALIGNBYTE_B32 0x1cf
3978#define SQ_V_MIN3_F32 0x1d0
3979#define SQ_V_MIN3_I32 0x1d1
3980#define SQ_V_MIN3_U32 0x1d2
3981#define SQ_V_MAX3_F32 0x1d3
3982#define SQ_V_MAX3_I32 0x1d4
3983#define SQ_V_MAX3_U32 0x1d5
3984#define SQ_V_MED3_F32 0x1d6
3985#define SQ_V_MED3_I32 0x1d7
3986#define SQ_V_MED3_U32 0x1d8
3987#define SQ_V_SAD_U8 0x1d9
3988#define SQ_V_SAD_HI_U8 0x1da
3989#define SQ_V_SAD_U16 0x1db
3990#define SQ_V_SAD_U32 0x1dc
3991#define SQ_V_CVT_PK_U8_F32 0x1dd
3992#define SQ_V_DIV_FIXUP_F32 0x1de
3993#define SQ_V_DIV_FIXUP_F64 0x1df
3994#define SQ_V_DIV_SCALE_F32 0x1e0
3995#define SQ_V_DIV_SCALE_F64 0x1e1
3996#define SQ_V_DIV_FMAS_F32 0x1e2
3997#define SQ_V_DIV_FMAS_F64 0x1e3
3998#define SQ_V_MSAD_U8 0x1e4
3999#define SQ_V_QSAD_PK_U16_U8 0x1e5
4000#define SQ_V_MQSAD_PK_U16_U8 0x1e6
4001#define SQ_V_MQSAD_U32_U8 0x1e7
4002#define SQ_V_MAD_U64_U32 0x1e8
4003#define SQ_V_MAD_I64_I32 0x1e9
4004#define SQ_V_MAD_F16 0x1ea
4005#define SQ_V_MAD_U16 0x1eb
4006#define SQ_V_MAD_I16 0x1ec
4007#define SQ_V_PERM_B32 0x1ed
4008#define SQ_V_FMA_F16 0x1ee
4009#define SQ_V_DIV_FIXUP_F16 0x1ef
4010#define SQ_V_CVT_PKACCUM_U8_F32 0x1f0
4011#define SQ_V_INTERP_P1LL_F16 0x274
4012#define SQ_V_INTERP_P1LV_F16 0x275
4013#define SQ_V_INTERP_P2_F16 0x276
4014#define SQ_V_ADD_F64 0x280
4015#define SQ_V_MUL_F64 0x281
4016#define SQ_V_MIN_F64 0x282
4017#define SQ_V_MAX_F64 0x283
4018#define SQ_V_LDEXP_F64 0x284
4019#define SQ_V_MUL_LO_U32 0x285
4020#define SQ_V_MUL_HI_U32 0x286
4021#define SQ_V_MUL_HI_I32 0x287
4022#define SQ_V_LDEXP_F32 0x288
4023#define SQ_V_READLANE_B32 0x289
4024#define SQ_V_WRITELANE_B32 0x28a
4025#define SQ_V_BCNT_U32_B32 0x28b
4026#define SQ_V_MBCNT_LO_U32_B32 0x28c
4027#define SQ_V_MBCNT_HI_U32_B32 0x28d
4028#define SQ_V_MAC_LEGACY_F32 0x28e
4029#define SQ_V_LSHLREV_B64 0x28f
4030#define SQ_V_LSHRREV_B64 0x290
4031#define SQ_V_ASHRREV_I64 0x291
4032#define SQ_V_TRIG_PREOP_F64 0x292
4033#define SQ_V_BFM_B32 0x293
4034#define SQ_V_CVT_PKNORM_I16_F32 0x294
4035#define SQ_V_CVT_PKNORM_U16_F32 0x295
4036#define SQ_V_CVT_PKRTZ_F16_F32 0x296
4037#define SQ_V_CVT_PK_U16_U32 0x297
4038#define SQ_V_CVT_PK_I16_I32 0x298
4039#define SQ_VCC_ALL 0x0
4040#define SQ_SRC_EXECZ 0xfc
4041#define SQ_FLAT_SCRATCH_LO 0x66
4042#define SQ_FLAT_SCRATCH_HI 0x67
4043#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x1
4044#define SQ_SYSMSG_OP_REG_RD 0x2
4045#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x3
4046#define SQ_SYSMSG_OP_TTRACE_PC 0x4
4047#define SQ_HW_REG_MODE 0x1
4048#define SQ_HW_REG_STATUS 0x2
4049#define SQ_HW_REG_TRAPSTS 0x3
4050#define SQ_HW_REG_HW_ID 0x4
4051#define SQ_HW_REG_GPR_ALLOC 0x5
4052#define SQ_HW_REG_LDS_ALLOC 0x6
4053#define SQ_HW_REG_IB_STS 0x7
4054#define SQ_HW_REG_PC_LO 0x8
4055#define SQ_HW_REG_PC_HI 0x9
4056#define SQ_HW_REG_INST_DW0 0xa
4057#define SQ_HW_REG_INST_DW1 0xb
4058#define SQ_HW_REG_IB_DBG0 0xc
4059#define SQ_HW_REG_IB_DBG1 0xd
4060#define SQ_DPP_BOUND_OFF 0x0
4061#define SQ_DPP_BOUND_ZERO 0x1
4062#define SQ_R1 0x1
4063#define SQ_R2 0x2
4064#define SQ_R3 0x3
4065#define SQ_R4 0x4
4066#define SQ_R5 0x5
4067#define SQ_R6 0x6
4068#define SQ_R7 0x7
4069#define SQ_R8 0x8
4070#define SQ_R9 0x9
4071#define SQ_R10 0xa
4072#define SQ_R11 0xb
4073#define SQ_R12 0xc
4074#define SQ_R13 0xd
4075#define SQ_R14 0xe
4076#define SQ_R15 0xf
4077#define SQ_S_ADD_U32 0x0
4078#define SQ_S_SUB_U32 0x1
4079#define SQ_S_ADD_I32 0x2
4080#define SQ_S_SUB_I32 0x3
4081#define SQ_S_ADDC_U32 0x4
4082#define SQ_S_SUBB_U32 0x5
4083#define SQ_S_MIN_I32 0x6
4084#define SQ_S_MIN_U32 0x7
4085#define SQ_S_MAX_I32 0x8
4086#define SQ_S_MAX_U32 0x9
4087#define SQ_S_CSELECT_B32 0xa
4088#define SQ_S_CSELECT_B64 0xb
4089#define SQ_S_AND_B32 0xc
4090#define SQ_S_AND_B64 0xd
4091#define SQ_S_OR_B32 0xe
4092#define SQ_S_OR_B64 0xf
4093#define SQ_S_XOR_B32 0x10
4094#define SQ_S_XOR_B64 0x11
4095#define SQ_S_ANDN2_B32 0x12
4096#define SQ_S_ANDN2_B64 0x13
4097#define SQ_S_ORN2_B32 0x14
4098#define SQ_S_ORN2_B64 0x15
4099#define SQ_S_NAND_B32 0x16
4100#define SQ_S_NAND_B64 0x17
4101#define SQ_S_NOR_B32 0x18
4102#define SQ_S_NOR_B64 0x19
4103#define SQ_S_XNOR_B32 0x1a
4104#define SQ_S_XNOR_B64 0x1b
4105#define SQ_S_LSHL_B32 0x1c
4106#define SQ_S_LSHL_B64 0x1d
4107#define SQ_S_LSHR_B32 0x1e
4108#define SQ_S_LSHR_B64 0x1f
4109#define SQ_S_ASHR_I32 0x20
4110#define SQ_S_ASHR_I64 0x21
4111#define SQ_S_BFM_B32 0x22
4112#define SQ_S_BFM_B64 0x23
4113#define SQ_S_MUL_I32 0x24
4114#define SQ_S_BFE_U32 0x25
4115#define SQ_S_BFE_I32 0x26
4116#define SQ_S_BFE_U64 0x27
4117#define SQ_S_BFE_I64 0x28
4118#define SQ_S_CBRANCH_G_FORK 0x29
4119#define SQ_S_ABSDIFF_I32 0x2a
4120#define SQ_S_RFE_RESTORE_B64 0x2b
4121#define SQ_MSG_INTERRUPT 0x1
4122#define SQ_MSG_GS 0x2
4123#define SQ_MSG_GS_DONE 0x3
4124#define SQ_MSG_SAVEWAVE 0x4
4125#define SQ_MSG_SYSMSG 0xf
4126typedef enum TEX_BORDER_COLOR_TYPE {
4127 TEX_BorderColor_TransparentBlack = 0x0,
4128 TEX_BorderColor_OpaqueBlack = 0x1,
4129 TEX_BorderColor_OpaqueWhite = 0x2,
4130 TEX_BorderColor_Register = 0x3,
4131} TEX_BORDER_COLOR_TYPE;
4132typedef enum TEX_CHROMA_KEY {
4133 TEX_ChromaKey_Disabled = 0x0,
4134 TEX_ChromaKey_Kill = 0x1,
4135 TEX_ChromaKey_Blend = 0x2,
4136 TEX_ChromaKey_RESERVED_3 = 0x3,
4137} TEX_CHROMA_KEY;
4138typedef enum TEX_CLAMP {
4139 TEX_Clamp_Repeat = 0x0,
4140 TEX_Clamp_Mirror = 0x1,
4141 TEX_Clamp_ClampToLast = 0x2,
4142 TEX_Clamp_MirrorOnceToLast = 0x3,
4143 TEX_Clamp_ClampHalfToBorder = 0x4,
4144 TEX_Clamp_MirrorOnceHalfToBorder = 0x5,
4145 TEX_Clamp_ClampToBorder = 0x6,
4146 TEX_Clamp_MirrorOnceToBorder = 0x7,
4147} TEX_CLAMP;
4148typedef enum TEX_COORD_TYPE {
4149 TEX_CoordType_Unnormalized = 0x0,
4150 TEX_CoordType_Normalized = 0x1,
4151} TEX_COORD_TYPE;
4152typedef enum TEX_DEPTH_COMPARE_FUNCTION {
4153 TEX_DepthCompareFunction_Never = 0x0,
4154 TEX_DepthCompareFunction_Less = 0x1,
4155 TEX_DepthCompareFunction_Equal = 0x2,
4156 TEX_DepthCompareFunction_LessEqual = 0x3,
4157 TEX_DepthCompareFunction_Greater = 0x4,
4158 TEX_DepthCompareFunction_NotEqual = 0x5,
4159 TEX_DepthCompareFunction_GreaterEqual = 0x6,
4160 TEX_DepthCompareFunction_Always = 0x7,
4161} TEX_DEPTH_COMPARE_FUNCTION;
4162typedef enum TEX_DIM {
4163 TEX_Dim_1D = 0x0,
4164 TEX_Dim_2D = 0x1,
4165 TEX_Dim_3D = 0x2,
4166 TEX_Dim_CubeMap = 0x3,
4167 TEX_Dim_1DArray = 0x4,
4168 TEX_Dim_2DArray = 0x5,
4169 TEX_Dim_2D_MSAA = 0x6,
4170 TEX_Dim_2DArray_MSAA = 0x7,
4171} TEX_DIM;
4172typedef enum TEX_FORMAT_COMP {
4173 TEX_FormatComp_Unsigned = 0x0,
4174 TEX_FormatComp_Signed = 0x1,
4175 TEX_FormatComp_UnsignedBiased = 0x2,
4176 TEX_FormatComp_RESERVED_3 = 0x3,
4177} TEX_FORMAT_COMP;
4178typedef enum TEX_MAX_ANISO_RATIO {
4179 TEX_MaxAnisoRatio_1to1 = 0x0,
4180 TEX_MaxAnisoRatio_2to1 = 0x1,
4181 TEX_MaxAnisoRatio_4to1 = 0x2,
4182 TEX_MaxAnisoRatio_8to1 = 0x3,
4183 TEX_MaxAnisoRatio_16to1 = 0x4,
4184 TEX_MaxAnisoRatio_RESERVED_5 = 0x5,
4185 TEX_MaxAnisoRatio_RESERVED_6 = 0x6,
4186 TEX_MaxAnisoRatio_RESERVED_7 = 0x7,
4187} TEX_MAX_ANISO_RATIO;
4188typedef enum TEX_MIP_FILTER {
4189 TEX_MipFilter_None = 0x0,
4190 TEX_MipFilter_Point = 0x1,
4191 TEX_MipFilter_Linear = 0x2,
4192 TEX_MipFilter_Point_Aniso_Adj = 0x3,
4193} TEX_MIP_FILTER;
4194typedef enum TEX_REQUEST_SIZE {
4195 TEX_RequestSize_32B = 0x0,
4196 TEX_RequestSize_64B = 0x1,
4197 TEX_RequestSize_128B = 0x2,
4198 TEX_RequestSize_2X64B = 0x3,
4199} TEX_REQUEST_SIZE;
4200typedef enum TEX_SAMPLER_TYPE {
4201 TEX_SamplerType_Invalid = 0x0,
4202 TEX_SamplerType_Valid = 0x1,
4203} TEX_SAMPLER_TYPE;
4204typedef enum TEX_XY_FILTER {
4205 TEX_XYFilter_Point = 0x0,
4206 TEX_XYFilter_Linear = 0x1,
4207 TEX_XYFilter_AnisoPoint = 0x2,
4208 TEX_XYFilter_AnisoLinear = 0x3,
4209} TEX_XY_FILTER;
4210typedef enum TEX_Z_FILTER {
4211 TEX_ZFilter_None = 0x0,
4212 TEX_ZFilter_Point = 0x1,
4213 TEX_ZFilter_Linear = 0x2,
4214 TEX_ZFilter_RESERVED_3 = 0x3,
4215} TEX_Z_FILTER;
4216typedef enum VTX_CLAMP {
4217 VTX_Clamp_ClampToZero = 0x0,
4218 VTX_Clamp_ClampToNAN = 0x1,
4219} VTX_CLAMP;
4220typedef enum VTX_FETCH_TYPE {
4221 VTX_FetchType_VertexData = 0x0,
4222 VTX_FetchType_InstanceData = 0x1,
4223 VTX_FetchType_NoIndexOffset = 0x2,
4224 VTX_FetchType_RESERVED_3 = 0x3,
4225} VTX_FETCH_TYPE;
4226typedef enum VTX_FORMAT_COMP_ALL {
4227 VTX_FormatCompAll_Unsigned = 0x0,
4228 VTX_FormatCompAll_Signed = 0x1,
4229} VTX_FORMAT_COMP_ALL;
4230typedef enum VTX_MEM_REQUEST_SIZE {
4231 VTX_MemRequestSize_32B = 0x0,
4232 VTX_MemRequestSize_64B = 0x1,
4233} VTX_MEM_REQUEST_SIZE;
4234typedef enum TVX_DATA_FORMAT {
4235 TVX_FMT_INVALID = 0x0,
4236 TVX_FMT_8 = 0x1,
4237 TVX_FMT_4_4 = 0x2,
4238 TVX_FMT_3_3_2 = 0x3,
4239 TVX_FMT_RESERVED_4 = 0x4,
4240 TVX_FMT_16 = 0x5,
4241 TVX_FMT_16_FLOAT = 0x6,
4242 TVX_FMT_8_8 = 0x7,
4243 TVX_FMT_5_6_5 = 0x8,
4244 TVX_FMT_6_5_5 = 0x9,
4245 TVX_FMT_1_5_5_5 = 0xa,
4246 TVX_FMT_4_4_4_4 = 0xb,
4247 TVX_FMT_5_5_5_1 = 0xc,
4248 TVX_FMT_32 = 0xd,
4249 TVX_FMT_32_FLOAT = 0xe,
4250 TVX_FMT_16_16 = 0xf,
4251 TVX_FMT_16_16_FLOAT = 0x10,
4252 TVX_FMT_8_24 = 0x11,
4253 TVX_FMT_8_24_FLOAT = 0x12,
4254 TVX_FMT_24_8 = 0x13,
4255 TVX_FMT_24_8_FLOAT = 0x14,
4256 TVX_FMT_10_11_11 = 0x15,
4257 TVX_FMT_10_11_11_FLOAT = 0x16,
4258 TVX_FMT_11_11_10 = 0x17,
4259 TVX_FMT_11_11_10_FLOAT = 0x18,
4260 TVX_FMT_2_10_10_10 = 0x19,
4261 TVX_FMT_8_8_8_8 = 0x1a,
4262 TVX_FMT_10_10_10_2 = 0x1b,
4263 TVX_FMT_X24_8_32_FLOAT = 0x1c,
4264 TVX_FMT_32_32 = 0x1d,
4265 TVX_FMT_32_32_FLOAT = 0x1e,
4266 TVX_FMT_16_16_16_16 = 0x1f,
4267 TVX_FMT_16_16_16_16_FLOAT = 0x20,
4268 TVX_FMT_RESERVED_33 = 0x21,
4269 TVX_FMT_32_32_32_32 = 0x22,
4270 TVX_FMT_32_32_32_32_FLOAT = 0x23,
4271 TVX_FMT_RESERVED_36 = 0x24,
4272 TVX_FMT_1 = 0x25,
4273 TVX_FMT_1_REVERSED = 0x26,
4274 TVX_FMT_GB_GR = 0x27,
4275 TVX_FMT_BG_RG = 0x28,
4276 TVX_FMT_32_AS_8 = 0x29,
4277 TVX_FMT_32_AS_8_8 = 0x2a,
4278 TVX_FMT_5_9_9_9_SHAREDEXP = 0x2b,
4279 TVX_FMT_8_8_8 = 0x2c,
4280 TVX_FMT_16_16_16 = 0x2d,
4281 TVX_FMT_16_16_16_FLOAT = 0x2e,
4282 TVX_FMT_32_32_32 = 0x2f,
4283 TVX_FMT_32_32_32_FLOAT = 0x30,
4284 TVX_FMT_BC1 = 0x31,
4285 TVX_FMT_BC2 = 0x32,
4286 TVX_FMT_BC3 = 0x33,
4287 TVX_FMT_BC4 = 0x34,
4288 TVX_FMT_BC5 = 0x35,
4289 TVX_FMT_APC0 = 0x36,
4290 TVX_FMT_APC1 = 0x37,
4291 TVX_FMT_APC2 = 0x38,
4292 TVX_FMT_APC3 = 0x39,
4293 TVX_FMT_APC4 = 0x3a,
4294 TVX_FMT_APC5 = 0x3b,
4295 TVX_FMT_APC6 = 0x3c,
4296 TVX_FMT_APC7 = 0x3d,
4297 TVX_FMT_CTX1 = 0x3e,
4298 TVX_FMT_RESERVED_63 = 0x3f,
4299} TVX_DATA_FORMAT;
4300typedef enum TVX_DST_SEL {
4301 TVX_DstSel_X = 0x0,
4302 TVX_DstSel_Y = 0x1,
4303 TVX_DstSel_Z = 0x2,
4304 TVX_DstSel_W = 0x3,
4305 TVX_DstSel_0f = 0x4,
4306 TVX_DstSel_1f = 0x5,
4307 TVX_DstSel_RESERVED_6 = 0x6,
4308 TVX_DstSel_Mask = 0x7,
4309} TVX_DST_SEL;
4310typedef enum TVX_ENDIAN_SWAP {
4311 TVX_EndianSwap_None = 0x0,
4312 TVX_EndianSwap_8in16 = 0x1,
4313 TVX_EndianSwap_8in32 = 0x2,
4314 TVX_EndianSwap_8in64 = 0x3,
4315} TVX_ENDIAN_SWAP;
4316typedef enum TVX_INST {
4317 TVX_Inst_NormalVertexFetch = 0x0,
4318 TVX_Inst_SemanticVertexFetch = 0x1,
4319 TVX_Inst_RESERVED_2 = 0x2,
4320 TVX_Inst_LD = 0x3,
4321 TVX_Inst_GetTextureResInfo = 0x4,
4322 TVX_Inst_GetNumberOfSamples = 0x5,
4323 TVX_Inst_GetLOD = 0x6,
4324 TVX_Inst_GetGradientsH = 0x7,
4325 TVX_Inst_GetGradientsV = 0x8,
4326 TVX_Inst_SetTextureOffsets = 0x9,
4327 TVX_Inst_KeepGradients = 0xa,
4328 TVX_Inst_SetGradientsH = 0xb,
4329 TVX_Inst_SetGradientsV = 0xc,
4330 TVX_Inst_Pass = 0xd,
4331 TVX_Inst_GetBufferResInfo = 0xe,
4332 TVX_Inst_RESERVED_15 = 0xf,
4333 TVX_Inst_Sample = 0x10,
4334 TVX_Inst_Sample_L = 0x11,
4335 TVX_Inst_Sample_LB = 0x12,
4336 TVX_Inst_Sample_LZ = 0x13,
4337 TVX_Inst_Sample_G = 0x14,
4338 TVX_Inst_Gather4 = 0x15,
4339 TVX_Inst_Sample_G_LB = 0x16,
4340 TVX_Inst_Gather4_O = 0x17,
4341 TVX_Inst_Sample_C = 0x18,
4342 TVX_Inst_Sample_C_L = 0x19,
4343 TVX_Inst_Sample_C_LB = 0x1a,
4344 TVX_Inst_Sample_C_LZ = 0x1b,
4345 TVX_Inst_Sample_C_G = 0x1c,
4346 TVX_Inst_Gather4_C = 0x1d,
4347 TVX_Inst_Sample_C_G_LB = 0x1e,
4348 TVX_Inst_Gather4_C_O = 0x1f,
4349} TVX_INST;
4350typedef enum TVX_NUM_FORMAT_ALL {
4351 TVX_NumFormatAll_Norm = 0x0,
4352 TVX_NumFormatAll_Int = 0x1,
4353 TVX_NumFormatAll_Scaled = 0x2,
4354 TVX_NumFormatAll_RESERVED_3 = 0x3,
4355} TVX_NUM_FORMAT_ALL;
4356typedef enum TVX_SRC_SEL {
4357 TVX_SrcSel_X = 0x0,
4358 TVX_SrcSel_Y = 0x1,
4359 TVX_SrcSel_Z = 0x2,
4360 TVX_SrcSel_W = 0x3,
4361 TVX_SrcSel_0f = 0x4,
4362 TVX_SrcSel_1f = 0x5,
4363} TVX_SRC_SEL;
4364typedef enum TVX_SRF_MODE_ALL {
4365 TVX_SRFModeAll_ZCMO = 0x0,
4366 TVX_SRFModeAll_NZ = 0x1,
4367} TVX_SRF_MODE_ALL;
4368typedef enum TVX_TYPE {
4369 TVX_Type_InvalidTextureResource = 0x0,
4370 TVX_Type_InvalidVertexBuffer = 0x1,
4371 TVX_Type_ValidTextureResource = 0x2,
4372 TVX_Type_ValidVertexBuffer = 0x3,
4373} TVX_TYPE;
4374typedef enum TC_OP_MASKS {
4375 TC_OP_MASK_FLUSH_DENROM = 0x8,
4376 TC_OP_MASK_64 = 0x20,
4377 TC_OP_MASK_NO_RTN = 0x40,
4378} TC_OP_MASKS;
4379typedef enum TC_OP {
4380 TC_OP_READ = 0x0,
4381 TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x1,
4382 TC_OP_ATOMIC_FMIN_RTN_32 = 0x2,
4383 TC_OP_ATOMIC_FMAX_RTN_32 = 0x3,
4384 TC_OP_RESERVED_FOP_RTN_32_0 = 0x4,
4385 TC_OP_RESERVED_FOP_RTN_32_1 = 0x5,
4386 TC_OP_RESERVED_FOP_RTN_32_2 = 0x6,
4387 TC_OP_ATOMIC_SWAP_RTN_32 = 0x7,
4388 TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x8,
4389 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x9,
4390 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0xa,
4391 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0xb,
4392 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0xc,
4393 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0xd,
4394 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0xe,
4395 TC_OP_ATOMIC_ADD_RTN_32 = 0xf,
4396 TC_OP_ATOMIC_SUB_RTN_32 = 0x10,
4397 TC_OP_ATOMIC_SMIN_RTN_32 = 0x11,
4398 TC_OP_ATOMIC_UMIN_RTN_32 = 0x12,
4399 TC_OP_ATOMIC_SMAX_RTN_32 = 0x13,
4400 TC_OP_ATOMIC_UMAX_RTN_32 = 0x14,
4401 TC_OP_ATOMIC_AND_RTN_32 = 0x15,
4402 TC_OP_ATOMIC_OR_RTN_32 = 0x16,
4403 TC_OP_ATOMIC_XOR_RTN_32 = 0x17,
4404 TC_OP_ATOMIC_INC_RTN_32 = 0x18,
4405 TC_OP_ATOMIC_DEC_RTN_32 = 0x19,
4406 TC_OP_WBINVL1_VOL = 0x1a,
4407 TC_OP_WBINVL1_SD = 0x1b,
4408 TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x1c,
4409 TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1d,
4410 TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x1e,
4411 TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x1f,
4412 TC_OP_WRITE = 0x20,
4413 TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x21,
4414 TC_OP_ATOMIC_FMIN_RTN_64 = 0x22,
4415 TC_OP_ATOMIC_FMAX_RTN_64 = 0x23,
4416 TC_OP_RESERVED_FOP_RTN_64_0 = 0x24,
4417 TC_OP_RESERVED_FOP_RTN_64_1 = 0x25,
4418 TC_OP_RESERVED_FOP_RTN_64_2 = 0x26,
4419 TC_OP_ATOMIC_SWAP_RTN_64 = 0x27,
4420 TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x28,
4421 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x29,
4422 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x2a,
4423 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x2b,
4424 TC_OP_WBINVL2_SD = 0x2c,
4425 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x2d,
4426 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x2e,
4427 TC_OP_ATOMIC_ADD_RTN_64 = 0x2f,
4428 TC_OP_ATOMIC_SUB_RTN_64 = 0x30,
4429 TC_OP_ATOMIC_SMIN_RTN_64 = 0x31,
4430 TC_OP_ATOMIC_UMIN_RTN_64 = 0x32,
4431 TC_OP_ATOMIC_SMAX_RTN_64 = 0x33,
4432 TC_OP_ATOMIC_UMAX_RTN_64 = 0x34,
4433 TC_OP_ATOMIC_AND_RTN_64 = 0x35,
4434 TC_OP_ATOMIC_OR_RTN_64 = 0x36,
4435 TC_OP_ATOMIC_XOR_RTN_64 = 0x37,
4436 TC_OP_ATOMIC_INC_RTN_64 = 0x38,
4437 TC_OP_ATOMIC_DEC_RTN_64 = 0x39,
4438 TC_OP_WBL2_NC = 0x3a,
4439 TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x3b,
4440 TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x3c,
4441 TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x3d,
4442 TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x3e,
4443 TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x3f,
4444 TC_OP_WBINVL1 = 0x40,
4445 TC_OP_ATOMIC_FCMPSWAP_32 = 0x41,
4446 TC_OP_ATOMIC_FMIN_32 = 0x42,
4447 TC_OP_ATOMIC_FMAX_32 = 0x43,
4448 TC_OP_RESERVED_FOP_32_0 = 0x44,
4449 TC_OP_RESERVED_FOP_32_1 = 0x45,
4450 TC_OP_RESERVED_FOP_32_2 = 0x46,
4451 TC_OP_ATOMIC_SWAP_32 = 0x47,
4452 TC_OP_ATOMIC_CMPSWAP_32 = 0x48,
4453 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x49,
4454 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x4a,
4455 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x4b,
4456 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x4c,
4457 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x4d,
4458 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x4e,
4459 TC_OP_ATOMIC_ADD_32 = 0x4f,
4460 TC_OP_ATOMIC_SUB_32 = 0x50,
4461 TC_OP_ATOMIC_SMIN_32 = 0x51,
4462 TC_OP_ATOMIC_UMIN_32 = 0x52,
4463 TC_OP_ATOMIC_SMAX_32 = 0x53,
4464 TC_OP_ATOMIC_UMAX_32 = 0x54,
4465 TC_OP_ATOMIC_AND_32 = 0x55,
4466 TC_OP_ATOMIC_OR_32 = 0x56,
4467 TC_OP_ATOMIC_XOR_32 = 0x57,
4468 TC_OP_ATOMIC_INC_32 = 0x58,
4469 TC_OP_ATOMIC_DEC_32 = 0x59,
4470 TC_OP_INVL2_NC = 0x5a,
4471 TC_OP_RESERVED_NON_FLOAT_32_0 = 0x5b,
4472 TC_OP_RESERVED_NON_FLOAT_32_1 = 0x5c,
4473 TC_OP_RESERVED_NON_FLOAT_32_2 = 0x5d,
4474 TC_OP_RESERVED_NON_FLOAT_32_3 = 0x5e,
4475 TC_OP_RESERVED_NON_FLOAT_32_4 = 0x5f,
4476 TC_OP_WBINVL2 = 0x60,
4477 TC_OP_ATOMIC_FCMPSWAP_64 = 0x61,
4478 TC_OP_ATOMIC_FMIN_64 = 0x62,
4479 TC_OP_ATOMIC_FMAX_64 = 0x63,
4480 TC_OP_RESERVED_FOP_64_0 = 0x64,
4481 TC_OP_RESERVED_FOP_64_1 = 0x65,
4482 TC_OP_RESERVED_FOP_64_2 = 0x66,
4483 TC_OP_ATOMIC_SWAP_64 = 0x67,
4484 TC_OP_ATOMIC_CMPSWAP_64 = 0x68,
4485 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x69,
4486 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x6a,
4487 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x6b,
4488 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x6c,
4489 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x6d,
4490 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x6e,
4491 TC_OP_ATOMIC_ADD_64 = 0x6f,
4492 TC_OP_ATOMIC_SUB_64 = 0x70,
4493 TC_OP_ATOMIC_SMIN_64 = 0x71,
4494 TC_OP_ATOMIC_UMIN_64 = 0x72,
4495 TC_OP_ATOMIC_SMAX_64 = 0x73,
4496 TC_OP_ATOMIC_UMAX_64 = 0x74,
4497 TC_OP_ATOMIC_AND_64 = 0x75,
4498 TC_OP_ATOMIC_OR_64 = 0x76,
4499 TC_OP_ATOMIC_XOR_64 = 0x77,
4500 TC_OP_ATOMIC_INC_64 = 0x78,
4501 TC_OP_ATOMIC_DEC_64 = 0x79,
4502 TC_OP_WBINVL2_NC = 0x7a,
4503 TC_OP_RESERVED_NON_FLOAT_64_0 = 0x7b,
4504 TC_OP_RESERVED_NON_FLOAT_64_1 = 0x7c,
4505 TC_OP_RESERVED_NON_FLOAT_64_2 = 0x7d,
4506 TC_OP_RESERVED_NON_FLOAT_64_3 = 0x7e,
4507 TC_OP_RESERVED_NON_FLOAT_64_4 = 0x7f,
4508} TC_OP;
4509typedef enum TC_CHUB_REQ_CREDITS_ENUM {
4510 TC_CHUB_REQ_CREDITS = 0x10,
4511} TC_CHUB_REQ_CREDITS_ENUM;
4512typedef enum CHUB_TC_RET_CREDITS_ENUM {
4513 CHUB_TC_RET_CREDITS = 0x20,
4514} CHUB_TC_RET_CREDITS_ENUM;
4515typedef enum TC_NACKS {
4516 TC_NACK_NO_FAULT = 0x0,
4517 TC_NACK_PAGE_FAULT = 0x1,
4518 TC_NACK_PROTECTION_FAULT = 0x2,
4519 TC_NACK_DATA_ERROR = 0x3,
4520} TC_NACKS;
4521typedef enum TCC_PERF_SEL {
4522 TCC_PERF_SEL_NONE = 0x0,
4523 TCC_PERF_SEL_CYCLE = 0x1,
4524 TCC_PERF_SEL_BUSY = 0x2,
4525 TCC_PERF_SEL_REQ = 0x3,
4526 TCC_PERF_SEL_STREAMING_REQ = 0x4,
4527 TCC_PERF_SEL_EXE_REQ = 0x5,
4528 TCC_PERF_SEL_COMPRESSED_REQ = 0x6,
4529 TCC_PERF_SEL_COMPRESSED_0_REQ = 0x7,
4530 TCC_PERF_SEL_METADATA_REQ = 0x8,
4531 TCC_PERF_SEL_NC_VIRTUAL_REQ = 0x9,
4532 TCC_PERF_SEL_NC_PHYSICAL_REQ = 0xa,
4533 TCC_PERF_SEL_UC_VIRTUAL_REQ = 0xb,
4534 TCC_PERF_SEL_UC_PHYSICAL_REQ = 0xc,
4535 TCC_PERF_SEL_CC_PHYSICAL_REQ = 0xd,
4536 TCC_PERF_SEL_PROBE = 0xe,
4537 TCC_PERF_SEL_READ = 0xf,
4538 TCC_PERF_SEL_WRITE = 0x10,
4539 TCC_PERF_SEL_ATOMIC = 0x11,
4540 TCC_PERF_SEL_HIT = 0x12,
4541 TCC_PERF_SEL_MISS = 0x13,
4542 TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x14,
4543 TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x15,
4544 TCC_PERF_SEL_WRITEBACK = 0x16,
4545 TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x17,
4546 TCC_PERF_SEL_SRC_FIFO_FULL = 0x18,
4547 TCC_PERF_SEL_HOLE_FIFO_FULL = 0x19,
4548 TCC_PERF_SEL_MC_WRREQ = 0x1a,
4549 TCC_PERF_SEL_MC_WRREQ_UNCACHED = 0x1b,
4550 TCC_PERF_SEL_MC_WRREQ_STALL = 0x1c,
4551 TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x1d,
4552 TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL = 0x1e,
4553 TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL = 0x1f,
4554 TCC_PERF_SEL_MC_WRREQ_LEVEL = 0x20,
4555 TCC_PERF_SEL_MC_ATOMIC = 0x21,
4556 TCC_PERF_SEL_MC_ATOMIC_LEVEL = 0x22,
4557 TCC_PERF_SEL_MC_RDREQ = 0x23,
4558 TCC_PERF_SEL_MC_RDREQ_UNCACHED = 0x24,
4559 TCC_PERF_SEL_MC_RDREQ_MDC = 0x25,
4560 TCC_PERF_SEL_MC_RDREQ_COMPRESSED = 0x26,
4561 TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL = 0x27,
4562 TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL = 0x28,
4563 TCC_PERF_SEL_MC_RDREQ_LEVEL = 0x29,
4564 TCC_PERF_SEL_TAG_STALL = 0x2a,
4565 TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x2b,
4566 TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x2c,
4567 TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL= 0x2d,
4568 TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL= 0x2e,
4569 TCC_PERF_SEL_TAG_PROBE_STALL = 0x2f,
4570 TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x30,
4571 TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x31,
4572 TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x32,
4573 TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x33,
4574 TCC_PERF_SEL_BUBBLE = 0x34,
4575 TCC_PERF_SEL_RETURN_ACK = 0x35,
4576 TCC_PERF_SEL_RETURN_DATA = 0x36,
4577 TCC_PERF_SEL_RETURN_HOLE = 0x37,
4578 TCC_PERF_SEL_RETURN_ACK_HOLE = 0x38,
4579 TCC_PERF_SEL_IB_REQ = 0x39,
4580 TCC_PERF_SEL_IB_STALL = 0x3a,
4581 TCC_PERF_SEL_IB_TAG_STALL = 0x3b,
4582 TCC_PERF_SEL_IB_MDC_STALL = 0x3c,
4583 TCC_PERF_SEL_TCA_LEVEL = 0x3d,
4584 TCC_PERF_SEL_HOLE_LEVEL = 0x3e,
4585 TCC_PERF_SEL_MC_RDRET_NACK = 0x3f,
4586 TCC_PERF_SEL_MC_WRRET_NACK = 0x40,
4587 TCC_PERF_SEL_NORMAL_WRITEBACK = 0x41,
4588 TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x42,
4589 TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x43,
4590 TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x44,
4591 TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x45,
4592 TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x46,
4593 TCC_PERF_SEL_NORMAL_EVICT = 0x47,
4594 TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x48,
4595 TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x49,
4596 TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x4a,
4597 TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x4b,
4598 TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x4c,
4599 TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x4d,
4600 TCC_PERF_SEL_PROBE_EVICT = 0x4e,
4601 TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x4f,
4602 TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x50,
4603 TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x51,
4604 TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x52,
4605 TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x53,
4606 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x54,
4607 TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x55,
4608 TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x56,
4609 TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x57,
4610 TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x58,
4611 TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x59,
4612 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x5a,
4613 TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x5b,
4614 TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x5c,
4615 TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x5d,
4616 TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x5e,
4617 TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x5f,
4618 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x60,
4619 TCC_PERF_SEL_MDC_REQ = 0x61,
4620 TCC_PERF_SEL_MDC_LEVEL = 0x62,
4621 TCC_PERF_SEL_MDC_TAG_HIT = 0x63,
4622 TCC_PERF_SEL_MDC_SECTOR_HIT = 0x64,
4623 TCC_PERF_SEL_MDC_SECTOR_MISS = 0x65,
4624 TCC_PERF_SEL_MDC_TAG_STALL = 0x66,
4625 TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL= 0x67,
4626 TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL= 0x68,
4627 TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL= 0x69,
4628 TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x6a,
4629 TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x6b,
4630 TCC_PERF_SEL_CLIENT0_REQ = 0x80,
4631 TCC_PERF_SEL_CLIENT1_REQ = 0x81,
4632 TCC_PERF_SEL_CLIENT2_REQ = 0x82,
4633 TCC_PERF_SEL_CLIENT3_REQ = 0x83,
4634 TCC_PERF_SEL_CLIENT4_REQ = 0x84,
4635 TCC_PERF_SEL_CLIENT5_REQ = 0x85,
4636 TCC_PERF_SEL_CLIENT6_REQ = 0x86,
4637 TCC_PERF_SEL_CLIENT7_REQ = 0x87,
4638 TCC_PERF_SEL_CLIENT8_REQ = 0x88,
4639 TCC_PERF_SEL_CLIENT9_REQ = 0x89,
4640 TCC_PERF_SEL_CLIENT10_REQ = 0x8a,
4641 TCC_PERF_SEL_CLIENT11_REQ = 0x8b,
4642 TCC_PERF_SEL_CLIENT12_REQ = 0x8c,
4643 TCC_PERF_SEL_CLIENT13_REQ = 0x8d,
4644 TCC_PERF_SEL_CLIENT14_REQ = 0x8e,
4645 TCC_PERF_SEL_CLIENT15_REQ = 0x8f,
4646 TCC_PERF_SEL_CLIENT16_REQ = 0x90,
4647 TCC_PERF_SEL_CLIENT17_REQ = 0x91,
4648 TCC_PERF_SEL_CLIENT18_REQ = 0x92,
4649 TCC_PERF_SEL_CLIENT19_REQ = 0x93,
4650 TCC_PERF_SEL_CLIENT20_REQ = 0x94,
4651 TCC_PERF_SEL_CLIENT21_REQ = 0x95,
4652 TCC_PERF_SEL_CLIENT22_REQ = 0x96,
4653 TCC_PERF_SEL_CLIENT23_REQ = 0x97,
4654 TCC_PERF_SEL_CLIENT24_REQ = 0x98,
4655 TCC_PERF_SEL_CLIENT25_REQ = 0x99,
4656 TCC_PERF_SEL_CLIENT26_REQ = 0x9a,
4657 TCC_PERF_SEL_CLIENT27_REQ = 0x9b,
4658 TCC_PERF_SEL_CLIENT28_REQ = 0x9c,
4659 TCC_PERF_SEL_CLIENT29_REQ = 0x9d,
4660 TCC_PERF_SEL_CLIENT30_REQ = 0x9e,
4661 TCC_PERF_SEL_CLIENT31_REQ = 0x9f,
4662 TCC_PERF_SEL_CLIENT32_REQ = 0xa0,
4663 TCC_PERF_SEL_CLIENT33_REQ = 0xa1,
4664 TCC_PERF_SEL_CLIENT34_REQ = 0xa2,
4665 TCC_PERF_SEL_CLIENT35_REQ = 0xa3,
4666 TCC_PERF_SEL_CLIENT36_REQ = 0xa4,
4667 TCC_PERF_SEL_CLIENT37_REQ = 0xa5,
4668 TCC_PERF_SEL_CLIENT38_REQ = 0xa6,
4669 TCC_PERF_SEL_CLIENT39_REQ = 0xa7,
4670 TCC_PERF_SEL_CLIENT40_REQ = 0xa8,
4671 TCC_PERF_SEL_CLIENT41_REQ = 0xa9,
4672 TCC_PERF_SEL_CLIENT42_REQ = 0xaa,
4673 TCC_PERF_SEL_CLIENT43_REQ = 0xab,
4674 TCC_PERF_SEL_CLIENT44_REQ = 0xac,
4675 TCC_PERF_SEL_CLIENT45_REQ = 0xad,
4676 TCC_PERF_SEL_CLIENT46_REQ = 0xae,
4677 TCC_PERF_SEL_CLIENT47_REQ = 0xaf,
4678 TCC_PERF_SEL_CLIENT48_REQ = 0xb0,
4679 TCC_PERF_SEL_CLIENT49_REQ = 0xb1,
4680 TCC_PERF_SEL_CLIENT50_REQ = 0xb2,
4681 TCC_PERF_SEL_CLIENT51_REQ = 0xb3,
4682 TCC_PERF_SEL_CLIENT52_REQ = 0xb4,
4683 TCC_PERF_SEL_CLIENT53_REQ = 0xb5,
4684 TCC_PERF_SEL_CLIENT54_REQ = 0xb6,
4685 TCC_PERF_SEL_CLIENT55_REQ = 0xb7,
4686 TCC_PERF_SEL_CLIENT56_REQ = 0xb8,
4687 TCC_PERF_SEL_CLIENT57_REQ = 0xb9,
4688 TCC_PERF_SEL_CLIENT58_REQ = 0xba,
4689 TCC_PERF_SEL_CLIENT59_REQ = 0xbb,
4690 TCC_PERF_SEL_CLIENT60_REQ = 0xbc,
4691 TCC_PERF_SEL_CLIENT61_REQ = 0xbd,
4692 TCC_PERF_SEL_CLIENT62_REQ = 0xbe,
4693 TCC_PERF_SEL_CLIENT63_REQ = 0xbf,
4694 TCC_PERF_SEL_CLIENT64_REQ = 0xc0,
4695 TCC_PERF_SEL_CLIENT65_REQ = 0xc1,
4696 TCC_PERF_SEL_CLIENT66_REQ = 0xc2,
4697 TCC_PERF_SEL_CLIENT67_REQ = 0xc3,
4698 TCC_PERF_SEL_CLIENT68_REQ = 0xc4,
4699 TCC_PERF_SEL_CLIENT69_REQ = 0xc5,
4700 TCC_PERF_SEL_CLIENT70_REQ = 0xc6,
4701 TCC_PERF_SEL_CLIENT71_REQ = 0xc7,
4702 TCC_PERF_SEL_CLIENT72_REQ = 0xc8,
4703 TCC_PERF_SEL_CLIENT73_REQ = 0xc9,
4704 TCC_PERF_SEL_CLIENT74_REQ = 0xca,
4705 TCC_PERF_SEL_CLIENT75_REQ = 0xcb,
4706 TCC_PERF_SEL_CLIENT76_REQ = 0xcc,
4707 TCC_PERF_SEL_CLIENT77_REQ = 0xcd,
4708 TCC_PERF_SEL_CLIENT78_REQ = 0xce,
4709 TCC_PERF_SEL_CLIENT79_REQ = 0xcf,
4710 TCC_PERF_SEL_CLIENT80_REQ = 0xd0,
4711 TCC_PERF_SEL_CLIENT81_REQ = 0xd1,
4712 TCC_PERF_SEL_CLIENT82_REQ = 0xd2,
4713 TCC_PERF_SEL_CLIENT83_REQ = 0xd3,
4714 TCC_PERF_SEL_CLIENT84_REQ = 0xd4,
4715 TCC_PERF_SEL_CLIENT85_REQ = 0xd5,
4716 TCC_PERF_SEL_CLIENT86_REQ = 0xd6,
4717 TCC_PERF_SEL_CLIENT87_REQ = 0xd7,
4718 TCC_PERF_SEL_CLIENT88_REQ = 0xd8,
4719 TCC_PERF_SEL_CLIENT89_REQ = 0xd9,
4720 TCC_PERF_SEL_CLIENT90_REQ = 0xda,
4721 TCC_PERF_SEL_CLIENT91_REQ = 0xdb,
4722 TCC_PERF_SEL_CLIENT92_REQ = 0xdc,
4723 TCC_PERF_SEL_CLIENT93_REQ = 0xdd,
4724 TCC_PERF_SEL_CLIENT94_REQ = 0xde,
4725 TCC_PERF_SEL_CLIENT95_REQ = 0xdf,
4726 TCC_PERF_SEL_CLIENT96_REQ = 0xe0,
4727 TCC_PERF_SEL_CLIENT97_REQ = 0xe1,
4728 TCC_PERF_SEL_CLIENT98_REQ = 0xe2,
4729 TCC_PERF_SEL_CLIENT99_REQ = 0xe3,
4730 TCC_PERF_SEL_CLIENT100_REQ = 0xe4,
4731 TCC_PERF_SEL_CLIENT101_REQ = 0xe5,
4732 TCC_PERF_SEL_CLIENT102_REQ = 0xe6,
4733 TCC_PERF_SEL_CLIENT103_REQ = 0xe7,
4734 TCC_PERF_SEL_CLIENT104_REQ = 0xe8,
4735 TCC_PERF_SEL_CLIENT105_REQ = 0xe9,
4736 TCC_PERF_SEL_CLIENT106_REQ = 0xea,
4737 TCC_PERF_SEL_CLIENT107_REQ = 0xeb,
4738 TCC_PERF_SEL_CLIENT108_REQ = 0xec,
4739 TCC_PERF_SEL_CLIENT109_REQ = 0xed,
4740 TCC_PERF_SEL_CLIENT110_REQ = 0xee,
4741 TCC_PERF_SEL_CLIENT111_REQ = 0xef,
4742 TCC_PERF_SEL_CLIENT112_REQ = 0xf0,
4743 TCC_PERF_SEL_CLIENT113_REQ = 0xf1,
4744 TCC_PERF_SEL_CLIENT114_REQ = 0xf2,
4745 TCC_PERF_SEL_CLIENT115_REQ = 0xf3,
4746 TCC_PERF_SEL_CLIENT116_REQ = 0xf4,
4747 TCC_PERF_SEL_CLIENT117_REQ = 0xf5,
4748 TCC_PERF_SEL_CLIENT118_REQ = 0xf6,
4749 TCC_PERF_SEL_CLIENT119_REQ = 0xf7,
4750 TCC_PERF_SEL_CLIENT120_REQ = 0xf8,
4751 TCC_PERF_SEL_CLIENT121_REQ = 0xf9,
4752 TCC_PERF_SEL_CLIENT122_REQ = 0xfa,
4753 TCC_PERF_SEL_CLIENT123_REQ = 0xfb,
4754 TCC_PERF_SEL_CLIENT124_REQ = 0xfc,
4755 TCC_PERF_SEL_CLIENT125_REQ = 0xfd,
4756 TCC_PERF_SEL_CLIENT126_REQ = 0xfe,
4757 TCC_PERF_SEL_CLIENT127_REQ = 0xff,
4758} TCC_PERF_SEL;
4759typedef enum TCA_PERF_SEL {
4760 TCA_PERF_SEL_NONE = 0x0,
4761 TCA_PERF_SEL_CYCLE = 0x1,
4762 TCA_PERF_SEL_BUSY = 0x2,
4763 TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x3,
4764 TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x4,
4765 TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x5,
4766 TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x6,
4767 TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x7,
4768 TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x8,
4769 TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x9,
4770 TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0xa,
4771 TCA_PERF_SEL_REQ_TCC0 = 0xb,
4772 TCA_PERF_SEL_REQ_TCC1 = 0xc,
4773 TCA_PERF_SEL_REQ_TCC2 = 0xd,
4774 TCA_PERF_SEL_REQ_TCC3 = 0xe,
4775 TCA_PERF_SEL_REQ_TCC4 = 0xf,
4776 TCA_PERF_SEL_REQ_TCC5 = 0x10,
4777 TCA_PERF_SEL_REQ_TCC6 = 0x11,
4778 TCA_PERF_SEL_REQ_TCC7 = 0x12,
4779 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x13,
4780 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x14,
4781 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x15,
4782 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x16,
4783 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x17,
4784 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x18,
4785 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x19,
4786 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x1a,
4787 TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x1b,
4788 TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x1c,
4789 TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d,
4790 TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x1e,
4791 TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x1f,
4792 TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x20,
4793 TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x21,
4794 TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x22,
4795} TCA_PERF_SEL;
4796typedef enum TA_TC_ADDR_MODES {
4797 TA_TC_ADDR_MODE_DEFAULT = 0x0,
4798 TA_TC_ADDR_MODE_COMP0 = 0x1,
4799 TA_TC_ADDR_MODE_COMP1 = 0x2,
4800 TA_TC_ADDR_MODE_COMP2 = 0x3,
4801 TA_TC_ADDR_MODE_COMP3 = 0x4,
4802 TA_TC_ADDR_MODE_UNALIGNED = 0x5,
4803 TA_TC_ADDR_MODE_BORDER_COLOR = 0x6,
4804} TA_TC_ADDR_MODES;
4805typedef enum TA_PERFCOUNT_SEL {
4806 TA_PERF_SEL_NULL = 0x0,
4807 TA_PERF_SEL_sh_fifo_busy = 0x1,
4808 TA_PERF_SEL_sh_fifo_cmd_busy = 0x2,
4809 TA_PERF_SEL_sh_fifo_addr_busy = 0x3,
4810 TA_PERF_SEL_sh_fifo_data_busy = 0x4,
4811 TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x5,
4812 TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x6,
4813 TA_PERF_SEL_gradient_busy = 0x7,
4814 TA_PERF_SEL_gradient_fifo_busy = 0x8,
4815 TA_PERF_SEL_lod_busy = 0x9,
4816 TA_PERF_SEL_lod_fifo_busy = 0xa,
4817 TA_PERF_SEL_addresser_busy = 0xb,
4818 TA_PERF_SEL_addresser_fifo_busy = 0xc,
4819 TA_PERF_SEL_aligner_busy = 0xd,
4820 TA_PERF_SEL_write_path_busy = 0xe,
4821 TA_PERF_SEL_ta_busy = 0xf,
4822 TA_PERF_SEL_sq_ta_cmd_cycles = 0x10,
4823 TA_PERF_SEL_sp_ta_addr_cycles = 0x11,
4824 TA_PERF_SEL_sp_ta_data_cycles = 0x12,
4825 TA_PERF_SEL_ta_fa_data_state_cycles = 0x13,
4826 TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x14,
4827 TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x15,
4828 TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16,
4829 TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17,
4830 TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18,
4831 TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19,
4832 TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a,
4833 TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b,
4834 TA_PERF_SEL_RESERVED_28 = 0x1c,
4835 TA_PERF_SEL_RESERVED_29 = 0x1d,
4836 TA_PERF_SEL_sh_fifo_addr_cycles = 0x1e,
4837 TA_PERF_SEL_sh_fifo_data_cycles = 0x1f,
4838 TA_PERF_SEL_total_wavefronts = 0x20,
4839 TA_PERF_SEL_gradient_cycles = 0x21,
4840 TA_PERF_SEL_walker_cycles = 0x22,
4841 TA_PERF_SEL_aligner_cycles = 0x23,
4842 TA_PERF_SEL_image_wavefronts = 0x24,
4843 TA_PERF_SEL_image_read_wavefronts = 0x25,
4844 TA_PERF_SEL_image_write_wavefronts = 0x26,
4845 TA_PERF_SEL_image_atomic_wavefronts = 0x27,
4846 TA_PERF_SEL_image_total_cycles = 0x28,
4847 TA_PERF_SEL_RESERVED_41 = 0x29,
4848 TA_PERF_SEL_RESERVED_42 = 0x2a,
4849 TA_PERF_SEL_RESERVED_43 = 0x2b,
4850 TA_PERF_SEL_buffer_wavefronts = 0x2c,
4851 TA_PERF_SEL_buffer_read_wavefronts = 0x2d,
4852 TA_PERF_SEL_buffer_write_wavefronts = 0x2e,
4853 TA_PERF_SEL_buffer_atomic_wavefronts = 0x2f,
4854 TA_PERF_SEL_buffer_coalescable_wavefronts = 0x30,
4855 TA_PERF_SEL_buffer_total_cycles = 0x31,
4856 TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32,
4857 TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33,
4858 TA_PERF_SEL_buffer_coalesced_read_cycles = 0x34,
4859 TA_PERF_SEL_buffer_coalesced_write_cycles = 0x35,
4860 TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x36,
4861 TA_PERF_SEL_addr_stalled_by_td_cycles = 0x37,
4862 TA_PERF_SEL_data_stalled_by_tc_cycles = 0x38,
4863 TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39,
4864 TA_PERF_SEL_addresser_stalled_cycles = 0x3a,
4865 TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b,
4866 TA_PERF_SEL_aniso_stalled_cycles = 0x3c,
4867 TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x3d,
4868 TA_PERF_SEL_deriv_stalled_cycles = 0x3e,
4869 TA_PERF_SEL_aniso_gt1_cycle_quads = 0x3f,
4870 TA_PERF_SEL_color_1_cycle_pixels = 0x40,
4871 TA_PERF_SEL_color_2_cycle_pixels = 0x41,
4872 TA_PERF_SEL_color_3_cycle_pixels = 0x42,
4873 TA_PERF_SEL_color_4_cycle_pixels = 0x43,
4874 TA_PERF_SEL_mip_1_cycle_pixels = 0x44,
4875 TA_PERF_SEL_mip_2_cycle_pixels = 0x45,
4876 TA_PERF_SEL_vol_1_cycle_pixels = 0x46,
4877 TA_PERF_SEL_vol_2_cycle_pixels = 0x47,
4878 TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x48,
4879 TA_PERF_SEL_mipmap_lod_0_samples = 0x49,
4880 TA_PERF_SEL_mipmap_lod_1_samples = 0x4a,
4881 TA_PERF_SEL_mipmap_lod_2_samples = 0x4b,
4882 TA_PERF_SEL_mipmap_lod_3_samples = 0x4c,
4883 TA_PERF_SEL_mipmap_lod_4_samples = 0x4d,
4884 TA_PERF_SEL_mipmap_lod_5_samples = 0x4e,
4885 TA_PERF_SEL_mipmap_lod_6_samples = 0x4f,
4886 TA_PERF_SEL_mipmap_lod_7_samples = 0x50,
4887 TA_PERF_SEL_mipmap_lod_8_samples = 0x51,
4888 TA_PERF_SEL_mipmap_lod_9_samples = 0x52,
4889 TA_PERF_SEL_mipmap_lod_10_samples = 0x53,
4890 TA_PERF_SEL_mipmap_lod_11_samples = 0x54,
4891 TA_PERF_SEL_mipmap_lod_12_samples = 0x55,
4892 TA_PERF_SEL_mipmap_lod_13_samples = 0x56,
4893 TA_PERF_SEL_mipmap_lod_14_samples = 0x57,
4894 TA_PERF_SEL_mipmap_invalid_samples = 0x58,
4895 TA_PERF_SEL_aniso_1_cycle_quads = 0x59,
4896 TA_PERF_SEL_aniso_2_cycle_quads = 0x5a,
4897 TA_PERF_SEL_aniso_4_cycle_quads = 0x5b,
4898 TA_PERF_SEL_aniso_6_cycle_quads = 0x5c,
4899 TA_PERF_SEL_aniso_8_cycle_quads = 0x5d,
4900 TA_PERF_SEL_aniso_10_cycle_quads = 0x5e,
4901 TA_PERF_SEL_aniso_12_cycle_quads = 0x5f,
4902 TA_PERF_SEL_aniso_14_cycle_quads = 0x60,
4903 TA_PERF_SEL_aniso_16_cycle_quads = 0x61,
4904 TA_PERF_SEL_write_path_input_cycles = 0x62,
4905 TA_PERF_SEL_write_path_output_cycles = 0x63,
4906 TA_PERF_SEL_flat_wavefronts = 0x64,
4907 TA_PERF_SEL_flat_read_wavefronts = 0x65,
4908 TA_PERF_SEL_flat_write_wavefronts = 0x66,
4909 TA_PERF_SEL_flat_atomic_wavefronts = 0x67,
4910 TA_PERF_SEL_flat_coalesceable_wavefronts = 0x68,
4911 TA_PERF_SEL_reg_sclk_vld = 0x69,
4912 TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6a,
4913 TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x6b,
4914 TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x6c,
4915 TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x6d,
4916 TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x6e,
4917 TA_PERF_SEL_xnack_on_phase0 = 0x6f,
4918 TA_PERF_SEL_xnack_on_phase1 = 0x70,
4919 TA_PERF_SEL_xnack_on_phase2 = 0x71,
4920 TA_PERF_SEL_xnack_on_phase3 = 0x72,
4921 TA_PERF_SEL_first_xnack_on_phase0 = 0x73,
4922 TA_PERF_SEL_first_xnack_on_phase1 = 0x74,
4923 TA_PERF_SEL_first_xnack_on_phase2 = 0x75,
4924 TA_PERF_SEL_first_xnack_on_phase3 = 0x76,
4925} TA_PERFCOUNT_SEL;
4926typedef enum TD_PERFCOUNT_SEL {
4927 TD_PERF_SEL_none = 0x0,
4928 TD_PERF_SEL_td_busy = 0x1,
4929 TD_PERF_SEL_input_busy = 0x2,
4930 TD_PERF_SEL_output_busy = 0x3,
4931 TD_PERF_SEL_lerp_busy = 0x4,
4932 TD_PERF_SEL_reg_sclk_vld = 0x5,
4933 TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6,
4934 TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x7,
4935 TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x8,
4936 TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x9,
4937 TD_PERF_SEL_tc_td_fifo_full = 0xa,
4938 TD_PERF_SEL_constant_state_full = 0xb,
4939 TD_PERF_SEL_sample_state_full = 0xc,
4940 TD_PERF_SEL_output_fifo_full = 0xd,
4941 TD_PERF_SEL_RESERVED_14 = 0xe,
4942 TD_PERF_SEL_tc_stall = 0xf,
4943 TD_PERF_SEL_pc_stall = 0x10,
4944 TD_PERF_SEL_gds_stall = 0x11,
4945 TD_PERF_SEL_RESERVED_18 = 0x12,
4946 TD_PERF_SEL_RESERVED_19 = 0x13,
4947 TD_PERF_SEL_gather4_wavefront = 0x14,
4948 TD_PERF_SEL_sample_c_wavefront = 0x15,
4949 TD_PERF_SEL_load_wavefront = 0x16,
4950 TD_PERF_SEL_atomic_wavefront = 0x17,
4951 TD_PERF_SEL_store_wavefront = 0x18,
4952 TD_PERF_SEL_ldfptr_wavefront = 0x19,
4953 TD_PERF_SEL_RESERVED_26 = 0x1a,
4954 TD_PERF_SEL_RESERVED_27 = 0x1b,
4955 TD_PERF_SEL_d16_en_wavefront = 0x1c,
4956 TD_PERF_SEL_bicubic_filter_wavefront = 0x1d,
4957 TD_PERF_SEL_bypass_filter_wavefront = 0x1e,
4958 TD_PERF_SEL_min_max_filter_wavefront = 0x1f,
4959 TD_PERF_SEL_coalescable_wavefront = 0x20,
4960 TD_PERF_SEL_coalesced_phase = 0x21,
4961 TD_PERF_SEL_four_phase_wavefront = 0x22,
4962 TD_PERF_SEL_eight_phase_wavefront = 0x23,
4963 TD_PERF_SEL_sixteen_phase_wavefront = 0x24,
4964 TD_PERF_SEL_four_phase_forward_wavefront = 0x25,
4965 TD_PERF_SEL_write_ack_wavefront = 0x26,
4966 TD_PERF_SEL_RESERVED_39 = 0x27,
4967 TD_PERF_SEL_user_defined_border = 0x28,
4968 TD_PERF_SEL_white_border = 0x29,
4969 TD_PERF_SEL_opaque_black_border = 0x2a,
4970 TD_PERF_SEL_RESERVED_43 = 0x2b,
4971 TD_PERF_SEL_RESERVED_44 = 0x2c,
4972 TD_PERF_SEL_nack = 0x2d,
4973 TD_PERF_SEL_td_sp_traffic = 0x2e,
4974 TD_PERF_SEL_consume_gds_traffic = 0x2f,
4975 TD_PERF_SEL_addresscmd_poison = 0x30,
4976 TD_PERF_SEL_data_poison = 0x31,
4977 TD_PERF_SEL_start_cycle_0 = 0x32,
4978 TD_PERF_SEL_start_cycle_1 = 0x33,
4979 TD_PERF_SEL_start_cycle_2 = 0x34,
4980 TD_PERF_SEL_start_cycle_3 = 0x35,
4981 TD_PERF_SEL_null_cycle_output = 0x36,
4982} TD_PERFCOUNT_SEL;
4983typedef enum TCP_PERFCOUNT_SELECT {
4984 TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x0,
4985 TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x1,
4986 TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2,
4987 TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x3,
4988 TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x4,
4989 TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x5,
4990 TCP_PERF_SEL_LOD_STALL_CYCLES = 0x6,
4991 TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x7,
4992 TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x8,
4993 TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x9,
4994 TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0xa,
4995 TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0xb,
4996 TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0xc,
4997 TCP_PERF_SEL_TCR_RDRET_STALL = 0xd,
4998 TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0xe,
4999 TCP_PERF_SEL_HOLE_READ_STALL = 0xf,
5000 TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x10,
5001 TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x11,
5002 TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x12,
5003 TCP_PERF_SEL_TCP_LATENCY = 0x13,
5004 TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x14,
5005 TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x15,
5006 TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x16,
5007 TCP_PERF_SEL_TCC_READ_REQ = 0x17,
5008 TCP_PERF_SEL_TCC_WRITE_REQ = 0x18,
5009 TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x19,
5010 TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x1a,
5011 TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x1b,
5012 TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x1c,
5013 TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d,
5014 TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x1e,
5015 TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x1f,
5016 TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x20,
5017 TCP_PERF_SEL_TOTAL_WBINVL1 = 0x21,
5018 TCP_PERF_SEL_IMG_READ_FMT_1 = 0x22,
5019 TCP_PERF_SEL_IMG_READ_FMT_8 = 0x23,
5020 TCP_PERF_SEL_IMG_READ_FMT_16 = 0x24,
5021 TCP_PERF_SEL_IMG_READ_FMT_32 = 0x25,
5022 TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x26,
5023 TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x27,
5024 TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x28,
5025 TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x29,
5026 TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x2a,
5027 TCP_PERF_SEL_IMG_READ_FMT_96 = 0x2b,
5028 TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x2c,
5029 TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x2d,
5030 TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x2e,
5031 TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x2f,
5032 TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x30,
5033 TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x31,
5034 TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x32,
5035 TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x33,
5036 TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x34,
5037 TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x35,
5038 TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x36,
5039 TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x37,
5040 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x38,
5041 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x39,
5042 TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x3a,
5043 TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x3b,
5044 TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x3c,
5045 TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x3d,
5046 TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x3e,
5047 TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x3f,
5048 TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x40,
5049 TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x41,
5050 TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x42,
5051 TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x43,
5052 TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x44,
5053 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x45,
5054 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x46,
5055 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x47,
5056 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x48,
5057 TCP_PERF_SEL_BUF_READ_FMT_8 = 0x49,
5058 TCP_PERF_SEL_BUF_READ_FMT_16 = 0x4a,
5059 TCP_PERF_SEL_BUF_READ_FMT_32 = 0x4b,
5060 TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x4c,
5061 TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x4d,
5062 TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x4e,
5063 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x4f,
5064 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x50,
5065 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x51,
5066 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x52,
5067 TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x53,
5068 TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x54,
5069 TCP_PERF_SEL_ARR_1D_THIN1 = 0x55,
5070 TCP_PERF_SEL_ARR_1D_THICK = 0x56,
5071 TCP_PERF_SEL_ARR_2D_THIN1 = 0x57,
5072 TCP_PERF_SEL_ARR_2D_THICK = 0x58,
5073 TCP_PERF_SEL_ARR_2D_XTHICK = 0x59,
5074 TCP_PERF_SEL_ARR_3D_THIN1 = 0x5a,
5075 TCP_PERF_SEL_ARR_3D_THICK = 0x5b,
5076 TCP_PERF_SEL_ARR_3D_XTHICK = 0x5c,
5077 TCP_PERF_SEL_DIM_1D = 0x5d,
5078 TCP_PERF_SEL_DIM_2D = 0x5e,
5079 TCP_PERF_SEL_DIM_3D = 0x5f,
5080 TCP_PERF_SEL_DIM_1D_ARRAY = 0x60,
5081 TCP_PERF_SEL_DIM_2D_ARRAY = 0x61,
5082 TCP_PERF_SEL_DIM_2D_MSAA = 0x62,
5083 TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x63,
5084 TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x64,
5085 TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x65,
5086 TCP_PERF_SEL_TA_TCP_STATE_READ = 0x66,
5087 TCP_PERF_SEL_TAGRAM0_REQ = 0x67,
5088 TCP_PERF_SEL_TAGRAM1_REQ = 0x68,
5089 TCP_PERF_SEL_TAGRAM2_REQ = 0x69,
5090 TCP_PERF_SEL_TAGRAM3_REQ = 0x6a,
5091 TCP_PERF_SEL_GATE_EN1 = 0x6b,
5092 TCP_PERF_SEL_GATE_EN2 = 0x6c,
5093 TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x6d,
5094 TCP_PERF_SEL_TCC_REQ = 0x6e,
5095 TCP_PERF_SEL_TCC_NON_READ_REQ = 0x6f,
5096 TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x70,
5097 TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x71,
5098 TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x72,
5099 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x73,
5100 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x74,
5101 TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x75,
5102 TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x76,
5103 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x77,
5104 TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x78,
5105 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x79,
5106 TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x7a,
5107 TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x7b,
5108 TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x7c,
5109 TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x7d,
5110 TCP_PERF_SEL_TOTAL_ACCESSES = 0x7e,
5111 TCP_PERF_SEL_TOTAL_READ = 0x7f,
5112 TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x80,
5113 TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x81,
5114 TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x82,
5115 TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x83,
5116 TCP_PERF_SEL_TOTAL_NON_READ = 0x84,
5117 TCP_PERF_SEL_TOTAL_WRITE = 0x85,
5118 TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x86,
5119 TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x87,
5120 TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x88,
5121 TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x89,
5122 TCP_PERF_SEL_DISPLAY_MICROTILING = 0x8a,
5123 TCP_PERF_SEL_THIN_MICROTILING = 0x8b,
5124 TCP_PERF_SEL_DEPTH_MICROTILING = 0x8c,
5125 TCP_PERF_SEL_ARR_PRT_THIN1 = 0x8d,
5126 TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x8e,
5127 TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x8f,
5128 TCP_PERF_SEL_ARR_PRT_THICK = 0x90,
5129 TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x91,
5130 TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x92,
5131 TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x93,
5132 TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x94,
5133 TCP_PERF_SEL_UNALIGNED = 0x95,
5134 TCP_PERF_SEL_ROTATED_MICROTILING = 0x96,
5135 TCP_PERF_SEL_THICK_MICROTILING = 0x97,
5136 TCP_PERF_SEL_ATC = 0x98,
5137 TCP_PERF_SEL_POWER_STALL = 0x99,
5138 TCP_PERF_SEL_RESERVED_154 = 0x9a,
5139 TCP_PERF_SEL_TCC_LRU_REQ = 0x9b,
5140 TCP_PERF_SEL_TCC_STREAM_REQ = 0x9c,
5141 TCP_PERF_SEL_TCC_NC_READ_REQ = 0x9d,
5142 TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x9e,
5143 TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x9f,
5144 TCP_PERF_SEL_TCC_UC_READ_REQ = 0xa0,
5145 TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0xa1,
5146 TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0xa2,
5147 TCP_PERF_SEL_TCC_CC_READ_REQ = 0xa3,
5148 TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0xa4,
5149 TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0xa5,
5150 TCP_PERF_SEL_TCC_DCC_REQ = 0xa6,
5151 TCP_PERF_SEL_TCC_PHYSICAL_REQ = 0xa7,
5152 TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0xa8,
5153 TCP_PERF_SEL_VOLATILE = 0xa9,
5154 TCP_PERF_SEL_TC_TA_XNACK_STALL = 0xaa,
5155 TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL = 0xab,
5156 TCP_PERF_SEL_SHOOTDOWN = 0xac,
5157 TCP_PERF_SEL_GATCL1_TRANSLATION_MISS = 0xad,
5158 TCP_PERF_SEL_GATCL1_PERMISSION_MISS = 0xae,
5159 TCP_PERF_SEL_GATCL1_REQUEST = 0xaf,
5160 TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX = 0xb0,
5161 TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT = 0xb1,
5162 TCP_PERF_SEL_GATCL1_LFIFO_FULL = 0xb2,
5163 TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES = 0xb3,
5164 TCP_PERF_SEL_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0xb4,
5165 TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT = 0xb5,
5166 TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL = 0xb6,
5167} TCP_PERFCOUNT_SELECT;
5168typedef enum TCP_CACHE_POLICIES {
5169 TCP_CACHE_POLICY_MISS_LRU = 0x0,
5170 TCP_CACHE_POLICY_MISS_EVICT = 0x1,
5171 TCP_CACHE_POLICY_HIT_LRU = 0x2,
5172 TCP_CACHE_POLICY_HIT_EVICT = 0x3,
5173} TCP_CACHE_POLICIES;
5174typedef enum TCP_CACHE_STORE_POLICIES {
5175 TCP_CACHE_STORE_POLICY_WT_LRU = 0x0,
5176 TCP_CACHE_STORE_POLICY_WT_EVICT = 0x1,
5177} TCP_CACHE_STORE_POLICIES;
5178typedef enum TCP_WATCH_MODES {
5179 TCP_WATCH_MODE_READ = 0x0,
5180 TCP_WATCH_MODE_NONREAD = 0x1,
5181 TCP_WATCH_MODE_ATOMIC = 0x2,
5182 TCP_WATCH_MODE_ALL = 0x3,
5183} TCP_WATCH_MODES;
5184typedef enum TCP_DSM_DATA_SEL {
5185 TCP_DSM_DISABLE = 0x0,
5186 TCP_DSM_SEL0 = 0x1,
5187 TCP_DSM_SEL1 = 0x2,
5188 TCP_DSM_SEL_BOTH = 0x3,
5189} TCP_DSM_DATA_SEL;
5190typedef enum TCP_DSM_SINGLE_WRITE {
5191 TCP_DSM_SINGLE_WRITE_EN = 0x1,
5192} TCP_DSM_SINGLE_WRITE;
5193typedef enum VGT_OUT_PRIM_TYPE {
5194 VGT_OUT_POINT = 0x0,
5195 VGT_OUT_LINE = 0x1,
5196 VGT_OUT_TRI = 0x2,
5197 VGT_OUT_RECT_V0 = 0x3,
5198 VGT_OUT_RECT_V1 = 0x4,
5199 VGT_OUT_RECT_V2 = 0x5,
5200 VGT_OUT_RECT_V3 = 0x6,
5201 VGT_OUT_RESERVED = 0x7,
5202 VGT_TE_QUAD = 0x8,
5203 VGT_TE_PRIM_INDEX_LINE = 0x9,
5204 VGT_TE_PRIM_INDEX_TRI = 0xa,
5205 VGT_TE_PRIM_INDEX_QUAD = 0xb,
5206 VGT_OUT_LINE_ADJ = 0xc,
5207 VGT_OUT_TRI_ADJ = 0xd,
5208 VGT_OUT_PATCH = 0xe,
5209} VGT_OUT_PRIM_TYPE;
5210typedef enum VGT_DI_PRIM_TYPE {
5211 DI_PT_NONE = 0x0,
5212 DI_PT_POINTLIST = 0x1,
5213 DI_PT_LINELIST = 0x2,
5214 DI_PT_LINESTRIP = 0x3,
5215 DI_PT_TRILIST = 0x4,
5216 DI_PT_TRIFAN = 0x5,
5217 DI_PT_TRISTRIP = 0x6,
5218 DI_PT_UNUSED_0 = 0x7,
5219 DI_PT_UNUSED_1 = 0x8,
5220 DI_PT_PATCH = 0x9,
5221 DI_PT_LINELIST_ADJ = 0xa,
5222 DI_PT_LINESTRIP_ADJ = 0xb,
5223 DI_PT_TRILIST_ADJ = 0xc,
5224 DI_PT_TRISTRIP_ADJ = 0xd,
5225 DI_PT_UNUSED_3 = 0xe,
5226 DI_PT_UNUSED_4 = 0xf,
5227 DI_PT_TRI_WITH_WFLAGS = 0x10,
5228 DI_PT_RECTLIST = 0x11,
5229 DI_PT_LINELOOP = 0x12,
5230 DI_PT_QUADLIST = 0x13,
5231 DI_PT_QUADSTRIP = 0x14,
5232 DI_PT_POLYGON = 0x15,
5233 DI_PT_2D_COPY_RECT_LIST_V0 = 0x16,
5234 DI_PT_2D_COPY_RECT_LIST_V1 = 0x17,
5235 DI_PT_2D_COPY_RECT_LIST_V2 = 0x18,
5236 DI_PT_2D_COPY_RECT_LIST_V3 = 0x19,
5237 DI_PT_2D_FILL_RECT_LIST = 0x1a,
5238 DI_PT_2D_LINE_STRIP = 0x1b,
5239 DI_PT_2D_TRI_STRIP = 0x1c,
5240} VGT_DI_PRIM_TYPE;
5241typedef enum VGT_DI_SOURCE_SELECT {
5242 DI_SRC_SEL_DMA = 0x0,
5243 DI_SRC_SEL_IMMEDIATE = 0x1,
5244 DI_SRC_SEL_AUTO_INDEX = 0x2,
5245 DI_SRC_SEL_RESERVED = 0x3,
5246} VGT_DI_SOURCE_SELECT;
5247typedef enum VGT_DI_MAJOR_MODE_SELECT {
5248 DI_MAJOR_MODE_0 = 0x0,
5249 DI_MAJOR_MODE_1 = 0x1,
5250} VGT_DI_MAJOR_MODE_SELECT;
5251typedef enum VGT_DI_INDEX_SIZE {
5252 DI_INDEX_SIZE_16_BIT = 0x0,
5253 DI_INDEX_SIZE_32_BIT = 0x1,
5254 DI_INDEX_SIZE_8_BIT = 0x2,
5255} VGT_DI_INDEX_SIZE;
5256typedef enum VGT_EVENT_TYPE {
5257 Reserved_0x00 = 0x0,
5258 SAMPLE_STREAMOUTSTATS1 = 0x1,
5259 SAMPLE_STREAMOUTSTATS2 = 0x2,
5260 SAMPLE_STREAMOUTSTATS3 = 0x3,
5261 CACHE_FLUSH_TS = 0x4,
5262 CONTEXT_DONE = 0x5,
5263 CACHE_FLUSH = 0x6,
5264 CS_PARTIAL_FLUSH = 0x7,
5265 VGT_STREAMOUT_SYNC = 0x8,
5266 Reserved_0x09 = 0x9,
5267 VGT_STREAMOUT_RESET = 0xa,
5268 END_OF_PIPE_INCR_DE = 0xb,
5269 END_OF_PIPE_IB_END = 0xc,
5270 RST_PIX_CNT = 0xd,
5271 Reserved_0x0E = 0xe,
5272 VS_PARTIAL_FLUSH = 0xf,
5273 PS_PARTIAL_FLUSH = 0x10,
5274 FLUSH_HS_OUTPUT = 0x11,
5275 FLUSH_LS_OUTPUT = 0x12,
5276 Reserved_0x13 = 0x13,
5277 CACHE_FLUSH_AND_INV_TS_EVENT = 0x14,
5278 ZPASS_DONE = 0x15,
5279 CACHE_FLUSH_AND_INV_EVENT = 0x16,
5280 PERFCOUNTER_START = 0x17,
5281 PERFCOUNTER_STOP = 0x18,
5282 PIPELINESTAT_START = 0x19,
5283 PIPELINESTAT_STOP = 0x1a,
5284 PERFCOUNTER_SAMPLE = 0x1b,
5285 FLUSH_ES_OUTPUT = 0x1c,
5286 FLUSH_GS_OUTPUT = 0x1d,
5287 SAMPLE_PIPELINESTAT = 0x1e,
5288 SO_VGTSTREAMOUT_FLUSH = 0x1f,
5289 SAMPLE_STREAMOUTSTATS = 0x20,
5290 RESET_VTX_CNT = 0x21,
5291 BLOCK_CONTEXT_DONE = 0x22,
5292 CS_CONTEXT_DONE = 0x23,
5293 VGT_FLUSH = 0x24,
5294 TGID_ROLLOVER = 0x25,
5295 SQ_NON_EVENT = 0x26,
5296 SC_SEND_DB_VPZ = 0x27,
5297 BOTTOM_OF_PIPE_TS = 0x28,
5298 FLUSH_SX_TS = 0x29,
5299 DB_CACHE_FLUSH_AND_INV = 0x2a,
5300 FLUSH_AND_INV_DB_DATA_TS = 0x2b,
5301 FLUSH_AND_INV_DB_META = 0x2c,
5302 FLUSH_AND_INV_CB_DATA_TS = 0x2d,
5303 FLUSH_AND_INV_CB_META = 0x2e,
5304 CS_DONE = 0x2f,
5305 PS_DONE = 0x30,
5306 FLUSH_AND_INV_CB_PIXEL_DATA = 0x31,
5307 SX_CB_RAT_ACK_REQUEST = 0x32,
5308 THREAD_TRACE_START = 0x33,
5309 THREAD_TRACE_STOP = 0x34,
5310 THREAD_TRACE_MARKER = 0x35,
5311 THREAD_TRACE_FLUSH = 0x36,
5312 THREAD_TRACE_FINISH = 0x37,
5313 PIXEL_PIPE_STAT_CONTROL = 0x38,
5314 PIXEL_PIPE_STAT_DUMP = 0x39,
5315 PIXEL_PIPE_STAT_RESET = 0x3a,
5316 CONTEXT_SUSPEND = 0x3b,
5317 OFFCHIP_HS_DEALLOC = 0x3c,
5318} VGT_EVENT_TYPE;
5319typedef enum VGT_DMA_SWAP_MODE {
5320 VGT_DMA_SWAP_NONE = 0x0,
5321 VGT_DMA_SWAP_16_BIT = 0x1,
5322 VGT_DMA_SWAP_32_BIT = 0x2,
5323 VGT_DMA_SWAP_WORD = 0x3,
5324} VGT_DMA_SWAP_MODE;
5325typedef enum VGT_INDEX_TYPE_MODE {
5326 VGT_INDEX_16 = 0x0,
5327 VGT_INDEX_32 = 0x1,
5328 VGT_INDEX_8 = 0x2,
5329} VGT_INDEX_TYPE_MODE;
5330typedef enum VGT_DMA_BUF_TYPE {
5331 VGT_DMA_BUF_MEM = 0x0,
5332 VGT_DMA_BUF_RING = 0x1,
5333 VGT_DMA_BUF_SETUP = 0x2,
5334 VGT_DMA_PTR_UPDATE = 0x3,
5335} VGT_DMA_BUF_TYPE;
5336typedef enum VGT_OUTPATH_SELECT {
5337 VGT_OUTPATH_VTX_REUSE = 0x0,
5338 VGT_OUTPATH_TESS_EN = 0x1,
5339 VGT_OUTPATH_PASSTHRU = 0x2,
5340 VGT_OUTPATH_GS_BLOCK = 0x3,
5341 VGT_OUTPATH_HS_BLOCK = 0x4,
5342} VGT_OUTPATH_SELECT;
5343typedef enum VGT_GRP_PRIM_TYPE {
5344 VGT_GRP_3D_POINT = 0x0,
5345 VGT_GRP_3D_LINE = 0x1,
5346 VGT_GRP_3D_TRI = 0x2,
5347 VGT_GRP_3D_RECT = 0x3,
5348 VGT_GRP_3D_QUAD = 0x4,
5349 VGT_GRP_2D_COPY_RECT_V0 = 0x5,
5350 VGT_GRP_2D_COPY_RECT_V1 = 0x6,
5351 VGT_GRP_2D_COPY_RECT_V2 = 0x7,
5352 VGT_GRP_2D_COPY_RECT_V3 = 0x8,
5353 VGT_GRP_2D_FILL_RECT = 0x9,
5354 VGT_GRP_2D_LINE = 0xa,
5355 VGT_GRP_2D_TRI = 0xb,
5356 VGT_GRP_PRIM_INDEX_LINE = 0xc,
5357 VGT_GRP_PRIM_INDEX_TRI = 0xd,
5358 VGT_GRP_PRIM_INDEX_QUAD = 0xe,
5359 VGT_GRP_3D_LINE_ADJ = 0xf,
5360 VGT_GRP_3D_TRI_ADJ = 0x10,
5361 VGT_GRP_3D_PATCH = 0x11,
5362} VGT_GRP_PRIM_TYPE;
5363typedef enum VGT_GRP_PRIM_ORDER {
5364 VGT_GRP_LIST = 0x0,
5365 VGT_GRP_STRIP = 0x1,
5366 VGT_GRP_FAN = 0x2,
5367 VGT_GRP_LOOP = 0x3,
5368 VGT_GRP_POLYGON = 0x4,
5369} VGT_GRP_PRIM_ORDER;
5370typedef enum VGT_GROUP_CONV_SEL {
5371 VGT_GRP_INDEX_16 = 0x0,
5372 VGT_GRP_INDEX_32 = 0x1,
5373 VGT_GRP_UINT_16 = 0x2,
5374 VGT_GRP_UINT_32 = 0x3,
5375 VGT_GRP_SINT_16 = 0x4,
5376 VGT_GRP_SINT_32 = 0x5,
5377 VGT_GRP_FLOAT_32 = 0x6,
5378 VGT_GRP_AUTO_PRIM = 0x7,
5379 VGT_GRP_FIX_1_23_TO_FLOAT = 0x8,
5380} VGT_GROUP_CONV_SEL;
5381typedef enum VGT_GS_MODE_TYPE {
5382 GS_OFF = 0x0,
5383 GS_SCENARIO_A = 0x1,
5384 GS_SCENARIO_B = 0x2,
5385 GS_SCENARIO_G = 0x3,
5386 GS_SCENARIO_C = 0x4,
5387 SPRITE_EN = 0x5,
5388} VGT_GS_MODE_TYPE;
5389typedef enum VGT_GS_CUT_MODE {
5390 GS_CUT_1024 = 0x0,
5391 GS_CUT_512 = 0x1,
5392 GS_CUT_256 = 0x2,
5393 GS_CUT_128 = 0x3,
5394} VGT_GS_CUT_MODE;
5395typedef enum VGT_GS_OUTPRIM_TYPE {
5396 POINTLIST = 0x0,
5397 LINESTRIP = 0x1,
5398 TRISTRIP = 0x2,
5399} VGT_GS_OUTPRIM_TYPE;
5400typedef enum VGT_CACHE_INVALID_MODE {
5401 VC_ONLY = 0x0,
5402 TC_ONLY = 0x1,
5403 VC_AND_TC = 0x2,
5404} VGT_CACHE_INVALID_MODE;
5405typedef enum VGT_TESS_TYPE {
5406 TESS_ISOLINE = 0x0,
5407 TESS_TRIANGLE = 0x1,
5408 TESS_QUAD = 0x2,
5409} VGT_TESS_TYPE;
5410typedef enum VGT_TESS_PARTITION {
5411 PART_INTEGER = 0x0,
5412 PART_POW2 = 0x1,
5413 PART_FRAC_ODD = 0x2,
5414 PART_FRAC_EVEN = 0x3,
5415} VGT_TESS_PARTITION;
5416typedef enum VGT_TESS_TOPOLOGY {
5417 OUTPUT_POINT = 0x0,
5418 OUTPUT_LINE = 0x1,
5419 OUTPUT_TRIANGLE_CW = 0x2,
5420 OUTPUT_TRIANGLE_CCW = 0x3,
5421} VGT_TESS_TOPOLOGY;
5422typedef enum VGT_RDREQ_POLICY {
5423 VGT_POLICY_LRU = 0x0,
5424 VGT_POLICY_STREAM = 0x1,
5425} VGT_RDREQ_POLICY;
5426typedef enum VGT_DIST_MODE {
5427 NO_DIST = 0x0,
5428 PATCHES = 0x1,
5429 DONUTS = 0x2,
5430} VGT_DIST_MODE;
5431typedef enum VGT_STAGES_LS_EN {
5432 LS_STAGE_OFF = 0x0,
5433 LS_STAGE_ON = 0x1,
5434 CS_STAGE_ON = 0x2,
5435 RESERVED_LS = 0x3,
5436} VGT_STAGES_LS_EN;
5437typedef enum VGT_STAGES_HS_EN {
5438 HS_STAGE_OFF = 0x0,
5439 HS_STAGE_ON = 0x1,
5440} VGT_STAGES_HS_EN;
5441typedef enum VGT_STAGES_ES_EN {
5442 ES_STAGE_OFF = 0x0,
5443 ES_STAGE_DS = 0x1,
5444 ES_STAGE_REAL = 0x2,
5445 RESERVED_ES = 0x3,
5446} VGT_STAGES_ES_EN;
5447typedef enum VGT_STAGES_GS_EN {
5448 GS_STAGE_OFF = 0x0,
5449 GS_STAGE_ON = 0x1,
5450} VGT_STAGES_GS_EN;
5451typedef enum VGT_STAGES_VS_EN {
5452 VS_STAGE_REAL = 0x0,
5453 VS_STAGE_DS = 0x1,
5454 VS_STAGE_COPY_SHADER = 0x2,
5455 RESERVED_VS = 0x3,
5456} VGT_STAGES_VS_EN;
5457typedef enum VGT_PERFCOUNT_SELECT {
5458 vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x0,
5459 vgt_perf_VGT_SPI_ESVERT_VALID = 0x1,
5460 vgt_perf_VGT_SPI_ESVERT_EOV = 0x2,
5461 vgt_perf_VGT_SPI_ESVERT_STALLED = 0x3,
5462 vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x4,
5463 vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x5,
5464 vgt_perf_VGT_SPI_ESVERT_STATIC = 0x6,
5465 vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x7,
5466 vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x8,
5467 vgt_perf_VGT_SPI_GSPRIM_VALID = 0x9,
5468 vgt_perf_VGT_SPI_GSPRIM_EOV = 0xa,
5469 vgt_perf_VGT_SPI_GSPRIM_CONT = 0xb,
5470 vgt_perf_VGT_SPI_GSPRIM_STALLED = 0xc,
5471 vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0xd,
5472 vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0xe,
5473 vgt_perf_VGT_SPI_GSPRIM_STATIC = 0xf,
5474 vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x10,
5475 vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x11,
5476 vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x12,
5477 vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x13,
5478 vgt_perf_VGT_SPI_VSVERT_SEND = 0x14,
5479 vgt_perf_VGT_SPI_VSVERT_EOV = 0x15,
5480 vgt_perf_VGT_SPI_VSVERT_STALLED = 0x16,
5481 vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x17,
5482 vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x18,
5483 vgt_perf_VGT_SPI_VSVERT_STATIC = 0x19,
5484 vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x1a,
5485 vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x1b,
5486 vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x1c,
5487 vgt_perf_VGT_PA_CLIPV_SEND = 0x1d,
5488 vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x1e,
5489 vgt_perf_VGT_PA_CLIPV_STALLED = 0x1f,
5490 vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x20,
5491 vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x21,
5492 vgt_perf_VGT_PA_CLIPV_STATIC = 0x22,
5493 vgt_perf_VGT_PA_CLIPP_SEND = 0x23,
5494 vgt_perf_VGT_PA_CLIPP_EOP = 0x24,
5495 vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x25,
5496 vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x26,
5497 vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x27,
5498 vgt_perf_VGT_PA_CLIPP_STALLED = 0x28,
5499 vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x29,
5500 vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x2a,
5501 vgt_perf_VGT_PA_CLIPP_STATIC = 0x2b,
5502 vgt_perf_VGT_PA_CLIPS_SEND = 0x2c,
5503 vgt_perf_VGT_PA_CLIPS_STALLED = 0x2d,
5504 vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x2e,
5505 vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x2f,
5506 vgt_perf_VGT_PA_CLIPS_STATIC = 0x30,
5507 vgt_perf_vsvert_ds_send = 0x31,
5508 vgt_perf_vsvert_api_send = 0x32,
5509 vgt_perf_hs_tif_stall = 0x33,
5510 vgt_perf_hs_input_stall = 0x34,
5511 vgt_perf_hs_interface_stall = 0x35,
5512 vgt_perf_hs_tfm_stall = 0x36,
5513 vgt_perf_te11_starved = 0x37,
5514 vgt_perf_gs_event_stall = 0x38,
5515 vgt_perf_vgt_pa_clipp_send_not_event = 0x39,
5516 vgt_perf_vgt_pa_clipp_valid_prim = 0x3a,
5517 vgt_perf_reused_es_indices = 0x3b,
5518 vgt_perf_vs_cache_hits = 0x3c,
5519 vgt_perf_gs_cache_hits = 0x3d,
5520 vgt_perf_ds_cache_hits = 0x3e,
5521 vgt_perf_total_cache_hits = 0x3f,
5522 vgt_perf_vgt_busy = 0x40,
5523 vgt_perf_vgt_gs_busy = 0x41,
5524 vgt_perf_esvert_stalled_es_tbl = 0x42,
5525 vgt_perf_esvert_stalled_gs_tbl = 0x43,
5526 vgt_perf_esvert_stalled_gs_event = 0x44,
5527 vgt_perf_esvert_stalled_gsprim = 0x45,
5528 vgt_perf_gsprim_stalled_es_tbl = 0x46,
5529 vgt_perf_gsprim_stalled_gs_tbl = 0x47,
5530 vgt_perf_gsprim_stalled_gs_event = 0x48,
5531 vgt_perf_gsprim_stalled_esvert = 0x49,
5532 vgt_perf_esthread_stalled_es_rb_full = 0x4a,
5533 vgt_perf_esthread_stalled_spi_bp = 0x4b,
5534 vgt_perf_counters_avail_stalled = 0x4c,
5535 vgt_perf_gs_rb_space_avail_stalled = 0x4d,
5536 vgt_perf_gs_issue_rtr_stalled = 0x4e,
5537 vgt_perf_gsthread_stalled = 0x4f,
5538 vgt_perf_strmout_stalled = 0x50,
5539 vgt_perf_wait_for_es_done_stalled = 0x51,
5540 vgt_perf_cm_stalled_by_gog = 0x52,
5541 vgt_perf_cm_reading_stalled = 0x53,
5542 vgt_perf_cm_stalled_by_gsfetch_done = 0x54,
5543 vgt_perf_gog_vs_tbl_stalled = 0x55,
5544 vgt_perf_gog_out_indx_stalled = 0x56,
5545 vgt_perf_gog_out_prim_stalled = 0x57,
5546 vgt_perf_waveid_stalled = 0x58,
5547 vgt_perf_gog_busy = 0x59,
5548 vgt_perf_reused_vs_indices = 0x5a,
5549 vgt_perf_sclk_reg_vld_event = 0x5b,
5550 vgt_perf_vs_conflicting_indices = 0x5c,
5551 vgt_perf_sclk_core_vld_event = 0x5d,
5552 vgt_perf_hswave_stalled = 0x5e,
5553 vgt_perf_sclk_gs_vld_event = 0x5f,
5554 vgt_perf_VGT_SPI_LSVERT_VALID = 0x60,
5555 vgt_perf_VGT_SPI_LSVERT_EOV = 0x61,
5556 vgt_perf_VGT_SPI_LSVERT_STALLED = 0x62,
5557 vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x63,
5558 vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x64,
5559 vgt_perf_VGT_SPI_LSVERT_STATIC = 0x65,
5560 vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x66,
5561 vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x67,
5562 vgt_perf_VGT_SPI_LSWAVE_SEND = 0x68,
5563 vgt_perf_VGT_SPI_HSVERT_VALID = 0x69,
5564 vgt_perf_VGT_SPI_HSVERT_EOV = 0x6a,
5565 vgt_perf_VGT_SPI_HSVERT_STALLED = 0x6b,
5566 vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x6c,
5567 vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x6d,
5568 vgt_perf_VGT_SPI_HSVERT_STATIC = 0x6e,
5569 vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x6f,
5570 vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x70,
5571 vgt_perf_VGT_SPI_HSWAVE_SEND = 0x71,
5572 vgt_perf_ds_prims = 0x72,
5573 vgt_perf_ls_thread_groups = 0x73,
5574 vgt_perf_hs_thread_groups = 0x74,
5575 vgt_perf_es_thread_groups = 0x75,
5576 vgt_perf_vs_thread_groups = 0x76,
5577 vgt_perf_ls_done_latency = 0x77,
5578 vgt_perf_hs_done_latency = 0x78,
5579 vgt_perf_es_done_latency = 0x79,
5580 vgt_perf_gs_done_latency = 0x7a,
5581 vgt_perf_vgt_hs_busy = 0x7b,
5582 vgt_perf_vgt_te11_busy = 0x7c,
5583 vgt_perf_ls_flush = 0x7d,
5584 vgt_perf_hs_flush = 0x7e,
5585 vgt_perf_es_flush = 0x7f,
5586 vgt_perf_vgt_pa_clipp_eopg = 0x80,
5587 vgt_perf_ls_done = 0x81,
5588 vgt_perf_hs_done = 0x82,
5589 vgt_perf_es_done = 0x83,
5590 vgt_perf_gs_done = 0x84,
5591 vgt_perf_vsfetch_done = 0x85,
5592 vgt_perf_gs_done_received = 0x86,
5593 vgt_perf_es_ring_high_water_mark = 0x87,
5594 vgt_perf_gs_ring_high_water_mark = 0x88,
5595 vgt_perf_vs_table_high_water_mark = 0x89,
5596 vgt_perf_hs_tgs_active_high_water_mark = 0x8a,
5597 vgt_perf_pa_clipp_dealloc = 0x8b,
5598 vgt_perf_cut_mem_flush_stalled = 0x8c,
5599 vgt_perf_vsvert_work_received = 0x8d,
5600 vgt_perf_vgt_pa_clipp_starved_after_work = 0x8e,
5601 vgt_perf_te11_con_starved_after_work = 0x8f,
5602 vgt_perf_hs_waiting_on_ls_done_stall = 0x90,
5603 vgt_spi_vsvert_valid = 0x91,
5604} VGT_PERFCOUNT_SELECT;
5605typedef enum IA_PERFCOUNT_SELECT {
5606 ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x0,
5607 ia_perf_dma_data_fifo_full = 0x1,
5608 ia_perf_RESERVED1 = 0x2,
5609 ia_perf_RESERVED2 = 0x3,
5610 ia_perf_RESERVED3 = 0x4,
5611 ia_perf_RESERVED4 = 0x5,
5612 ia_perf_RESERVED5 = 0x6,
5613 ia_perf_MC_LAT_BIN_0 = 0x7,
5614 ia_perf_MC_LAT_BIN_1 = 0x8,
5615 ia_perf_MC_LAT_BIN_2 = 0x9,
5616 ia_perf_MC_LAT_BIN_3 = 0xa,
5617 ia_perf_MC_LAT_BIN_4 = 0xb,
5618 ia_perf_MC_LAT_BIN_5 = 0xc,
5619 ia_perf_MC_LAT_BIN_6 = 0xd,
5620 ia_perf_MC_LAT_BIN_7 = 0xe,
5621 ia_perf_ia_busy = 0xf,
5622 ia_perf_ia_sclk_reg_vld_event = 0x10,
5623 ia_perf_RESERVED6 = 0x11,
5624 ia_perf_ia_sclk_core_vld_event = 0x12,
5625 ia_perf_RESERVED7 = 0x13,
5626 ia_perf_ia_dma_return = 0x14,
5627 ia_perf_ia_stalled = 0x15,
5628 ia_perf_shift_starved_pipe0_event = 0x16,
5629 ia_perf_shift_starved_pipe1_event = 0x17,
5630} IA_PERFCOUNT_SELECT;
5631typedef enum WD_PERFCOUNT_SELECT {
5632 wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x0,
5633 wd_perf_RBIU_DR_FIFO_STARVED = 0x1,
5634 wd_perf_RBIU_DR_FIFO_STALLED = 0x2,
5635 wd_perf_RBIU_DI_FIFO_STARVED = 0x3,
5636 wd_perf_RBIU_DI_FIFO_STALLED = 0x4,
5637 wd_perf_wd_busy = 0x5,
5638 wd_perf_wd_sclk_reg_vld_event = 0x6,
5639 wd_perf_wd_sclk_input_vld_event = 0x7,
5640 wd_perf_wd_sclk_core_vld_event = 0x8,
5641 wd_perf_wd_stalled = 0x9,
5642 wd_perf_inside_tf_bin_0 = 0xa,
5643 wd_perf_inside_tf_bin_1 = 0xb,
5644 wd_perf_inside_tf_bin_2 = 0xc,
5645 wd_perf_inside_tf_bin_3 = 0xd,
5646 wd_perf_inside_tf_bin_4 = 0xe,
5647 wd_perf_inside_tf_bin_5 = 0xf,
5648 wd_perf_inside_tf_bin_6 = 0x10,
5649 wd_perf_inside_tf_bin_7 = 0x11,
5650 wd_perf_inside_tf_bin_8 = 0x12,
5651 wd_perf_tfreq_lat_bin_0 = 0x13,
5652 wd_perf_tfreq_lat_bin_1 = 0x14,
5653 wd_perf_tfreq_lat_bin_2 = 0x15,
5654 wd_perf_tfreq_lat_bin_3 = 0x16,
5655 wd_perf_tfreq_lat_bin_4 = 0x17,
5656 wd_perf_tfreq_lat_bin_5 = 0x18,
5657 wd_perf_tfreq_lat_bin_6 = 0x19,
5658 wd_perf_tfreq_lat_bin_7 = 0x1a,
5659 wd_starved_on_hs_done = 0x1b,
5660 wd_perf_se0_hs_done_latency = 0x1c,
5661 wd_perf_se1_hs_done_latency = 0x1d,
5662 wd_perf_se2_hs_done_latency = 0x1e,
5663 wd_perf_se3_hs_done_latency = 0x1f,
5664 wd_perf_hs_done_se0 = 0x20,
5665 wd_perf_hs_done_se1 = 0x21,
5666 wd_perf_hs_done_se2 = 0x22,
5667 wd_perf_hs_done_se3 = 0x23,
5668 wd_perf_null_patches = 0x24,
5669} WD_PERFCOUNT_SELECT;
5670typedef enum WD_IA_DRAW_TYPE {
5671 WD_IA_DRAW_TYPE_DI_MM0 = 0x0,
5672 WD_IA_DRAW_TYPE_DI_MM1 = 0x1,
5673 WD_IA_DRAW_TYPE_EVENT_INIT = 0x2,
5674 WD_IA_DRAW_TYPE_EVENT_ADDR = 0x3,
5675 WD_IA_DRAW_TYPE_MIN_INDX = 0x4,
5676 WD_IA_DRAW_TYPE_MAX_INDX = 0x5,
5677 WD_IA_DRAW_TYPE_INDX_OFF = 0x6,
5678 WD_IA_DRAW_TYPE_IMM_DATA = 0x7,
5679} WD_IA_DRAW_TYPE;
5680typedef enum WD_IA_DRAW_SOURCE {
5681 WD_IA_DRAW_SOURCE_DMA = 0x0,
5682 WD_IA_DRAW_SOURCE_IMMD = 0x1,
5683 WD_IA_DRAW_SOURCE_AUTO = 0x2,
5684 WD_IA_DRAW_SOURCE_OPAQ = 0x3,
5685} WD_IA_DRAW_SOURCE;
5686#define GSTHREADID_SIZE 0x2
5687typedef enum SurfaceEndian {
5688 ENDIAN_NONE = 0x0,
5689 ENDIAN_8IN16 = 0x1,
5690 ENDIAN_8IN32 = 0x2,
5691 ENDIAN_8IN64 = 0x3,
5692} SurfaceEndian;
5693typedef enum ArrayMode {
5694 ARRAY_LINEAR_GENERAL = 0x0,
5695 ARRAY_LINEAR_ALIGNED = 0x1,
5696 ARRAY_1D_TILED_THIN1 = 0x2,
5697 ARRAY_1D_TILED_THICK = 0x3,
5698 ARRAY_2D_TILED_THIN1 = 0x4,
5699 ARRAY_PRT_TILED_THIN1 = 0x5,
5700 ARRAY_PRT_2D_TILED_THIN1 = 0x6,
5701 ARRAY_2D_TILED_THICK = 0x7,
5702 ARRAY_2D_TILED_XTHICK = 0x8,
5703 ARRAY_PRT_TILED_THICK = 0x9,
5704 ARRAY_PRT_2D_TILED_THICK = 0xa,
5705 ARRAY_PRT_3D_TILED_THIN1 = 0xb,
5706 ARRAY_3D_TILED_THIN1 = 0xc,
5707 ARRAY_3D_TILED_THICK = 0xd,
5708 ARRAY_3D_TILED_XTHICK = 0xe,
5709 ARRAY_PRT_3D_TILED_THICK = 0xf,
5710} ArrayMode;
5711typedef enum PipeTiling {
5712 CONFIG_1_PIPE = 0x0,
5713 CONFIG_2_PIPE = 0x1,
5714 CONFIG_4_PIPE = 0x2,
5715 CONFIG_8_PIPE = 0x3,
5716} PipeTiling;
5717typedef enum BankTiling {
5718 CONFIG_4_BANK = 0x0,
5719 CONFIG_8_BANK = 0x1,
5720} BankTiling;
5721typedef enum GroupInterleave {
5722 CONFIG_256B_GROUP = 0x0,
5723 CONFIG_512B_GROUP = 0x1,
5724} GroupInterleave;
5725typedef enum RowTiling {
5726 CONFIG_1KB_ROW = 0x0,
5727 CONFIG_2KB_ROW = 0x1,
5728 CONFIG_4KB_ROW = 0x2,
5729 CONFIG_8KB_ROW = 0x3,
5730 CONFIG_1KB_ROW_OPT = 0x4,
5731 CONFIG_2KB_ROW_OPT = 0x5,
5732 CONFIG_4KB_ROW_OPT = 0x6,
5733 CONFIG_8KB_ROW_OPT = 0x7,
5734} RowTiling;
5735typedef enum BankSwapBytes {
5736 CONFIG_128B_SWAPS = 0x0,
5737 CONFIG_256B_SWAPS = 0x1,
5738 CONFIG_512B_SWAPS = 0x2,
5739 CONFIG_1KB_SWAPS = 0x3,
5740} BankSwapBytes;
5741typedef enum SampleSplitBytes {
5742 CONFIG_1KB_SPLIT = 0x0,
5743 CONFIG_2KB_SPLIT = 0x1,
5744 CONFIG_4KB_SPLIT = 0x2,
5745 CONFIG_8KB_SPLIT = 0x3,
5746} SampleSplitBytes;
5747typedef enum NumPipes {
5748 ADDR_CONFIG_1_PIPE = 0x0,
5749 ADDR_CONFIG_2_PIPE = 0x1,
5750 ADDR_CONFIG_4_PIPE = 0x2,
5751 ADDR_CONFIG_8_PIPE = 0x3,
5752} NumPipes;
5753typedef enum PipeInterleaveSize {
5754 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
5755 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
5756} PipeInterleaveSize;
5757typedef enum BankInterleaveSize {
5758 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
5759 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
5760 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
5761 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
5762} BankInterleaveSize;
5763typedef enum NumShaderEngines {
5764 ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
5765 ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
5766} NumShaderEngines;
5767typedef enum ShaderEngineTileSize {
5768 ADDR_CONFIG_SE_TILE_16 = 0x0,
5769 ADDR_CONFIG_SE_TILE_32 = 0x1,
5770} ShaderEngineTileSize;
5771typedef enum NumGPUs {
5772 ADDR_CONFIG_1_GPU = 0x0,
5773 ADDR_CONFIG_2_GPU = 0x1,
5774 ADDR_CONFIG_4_GPU = 0x2,
5775} NumGPUs;
5776typedef enum MultiGPUTileSize {
5777 ADDR_CONFIG_GPU_TILE_16 = 0x0,
5778 ADDR_CONFIG_GPU_TILE_32 = 0x1,
5779 ADDR_CONFIG_GPU_TILE_64 = 0x2,
5780 ADDR_CONFIG_GPU_TILE_128 = 0x3,
5781} MultiGPUTileSize;
5782typedef enum RowSize {
5783 ADDR_CONFIG_1KB_ROW = 0x0,
5784 ADDR_CONFIG_2KB_ROW = 0x1,
5785 ADDR_CONFIG_4KB_ROW = 0x2,
5786} RowSize;
5787typedef enum NumLowerPipes {
5788 ADDR_CONFIG_1_LOWER_PIPES = 0x0,
5789 ADDR_CONFIG_2_LOWER_PIPES = 0x1,
5790} NumLowerPipes;
5791typedef enum DebugBlockId {
5792 DBG_CLIENT_BLKID_RESERVED = 0x0,
5793 DBG_CLIENT_BLKID_dbg = 0x1,
5794 DBG_CLIENT_BLKID_scf2 = 0x2,
5795 DBG_CLIENT_BLKID_mcd5 = 0x3,
5796 DBG_CLIENT_BLKID_vmc = 0x4,
5797 DBG_CLIENT_BLKID_sx30 = 0x5,
5798 DBG_CLIENT_BLKID_mcd2 = 0x6,
5799 DBG_CLIENT_BLKID_bci1 = 0x7,
5800 DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
5801 DBG_CLIENT_BLKID_mcc0 = 0x9,
5802 DBG_CLIENT_BLKID_uvdf_0 = 0xa,
5803 DBG_CLIENT_BLKID_uvdf_1 = 0xb,
5804 DBG_CLIENT_BLKID_uvdf_2 = 0xc,
5805 DBG_CLIENT_BLKID_uvdi_0 = 0xd,
5806 DBG_CLIENT_BLKID_bci0 = 0xe,
5807 DBG_CLIENT_BLKID_vcec0_0 = 0xf,
5808 DBG_CLIENT_BLKID_cb100 = 0x10,
5809 DBG_CLIENT_BLKID_cb001 = 0x11,
5810 DBG_CLIENT_BLKID_mcd4 = 0x12,
5811 DBG_CLIENT_BLKID_tmonw00 = 0x13,
5812 DBG_CLIENT_BLKID_cb101 = 0x14,
5813 DBG_CLIENT_BLKID_sx10 = 0x15,
5814 DBG_CLIENT_BLKID_cb301 = 0x16,
5815 DBG_CLIENT_BLKID_tmonw01 = 0x17,
5816 DBG_CLIENT_BLKID_vcea0_0 = 0x18,
5817 DBG_CLIENT_BLKID_vcea0_1 = 0x19,
5818 DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
5819 DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
5820 DBG_CLIENT_BLKID_scf1 = 0x1c,
5821 DBG_CLIENT_BLKID_sx20 = 0x1d,
5822 DBG_CLIENT_BLKID_spim1 = 0x1e,
5823 DBG_CLIENT_BLKID_pa10 = 0x1f,
5824 DBG_CLIENT_BLKID_pa00 = 0x20,
5825 DBG_CLIENT_BLKID_gmcon = 0x21,
5826 DBG_CLIENT_BLKID_mcb = 0x22,
5827 DBG_CLIENT_BLKID_vgt0 = 0x23,
5828 DBG_CLIENT_BLKID_pc0 = 0x24,
5829 DBG_CLIENT_BLKID_bci2 = 0x25,
5830 DBG_CLIENT_BLKID_uvdb_0 = 0x26,
5831 DBG_CLIENT_BLKID_spim3 = 0x27,
5832 DBG_CLIENT_BLKID_cpc_0 = 0x28,
5833 DBG_CLIENT_BLKID_cpc_1 = 0x29,
5834 DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
5835 DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
5836 DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
5837 DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
5838 DBG_CLIENT_BLKID_cb000 = 0x2e,
5839 DBG_CLIENT_BLKID_spim0 = 0x2f,
5840 DBG_CLIENT_BLKID_mcc2 = 0x30,
5841 DBG_CLIENT_BLKID_ds0 = 0x31,
5842 DBG_CLIENT_BLKID_srbm = 0x32,
5843 DBG_CLIENT_BLKID_ih = 0x33,
5844 DBG_CLIENT_BLKID_sem = 0x34,
5845 DBG_CLIENT_BLKID_sdma_0 = 0x35,
5846 DBG_CLIENT_BLKID_sdma_1 = 0x36,
5847 DBG_CLIENT_BLKID_hdp = 0x37,
5848 DBG_CLIENT_BLKID_acp_0 = 0x38,
5849 DBG_CLIENT_BLKID_acp_1 = 0x39,
5850 DBG_CLIENT_BLKID_cb200 = 0x3a,
5851 DBG_CLIENT_BLKID_scf3 = 0x3b,
5852 DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
5853 DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
5854 DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
5855 DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
5856 DBG_CLIENT_BLKID_vcea1_3 = 0x40,
5857 DBG_CLIENT_BLKID_bci3 = 0x41,
5858 DBG_CLIENT_BLKID_mcd0 = 0x42,
5859 DBG_CLIENT_BLKID_pa11 = 0x43,
5860 DBG_CLIENT_BLKID_pa01 = 0x44,
5861 DBG_CLIENT_BLKID_cb201 = 0x45,
5862 DBG_CLIENT_BLKID_spim2 = 0x46,
5863 DBG_CLIENT_BLKID_vgt2 = 0x47,
5864 DBG_CLIENT_BLKID_pc2 = 0x48,
5865 DBG_CLIENT_BLKID_smu_0 = 0x49,
5866 DBG_CLIENT_BLKID_smu_1 = 0x4a,
5867 DBG_CLIENT_BLKID_smu_2 = 0x4b,
5868 DBG_CLIENT_BLKID_cb1 = 0x4c,
5869 DBG_CLIENT_BLKID_ia0 = 0x4d,
5870 DBG_CLIENT_BLKID_wd = 0x4e,
5871 DBG_CLIENT_BLKID_ia1 = 0x4f,
5872 DBG_CLIENT_BLKID_vcec1_0 = 0x50,
5873 DBG_CLIENT_BLKID_scf0 = 0x51,
5874 DBG_CLIENT_BLKID_vgt1 = 0x52,
5875 DBG_CLIENT_BLKID_pc1 = 0x53,
5876 DBG_CLIENT_BLKID_cb0 = 0x54,
5877 DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
5878 DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
5879 DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
5880 DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
5881 DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
5882 DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
5883 DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
5884 DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
5885 DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
5886 DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
5887 DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
5888 DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
5889 DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
5890 DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
5891 DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
5892 DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
5893 DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
5894 DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
5895 DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
5896 DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
5897 DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
5898 DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
5899 DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
5900 DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
5901 DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
5902 DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
5903 DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
5904 DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
5905 DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
5906 DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
5907 DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
5908 DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
5909 DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
5910 DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
5911 DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
5912 DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
5913 DBG_CLIENT_BLKID_vceb0_0 = 0x79,
5914 DBG_CLIENT_BLKID_vgt3 = 0x7a,
5915 DBG_CLIENT_BLKID_pc3 = 0x7b,
5916 DBG_CLIENT_BLKID_mcd3 = 0x7c,
5917 DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
5918 DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
5919 DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
5920 DBG_CLIENT_BLKID_uvdu_3 = 0x80,
5921 DBG_CLIENT_BLKID_uvdu_4 = 0x81,
5922 DBG_CLIENT_BLKID_uvdu_5 = 0x82,
5923 DBG_CLIENT_BLKID_uvdu_6 = 0x83,
5924 DBG_CLIENT_BLKID_cb300 = 0x84,
5925 DBG_CLIENT_BLKID_mcd1 = 0x85,
5926 DBG_CLIENT_BLKID_sx00 = 0x86,
5927 DBG_CLIENT_BLKID_uvdc_0 = 0x87,
5928 DBG_CLIENT_BLKID_uvdc_1 = 0x88,
5929 DBG_CLIENT_BLKID_mcc3 = 0x89,
5930 DBG_CLIENT_BLKID_cpg_0 = 0x8a,
5931 DBG_CLIENT_BLKID_cpg_1 = 0x8b,
5932 DBG_CLIENT_BLKID_gck = 0x8c,
5933 DBG_CLIENT_BLKID_mcc1 = 0x8d,
5934 DBG_CLIENT_BLKID_cpf_0 = 0x8e,
5935 DBG_CLIENT_BLKID_cpf_1 = 0x8f,
5936 DBG_CLIENT_BLKID_rlc = 0x90,
5937 DBG_CLIENT_BLKID_grbm = 0x91,
5938 DBG_CLIENT_BLKID_sammsp = 0x92,
5939 DBG_CLIENT_BLKID_dci_pg = 0x93,
5940 DBG_CLIENT_BLKID_dci_0 = 0x94,
5941 DBG_CLIENT_BLKID_dccg0_0 = 0x95,
5942 DBG_CLIENT_BLKID_dccg0_1 = 0x96,
5943 DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
5944 DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
5945 DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
5946 DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
5947 DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
5948 DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
5949 DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
5950} DebugBlockId;
5951typedef enum DebugBlockId_OLD {
5952 DBG_BLOCK_ID_RESERVED = 0x0,
5953 DBG_BLOCK_ID_DBG = 0x1,
5954 DBG_BLOCK_ID_VMC = 0x2,
5955 DBG_BLOCK_ID_PDMA = 0x3,
5956 DBG_BLOCK_ID_CG = 0x4,
5957 DBG_BLOCK_ID_SRBM = 0x5,
5958 DBG_BLOCK_ID_GRBM = 0x6,
5959 DBG_BLOCK_ID_RLC = 0x7,
5960 DBG_BLOCK_ID_CSC = 0x8,
5961 DBG_BLOCK_ID_SEM = 0x9,
5962 DBG_BLOCK_ID_IH = 0xa,
5963 DBG_BLOCK_ID_SC = 0xb,
5964 DBG_BLOCK_ID_SQ = 0xc,
5965 DBG_BLOCK_ID_AVP = 0xd,
5966 DBG_BLOCK_ID_GMCON = 0xe,
5967 DBG_BLOCK_ID_SMU = 0xf,
5968 DBG_BLOCK_ID_DMA0 = 0x10,
5969 DBG_BLOCK_ID_DMA1 = 0x11,
5970 DBG_BLOCK_ID_SPIM = 0x12,
5971 DBG_BLOCK_ID_GDS = 0x13,
5972 DBG_BLOCK_ID_SPIS = 0x14,
5973 DBG_BLOCK_ID_UNUSED0 = 0x15,
5974 DBG_BLOCK_ID_PA0 = 0x16,
5975 DBG_BLOCK_ID_PA1 = 0x17,
5976 DBG_BLOCK_ID_CP0 = 0x18,
5977 DBG_BLOCK_ID_CP1 = 0x19,
5978 DBG_BLOCK_ID_CP2 = 0x1a,
5979 DBG_BLOCK_ID_UNUSED1 = 0x1b,
5980 DBG_BLOCK_ID_UVDU = 0x1c,
5981 DBG_BLOCK_ID_UVDM = 0x1d,
5982 DBG_BLOCK_ID_VCE = 0x1e,
5983 DBG_BLOCK_ID_UNUSED2 = 0x1f,
5984 DBG_BLOCK_ID_VGT0 = 0x20,
5985 DBG_BLOCK_ID_VGT1 = 0x21,
5986 DBG_BLOCK_ID_IA = 0x22,
5987 DBG_BLOCK_ID_UNUSED3 = 0x23,
5988 DBG_BLOCK_ID_SCT0 = 0x24,
5989 DBG_BLOCK_ID_SCT1 = 0x25,
5990 DBG_BLOCK_ID_SPM0 = 0x26,
5991 DBG_BLOCK_ID_SPM1 = 0x27,
5992 DBG_BLOCK_ID_TCAA = 0x28,
5993 DBG_BLOCK_ID_TCAB = 0x29,
5994 DBG_BLOCK_ID_TCCA = 0x2a,
5995 DBG_BLOCK_ID_TCCB = 0x2b,
5996 DBG_BLOCK_ID_MCC0 = 0x2c,
5997 DBG_BLOCK_ID_MCC1 = 0x2d,
5998 DBG_BLOCK_ID_MCC2 = 0x2e,
5999 DBG_BLOCK_ID_MCC3 = 0x2f,
6000 DBG_BLOCK_ID_SX0 = 0x30,
6001 DBG_BLOCK_ID_SX1 = 0x31,
6002 DBG_BLOCK_ID_SX2 = 0x32,
6003 DBG_BLOCK_ID_SX3 = 0x33,
6004 DBG_BLOCK_ID_UNUSED4 = 0x34,
6005 DBG_BLOCK_ID_UNUSED5 = 0x35,
6006 DBG_BLOCK_ID_UNUSED6 = 0x36,
6007 DBG_BLOCK_ID_UNUSED7 = 0x37,
6008 DBG_BLOCK_ID_PC0 = 0x38,
6009 DBG_BLOCK_ID_PC1 = 0x39,
6010 DBG_BLOCK_ID_UNUSED8 = 0x3a,
6011 DBG_BLOCK_ID_UNUSED9 = 0x3b,
6012 DBG_BLOCK_ID_UNUSED10 = 0x3c,
6013 DBG_BLOCK_ID_UNUSED11 = 0x3d,
6014 DBG_BLOCK_ID_MCB = 0x3e,
6015 DBG_BLOCK_ID_UNUSED12 = 0x3f,
6016 DBG_BLOCK_ID_SCB0 = 0x40,
6017 DBG_BLOCK_ID_SCB1 = 0x41,
6018 DBG_BLOCK_ID_UNUSED13 = 0x42,
6019 DBG_BLOCK_ID_UNUSED14 = 0x43,
6020 DBG_BLOCK_ID_SCF0 = 0x44,
6021 DBG_BLOCK_ID_SCF1 = 0x45,
6022 DBG_BLOCK_ID_UNUSED15 = 0x46,
6023 DBG_BLOCK_ID_UNUSED16 = 0x47,
6024 DBG_BLOCK_ID_BCI0 = 0x48,
6025 DBG_BLOCK_ID_BCI1 = 0x49,
6026 DBG_BLOCK_ID_BCI2 = 0x4a,
6027 DBG_BLOCK_ID_BCI3 = 0x4b,
6028 DBG_BLOCK_ID_UNUSED17 = 0x4c,
6029 DBG_BLOCK_ID_UNUSED18 = 0x4d,
6030 DBG_BLOCK_ID_UNUSED19 = 0x4e,
6031 DBG_BLOCK_ID_UNUSED20 = 0x4f,
6032 DBG_BLOCK_ID_CB00 = 0x50,
6033 DBG_BLOCK_ID_CB01 = 0x51,
6034 DBG_BLOCK_ID_CB02 = 0x52,
6035 DBG_BLOCK_ID_CB03 = 0x53,
6036 DBG_BLOCK_ID_CB04 = 0x54,
6037 DBG_BLOCK_ID_UNUSED21 = 0x55,
6038 DBG_BLOCK_ID_UNUSED22 = 0x56,
6039 DBG_BLOCK_ID_UNUSED23 = 0x57,
6040 DBG_BLOCK_ID_CB10 = 0x58,
6041 DBG_BLOCK_ID_CB11 = 0x59,
6042 DBG_BLOCK_ID_CB12 = 0x5a,
6043 DBG_BLOCK_ID_CB13 = 0x5b,
6044 DBG_BLOCK_ID_CB14 = 0x5c,
6045 DBG_BLOCK_ID_UNUSED24 = 0x5d,
6046 DBG_BLOCK_ID_UNUSED25 = 0x5e,
6047 DBG_BLOCK_ID_UNUSED26 = 0x5f,
6048 DBG_BLOCK_ID_TCP0 = 0x60,
6049 DBG_BLOCK_ID_TCP1 = 0x61,
6050 DBG_BLOCK_ID_TCP2 = 0x62,
6051 DBG_BLOCK_ID_TCP3 = 0x63,
6052 DBG_BLOCK_ID_TCP4 = 0x64,
6053 DBG_BLOCK_ID_TCP5 = 0x65,
6054 DBG_BLOCK_ID_TCP6 = 0x66,
6055 DBG_BLOCK_ID_TCP7 = 0x67,
6056 DBG_BLOCK_ID_TCP8 = 0x68,
6057 DBG_BLOCK_ID_TCP9 = 0x69,
6058 DBG_BLOCK_ID_TCP10 = 0x6a,
6059 DBG_BLOCK_ID_TCP11 = 0x6b,
6060 DBG_BLOCK_ID_TCP12 = 0x6c,
6061 DBG_BLOCK_ID_TCP13 = 0x6d,
6062 DBG_BLOCK_ID_TCP14 = 0x6e,
6063 DBG_BLOCK_ID_TCP15 = 0x6f,
6064 DBG_BLOCK_ID_TCP16 = 0x70,
6065 DBG_BLOCK_ID_TCP17 = 0x71,
6066 DBG_BLOCK_ID_TCP18 = 0x72,
6067 DBG_BLOCK_ID_TCP19 = 0x73,
6068 DBG_BLOCK_ID_TCP20 = 0x74,
6069 DBG_BLOCK_ID_TCP21 = 0x75,
6070 DBG_BLOCK_ID_TCP22 = 0x76,
6071 DBG_BLOCK_ID_TCP23 = 0x77,
6072 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
6073 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
6074 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
6075 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
6076 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
6077 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
6078 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
6079 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
6080 DBG_BLOCK_ID_DB00 = 0x80,
6081 DBG_BLOCK_ID_DB01 = 0x81,
6082 DBG_BLOCK_ID_DB02 = 0x82,
6083 DBG_BLOCK_ID_DB03 = 0x83,
6084 DBG_BLOCK_ID_DB04 = 0x84,
6085 DBG_BLOCK_ID_UNUSED27 = 0x85,
6086 DBG_BLOCK_ID_UNUSED28 = 0x86,
6087 DBG_BLOCK_ID_UNUSED29 = 0x87,
6088 DBG_BLOCK_ID_DB10 = 0x88,
6089 DBG_BLOCK_ID_DB11 = 0x89,
6090 DBG_BLOCK_ID_DB12 = 0x8a,
6091 DBG_BLOCK_ID_DB13 = 0x8b,
6092 DBG_BLOCK_ID_DB14 = 0x8c,
6093 DBG_BLOCK_ID_UNUSED30 = 0x8d,
6094 DBG_BLOCK_ID_UNUSED31 = 0x8e,
6095 DBG_BLOCK_ID_UNUSED32 = 0x8f,
6096 DBG_BLOCK_ID_TCC0 = 0x90,
6097 DBG_BLOCK_ID_TCC1 = 0x91,
6098 DBG_BLOCK_ID_TCC2 = 0x92,
6099 DBG_BLOCK_ID_TCC3 = 0x93,
6100 DBG_BLOCK_ID_TCC4 = 0x94,
6101 DBG_BLOCK_ID_TCC5 = 0x95,
6102 DBG_BLOCK_ID_TCC6 = 0x96,
6103 DBG_BLOCK_ID_TCC7 = 0x97,
6104 DBG_BLOCK_ID_SPS00 = 0x98,
6105 DBG_BLOCK_ID_SPS01 = 0x99,
6106 DBG_BLOCK_ID_SPS02 = 0x9a,
6107 DBG_BLOCK_ID_SPS10 = 0x9b,
6108 DBG_BLOCK_ID_SPS11 = 0x9c,
6109 DBG_BLOCK_ID_SPS12 = 0x9d,
6110 DBG_BLOCK_ID_UNUSED33 = 0x9e,
6111 DBG_BLOCK_ID_UNUSED34 = 0x9f,
6112 DBG_BLOCK_ID_TA00 = 0xa0,
6113 DBG_BLOCK_ID_TA01 = 0xa1,
6114 DBG_BLOCK_ID_TA02 = 0xa2,
6115 DBG_BLOCK_ID_TA03 = 0xa3,
6116 DBG_BLOCK_ID_TA04 = 0xa4,
6117 DBG_BLOCK_ID_TA05 = 0xa5,
6118 DBG_BLOCK_ID_TA06 = 0xa6,
6119 DBG_BLOCK_ID_TA07 = 0xa7,
6120 DBG_BLOCK_ID_TA08 = 0xa8,
6121 DBG_BLOCK_ID_TA09 = 0xa9,
6122 DBG_BLOCK_ID_TA0A = 0xaa,
6123 DBG_BLOCK_ID_TA0B = 0xab,
6124 DBG_BLOCK_ID_UNUSED35 = 0xac,
6125 DBG_BLOCK_ID_UNUSED36 = 0xad,
6126 DBG_BLOCK_ID_UNUSED37 = 0xae,
6127 DBG_BLOCK_ID_UNUSED38 = 0xaf,
6128 DBG_BLOCK_ID_TA10 = 0xb0,
6129 DBG_BLOCK_ID_TA11 = 0xb1,
6130 DBG_BLOCK_ID_TA12 = 0xb2,
6131 DBG_BLOCK_ID_TA13 = 0xb3,
6132 DBG_BLOCK_ID_TA14 = 0xb4,
6133 DBG_BLOCK_ID_TA15 = 0xb5,
6134 DBG_BLOCK_ID_TA16 = 0xb6,
6135 DBG_BLOCK_ID_TA17 = 0xb7,
6136 DBG_BLOCK_ID_TA18 = 0xb8,
6137 DBG_BLOCK_ID_TA19 = 0xb9,
6138 DBG_BLOCK_ID_TA1A = 0xba,
6139 DBG_BLOCK_ID_TA1B = 0xbb,
6140 DBG_BLOCK_ID_UNUSED39 = 0xbc,
6141 DBG_BLOCK_ID_UNUSED40 = 0xbd,
6142 DBG_BLOCK_ID_UNUSED41 = 0xbe,
6143 DBG_BLOCK_ID_UNUSED42 = 0xbf,
6144 DBG_BLOCK_ID_TD00 = 0xc0,
6145 DBG_BLOCK_ID_TD01 = 0xc1,
6146 DBG_BLOCK_ID_TD02 = 0xc2,
6147 DBG_BLOCK_ID_TD03 = 0xc3,
6148 DBG_BLOCK_ID_TD04 = 0xc4,
6149 DBG_BLOCK_ID_TD05 = 0xc5,
6150 DBG_BLOCK_ID_TD06 = 0xc6,
6151 DBG_BLOCK_ID_TD07 = 0xc7,
6152 DBG_BLOCK_ID_TD08 = 0xc8,
6153 DBG_BLOCK_ID_TD09 = 0xc9,
6154 DBG_BLOCK_ID_TD0A = 0xca,
6155 DBG_BLOCK_ID_TD0B = 0xcb,
6156 DBG_BLOCK_ID_UNUSED43 = 0xcc,
6157 DBG_BLOCK_ID_UNUSED44 = 0xcd,
6158 DBG_BLOCK_ID_UNUSED45 = 0xce,
6159 DBG_BLOCK_ID_UNUSED46 = 0xcf,
6160 DBG_BLOCK_ID_TD10 = 0xd0,
6161 DBG_BLOCK_ID_TD11 = 0xd1,
6162 DBG_BLOCK_ID_TD12 = 0xd2,
6163 DBG_BLOCK_ID_TD13 = 0xd3,
6164 DBG_BLOCK_ID_TD14 = 0xd4,
6165 DBG_BLOCK_ID_TD15 = 0xd5,
6166 DBG_BLOCK_ID_TD16 = 0xd6,
6167 DBG_BLOCK_ID_TD17 = 0xd7,
6168 DBG_BLOCK_ID_TD18 = 0xd8,
6169 DBG_BLOCK_ID_TD19 = 0xd9,
6170 DBG_BLOCK_ID_TD1A = 0xda,
6171 DBG_BLOCK_ID_TD1B = 0xdb,
6172 DBG_BLOCK_ID_UNUSED47 = 0xdc,
6173 DBG_BLOCK_ID_UNUSED48 = 0xdd,
6174 DBG_BLOCK_ID_UNUSED49 = 0xde,
6175 DBG_BLOCK_ID_UNUSED50 = 0xdf,
6176 DBG_BLOCK_ID_MCD0 = 0xe0,
6177 DBG_BLOCK_ID_MCD1 = 0xe1,
6178 DBG_BLOCK_ID_MCD2 = 0xe2,
6179 DBG_BLOCK_ID_MCD3 = 0xe3,
6180 DBG_BLOCK_ID_MCD4 = 0xe4,
6181 DBG_BLOCK_ID_MCD5 = 0xe5,
6182 DBG_BLOCK_ID_UNUSED51 = 0xe6,
6183 DBG_BLOCK_ID_UNUSED52 = 0xe7,
6184} DebugBlockId_OLD;
6185typedef enum DebugBlockId_BY2 {
6186 DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
6187 DBG_BLOCK_ID_VMC_BY2 = 0x1,
6188 DBG_BLOCK_ID_CG_BY2 = 0x2,
6189 DBG_BLOCK_ID_GRBM_BY2 = 0x3,
6190 DBG_BLOCK_ID_CSC_BY2 = 0x4,
6191 DBG_BLOCK_ID_IH_BY2 = 0x5,
6192 DBG_BLOCK_ID_SQ_BY2 = 0x6,
6193 DBG_BLOCK_ID_GMCON_BY2 = 0x7,
6194 DBG_BLOCK_ID_DMA0_BY2 = 0x8,
6195 DBG_BLOCK_ID_SPIM_BY2 = 0x9,
6196 DBG_BLOCK_ID_SPIS_BY2 = 0xa,
6197 DBG_BLOCK_ID_PA0_BY2 = 0xb,
6198 DBG_BLOCK_ID_CP0_BY2 = 0xc,
6199 DBG_BLOCK_ID_CP2_BY2 = 0xd,
6200 DBG_BLOCK_ID_UVDU_BY2 = 0xe,
6201 DBG_BLOCK_ID_VCE_BY2 = 0xf,
6202 DBG_BLOCK_ID_VGT0_BY2 = 0x10,
6203 DBG_BLOCK_ID_IA_BY2 = 0x11,
6204 DBG_BLOCK_ID_SCT0_BY2 = 0x12,
6205 DBG_BLOCK_ID_SPM0_BY2 = 0x13,
6206 DBG_BLOCK_ID_TCAA_BY2 = 0x14,
6207 DBG_BLOCK_ID_TCCA_BY2 = 0x15,
6208 DBG_BLOCK_ID_MCC0_BY2 = 0x16,
6209 DBG_BLOCK_ID_MCC2_BY2 = 0x17,
6210 DBG_BLOCK_ID_SX0_BY2 = 0x18,
6211 DBG_BLOCK_ID_SX2_BY2 = 0x19,
6212 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
6213 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
6214 DBG_BLOCK_ID_PC0_BY2 = 0x1c,
6215 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
6216 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
6217 DBG_BLOCK_ID_MCB_BY2 = 0x1f,
6218 DBG_BLOCK_ID_SCB0_BY2 = 0x20,
6219 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
6220 DBG_BLOCK_ID_SCF0_BY2 = 0x22,
6221 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
6222 DBG_BLOCK_ID_BCI0_BY2 = 0x24,
6223 DBG_BLOCK_ID_BCI2_BY2 = 0x25,
6224 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
6225 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
6226 DBG_BLOCK_ID_CB00_BY2 = 0x28,
6227 DBG_BLOCK_ID_CB02_BY2 = 0x29,
6228 DBG_BLOCK_ID_CB04_BY2 = 0x2a,
6229 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
6230 DBG_BLOCK_ID_CB10_BY2 = 0x2c,
6231 DBG_BLOCK_ID_CB12_BY2 = 0x2d,
6232 DBG_BLOCK_ID_CB14_BY2 = 0x2e,
6233 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
6234 DBG_BLOCK_ID_TCP0_BY2 = 0x30,
6235 DBG_BLOCK_ID_TCP2_BY2 = 0x31,
6236 DBG_BLOCK_ID_TCP4_BY2 = 0x32,
6237 DBG_BLOCK_ID_TCP6_BY2 = 0x33,
6238 DBG_BLOCK_ID_TCP8_BY2 = 0x34,
6239 DBG_BLOCK_ID_TCP10_BY2 = 0x35,
6240 DBG_BLOCK_ID_TCP12_BY2 = 0x36,
6241 DBG_BLOCK_ID_TCP14_BY2 = 0x37,
6242 DBG_BLOCK_ID_TCP16_BY2 = 0x38,
6243 DBG_BLOCK_ID_TCP18_BY2 = 0x39,
6244 DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
6245 DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
6246 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
6247 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
6248 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
6249 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
6250 DBG_BLOCK_ID_DB00_BY2 = 0x40,
6251 DBG_BLOCK_ID_DB02_BY2 = 0x41,
6252 DBG_BLOCK_ID_DB04_BY2 = 0x42,
6253 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
6254 DBG_BLOCK_ID_DB10_BY2 = 0x44,
6255 DBG_BLOCK_ID_DB12_BY2 = 0x45,
6256 DBG_BLOCK_ID_DB14_BY2 = 0x46,
6257 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
6258 DBG_BLOCK_ID_TCC0_BY2 = 0x48,
6259 DBG_BLOCK_ID_TCC2_BY2 = 0x49,
6260 DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
6261 DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
6262 DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
6263 DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
6264 DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
6265 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
6266 DBG_BLOCK_ID_TA00_BY2 = 0x50,
6267 DBG_BLOCK_ID_TA02_BY2 = 0x51,
6268 DBG_BLOCK_ID_TA04_BY2 = 0x52,
6269 DBG_BLOCK_ID_TA06_BY2 = 0x53,
6270 DBG_BLOCK_ID_TA08_BY2 = 0x54,
6271 DBG_BLOCK_ID_TA0A_BY2 = 0x55,
6272 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
6273 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
6274 DBG_BLOCK_ID_TA10_BY2 = 0x58,
6275 DBG_BLOCK_ID_TA12_BY2 = 0x59,
6276 DBG_BLOCK_ID_TA14_BY2 = 0x5a,
6277 DBG_BLOCK_ID_TA16_BY2 = 0x5b,
6278 DBG_BLOCK_ID_TA18_BY2 = 0x5c,
6279 DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
6280 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
6281 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
6282 DBG_BLOCK_ID_TD00_BY2 = 0x60,
6283 DBG_BLOCK_ID_TD02_BY2 = 0x61,
6284 DBG_BLOCK_ID_TD04_BY2 = 0x62,
6285 DBG_BLOCK_ID_TD06_BY2 = 0x63,
6286 DBG_BLOCK_ID_TD08_BY2 = 0x64,
6287 DBG_BLOCK_ID_TD0A_BY2 = 0x65,
6288 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
6289 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
6290 DBG_BLOCK_ID_TD10_BY2 = 0x68,
6291 DBG_BLOCK_ID_TD12_BY2 = 0x69,
6292 DBG_BLOCK_ID_TD14_BY2 = 0x6a,
6293 DBG_BLOCK_ID_TD16_BY2 = 0x6b,
6294 DBG_BLOCK_ID_TD18_BY2 = 0x6c,
6295 DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
6296 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
6297 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
6298 DBG_BLOCK_ID_MCD0_BY2 = 0x70,
6299 DBG_BLOCK_ID_MCD2_BY2 = 0x71,
6300 DBG_BLOCK_ID_MCD4_BY2 = 0x72,
6301 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
6302} DebugBlockId_BY2;
6303typedef enum DebugBlockId_BY4 {
6304 DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
6305 DBG_BLOCK_ID_CG_BY4 = 0x1,
6306 DBG_BLOCK_ID_CSC_BY4 = 0x2,
6307 DBG_BLOCK_ID_SQ_BY4 = 0x3,
6308 DBG_BLOCK_ID_DMA0_BY4 = 0x4,
6309 DBG_BLOCK_ID_SPIS_BY4 = 0x5,
6310 DBG_BLOCK_ID_CP0_BY4 = 0x6,
6311 DBG_BLOCK_ID_UVDU_BY4 = 0x7,
6312 DBG_BLOCK_ID_VGT0_BY4 = 0x8,
6313 DBG_BLOCK_ID_SCT0_BY4 = 0x9,
6314 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
6315 DBG_BLOCK_ID_MCC0_BY4 = 0xb,
6316 DBG_BLOCK_ID_SX0_BY4 = 0xc,
6317 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
6318 DBG_BLOCK_ID_PC0_BY4 = 0xe,
6319 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
6320 DBG_BLOCK_ID_SCB0_BY4 = 0x10,
6321 DBG_BLOCK_ID_SCF0_BY4 = 0x11,
6322 DBG_BLOCK_ID_BCI0_BY4 = 0x12,
6323 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
6324 DBG_BLOCK_ID_CB00_BY4 = 0x14,
6325 DBG_BLOCK_ID_CB04_BY4 = 0x15,
6326 DBG_BLOCK_ID_CB10_BY4 = 0x16,
6327 DBG_BLOCK_ID_CB14_BY4 = 0x17,
6328 DBG_BLOCK_ID_TCP0_BY4 = 0x18,
6329 DBG_BLOCK_ID_TCP4_BY4 = 0x19,
6330 DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
6331 DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
6332 DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
6333 DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
6334 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
6335 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
6336 DBG_BLOCK_ID_DB_BY4 = 0x20,
6337 DBG_BLOCK_ID_DB04_BY4 = 0x21,
6338 DBG_BLOCK_ID_DB10_BY4 = 0x22,
6339 DBG_BLOCK_ID_DB14_BY4 = 0x23,
6340 DBG_BLOCK_ID_TCC0_BY4 = 0x24,
6341 DBG_BLOCK_ID_TCC4_BY4 = 0x25,
6342 DBG_BLOCK_ID_SPS00_BY4 = 0x26,
6343 DBG_BLOCK_ID_SPS11_BY4 = 0x27,
6344 DBG_BLOCK_ID_TA00_BY4 = 0x28,
6345 DBG_BLOCK_ID_TA04_BY4 = 0x29,
6346 DBG_BLOCK_ID_TA08_BY4 = 0x2a,
6347 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
6348 DBG_BLOCK_ID_TA10_BY4 = 0x2c,
6349 DBG_BLOCK_ID_TA14_BY4 = 0x2d,
6350 DBG_BLOCK_ID_TA18_BY4 = 0x2e,
6351 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
6352 DBG_BLOCK_ID_TD00_BY4 = 0x30,
6353 DBG_BLOCK_ID_TD04_BY4 = 0x31,
6354 DBG_BLOCK_ID_TD08_BY4 = 0x32,
6355 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
6356 DBG_BLOCK_ID_TD10_BY4 = 0x34,
6357 DBG_BLOCK_ID_TD14_BY4 = 0x35,
6358 DBG_BLOCK_ID_TD18_BY4 = 0x36,
6359 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
6360 DBG_BLOCK_ID_MCD0_BY4 = 0x38,
6361 DBG_BLOCK_ID_MCD4_BY4 = 0x39,
6362} DebugBlockId_BY4;
6363typedef enum DebugBlockId_BY8 {
6364 DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
6365 DBG_BLOCK_ID_CSC_BY8 = 0x1,
6366 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
6367 DBG_BLOCK_ID_CP0_BY8 = 0x3,
6368 DBG_BLOCK_ID_VGT0_BY8 = 0x4,
6369 DBG_BLOCK_ID_TCAA_BY8 = 0x5,
6370 DBG_BLOCK_ID_SX0_BY8 = 0x6,
6371 DBG_BLOCK_ID_PC0_BY8 = 0x7,
6372 DBG_BLOCK_ID_SCB0_BY8 = 0x8,
6373 DBG_BLOCK_ID_BCI0_BY8 = 0x9,
6374 DBG_BLOCK_ID_CB00_BY8 = 0xa,
6375 DBG_BLOCK_ID_CB10_BY8 = 0xb,
6376 DBG_BLOCK_ID_TCP0_BY8 = 0xc,
6377 DBG_BLOCK_ID_TCP8_BY8 = 0xd,
6378 DBG_BLOCK_ID_TCP16_BY8 = 0xe,
6379 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
6380 DBG_BLOCK_ID_DB00_BY8 = 0x10,
6381 DBG_BLOCK_ID_DB10_BY8 = 0x11,
6382 DBG_BLOCK_ID_TCC0_BY8 = 0x12,
6383 DBG_BLOCK_ID_SPS00_BY8 = 0x13,
6384 DBG_BLOCK_ID_TA00_BY8 = 0x14,
6385 DBG_BLOCK_ID_TA08_BY8 = 0x15,
6386 DBG_BLOCK_ID_TA10_BY8 = 0x16,
6387 DBG_BLOCK_ID_TA18_BY8 = 0x17,
6388 DBG_BLOCK_ID_TD00_BY8 = 0x18,
6389 DBG_BLOCK_ID_TD08_BY8 = 0x19,
6390 DBG_BLOCK_ID_TD10_BY8 = 0x1a,
6391 DBG_BLOCK_ID_TD18_BY8 = 0x1b,
6392 DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
6393} DebugBlockId_BY8;
6394typedef enum DebugBlockId_BY16 {
6395 DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
6396 DBG_BLOCK_ID_DMA0_BY16 = 0x1,
6397 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
6398 DBG_BLOCK_ID_SX0_BY16 = 0x3,
6399 DBG_BLOCK_ID_SCB0_BY16 = 0x4,
6400 DBG_BLOCK_ID_CB00_BY16 = 0x5,
6401 DBG_BLOCK_ID_TCP0_BY16 = 0x6,
6402 DBG_BLOCK_ID_TCP16_BY16 = 0x7,
6403 DBG_BLOCK_ID_DB00_BY16 = 0x8,
6404 DBG_BLOCK_ID_TCC0_BY16 = 0x9,
6405 DBG_BLOCK_ID_TA00_BY16 = 0xa,
6406 DBG_BLOCK_ID_TA10_BY16 = 0xb,
6407 DBG_BLOCK_ID_TD00_BY16 = 0xc,
6408 DBG_BLOCK_ID_TD10_BY16 = 0xd,
6409 DBG_BLOCK_ID_MCD0_BY16 = 0xe,
6410} DebugBlockId_BY16;
6411typedef enum ColorTransform {
6412 DCC_CT_AUTO = 0x0,
6413 DCC_CT_NONE = 0x1,
6414 ABGR_TO_A_BG_G_RB = 0x2,
6415 BGRA_TO_BG_G_RB_A = 0x3,
6416} ColorTransform;
6417typedef enum CompareRef {
6418 REF_NEVER = 0x0,
6419 REF_LESS = 0x1,
6420 REF_EQUAL = 0x2,
6421 REF_LEQUAL = 0x3,
6422 REF_GREATER = 0x4,
6423 REF_NOTEQUAL = 0x5,
6424 REF_GEQUAL = 0x6,
6425 REF_ALWAYS = 0x7,
6426} CompareRef;
6427typedef enum ReadSize {
6428 READ_256_BITS = 0x0,
6429 READ_512_BITS = 0x1,
6430} ReadSize;
6431typedef enum DepthFormat {
6432 DEPTH_INVALID = 0x0,
6433 DEPTH_16 = 0x1,
6434 DEPTH_X8_24 = 0x2,
6435 DEPTH_8_24 = 0x3,
6436 DEPTH_X8_24_FLOAT = 0x4,
6437 DEPTH_8_24_FLOAT = 0x5,
6438 DEPTH_32_FLOAT = 0x6,
6439 DEPTH_X24_8_32_FLOAT = 0x7,
6440} DepthFormat;
6441typedef enum ZFormat {
6442 Z_INVALID = 0x0,
6443 Z_16 = 0x1,
6444 Z_24 = 0x2,
6445 Z_32_FLOAT = 0x3,
6446} ZFormat;
6447typedef enum StencilFormat {
6448 STENCIL_INVALID = 0x0,
6449 STENCIL_8 = 0x1,
6450} StencilFormat;
6451typedef enum CmaskMode {
6452 CMASK_CLEAR_NONE = 0x0,
6453 CMASK_CLEAR_ONE = 0x1,
6454 CMASK_CLEAR_ALL = 0x2,
6455 CMASK_ANY_EXPANDED = 0x3,
6456 CMASK_ALPHA0_FRAG1 = 0x4,
6457 CMASK_ALPHA0_FRAG2 = 0x5,
6458 CMASK_ALPHA0_FRAG4 = 0x6,
6459 CMASK_ALPHA0_FRAGS = 0x7,
6460 CMASK_ALPHA1_FRAG1 = 0x8,
6461 CMASK_ALPHA1_FRAG2 = 0x9,
6462 CMASK_ALPHA1_FRAG4 = 0xa,
6463 CMASK_ALPHA1_FRAGS = 0xb,
6464 CMASK_ALPHAX_FRAG1 = 0xc,
6465 CMASK_ALPHAX_FRAG2 = 0xd,
6466 CMASK_ALPHAX_FRAG4 = 0xe,
6467 CMASK_ALPHAX_FRAGS = 0xf,
6468} CmaskMode;
6469typedef enum QuadExportFormat {
6470 EXPORT_UNUSED = 0x0,
6471 EXPORT_32_R = 0x1,
6472 EXPORT_32_GR = 0x2,
6473 EXPORT_32_AR = 0x3,
6474 EXPORT_FP16_ABGR = 0x4,
6475 EXPORT_UNSIGNED16_ABGR = 0x5,
6476 EXPORT_SIGNED16_ABGR = 0x6,
6477 EXPORT_32_ABGR = 0x7,
6478} QuadExportFormat;
6479typedef enum QuadExportFormatOld {
6480 EXPORT_4P_32BPC_ABGR = 0x0,
6481 EXPORT_4P_16BPC_ABGR = 0x1,
6482 EXPORT_4P_32BPC_GR = 0x2,
6483 EXPORT_4P_32BPC_AR = 0x3,
6484 EXPORT_2P_32BPC_ABGR = 0x4,
6485 EXPORT_8P_32BPC_R = 0x5,
6486} QuadExportFormatOld;
6487typedef enum ColorFormat {
6488 COLOR_INVALID = 0x0,
6489 COLOR_8 = 0x1,
6490 COLOR_16 = 0x2,
6491 COLOR_8_8 = 0x3,
6492 COLOR_32 = 0x4,
6493 COLOR_16_16 = 0x5,
6494 COLOR_10_11_11 = 0x6,
6495 COLOR_11_11_10 = 0x7,
6496 COLOR_10_10_10_2 = 0x8,
6497 COLOR_2_10_10_10 = 0x9,
6498 COLOR_8_8_8_8 = 0xa,
6499 COLOR_32_32 = 0xb,
6500 COLOR_16_16_16_16 = 0xc,
6501 COLOR_RESERVED_13 = 0xd,
6502 COLOR_32_32_32_32 = 0xe,
6503 COLOR_RESERVED_15 = 0xf,
6504 COLOR_5_6_5 = 0x10,
6505 COLOR_1_5_5_5 = 0x11,
6506 COLOR_5_5_5_1 = 0x12,
6507 COLOR_4_4_4_4 = 0x13,
6508 COLOR_8_24 = 0x14,
6509 COLOR_24_8 = 0x15,
6510 COLOR_X24_8_32_FLOAT = 0x16,
6511 COLOR_RESERVED_23 = 0x17,
6512} ColorFormat;
6513typedef enum SurfaceFormat {
6514 FMT_INVALID = 0x0,
6515 FMT_8 = 0x1,
6516 FMT_16 = 0x2,
6517 FMT_8_8 = 0x3,
6518 FMT_32 = 0x4,
6519 FMT_16_16 = 0x5,
6520 FMT_10_11_11 = 0x6,
6521 FMT_11_11_10 = 0x7,
6522 FMT_10_10_10_2 = 0x8,
6523 FMT_2_10_10_10 = 0x9,
6524 FMT_8_8_8_8 = 0xa,
6525 FMT_32_32 = 0xb,
6526 FMT_16_16_16_16 = 0xc,
6527 FMT_32_32_32 = 0xd,
6528 FMT_32_32_32_32 = 0xe,
6529 FMT_RESERVED_4 = 0xf,
6530 FMT_5_6_5 = 0x10,
6531 FMT_1_5_5_5 = 0x11,
6532 FMT_5_5_5_1 = 0x12,
6533 FMT_4_4_4_4 = 0x13,
6534 FMT_8_24 = 0x14,
6535 FMT_24_8 = 0x15,
6536 FMT_X24_8_32_FLOAT = 0x16,
6537 FMT_RESERVED_33 = 0x17,
6538 FMT_11_11_10_FLOAT = 0x18,
6539 FMT_16_FLOAT = 0x19,
6540 FMT_32_FLOAT = 0x1a,
6541 FMT_16_16_FLOAT = 0x1b,
6542 FMT_8_24_FLOAT = 0x1c,
6543 FMT_24_8_FLOAT = 0x1d,
6544 FMT_32_32_FLOAT = 0x1e,
6545 FMT_10_11_11_FLOAT = 0x1f,
6546 FMT_16_16_16_16_FLOAT = 0x20,
6547 FMT_3_3_2 = 0x21,
6548 FMT_6_5_5 = 0x22,
6549 FMT_32_32_32_32_FLOAT = 0x23,
6550 FMT_RESERVED_36 = 0x24,
6551 FMT_1 = 0x25,
6552 FMT_1_REVERSED = 0x26,
6553 FMT_GB_GR = 0x27,
6554 FMT_BG_RG = 0x28,
6555 FMT_32_AS_8 = 0x29,
6556 FMT_32_AS_8_8 = 0x2a,
6557 FMT_5_9_9_9_SHAREDEXP = 0x2b,
6558 FMT_8_8_8 = 0x2c,
6559 FMT_16_16_16 = 0x2d,
6560 FMT_16_16_16_FLOAT = 0x2e,
6561 FMT_4_4 = 0x2f,
6562 FMT_32_32_32_FLOAT = 0x30,
6563 FMT_BC1 = 0x31,
6564 FMT_BC2 = 0x32,
6565 FMT_BC3 = 0x33,
6566 FMT_BC4 = 0x34,
6567 FMT_BC5 = 0x35,
6568 FMT_BC6 = 0x36,
6569 FMT_BC7 = 0x37,
6570 FMT_32_AS_32_32_32_32 = 0x38,
6571 FMT_APC3 = 0x39,
6572 FMT_APC4 = 0x3a,
6573 FMT_APC5 = 0x3b,
6574 FMT_APC6 = 0x3c,
6575 FMT_APC7 = 0x3d,
6576 FMT_CTX1 = 0x3e,
6577 FMT_RESERVED_63 = 0x3f,
6578} SurfaceFormat;
6579typedef enum BUF_DATA_FORMAT {
6580 BUF_DATA_FORMAT_INVALID = 0x0,
6581 BUF_DATA_FORMAT_8 = 0x1,
6582 BUF_DATA_FORMAT_16 = 0x2,
6583 BUF_DATA_FORMAT_8_8 = 0x3,
6584 BUF_DATA_FORMAT_32 = 0x4,
6585 BUF_DATA_FORMAT_16_16 = 0x5,
6586 BUF_DATA_FORMAT_10_11_11 = 0x6,
6587 BUF_DATA_FORMAT_11_11_10 = 0x7,
6588 BUF_DATA_FORMAT_10_10_10_2 = 0x8,
6589 BUF_DATA_FORMAT_2_10_10_10 = 0x9,
6590 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
6591 BUF_DATA_FORMAT_32_32 = 0xb,
6592 BUF_DATA_FORMAT_16_16_16_16 = 0xc,
6593 BUF_DATA_FORMAT_32_32_32 = 0xd,
6594 BUF_DATA_FORMAT_32_32_32_32 = 0xe,
6595 BUF_DATA_FORMAT_RESERVED_15 = 0xf,
6596} BUF_DATA_FORMAT;
6597typedef enum IMG_DATA_FORMAT {
6598 IMG_DATA_FORMAT_INVALID = 0x0,
6599 IMG_DATA_FORMAT_8 = 0x1,
6600 IMG_DATA_FORMAT_16 = 0x2,
6601 IMG_DATA_FORMAT_8_8 = 0x3,
6602 IMG_DATA_FORMAT_32 = 0x4,
6603 IMG_DATA_FORMAT_16_16 = 0x5,
6604 IMG_DATA_FORMAT_10_11_11 = 0x6,
6605 IMG_DATA_FORMAT_11_11_10 = 0x7,
6606 IMG_DATA_FORMAT_10_10_10_2 = 0x8,
6607 IMG_DATA_FORMAT_2_10_10_10 = 0x9,
6608 IMG_DATA_FORMAT_8_8_8_8 = 0xa,
6609 IMG_DATA_FORMAT_32_32 = 0xb,
6610 IMG_DATA_FORMAT_16_16_16_16 = 0xc,
6611 IMG_DATA_FORMAT_32_32_32 = 0xd,
6612 IMG_DATA_FORMAT_32_32_32_32 = 0xe,
6613 IMG_DATA_FORMAT_RESERVED_15 = 0xf,
6614 IMG_DATA_FORMAT_5_6_5 = 0x10,
6615 IMG_DATA_FORMAT_1_5_5_5 = 0x11,
6616 IMG_DATA_FORMAT_5_5_5_1 = 0x12,
6617 IMG_DATA_FORMAT_4_4_4_4 = 0x13,
6618 IMG_DATA_FORMAT_8_24 = 0x14,
6619 IMG_DATA_FORMAT_24_8 = 0x15,
6620 IMG_DATA_FORMAT_X24_8_32 = 0x16,
6621 IMG_DATA_FORMAT_RESERVED_23 = 0x17,
6622 IMG_DATA_FORMAT_RESERVED_24 = 0x18,
6623 IMG_DATA_FORMAT_RESERVED_25 = 0x19,
6624 IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
6625 IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
6626 IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
6627 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
6628 IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
6629 IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
6630 IMG_DATA_FORMAT_GB_GR = 0x20,
6631 IMG_DATA_FORMAT_BG_RG = 0x21,
6632 IMG_DATA_FORMAT_5_9_9_9 = 0x22,
6633 IMG_DATA_FORMAT_BC1 = 0x23,
6634 IMG_DATA_FORMAT_BC2 = 0x24,
6635 IMG_DATA_FORMAT_BC3 = 0x25,
6636 IMG_DATA_FORMAT_BC4 = 0x26,
6637 IMG_DATA_FORMAT_BC5 = 0x27,
6638 IMG_DATA_FORMAT_BC6 = 0x28,
6639 IMG_DATA_FORMAT_BC7 = 0x29,
6640 IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
6641 IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
6642 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
6643 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
6644 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
6645 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
6646 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
6647 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
6648 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
6649 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
6650 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
6651 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
6652 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
6653 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
6654 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
6655 IMG_DATA_FORMAT_4_4 = 0x39,
6656 IMG_DATA_FORMAT_6_5_5 = 0x3a,
6657 IMG_DATA_FORMAT_1 = 0x3b,
6658 IMG_DATA_FORMAT_1_REVERSED = 0x3c,
6659 IMG_DATA_FORMAT_32_AS_8 = 0x3d,
6660 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
6661 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
6662} IMG_DATA_FORMAT;
6663typedef enum BUF_NUM_FORMAT {
6664 BUF_NUM_FORMAT_UNORM = 0x0,
6665 BUF_NUM_FORMAT_SNORM = 0x1,
6666 BUF_NUM_FORMAT_USCALED = 0x2,
6667 BUF_NUM_FORMAT_SSCALED = 0x3,
6668 BUF_NUM_FORMAT_UINT = 0x4,
6669 BUF_NUM_FORMAT_SINT = 0x5,
6670 BUF_NUM_FORMAT_RESERVED_6 = 0x6,
6671 BUF_NUM_FORMAT_FLOAT = 0x7,
6672} BUF_NUM_FORMAT;
6673typedef enum IMG_NUM_FORMAT {
6674 IMG_NUM_FORMAT_UNORM = 0x0,
6675 IMG_NUM_FORMAT_SNORM = 0x1,
6676 IMG_NUM_FORMAT_USCALED = 0x2,
6677 IMG_NUM_FORMAT_SSCALED = 0x3,
6678 IMG_NUM_FORMAT_UINT = 0x4,
6679 IMG_NUM_FORMAT_SINT = 0x5,
6680 IMG_NUM_FORMAT_RESERVED_6 = 0x6,
6681 IMG_NUM_FORMAT_FLOAT = 0x7,
6682 IMG_NUM_FORMAT_RESERVED_8 = 0x8,
6683 IMG_NUM_FORMAT_SRGB = 0x9,
6684 IMG_NUM_FORMAT_RESERVED_10 = 0xa,
6685 IMG_NUM_FORMAT_RESERVED_11 = 0xb,
6686 IMG_NUM_FORMAT_RESERVED_12 = 0xc,
6687 IMG_NUM_FORMAT_RESERVED_13 = 0xd,
6688 IMG_NUM_FORMAT_RESERVED_14 = 0xe,
6689 IMG_NUM_FORMAT_RESERVED_15 = 0xf,
6690} IMG_NUM_FORMAT;
6691typedef enum TileType {
6692 ARRAY_COLOR_TILE = 0x0,
6693 ARRAY_DEPTH_TILE = 0x1,
6694} TileType;
6695typedef enum NonDispTilingOrder {
6696 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
6697 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
6698} NonDispTilingOrder;
6699typedef enum MicroTileMode {
6700 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
6701 ADDR_SURF_THIN_MICRO_TILING = 0x1,
6702 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
6703 ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
6704 ADDR_SURF_THICK_MICRO_TILING = 0x4,
6705} MicroTileMode;
6706typedef enum TileSplit {
6707 ADDR_SURF_TILE_SPLIT_64B = 0x0,
6708 ADDR_SURF_TILE_SPLIT_128B = 0x1,
6709 ADDR_SURF_TILE_SPLIT_256B = 0x2,
6710 ADDR_SURF_TILE_SPLIT_512B = 0x3,
6711 ADDR_SURF_TILE_SPLIT_1KB = 0x4,
6712 ADDR_SURF_TILE_SPLIT_2KB = 0x5,
6713 ADDR_SURF_TILE_SPLIT_4KB = 0x6,
6714} TileSplit;
6715typedef enum SampleSplit {
6716 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
6717 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
6718 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
6719 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
6720} SampleSplit;
6721typedef enum PipeConfig {
6722 ADDR_SURF_P2 = 0x0,
6723 ADDR_SURF_P2_RESERVED0 = 0x1,
6724 ADDR_SURF_P2_RESERVED1 = 0x2,
6725 ADDR_SURF_P2_RESERVED2 = 0x3,
6726 ADDR_SURF_P4_8x16 = 0x4,
6727 ADDR_SURF_P4_16x16 = 0x5,
6728 ADDR_SURF_P4_16x32 = 0x6,
6729 ADDR_SURF_P4_32x32 = 0x7,
6730 ADDR_SURF_P8_16x16_8x16 = 0x8,
6731 ADDR_SURF_P8_16x32_8x16 = 0x9,
6732 ADDR_SURF_P8_32x32_8x16 = 0xa,
6733 ADDR_SURF_P8_16x32_16x16 = 0xb,
6734 ADDR_SURF_P8_32x32_16x16 = 0xc,
6735 ADDR_SURF_P8_32x32_16x32 = 0xd,
6736 ADDR_SURF_P8_32x64_32x32 = 0xe,
6737 ADDR_SURF_P8_RESERVED0 = 0xf,
6738 ADDR_SURF_P16_32x32_8x16 = 0x10,
6739 ADDR_SURF_P16_32x32_16x16 = 0x11,
6740} PipeConfig;
6741typedef enum NumBanks {
6742 ADDR_SURF_2_BANK = 0x0,
6743 ADDR_SURF_4_BANK = 0x1,
6744 ADDR_SURF_8_BANK = 0x2,
6745 ADDR_SURF_16_BANK = 0x3,
6746} NumBanks;
6747typedef enum BankWidth {
6748 ADDR_SURF_BANK_WIDTH_1 = 0x0,
6749 ADDR_SURF_BANK_WIDTH_2 = 0x1,
6750 ADDR_SURF_BANK_WIDTH_4 = 0x2,
6751 ADDR_SURF_BANK_WIDTH_8 = 0x3,
6752} BankWidth;
6753typedef enum BankHeight {
6754 ADDR_SURF_BANK_HEIGHT_1 = 0x0,
6755 ADDR_SURF_BANK_HEIGHT_2 = 0x1,
6756 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
6757 ADDR_SURF_BANK_HEIGHT_8 = 0x3,
6758} BankHeight;
6759typedef enum BankWidthHeight {
6760 ADDR_SURF_BANK_WH_1 = 0x0,
6761 ADDR_SURF_BANK_WH_2 = 0x1,
6762 ADDR_SURF_BANK_WH_4 = 0x2,
6763 ADDR_SURF_BANK_WH_8 = 0x3,
6764} BankWidthHeight;
6765typedef enum MacroTileAspect {
6766 ADDR_SURF_MACRO_ASPECT_1 = 0x0,
6767 ADDR_SURF_MACRO_ASPECT_2 = 0x1,
6768 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
6769 ADDR_SURF_MACRO_ASPECT_8 = 0x3,
6770} MacroTileAspect;
6771typedef enum GATCL1RequestType {
6772 GATCL1_TYPE_NORMAL = 0x0,
6773 GATCL1_TYPE_SHOOTDOWN = 0x1,
6774 GATCL1_TYPE_BYPASS = 0x2,
6775} GATCL1RequestType;
6776typedef enum TCC_CACHE_POLICIES {
6777 TCC_CACHE_POLICY_LRU = 0x0,
6778 TCC_CACHE_POLICY_STREAM = 0x1,
6779} TCC_CACHE_POLICIES;
6780typedef enum MTYPE {
6781 MTYPE_NC_NV = 0x0,
6782 MTYPE_NC = 0x1,
6783 MTYPE_CC = 0x2,
6784 MTYPE_UC = 0x3,
6785} MTYPE;
6786typedef enum PERFMON_COUNTER_MODE {
6787 PERFMON_COUNTER_MODE_ACCUM = 0x0,
6788 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
6789 PERFMON_COUNTER_MODE_MAX = 0x2,
6790 PERFMON_COUNTER_MODE_DIRTY = 0x3,
6791 PERFMON_COUNTER_MODE_SAMPLE = 0x4,
6792 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
6793 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
6794 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
6795 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
6796 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
6797 PERFMON_COUNTER_MODE_RESERVED = 0xf,
6798} PERFMON_COUNTER_MODE;
6799typedef enum PERFMON_SPM_MODE {
6800 PERFMON_SPM_MODE_OFF = 0x0,
6801 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
6802 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
6803 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
6804 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
6805 PERFMON_SPM_MODE_RESERVED_5 = 0x5,
6806 PERFMON_SPM_MODE_RESERVED_6 = 0x6,
6807 PERFMON_SPM_MODE_RESERVED_7 = 0x7,
6808 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
6809 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
6810 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
6811} PERFMON_SPM_MODE;
6812typedef enum SurfaceTiling {
6813 ARRAY_LINEAR = 0x0,
6814 ARRAY_TILED = 0x1,
6815} SurfaceTiling;
6816typedef enum SurfaceArray {
6817 ARRAY_1D = 0x0,
6818 ARRAY_2D = 0x1,
6819 ARRAY_3D = 0x2,
6820 ARRAY_3D_SLICE = 0x3,
6821} SurfaceArray;
6822typedef enum ColorArray {
6823 ARRAY_2D_ALT_COLOR = 0x0,
6824 ARRAY_2D_COLOR = 0x1,
6825 ARRAY_3D_SLICE_COLOR = 0x3,
6826} ColorArray;
6827typedef enum DepthArray {
6828 ARRAY_2D_ALT_DEPTH = 0x0,
6829 ARRAY_2D_DEPTH = 0x1,
6830} DepthArray;
6831typedef enum ENUM_NUM_SIMD_PER_CU {
6832 NUM_SIMD_PER_CU = 0x4,
6833} ENUM_NUM_SIMD_PER_CU;
6834typedef enum MEM_PWR_FORCE_CTRL {
6835 NO_FORCE_REQUEST = 0x0,
6836 FORCE_LIGHT_SLEEP_REQUEST = 0x1,
6837 FORCE_DEEP_SLEEP_REQUEST = 0x2,
6838 FORCE_SHUT_DOWN_REQUEST = 0x3,
6839} MEM_PWR_FORCE_CTRL;
6840typedef enum MEM_PWR_FORCE_CTRL2 {
6841 NO_FORCE_REQ = 0x0,
6842 FORCE_LIGHT_SLEEP_REQ = 0x1,
6843} MEM_PWR_FORCE_CTRL2;
6844typedef enum MEM_PWR_DIS_CTRL {
6845 ENABLE_MEM_PWR_CTRL = 0x0,
6846 DISABLE_MEM_PWR_CTRL = 0x1,
6847} MEM_PWR_DIS_CTRL;
6848typedef enum MEM_PWR_SEL_CTRL {
6849 DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
6850 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
6851 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
6852} MEM_PWR_SEL_CTRL;
6853typedef enum MEM_PWR_SEL_CTRL2 {
6854 DYNAMIC_DEEP_SLEEP_EN = 0x0,
6855 DYNAMIC_LIGHT_SLEEP_EN = 0x1,
6856} MEM_PWR_SEL_CTRL2;
6857
6858#endif /* GFX_8_0_ENUM_H */
6859

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source code of linux/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h