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1/*
2 * GFX_8_1 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef GFX_8_1_SH_MASK_H
25#define GFX_8_1_SH_MASK_H
26
27#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
37#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2
38#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
39#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c
40#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
41#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x1
42#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0
43#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
44#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
45#define CB_COLOR_CONTROL__MODE_MASK 0x70
46#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
47#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
48#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
49#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
50#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
51#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
52#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
53#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
54#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
55#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
56#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
57#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
58#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
59#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
60#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
61#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
62#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
63#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
64#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
65#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
66#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
67#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
68#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
69#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
70#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
71#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
72#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
73#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
74#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
75#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
76#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
77#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
78#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
79#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
80#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
81#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
82#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
83#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
84#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
85#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
86#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
87#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
88#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
89#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
90#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
91#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
92#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
93#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
94#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
95#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
96#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
97#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
98#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
99#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
100#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
101#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
102#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
103#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
104#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
105#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
106#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
107#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
108#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
109#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
110#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
111#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
112#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
113#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
114#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
115#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
116#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
117#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
118#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
119#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
120#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
121#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
122#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
123#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
124#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
125#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
126#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
127#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
128#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
129#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
130#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
131#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
132#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
133#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
134#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
135#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
136#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
137#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
138#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
139#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
140#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
141#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
142#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
143#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
144#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
145#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
146#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
147#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
148#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
149#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
150#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
151#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
152#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
153#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
154#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
155#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
156#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
157#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
158#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
159#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
160#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
161#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
162#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
163#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
164#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
165#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
166#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
167#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
168#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
169#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
170#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
171#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
172#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
173#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
174#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
175#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
176#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
177#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
178#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
179#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
180#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
181#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
182#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
183#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
184#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
185#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
186#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
187#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
188#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
189#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
190#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
191#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
192#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
193#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
194#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
195#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
196#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
197#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
198#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
199#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
200#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
201#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
202#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
203#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
204#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
205#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
206#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
207#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
208#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
209#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
210#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
211#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
212#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
213#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
214#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
215#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
216#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
217#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
218#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
219#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
220#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
221#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
222#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
223#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
224#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
225#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
226#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
227#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
228#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
229#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
230#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
231#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
232#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
233#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
234#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
235#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
236#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
237#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
238#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
239#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
240#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
241#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
242#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
243#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
244#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
245#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
246#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
247#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
248#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
249#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
250#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
251#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
252#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
253#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
254#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
255#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
256#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
257#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
258#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
259#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
260#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
261#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
262#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
263#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
264#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
265#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
266#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
267#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
268#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
269#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
270#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
271#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
272#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
273#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
274#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
275#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
276#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
277#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
278#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
279#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
280#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
281#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
282#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
283#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
284#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
285#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
286#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
287#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
288#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
289#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
290#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
291#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
292#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
293#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
294#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
295#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
296#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
297#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
298#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
299#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
300#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
301#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
302#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
303#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
304#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
305#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
306#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
307#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
308#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
309#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
310#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
311#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
312#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
313#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
314#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
315#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
316#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
317#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
318#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
319#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
320#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
321#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000
322#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
323#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
324#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
325#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
326#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
327#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
328#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
329#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
330#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
331#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
332#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
333#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
334#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
335#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
336#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
337#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
338#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
339#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
340#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
341#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
342#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
343#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
344#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
345#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
346#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
347#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
348#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
349#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
350#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
351#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
352#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
353#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
354#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
355#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
356#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
357#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000
358#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
359#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
360#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
361#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
362#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
363#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
364#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
365#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
366#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
367#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
368#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
369#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
370#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
371#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
372#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
373#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
374#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
375#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
376#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
377#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
378#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
379#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
380#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
381#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
382#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
383#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
384#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
385#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
386#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
387#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
388#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
389#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
390#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
391#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
392#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
393#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000
394#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
395#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
396#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
397#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
398#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
399#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
400#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
401#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
402#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
403#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
404#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
405#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
406#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
407#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
408#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
409#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
410#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
411#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
412#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
413#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
414#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
415#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
416#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
417#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
418#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
419#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
420#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
421#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
422#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
423#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
424#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
425#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
426#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
427#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
428#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
429#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000
430#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
431#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
432#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
433#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
434#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
435#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
436#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
437#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
438#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
439#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
440#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
441#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
442#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
443#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
444#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
445#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
446#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
447#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
448#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
449#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
450#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
451#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
452#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
453#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
454#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
455#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
456#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
457#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
458#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
459#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
460#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
461#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
462#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
463#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
464#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
465#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000
466#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
467#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
468#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
469#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
470#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
471#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
472#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
473#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
474#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
475#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
476#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
477#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
478#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
479#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
480#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
481#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
482#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
483#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
484#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
485#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
486#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
487#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
488#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
489#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
490#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
491#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
492#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
493#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
494#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
495#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
496#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
497#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
498#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
499#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
500#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
501#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000
502#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
503#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
504#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
505#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
506#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
507#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
508#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
509#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
510#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
511#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
512#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
513#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
514#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
515#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
516#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
517#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
518#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
519#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
520#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
521#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
522#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
523#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
524#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
525#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
526#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
527#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
528#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
529#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
530#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
531#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
532#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
533#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
534#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
535#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
536#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
537#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000
538#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
539#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
540#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
541#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
542#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
543#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
544#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
545#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
546#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
547#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
548#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
549#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
550#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
551#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
552#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
553#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
554#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
555#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
556#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
557#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
558#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
559#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
560#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
561#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
562#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
563#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
564#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
565#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
566#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
567#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
568#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
569#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
570#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
571#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
572#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
573#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000
574#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
575#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
576#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
577#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
578#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
579#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
580#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
581#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
582#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
583#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
584#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
585#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
586#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
587#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
588#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
589#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
590#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
591#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
592#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
593#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
594#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
595#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
596#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
597#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
598#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
599#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
600#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
601#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
602#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
603#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
604#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
605#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
606#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
607#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
608#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
609#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
610#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
611#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
612#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
613#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
614#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
615#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
616#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
617#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
618#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
619#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
620#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
621#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
622#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
623#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
624#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
625#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
626#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
627#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
628#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
629#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
630#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
631#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
632#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
633#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
634#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
635#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
636#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
637#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
638#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
639#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
640#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
641#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
642#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
643#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
644#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
645#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
646#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
647#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
648#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
649#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
650#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
651#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
652#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
653#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
654#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
655#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
656#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
657#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
658#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
659#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
660#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
661#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
662#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
663#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
664#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
665#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
666#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
667#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
668#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
669#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
670#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
671#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
672#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
673#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
674#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
675#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
676#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
677#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
678#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
679#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
680#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
681#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
682#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
683#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
684#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
685#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
686#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
687#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
688#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
689#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
690#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
691#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
692#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
693#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
694#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
695#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
696#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
697#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
698#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
699#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
700#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
701#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
702#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
703#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
704#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
705#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
706#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
707#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
708#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
709#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
710#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
711#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
712#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
713#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
714#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
715#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
716#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
717#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
718#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
719#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
720#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
721#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
722#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
723#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
724#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
725#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
726#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
727#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
728#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
729#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
730#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
731#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
732#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
733#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
734#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
735#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
736#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
737#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
738#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
739#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
740#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
741#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
742#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
743#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
744#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
745#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
746#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
747#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
748#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
749#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
750#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
751#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
752#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
753#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
754#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
755#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
756#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
757#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
758#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
759#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
760#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
761#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
762#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
763#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
764#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
765#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
766#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
767#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
768#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
769#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
770#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
771#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
772#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
773#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
774#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
775#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
776#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
777#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
778#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
779#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
780#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
781#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
782#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
783#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
784#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
785#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
786#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
787#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
788#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
789#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
790#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
791#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
792#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
793#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
794#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
795#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
796#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
797#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
798#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
799#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
800#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
801#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
802#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
803#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
804#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
805#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
806#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
807#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
808#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
809#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
810#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
811#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
812#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
813#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
814#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
815#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
816#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
817#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
818#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
819#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
820#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
821#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
822#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
823#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
824#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
825#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
826#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
827#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
828#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
829#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
830#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
831#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
832#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
833#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
834#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
835#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
836#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
837#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
838#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
839#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
840#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
841#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
842#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
843#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
844#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
845#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
846#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
847#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
848#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
849#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
850#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
851#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
852#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
853#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
854#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
855#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
856#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
857#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
858#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
859#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
860#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
861#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
862#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
863#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
864#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
865#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
866#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
867#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
868#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
869#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
870#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
871#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
872#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
873#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
874#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
875#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
876#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
877#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
878#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
879#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
880#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
881#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
882#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
883#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
884#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
885#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
886#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
887#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
888#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
889#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
890#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
891#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
892#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
893#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
894#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
895#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
896#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
897#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
898#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
899#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
900#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
901#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
902#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
903#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
904#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
905#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
906#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
907#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
908#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
909#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
910#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
911#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
912#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
913#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff
914#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
915#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff
916#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
917#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff
918#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
919#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff
920#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
921#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff
922#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
923#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff
924#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
925#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff
926#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
927#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff
928#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
929#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
930#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
931#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
932#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
933#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
934#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
935#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
936#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
937#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
938#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
939#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
940#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
941#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
942#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
943#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
944#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
945#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
946#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
947#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
948#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
949#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
950#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
951#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
952#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
953#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
954#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
955#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
956#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
957#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
958#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
959#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
960#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
961#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
962#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
963#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
964#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
965#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
966#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
967#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
968#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
969#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
970#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
971#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
972#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
973#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
974#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
975#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
976#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
977#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
978#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
979#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
980#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
981#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
982#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
983#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
984#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
985#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
986#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
987#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
988#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
989#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
990#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
991#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
992#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
993#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
994#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
995#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
996#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
997#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
998#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
999#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
1000#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
1001#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
1002#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
1003#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
1004#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
1005#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
1006#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
1007#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
1008#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
1009#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
1010#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
1011#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
1012#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
1013#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000
1014#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
1015#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000
1016#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
1017#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
1018#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
1019#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2
1020#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
1021#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4
1022#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
1023#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8
1024#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
1025#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10
1026#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
1027#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20
1028#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
1029#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80
1030#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
1031#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100
1032#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
1033#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x200
1034#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9
1035#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x400
1036#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
1037#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x800
1038#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb
1039#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x1000
1040#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc
1041#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x2000
1042#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd
1043#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f
1044#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
1045#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20
1046#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
1047#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40
1048#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
1049#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00
1050#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
1051#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000
1052#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
1053#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000
1054#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
1055#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000
1056#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
1057#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
1058#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
1059#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
1060#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
1061#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
1062#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
1063#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
1064#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
1065#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
1066#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
1067#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
1068#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
1069#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
1070#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
1071#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
1072#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
1073#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
1074#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
1075#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
1076#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
1077#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
1078#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
1079#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
1080#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
1081#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
1082#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
1083#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
1084#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
1085#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
1086#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
1087#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
1088#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
1089#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
1090#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
1091#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
1092#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
1093#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
1094#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
1095#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
1096#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
1097#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
1098#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
1099#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
1100#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
1101#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
1102#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
1103#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
1104#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
1105#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
1106#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
1107#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
1108#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
1109#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
1110#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
1111#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
1112#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
1113#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
1114#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
1115#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
1116#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
1117#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
1118#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
1119#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
1120#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
1121#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
1122#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
1123#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
1124#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
1125#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
1126#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
1127#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
1128#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
1129#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1130#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1131#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
1132#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
1133#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
1134#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
1135#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
1136#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
1137#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
1138#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
1139#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
1140#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
1141#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
1142#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
1143#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
1144#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
1145#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
1146#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
1147#define CB_DEBUG_BUS_1__CB_BUSY_MASK 0x1
1148#define CB_DEBUG_BUS_1__CB_BUSY__SHIFT 0x0
1149#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READY_MASK 0x2
1150#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READY__SHIFT 0x1
1151#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READYB_MASK 0x4
1152#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READYB__SHIFT 0x2
1153#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READY_MASK 0x8
1154#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READY__SHIFT 0x3
1155#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READYB_MASK 0x10
1156#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READYB__SHIFT 0x4
1157#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READY_MASK 0x20
1158#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READY__SHIFT 0x5
1159#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READYB_MASK 0x40
1160#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READYB__SHIFT 0x6
1161#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READY_MASK 0x80
1162#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READY__SHIFT 0x7
1163#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READYB_MASK 0x100
1164#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READYB__SHIFT 0x8
1165#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READY_MASK 0x200
1166#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READY__SHIFT 0x9
1167#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READYB_MASK 0x400
1168#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READYB__SHIFT 0xa
1169#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY_MASK 0x800
1170#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY__SHIFT 0xb
1171#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READYB_MASK 0x1000
1172#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READYB__SHIFT 0xc
1173#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READY_MASK 0x2000
1174#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READY__SHIFT 0xd
1175#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READYB_MASK 0x4000
1176#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READYB__SHIFT 0xe
1177#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READY_MASK 0x8000
1178#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READY__SHIFT 0xf
1179#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READYB_MASK 0x10000
1180#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READYB__SHIFT 0x10
1181#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READY_MASK 0x20000
1182#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READY__SHIFT 0x11
1183#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READYB_MASK 0x40000
1184#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READYB__SHIFT 0x12
1185#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READY_MASK 0x80000
1186#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READY__SHIFT 0x13
1187#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READYB_MASK 0x100000
1188#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READYB__SHIFT 0x14
1189#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READY_MASK 0x200000
1190#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READY__SHIFT 0x15
1191#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READYB_MASK 0x400000
1192#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READYB__SHIFT 0x16
1193#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALIDB_READY_MASK 0x800000
1194#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALIDB_READY__SHIFT 0x17
1195#define CB_DEBUG_BUS_2__FC_CLEAR_QUAD_VALIDB_READYB_MASK 0x1
1196#define CB_DEBUG_BUS_2__FC_CLEAR_QUAD_VALIDB_READYB__SHIFT 0x0
1197#define CB_DEBUG_BUS_2__FC_QUAD_RESIDENCY_STALL_MASK 0x2
1198#define CB_DEBUG_BUS_2__FC_QUAD_RESIDENCY_STALL__SHIFT 0x1
1199#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READY_MASK 0x4
1200#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READY__SHIFT 0x2
1201#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READYB_MASK 0x8
1202#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READYB__SHIFT 0x3
1203#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READY_MASK 0x10
1204#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READY__SHIFT 0x4
1205#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READYB_MASK 0x20
1206#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READYB__SHIFT 0x5
1207#define CB_DEBUG_BUS_2__FOP_IN_VALID_READY_MASK 0x40
1208#define CB_DEBUG_BUS_2__FOP_IN_VALID_READY__SHIFT 0x6
1209#define CB_DEBUG_BUS_2__FOP_IN_VALID_READYB_MASK 0x80
1210#define CB_DEBUG_BUS_2__FOP_IN_VALID_READYB__SHIFT 0x7
1211#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READY_MASK 0x100
1212#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READY__SHIFT 0x8
1213#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READYB_MASK 0x200
1214#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READYB__SHIFT 0x9
1215#define CB_DEBUG_BUS_2__FOP_FMASK_RAW_STALL_MASK 0x400
1216#define CB_DEBUG_BUS_2__FOP_FMASK_RAW_STALL__SHIFT 0xa
1217#define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL_MASK 0x800
1218#define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL__SHIFT 0xb
1219#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READY_MASK 0x1000
1220#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READY__SHIFT 0xc
1221#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READYB_MASK 0x2000
1222#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READYB__SHIFT 0xd
1223#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READY_MASK 0x4000
1224#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READY__SHIFT 0xe
1225#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READYB_MASK 0x8000
1226#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READYB__SHIFT 0xf
1227#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READY_MASK 0x10000
1228#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READY__SHIFT 0x10
1229#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READYB_MASK 0x20000
1230#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READYB__SHIFT 0x11
1231#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READY_MASK 0x40000
1232#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READY__SHIFT 0x12
1233#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READYB_MASK 0x80000
1234#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READYB__SHIFT 0x13
1235#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READY_MASK 0x100000
1236#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READY__SHIFT 0x14
1237#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READYB_MASK 0x200000
1238#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READYB__SHIFT 0x15
1239#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY_MASK 0x400000
1240#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY__SHIFT 0x16
1241#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB_MASK 0x800000
1242#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB__SHIFT 0x17
1243#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READY_MASK 0x1
1244#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READY__SHIFT 0x0
1245#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READYB_MASK 0x2
1246#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READYB__SHIFT 0x1
1247#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY_MASK 0x4
1248#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY__SHIFT 0x2
1249#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB_MASK 0x8
1250#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB__SHIFT 0x3
1251#define CB_DEBUG_BUS_3__CC_BC_CS_FRAG_VALID_MASK 0x10
1252#define CB_DEBUG_BUS_3__CC_BC_CS_FRAG_VALID__SHIFT 0x4
1253#define CB_DEBUG_BUS_3__CC_SF_FULL_MASK 0x20
1254#define CB_DEBUG_BUS_3__CC_SF_FULL__SHIFT 0x5
1255#define CB_DEBUG_BUS_3__CC_RB_FULL_MASK 0x40
1256#define CB_DEBUG_BUS_3__CC_RB_FULL__SHIFT 0x6
1257#define CB_DEBUG_BUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL_MASK 0x80
1258#define CB_DEBUG_BUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL__SHIFT 0x7
1259#define CB_DEBUG_BUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL_MASK 0x100
1260#define CB_DEBUG_BUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL__SHIFT 0x8
1261#define CB_DEBUG_BUS_3__CM_TQ_FULL_MASK 0x200
1262#define CB_DEBUG_BUS_3__CM_TQ_FULL__SHIFT 0x9
1263#define CB_DEBUG_BUS_3__CM_TILE_RESIDENCY_STALL_MASK 0x400
1264#define CB_DEBUG_BUS_3__CM_TILE_RESIDENCY_STALL__SHIFT 0xa
1265#define CB_DEBUG_BUS_3__LQUAD_NO_TILE_MASK 0x800
1266#define CB_DEBUG_BUS_3__LQUAD_NO_TILE__SHIFT 0xb
1267#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_R_MASK 0x1000
1268#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_R__SHIFT 0xc
1269#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR_MASK 0x2000
1270#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR__SHIFT 0xd
1271#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR_MASK 0x4000
1272#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR__SHIFT 0xe
1273#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR_MASK 0x8000
1274#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR__SHIFT 0xf
1275#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR_MASK 0x10000
1276#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR__SHIFT 0x10
1277#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR_MASK 0x20000
1278#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR__SHIFT 0x11
1279#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR_MASK 0x40000
1280#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR__SHIFT 0x12
1281#define CB_DEBUG_BUS_3__CM_CACHE_HIT_MASK 0x80000
1282#define CB_DEBUG_BUS_3__CM_CACHE_HIT__SHIFT 0x13
1283#define CB_DEBUG_BUS_3__CM_CACHE_TAG_MISS_MASK 0x100000
1284#define CB_DEBUG_BUS_3__CM_CACHE_TAG_MISS__SHIFT 0x14
1285#define CB_DEBUG_BUS_3__CM_CACHE_SECTOR_MISS_MASK 0x200000
1286#define CB_DEBUG_BUS_3__CM_CACHE_SECTOR_MISS__SHIFT 0x15
1287#define CB_DEBUG_BUS_3__CM_CACHE_REEVICTION_STALL_MASK 0x400000
1288#define CB_DEBUG_BUS_3__CM_CACHE_REEVICTION_STALL__SHIFT 0x16
1289#define CB_DEBUG_BUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x800000
1290#define CB_DEBUG_BUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x17
1291#define CB_DEBUG_BUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x1
1292#define CB_DEBUG_BUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x0
1293#define CB_DEBUG_BUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x2
1294#define CB_DEBUG_BUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x1
1295#define CB_DEBUG_BUS_4__CM_CACHE_READ_OUTPUT_STALL_MASK 0x4
1296#define CB_DEBUG_BUS_4__CM_CACHE_READ_OUTPUT_STALL__SHIFT 0x2
1297#define CB_DEBUG_BUS_4__CM_CACHE_WRITE_OUTPUT_STALL_MASK 0x8
1298#define CB_DEBUG_BUS_4__CM_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x3
1299#define CB_DEBUG_BUS_4__CM_CACHE_ACK_OUTPUT_STALL_MASK 0x10
1300#define CB_DEBUG_BUS_4__CM_CACHE_ACK_OUTPUT_STALL__SHIFT 0x4
1301#define CB_DEBUG_BUS_4__CM_CACHE_STALL_MASK 0x20
1302#define CB_DEBUG_BUS_4__CM_CACHE_STALL__SHIFT 0x5
1303#define CB_DEBUG_BUS_4__FC_CACHE_HIT_MASK 0x40
1304#define CB_DEBUG_BUS_4__FC_CACHE_HIT__SHIFT 0x6
1305#define CB_DEBUG_BUS_4__FC_CACHE_TAG_MISS_MASK 0x80
1306#define CB_DEBUG_BUS_4__FC_CACHE_TAG_MISS__SHIFT 0x7
1307#define CB_DEBUG_BUS_4__FC_CACHE_SECTOR_MISS_MASK 0x100
1308#define CB_DEBUG_BUS_4__FC_CACHE_SECTOR_MISS__SHIFT 0x8
1309#define CB_DEBUG_BUS_4__FC_CACHE_REEVICTION_STALL_MASK 0x200
1310#define CB_DEBUG_BUS_4__FC_CACHE_REEVICTION_STALL__SHIFT 0x9
1311#define CB_DEBUG_BUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x400
1312#define CB_DEBUG_BUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0xa
1313#define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x800
1314#define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0xb
1315#define CB_DEBUG_BUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x1000
1316#define CB_DEBUG_BUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0xc
1317#define CB_DEBUG_BUS_4__FC_CACHE_READ_OUTPUT_STALL_MASK 0x2000
1318#define CB_DEBUG_BUS_4__FC_CACHE_READ_OUTPUT_STALL__SHIFT 0xd
1319#define CB_DEBUG_BUS_4__FC_CACHE_WRITE_OUTPUT_STALL_MASK 0x4000
1320#define CB_DEBUG_BUS_4__FC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0xe
1321#define CB_DEBUG_BUS_4__FC_CACHE_ACK_OUTPUT_STALL_MASK 0x8000
1322#define CB_DEBUG_BUS_4__FC_CACHE_ACK_OUTPUT_STALL__SHIFT 0xf
1323#define CB_DEBUG_BUS_4__FC_CACHE_STALL_MASK 0x10000
1324#define CB_DEBUG_BUS_4__FC_CACHE_STALL__SHIFT 0x10
1325#define CB_DEBUG_BUS_4__CC_CACHE_HIT_MASK 0x20000
1326#define CB_DEBUG_BUS_4__CC_CACHE_HIT__SHIFT 0x11
1327#define CB_DEBUG_BUS_4__CC_CACHE_TAG_MISS_MASK 0x40000
1328#define CB_DEBUG_BUS_4__CC_CACHE_TAG_MISS__SHIFT 0x12
1329#define CB_DEBUG_BUS_4__CC_CACHE_SECTOR_MISS_MASK 0x80000
1330#define CB_DEBUG_BUS_4__CC_CACHE_SECTOR_MISS__SHIFT 0x13
1331#define CB_DEBUG_BUS_4__CC_CACHE_REEVICTION_STALL_MASK 0x100000
1332#define CB_DEBUG_BUS_4__CC_CACHE_REEVICTION_STALL__SHIFT 0x14
1333#define CB_DEBUG_BUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x200000
1334#define CB_DEBUG_BUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x15
1335#define CB_DEBUG_BUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x400000
1336#define CB_DEBUG_BUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x16
1337#define CB_DEBUG_BUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x800000
1338#define CB_DEBUG_BUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x17
1339#define CB_DEBUG_BUS_5__CC_CACHE_READ_OUTPUT_STALL_MASK 0x1
1340#define CB_DEBUG_BUS_5__CC_CACHE_READ_OUTPUT_STALL__SHIFT 0x0
1341#define CB_DEBUG_BUS_5__CC_CACHE_WRITE_OUTPUT_STALL_MASK 0x2
1342#define CB_DEBUG_BUS_5__CC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x1
1343#define CB_DEBUG_BUS_5__CC_CACHE_ACK_OUTPUT_STALL_MASK 0x4
1344#define CB_DEBUG_BUS_5__CC_CACHE_ACK_OUTPUT_STALL__SHIFT 0x2
1345#define CB_DEBUG_BUS_5__CC_CACHE_STALL_MASK 0x8
1346#define CB_DEBUG_BUS_5__CC_CACHE_STALL__SHIFT 0x3
1347#define CB_DEBUG_BUS_5__CC_CACHE_WA_TO_RMW_CONVERSION_MASK 0x10
1348#define CB_DEBUG_BUS_5__CC_CACHE_WA_TO_RMW_CONVERSION__SHIFT 0x4
1349#define CB_DEBUG_BUS_5__CM_CACHE_FLUSH_MASK 0x20
1350#define CB_DEBUG_BUS_5__CM_CACHE_FLUSH__SHIFT 0x5
1351#define CB_DEBUG_BUS_5__CM_CACHE_TAGS_FLUSHED_MASK 0x40
1352#define CB_DEBUG_BUS_5__CM_CACHE_TAGS_FLUSHED__SHIFT 0x6
1353#define CB_DEBUG_BUS_5__CM_CACHE_SECTORS_FLUSHED_MASK 0x80
1354#define CB_DEBUG_BUS_5__CM_CACHE_SECTORS_FLUSHED__SHIFT 0x7
1355#define CB_DEBUG_BUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x100
1356#define CB_DEBUG_BUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x8
1357#define CB_DEBUG_BUS_5__FC_CACHE_FLUSH_MASK 0x200
1358#define CB_DEBUG_BUS_5__FC_CACHE_FLUSH__SHIFT 0x9
1359#define CB_DEBUG_BUS_5__FC_CACHE_TAGS_FLUSHED_MASK 0x400
1360#define CB_DEBUG_BUS_5__FC_CACHE_TAGS_FLUSHED__SHIFT 0xa
1361#define CB_DEBUG_BUS_5__FC_CACHE_SECTORS_FLUSHED_MASK 0x3800
1362#define CB_DEBUG_BUS_5__FC_CACHE_SECTORS_FLUSHED__SHIFT 0xb
1363#define CB_DEBUG_BUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x1c000
1364#define CB_DEBUG_BUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0xe
1365#define CB_DEBUG_BUS_5__CC_CACHE_FLUSH_MASK 0x20000
1366#define CB_DEBUG_BUS_5__CC_CACHE_FLUSH__SHIFT 0x11
1367#define CB_DEBUG_BUS_5__CC_CACHE_TAGS_FLUSHED_MASK 0x40000
1368#define CB_DEBUG_BUS_5__CC_CACHE_TAGS_FLUSHED__SHIFT 0x12
1369#define CB_DEBUG_BUS_5__CC_CACHE_SECTORS_FLUSHED_MASK 0x380000
1370#define CB_DEBUG_BUS_5__CC_CACHE_SECTORS_FLUSHED__SHIFT 0x13
1371#define CB_DEBUG_BUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x7
1372#define CB_DEBUG_BUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x0
1373#define CB_DEBUG_BUS_6__CM_MC_READ_REQUEST_MASK 0x8
1374#define CB_DEBUG_BUS_6__CM_MC_READ_REQUEST__SHIFT 0x3
1375#define CB_DEBUG_BUS_6__FC_MC_READ_REQUEST_MASK 0x10
1376#define CB_DEBUG_BUS_6__FC_MC_READ_REQUEST__SHIFT 0x4
1377#define CB_DEBUG_BUS_6__CC_MC_READ_REQUEST_MASK 0x20
1378#define CB_DEBUG_BUS_6__CC_MC_READ_REQUEST__SHIFT 0x5
1379#define CB_DEBUG_BUS_6__CM_MC_WRITE_REQUEST_MASK 0x40
1380#define CB_DEBUG_BUS_6__CM_MC_WRITE_REQUEST__SHIFT 0x6
1381#define CB_DEBUG_BUS_6__FC_MC_WRITE_REQUEST_MASK 0x80
1382#define CB_DEBUG_BUS_6__FC_MC_WRITE_REQUEST__SHIFT 0x7
1383#define CB_DEBUG_BUS_6__CC_MC_WRITE_REQUEST_MASK 0x100
1384#define CB_DEBUG_BUS_6__CC_MC_WRITE_REQUEST__SHIFT 0x8
1385#define CB_DEBUG_BUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x1fe00
1386#define CB_DEBUG_BUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x9
1387#define CB_DEBUG_BUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x7ff
1388#define CB_DEBUG_BUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x0
1389#define CB_DEBUG_BUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x1ff800
1390#define CB_DEBUG_BUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0xb
1391#define CB_DEBUG_BUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0xff
1392#define CB_DEBUG_BUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0
1393#define CB_DEBUG_BUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x7ff00
1394#define CB_DEBUG_BUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x8
1395#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE_MASK 0x80000
1396#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE__SHIFT 0x13
1397#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_DECOMPRESS_MASK 0x100000
1398#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_DECOMPRESS__SHIFT 0x14
1399#define CB_DEBUG_BUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR_MASK 0x200000
1400#define CB_DEBUG_BUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR__SHIFT 0x15
1401#define CB_DEBUG_BUS_8__FC_SEQUENCER_CLEAR_MASK 0x400000
1402#define CB_DEBUG_BUS_8__FC_SEQUENCER_CLEAR__SHIFT 0x16
1403#define CB_DEBUG_BUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x3ff
1404#define CB_DEBUG_BUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0
1405#define CB_DEBUG_BUS_9__CC_SURFACE_SYNC_MASK 0x400
1406#define CB_DEBUG_BUS_9__CC_SURFACE_SYNC__SHIFT 0xa
1407#define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT_MASK 0x800
1408#define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT__SHIFT 0xb
1409#define CB_DEBUG_BUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT_MASK 0x1000
1410#define CB_DEBUG_BUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT__SHIFT 0xc
1411#define CB_DEBUG_BUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT_MASK 0x2000
1412#define CB_DEBUG_BUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT__SHIFT 0xd
1413#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_MASK 0x4000
1414#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD__SHIFT 0xe
1415#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_PIXEL_MASK 0x78000
1416#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_PIXEL__SHIFT 0xf
1417#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT_MASK 0x80000
1418#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT__SHIFT 0x13
1419#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_TILE_MASK 0x100000
1420#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_TILE__SHIFT 0x14
1421#define CB_DEBUG_BUS_9__EVENT_ALL_MASK 0x200000
1422#define CB_DEBUG_BUS_9__EVENT_ALL__SHIFT 0x15
1423#define CB_DEBUG_BUS_9__EVENT_CACHE_FLUSH_TS_MASK 0x400000
1424#define CB_DEBUG_BUS_9__EVENT_CACHE_FLUSH_TS__SHIFT 0x16
1425#define CB_DEBUG_BUS_9__EVENT_CONTEXT_DONE_MASK 0x800000
1426#define CB_DEBUG_BUS_9__EVENT_CONTEXT_DONE__SHIFT 0x17
1427#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_MASK 0x1
1428#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH__SHIFT 0x0
1429#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x2
1430#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x1
1431#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT_MASK 0x4
1432#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT__SHIFT 0x2
1433#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS_MASK 0x8
1434#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x3
1435#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_META_MASK 0x10
1436#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_META__SHIFT 0x4
1437#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XC_MASK 0x20
1438#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XC__SHIFT 0x5
1439#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XD_MASK 0x40
1440#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XD__SHIFT 0x6
1441#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XE_MASK 0x80
1442#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XE__SHIFT 0x7
1443#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XF_MASK 0x100
1444#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XF__SHIFT 0x8
1445#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XC_MASK 0x200
1446#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XC__SHIFT 0x9
1447#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XD_MASK 0x400
1448#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XD__SHIFT 0xa
1449#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE_MASK 0x800
1450#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE__SHIFT 0xb
1451#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XF_MASK 0x1000
1452#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XF__SHIFT 0xc
1453#define CB_DEBUG_BUS_10__CORE_SCLK_VLD_MASK 0x2000
1454#define CB_DEBUG_BUS_10__CORE_SCLK_VLD__SHIFT 0xd
1455#define CB_DEBUG_BUS_10__REG_SCLK0_VLD_MASK 0x4000
1456#define CB_DEBUG_BUS_10__REG_SCLK0_VLD__SHIFT 0xe
1457#define CB_DEBUG_BUS_10__REG_SCLK1_VLD_MASK 0x8000
1458#define CB_DEBUG_BUS_10__REG_SCLK1_VLD__SHIFT 0xf
1459#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READY_MASK 0x10000
1460#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READY__SHIFT 0x10
1461#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READYB_MASK 0x20000
1462#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READYB__SHIFT 0x11
1463#define CB_DEBUG_BUS_10__FC_QUAD_RDLAT_FIFO_FULL_MASK 0x40000
1464#define CB_DEBUG_BUS_10__FC_QUAD_RDLAT_FIFO_FULL__SHIFT 0x12
1465#define CB_DEBUG_BUS_10__FC_TILE_RDLAT_FIFO_FULL_MASK 0x80000
1466#define CB_DEBUG_BUS_10__FC_TILE_RDLAT_FIFO_FULL__SHIFT 0x13
1467#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE_MASK 0x100000
1468#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__SHIFT 0x14
1469#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE_MASK 0x200000
1470#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x15
1471#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE_MASK 0x400000
1472#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x16
1473#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE_MASK 0x800000
1474#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x17
1475#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE_MASK 0x1
1476#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x0
1477#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE_MASK 0x2
1478#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x1
1479#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE_MASK 0x4
1480#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x2
1481#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE_MASK 0x8
1482#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x3
1483#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE_MASK 0x10
1484#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__SHIFT 0x4
1485#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE_MASK 0x20
1486#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__SHIFT 0x5
1487#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE_MASK 0x40
1488#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__SHIFT 0x6
1489#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE_MASK 0x80
1490#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__SHIFT 0x7
1491#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE_MASK 0x100
1492#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__SHIFT 0x8
1493#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE_MASK 0x200
1494#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__SHIFT 0x9
1495#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE_MASK 0x400
1496#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__SHIFT 0xa
1497#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE_MASK 0x800
1498#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__SHIFT 0xb
1499#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_1_FRAGMENT_MASK 0x1000
1500#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_1_FRAGMENT__SHIFT 0xc
1501#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_2_FRAGMENTS_MASK 0x2000
1502#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_2_FRAGMENTS__SHIFT 0xd
1503#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_3_FRAGMENTS_MASK 0x4000
1504#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_3_FRAGMENTS__SHIFT 0xe
1505#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_4_FRAGMENTS_MASK 0x8000
1506#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_4_FRAGMENTS__SHIFT 0xf
1507#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_5_FRAGMENTS_MASK 0x10000
1508#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_5_FRAGMENTS__SHIFT 0x10
1509#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_6_FRAGMENTS_MASK 0x20000
1510#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_6_FRAGMENTS__SHIFT 0x11
1511#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_7_FRAGMENTS_MASK 0x40000
1512#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_7_FRAGMENTS__SHIFT 0x12
1513#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_1_FRAGMENT_MASK 0x80000
1514#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_1_FRAGMENT__SHIFT 0x13
1515#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS_MASK 0x100000
1516#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS__SHIFT 0x14
1517#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS_MASK 0x200000
1518#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS__SHIFT 0x15
1519#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS_MASK 0x400000
1520#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS__SHIFT 0x16
1521#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS_MASK 0x800000
1522#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS__SHIFT 0x17
1523#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS_MASK 0x1
1524#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS__SHIFT 0x0
1525#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS_MASK 0x2
1526#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS__SHIFT 0x1
1527#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0_MASK 0x4
1528#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0__SHIFT 0x2
1529#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1_MASK 0x8
1530#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1__SHIFT 0x3
1531#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2_MASK 0x10
1532#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2__SHIFT 0x4
1533#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3_MASK 0x20
1534#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3__SHIFT 0x5
1535#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4_MASK 0x40
1536#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4__SHIFT 0x6
1537#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5_MASK 0x80
1538#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5__SHIFT 0x7
1539#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6_MASK 0x100
1540#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6__SHIFT 0x8
1541#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7_MASK 0x200
1542#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7__SHIFT 0x9
1543#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0_MASK 0x400
1544#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0__SHIFT 0xa
1545#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1_MASK 0x800
1546#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1__SHIFT 0xb
1547#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2_MASK 0x1000
1548#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2__SHIFT 0xc
1549#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3_MASK 0x2000
1550#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3__SHIFT 0xd
1551#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4_MASK 0x4000
1552#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4__SHIFT 0xe
1553#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5_MASK 0x8000
1554#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5__SHIFT 0xf
1555#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6_MASK 0x10000
1556#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6__SHIFT 0x10
1557#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7_MASK 0x20000
1558#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7__SHIFT 0x11
1559#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST_MASK 0x40000
1560#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST__SHIFT 0x12
1561#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS_MASK 0x80000
1562#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS__SHIFT 0x13
1563#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS_MASK 0x100000
1564#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS__SHIFT 0x14
1565#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT_MASK 0x200000
1566#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT__SHIFT 0x15
1567#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID_MASK 0x400000
1568#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID__SHIFT 0x16
1569#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK_MASK 0x800000
1570#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK__SHIFT 0x17
1571#define CB_DEBUG_BUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL_MASK 0x1
1572#define CB_DEBUG_BUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL__SHIFT 0x0
1573#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_MISS_MASK 0x2
1574#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_MISS__SHIFT 0x1
1575#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_HIT_MASK 0x4
1576#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_HIT__SHIFT 0x2
1577#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_MISS_MASK 0x8
1578#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_MISS__SHIFT 0x3
1579#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_HIT_MASK 0x10
1580#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_HIT__SHIFT 0x4
1581#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_1_SECTOR_MASK 0x20
1582#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_1_SECTOR__SHIFT 0x5
1583#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_2_SECTORS_MASK 0x40
1584#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_2_SECTORS__SHIFT 0x6
1585#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_3_SECTORS_MASK 0x80
1586#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_3_SECTORS__SHIFT 0x7
1587#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_4_SECTORS_MASK 0x100
1588#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_4_SECTORS__SHIFT 0x8
1589#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_HIT_MASK 0x200
1590#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_HIT__SHIFT 0x9
1591#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAG_MISS_MASK 0x400
1592#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAG_MISS__SHIFT 0xa
1593#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTOR_MISS_MASK 0x800
1594#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTOR_MISS__SHIFT 0xb
1595#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL_MASK 0x1000
1596#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL__SHIFT 0xc
1597#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x2000
1598#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0xd
1599#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x4000
1600#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0xe
1601#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x8000
1602#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0xf
1603#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL_MASK 0x10000
1604#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL__SHIFT 0x10
1605#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL_MASK 0x20000
1606#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x11
1607#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL_MASK 0x40000
1608#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL__SHIFT 0x12
1609#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_STALL_MASK 0x80000
1610#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_STALL__SHIFT 0x13
1611#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_FLUSH_MASK 0x100000
1612#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_FLUSH__SHIFT 0x14
1613#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED_MASK 0x200000
1614#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED__SHIFT 0x15
1615#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x400000
1616#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x16
1617#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED_MASK 0x800000
1618#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED__SHIFT 0x17
1619#define CB_DEBUG_BUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x7ff
1620#define CB_DEBUG_BUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0
1621#define CB_DEBUG_BUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT_MASK 0x3ff800
1622#define CB_DEBUG_BUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT__SHIFT 0xb
1623#define CB_DEBUG_BUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT_MASK 0x400000
1624#define CB_DEBUG_BUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT__SHIFT 0x16
1625#define CB_DEBUG_BUS_14__CC_PF_DCC_RDREQ_STALL_MASK 0x800000
1626#define CB_DEBUG_BUS_14__CC_PF_DCC_RDREQ_STALL__SHIFT 0x17
1627#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1_MASK 0x7
1628#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1__SHIFT 0x0
1629#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1_MASK 0x18
1630#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1__SHIFT 0x3
1631#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2_MASK 0x60
1632#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2__SHIFT 0x5
1633#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3_MASK 0x180
1634#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3__SHIFT 0x7
1635#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1_MASK 0x600
1636#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1__SHIFT 0x9
1637#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2_MASK 0x1800
1638#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2__SHIFT 0xb
1639#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3_MASK 0x6000
1640#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3__SHIFT 0xd
1641#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4_MASK 0x18000
1642#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4__SHIFT 0xf
1643#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5_MASK 0x60000
1644#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5__SHIFT 0x11
1645#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1_MASK 0x1
1646#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1__SHIFT 0x0
1647#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2_MASK 0x2
1648#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2__SHIFT 0x1
1649#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3_MASK 0x4
1650#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3__SHIFT 0x2
1651#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4_MASK 0x8
1652#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4__SHIFT 0x3
1653#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5_MASK 0x10
1654#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5__SHIFT 0x4
1655#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6_MASK 0x20
1656#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6__SHIFT 0x5
1657#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7_MASK 0x40
1658#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7__SHIFT 0x6
1659#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1
1660#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0
1661#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2
1662#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1
1663#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4
1664#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2
1665#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8
1666#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3
1667#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10
1668#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4
1669#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20
1670#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5
1671#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40
1672#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6
1673#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80
1674#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7
1675#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100
1676#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8
1677#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200
1678#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9
1679#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400
1680#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa
1681#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800
1682#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb
1683#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1
1684#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0
1685#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2
1686#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1
1687#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4
1688#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2
1689#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8
1690#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3
1691#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10
1692#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4
1693#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20
1694#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5
1695#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40
1696#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6
1697#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80
1698#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7
1699#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100
1700#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8
1701#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200
1702#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9
1703#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400
1704#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa
1705#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
1706#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb
1707#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000
1708#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc
1709#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000
1710#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd
1711#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000
1712#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe
1713#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000
1714#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf
1715#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000
1716#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10
1717#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000
1718#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11
1719#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000
1720#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12
1721#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000
1722#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13
1723#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000
1724#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14
1725#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000
1726#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15
1727#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3
1728#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0
1729#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4
1730#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2
1731#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8
1732#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3
1733#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10
1734#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4
1735#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20
1736#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5
1737#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40
1738#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6
1739#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80
1740#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7
1741#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100
1742#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8
1743#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200
1744#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9
1745#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400
1746#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa
1747#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
1748#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb
1749#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000
1750#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc
1751#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000
1752#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd
1753#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000
1754#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe
1755#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000
1756#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf
1757#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000
1758#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10
1759#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000
1760#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11
1761#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000
1762#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12
1763#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f
1764#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0
1765#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0
1766#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6
1767#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000
1768#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc
1769#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000
1770#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd
1771#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000
1772#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe
1773#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000
1774#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10
1775#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000
1776#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11
1777#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000
1778#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12
1779#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
1780#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
1781#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
1782#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
1783#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
1784#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
1785#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000
1786#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17
1787#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1
1788#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0
1789#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2
1790#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1
1791#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4
1792#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2
1793#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8
1794#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3
1795#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10
1796#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4
1797#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20
1798#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5
1799#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40
1800#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6
1801#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80
1802#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7
1803#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff
1804#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0
1805#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000
1806#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc
1807#define CP_DFY_CNTL__POLICY_MASK 0x1
1808#define CP_DFY_CNTL__POLICY__SHIFT 0x0
1809#define CP_DFY_CNTL__MTYPE_MASK 0xc
1810#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
1811#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000
1812#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
1813#define CP_DFY_CNTL__MODE_MASK 0x60000000
1814#define CP_DFY_CNTL__MODE__SHIFT 0x1d
1815#define CP_DFY_CNTL__ENABLE_MASK 0x80000000
1816#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
1817#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
1818#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
1819#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000
1820#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
1821#define CP_DFY_STAT__BUSY_MASK 0x80000000
1822#define CP_DFY_STAT__BUSY__SHIFT 0x1f
1823#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
1824#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
1825#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
1826#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
1827#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
1828#define CP_DFY_DATA_0__DATA__SHIFT 0x0
1829#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
1830#define CP_DFY_DATA_1__DATA__SHIFT 0x0
1831#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
1832#define CP_DFY_DATA_2__DATA__SHIFT 0x0
1833#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
1834#define CP_DFY_DATA_3__DATA__SHIFT 0x0
1835#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
1836#define CP_DFY_DATA_4__DATA__SHIFT 0x0
1837#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
1838#define CP_DFY_DATA_5__DATA__SHIFT 0x0
1839#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
1840#define CP_DFY_DATA_6__DATA__SHIFT 0x0
1841#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
1842#define CP_DFY_DATA_7__DATA__SHIFT 0x0
1843#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
1844#define CP_DFY_DATA_8__DATA__SHIFT 0x0
1845#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
1846#define CP_DFY_DATA_9__DATA__SHIFT 0x0
1847#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
1848#define CP_DFY_DATA_10__DATA__SHIFT 0x0
1849#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
1850#define CP_DFY_DATA_11__DATA__SHIFT 0x0
1851#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
1852#define CP_DFY_DATA_12__DATA__SHIFT 0x0
1853#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
1854#define CP_DFY_DATA_13__DATA__SHIFT 0x0
1855#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
1856#define CP_DFY_DATA_14__DATA__SHIFT 0x0
1857#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
1858#define CP_DFY_DATA_15__DATA__SHIFT 0x0
1859#define CP_DFY_CMD__OFFSET_MASK 0x1ff
1860#define CP_DFY_CMD__OFFSET__SHIFT 0x0
1861#define CP_DFY_CMD__SIZE_MASK 0xffff0000
1862#define CP_DFY_CMD__SIZE__SHIFT 0x10
1863#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff
1864#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
1865#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00
1866#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
1867#define CP_ATCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x3ff
1868#define CP_ATCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
1869#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
1870#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
1871#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
1872#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
1873#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
1874#define CP_RB_BASE__RB_BASE__SHIFT 0x0
1875#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
1876#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
1877#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
1878#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
1879#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
1880#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
1881#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
1882#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
1883#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
1884#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
1885#define CP_RB0_CNTL__MTYPE_MASK 0x18000
1886#define CP_RB0_CNTL__MTYPE__SHIFT 0xf
1887#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000
1888#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
1889#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
1890#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
1891#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1892#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1893#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000
1894#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
1895#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
1896#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1897#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1898#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1899#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
1900#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
1901#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
1902#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
1903#define CP_RB_CNTL__MTYPE_MASK 0x18000
1904#define CP_RB_CNTL__MTYPE__SHIFT 0xf
1905#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000
1906#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11
1907#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
1908#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
1909#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1910#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1911#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000
1912#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
1913#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
1914#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1915#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1916#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1917#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
1918#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
1919#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
1920#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
1921#define CP_RB1_CNTL__MTYPE_MASK 0x18000
1922#define CP_RB1_CNTL__MTYPE__SHIFT 0xf
1923#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
1924#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
1925#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1926#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1927#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000
1928#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
1929#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
1930#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1931#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1932#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1933#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
1934#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
1935#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
1936#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
1937#define CP_RB2_CNTL__MTYPE_MASK 0x18000
1938#define CP_RB2_CNTL__MTYPE__SHIFT 0xf
1939#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
1940#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
1941#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1942#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1943#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000
1944#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
1945#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
1946#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1947#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1948#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1949#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
1950#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
1951#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1952#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1953#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1954#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1955#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1956#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1957#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1958#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1959#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1960#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1961#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1962#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1963#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1964#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1965#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1966#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1967#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1968#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1969#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1970#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1971#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1972#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1973#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1974#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1975#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
1976#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
1977#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
1978#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
1979#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
1980#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
1981#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
1982#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
1983#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc
1984#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
1985#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff
1986#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
1987#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1988#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
1989#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1990#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1991#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1992#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1993#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000
1994#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
1995#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1996#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1997#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1998#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1999#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000
2000#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
2001#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
2002#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
2003#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2004#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2005#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2006#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2007#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2008#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2009#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2010#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2011#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2012#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2013#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2014#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2015#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2016#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2017#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
2018#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
2019#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2020#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2021#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2022#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2023#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000
2024#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
2025#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
2026#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
2027#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
2028#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
2029#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000
2030#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
2031#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
2032#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
2033#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
2034#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
2035#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2036#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2037#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2038#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2039#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2040#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2041#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
2042#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
2043#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
2044#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
2045#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
2046#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
2047#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
2048#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
2049#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2050#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2051#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2052#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2053#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000
2054#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
2055#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
2056#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
2057#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
2058#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
2059#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000
2060#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
2061#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
2062#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
2063#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
2064#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
2065#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2066#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2067#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2068#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2069#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2070#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2071#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
2072#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
2073#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
2074#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
2075#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
2076#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
2077#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
2078#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
2079#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2080#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2081#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2082#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2083#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000
2084#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
2085#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
2086#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
2087#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
2088#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
2089#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000
2090#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
2091#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
2092#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
2093#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
2094#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
2095#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2096#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2097#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2098#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2099#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2100#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2101#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
2102#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
2103#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
2104#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
2105#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
2106#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
2107#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
2108#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
2109#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
2110#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
2111#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
2112#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
2113#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000
2114#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
2115#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
2116#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
2117#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
2118#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
2119#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000
2120#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
2121#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
2122#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
2123#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
2124#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
2125#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
2126#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
2127#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
2128#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
2129#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
2130#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
2131#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
2132#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
2133#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
2134#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
2135#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
2136#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
2137#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
2138#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
2139#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
2140#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
2141#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
2142#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
2143#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000
2144#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
2145#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000
2146#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
2147#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
2148#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
2149#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000
2150#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
2151#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
2152#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
2153#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
2154#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
2155#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
2156#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
2157#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
2158#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
2159#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
2160#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
2161#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
2162#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
2163#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
2164#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
2165#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
2166#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
2167#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
2168#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
2169#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
2170#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
2171#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
2172#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
2173#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000
2174#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
2175#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
2176#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
2177#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
2178#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
2179#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000
2180#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
2181#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
2182#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
2183#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
2184#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
2185#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
2186#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
2187#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
2188#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
2189#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
2190#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
2191#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
2192#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
2193#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
2194#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
2195#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
2196#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
2197#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
2198#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
2199#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
2200#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
2201#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
2202#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
2203#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000
2204#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
2205#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
2206#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
2207#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
2208#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
2209#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000
2210#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
2211#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
2212#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
2213#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
2214#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
2215#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
2216#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
2217#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
2218#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
2219#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
2220#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
2221#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
2222#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
2223#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
2224#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
2225#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
2226#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
2227#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
2228#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
2229#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
2230#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
2231#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
2232#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
2233#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
2234#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
2235#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
2236#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
2237#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
2238#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
2239#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
2240#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
2241#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
2242#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
2243#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
2244#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
2245#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
2246#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
2247#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
2248#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
2249#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
2250#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
2251#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
2252#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
2253#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
2254#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
2255#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
2256#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
2257#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
2258#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
2259#define CP_RB_VMID__RB0_VMID_MASK 0xf
2260#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
2261#define CP_RB_VMID__RB1_VMID_MASK 0xf00
2262#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
2263#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
2264#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
2265#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
2266#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
2267#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
2268#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
2269#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
2270#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
2271#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
2272#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
2273#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
2274#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
2275#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
2276#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
2277#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
2278#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
2279#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
2280#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
2281#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
2282#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
2283#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
2284#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
2285#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
2286#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
2287#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff
2288#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
2289#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff
2290#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
2291#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
2292#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
2293#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
2294#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
2295#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
2296#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
2297#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
2298#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
2299#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
2300#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
2301#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
2302#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
2303#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
2304#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
2305#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
2306#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
2307#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
2308#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
2309#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
2310#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
2311#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
2312#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
2313#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
2314#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
2315#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
2316#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
2317#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
2318#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
2319#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
2320#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
2321#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
2322#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
2323#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
2324#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
2325#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
2326#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
2327#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
2328#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
2329#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
2330#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
2331#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
2332#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
2333#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
2334#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
2335#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
2336#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
2337#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
2338#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
2339#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
2340#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
2341#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
2342#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
2343#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
2344#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
2345#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
2346#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
2347#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
2348#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
2349#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
2350#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
2351#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
2352#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
2353#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
2354#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
2355#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
2356#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
2357#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
2358#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
2359#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
2360#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
2361#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
2362#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
2363#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
2364#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
2365#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
2366#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
2367#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
2368#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
2369#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
2370#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
2371#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
2372#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
2373#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
2374#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
2375#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
2376#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
2377#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
2378#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
2379#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
2380#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
2381#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1
2382#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
2383#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2
2384#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
2385#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100
2386#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
2387#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200
2388#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
2389#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400
2390#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
2391#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800
2392#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
2393#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000
2394#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
2395#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000
2396#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
2397#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000
2398#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
2399#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000
2400#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
2401#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
2402#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
2403#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
2404#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
2405#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c
2406#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
2407#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80
2408#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
2409#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
2410#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
2411#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
2412#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
2413#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
2414#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
2415#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
2416#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
2417#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0
2418#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
2419#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300
2420#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
2421#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00
2422#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
2423#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000
2424#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
2425#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
2426#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
2427#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff
2428#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
2429#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff
2430#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
2431#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff
2432#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
2433#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
2434#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
2435#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
2436#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
2437#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
2438#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
2439#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
2440#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
2441#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2442#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2443#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2444#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2445#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2446#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2447#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2448#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2449#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2450#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2451#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2452#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2453#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2454#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2455#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2456#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2457#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2458#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2459#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2460#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2461#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2462#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2463#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2464#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2465#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2466#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2467#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2468#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2469#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2470#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2471#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2472#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2473#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2474#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2475#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2476#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2477#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2478#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2479#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2480#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2481#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2482#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2483#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2484#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2485#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2486#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2487#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2488#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2489#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2490#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2491#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2492#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2493#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2494#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2495#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2496#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2497#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2498#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2499#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2500#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2501#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2502#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2503#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2504#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2505#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2506#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2507#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2508#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2509#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2510#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2511#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2512#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2513#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2514#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2515#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2516#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2517#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2518#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2519#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2520#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2521#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2522#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2523#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2524#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2525#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2526#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2527#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2528#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2529#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2530#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2531#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2532#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2533#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2534#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2535#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2536#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2537#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2538#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2539#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2540#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2541#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2542#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2543#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2544#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2545#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2546#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2547#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2548#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2549#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2550#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2551#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2552#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2553#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2554#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2555#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2556#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2557#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2558#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2559#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2560#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2561#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2562#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2563#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2564#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2565#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2566#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2567#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2568#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2569#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2570#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2571#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2572#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2573#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2574#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2575#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2576#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2577#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2578#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2579#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2580#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2581#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2582#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2583#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2584#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2585#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2586#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2587#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2588#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2589#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2590#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2591#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2592#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2593#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2594#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2595#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2596#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2597#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2598#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2599#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2600#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2601#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2602#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2603#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2604#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2605#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2606#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2607#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2608#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2609#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2610#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2611#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2612#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2613#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2614#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2615#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2616#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2617#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2618#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2619#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2620#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2621#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2622#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2623#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2624#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2625#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2626#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2627#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2628#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2629#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2630#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2631#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2632#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2633#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2634#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2635#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2636#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2637#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2638#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2639#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2640#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2641#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2642#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2643#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2644#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2645#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2646#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2647#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2648#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2649#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2650#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2651#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2652#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2653#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2654#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2655#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2656#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2657#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2658#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2659#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2660#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2661#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2662#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2663#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2664#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2665#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2666#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2667#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2668#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2669#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2670#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2671#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2672#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2673#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2674#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2675#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2676#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2677#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2678#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2679#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2680#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2681#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2682#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2683#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2684#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2685#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2686#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2687#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2688#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2689#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2690#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2691#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2692#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2693#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2694#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2695#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2696#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2697#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2698#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2699#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2700#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2701#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2702#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2703#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2704#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2705#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2706#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2707#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2708#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2709#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2710#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2711#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2712#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2713#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2714#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2715#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2716#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2717#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2718#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2719#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2720#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2721#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2722#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2723#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2724#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2725#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2726#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2727#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2728#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2729#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2730#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2731#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2732#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2733#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2734#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2735#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2736#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2737#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2738#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2739#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2740#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2741#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2742#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2743#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2744#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2745#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2746#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2747#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2748#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2749#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2750#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2751#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2752#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2753#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2754#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2755#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2756#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2757#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2758#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2759#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2760#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2761#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2762#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2763#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2764#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2765#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2766#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2767#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2768#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2769#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2770#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2771#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2772#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2773#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2774#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2775#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2776#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2777#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2778#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2779#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2780#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2781#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2782#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2783#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2784#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2785#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2786#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2787#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2788#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2789#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2790#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2791#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2792#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2793#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2794#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2795#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2796#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2797#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2798#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2799#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2800#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2801#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2802#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2803#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2804#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2805#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2806#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2807#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2808#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2809#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2810#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2811#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2812#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2813#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2814#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2815#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2816#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2817#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2818#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2819#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2820#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2821#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2822#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2823#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2824#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2825#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2826#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2827#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2828#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2829#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2830#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2831#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2832#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2833#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2834#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2835#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2836#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2837#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2838#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2839#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2840#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2841#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2842#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2843#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2844#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2845#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2846#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2847#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2848#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2849#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2850#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2851#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2852#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2853#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2854#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2855#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2856#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2857#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2858#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2859#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2860#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2861#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2862#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2863#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2864#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2865#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2866#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2867#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2868#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2869#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2870#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2871#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2872#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2873#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
2874#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
2875#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
2876#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
2877#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
2878#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
2879#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2880#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2881#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
2882#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
2883#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
2884#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
2885#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
2886#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
2887#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
2888#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
2889#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
2890#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
2891#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
2892#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
2893#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
2894#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
2895#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
2896#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
2897#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
2898#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
2899#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
2900#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
2901#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
2902#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
2903#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2904#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2905#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
2906#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
2907#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
2908#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
2909#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
2910#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
2911#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
2912#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
2913#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
2914#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
2915#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
2916#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
2917#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
2918#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
2919#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
2920#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
2921#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
2922#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
2923#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
2924#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
2925#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
2926#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
2927#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
2928#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
2929#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
2930#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
2931#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
2932#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
2933#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
2934#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
2935#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
2936#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
2937#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
2938#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
2939#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
2940#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
2941#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
2942#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
2943#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
2944#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
2945#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
2946#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
2947#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
2948#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
2949#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
2950#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
2951#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
2952#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
2953#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
2954#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2955#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff
2956#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2957#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff
2958#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2959#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff
2960#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2961#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff
2962#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2963#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
2964#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2965#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff
2966#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2967#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff
2968#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2969#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff
2970#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2971#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff
2972#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2973#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
2974#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
2975#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
2976#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
2977#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
2978#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
2979#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
2980#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
2981#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
2982#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
2983#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
2984#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
2985#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
2986#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
2987#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
2988#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
2989#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
2990#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
2991#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
2992#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
2993#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
2994#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
2995#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
2996#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
2997#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
2998#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
2999#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
3000#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
3001#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
3002#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
3003#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
3004#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
3005#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000
3006#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
3007#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff
3008#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
3009#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000
3010#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
3011#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff
3012#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
3013#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000
3014#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c
3015#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
3016#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
3017#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
3018#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
3019#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000
3020#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
3021#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff
3022#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
3023#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf
3024#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
3025#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000
3026#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17
3027#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000
3028#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
3029#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000
3030#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b
3031#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1
3032#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
3033#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10
3034#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
3035#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20
3036#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
3037#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
3038#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
3039#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
3040#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
3041#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
3042#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
3043#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
3044#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
3045#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
3046#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
3047#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
3048#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
3049#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
3050#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
3051#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
3052#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
3053#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
3054#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
3055#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
3056#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
3057#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
3058#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
3059#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000
3060#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd
3061#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
3062#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
3063#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
3064#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
3065#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
3066#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
3067#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
3068#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
3069#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
3070#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
3071#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
3072#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
3073#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
3074#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
3075#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
3076#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
3077#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
3078#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
3079#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
3080#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
3081#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
3082#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
3083#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
3084#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
3085#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
3086#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
3087#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
3088#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
3089#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
3090#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
3091#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
3092#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
3093#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
3094#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
3095#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
3096#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
3097#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
3098#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
3099#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
3100#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
3101#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
3102#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
3103#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
3104#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
3105#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
3106#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
3107#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
3108#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
3109#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
3110#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
3111#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
3112#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
3113#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
3114#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
3115#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
3116#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
3117#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
3118#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
3119#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
3120#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
3121#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
3122#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
3123#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
3124#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
3125#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
3126#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
3127#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
3128#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
3129#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
3130#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
3131#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
3132#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
3133#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
3134#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
3135#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
3136#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
3137#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
3138#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
3139#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
3140#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
3141#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
3142#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
3143#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
3144#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
3145#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000
3146#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16
3147#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000
3148#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17
3149#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000
3150#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18
3151#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
3152#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
3153#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
3154#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
3155#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
3156#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
3157#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
3158#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
3159#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
3160#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
3161#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
3162#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
3163#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
3164#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
3165#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
3166#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
3167#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
3168#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
3169#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
3170#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
3171#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
3172#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
3173#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
3174#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
3175#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
3176#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
3177#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
3178#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
3179#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000
3180#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
3181#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000
3182#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11
3183#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000
3184#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
3185#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000
3186#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
3187#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000
3188#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
3189#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
3190#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
3191#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
3192#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
3193#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
3194#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
3195#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
3196#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
3197#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
3198#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
3199#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
3200#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
3201#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
3202#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
3203#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
3204#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
3205#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
3206#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
3207#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
3208#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
3209#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
3210#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
3211#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
3212#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
3213#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
3214#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
3215#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
3216#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
3217#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
3218#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
3219#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
3220#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
3221#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
3222#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
3223#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
3224#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
3225#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
3226#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
3227#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
3228#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
3229#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
3230#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
3231#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
3232#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
3233#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
3234#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
3235#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
3236#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
3237#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
3238#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
3239#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
3240#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
3241#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
3242#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
3243#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
3244#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
3245#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
3246#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
3247#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
3248#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
3249#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
3250#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
3251#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
3252#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
3253#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
3254#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
3255#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
3256#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
3257#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
3258#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
3259#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
3260#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
3261#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
3262#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
3263#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
3264#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
3265#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
3266#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
3267#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80
3268#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7
3269#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100
3270#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8
3271#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200
3272#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9
3273#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
3274#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
3275#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
3276#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
3277#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000
3278#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
3279#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000
3280#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
3281#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000
3282#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
3283#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000
3284#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
3285#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000
3286#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
3287#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000
3288#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
3289#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
3290#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
3291#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
3292#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
3293#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
3294#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
3295#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
3296#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
3297#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
3298#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
3299#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
3300#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
3301#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff
3302#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
3303#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
3304#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
3305#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
3306#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
3307#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
3308#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
3309#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
3310#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
3311#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
3312#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
3313#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
3314#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
3315#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
3316#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
3317#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
3318#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
3319#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
3320#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
3321#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
3322#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
3323#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
3324#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
3325#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
3326#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
3327#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
3328#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
3329#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
3330#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
3331#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
3332#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
3333#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
3334#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
3335#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
3336#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
3337#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
3338#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
3339#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
3340#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
3341#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
3342#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
3343#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
3344#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
3345#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
3346#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
3347#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
3348#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
3349#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
3350#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
3351#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
3352#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
3353#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
3354#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
3355#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
3356#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
3357#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
3358#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
3359#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
3360#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
3361#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
3362#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
3363#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
3364#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
3365#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
3366#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
3367#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
3368#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
3369#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
3370#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
3371#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
3372#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
3373#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
3374#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
3375#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
3376#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
3377#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
3378#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
3379#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
3380#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
3381#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
3382#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
3383#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
3384#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
3385#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
3386#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
3387#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
3388#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
3389#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
3390#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
3391#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
3392#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
3393#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
3394#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
3395#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
3396#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
3397#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
3398#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
3399#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
3400#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
3401#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
3402#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
3403#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000
3404#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c
3405#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000
3406#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e
3407#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
3408#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
3409#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
3410#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
3411#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
3412#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
3413#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
3414#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
3415#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
3416#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
3417#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
3418#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
3419#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
3420#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
3421#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000
3422#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
3423#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000
3424#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b
3425#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
3426#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
3427#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
3428#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
3429#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
3430#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
3431#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
3432#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
3433#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff
3434#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
3435#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
3436#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
3437#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
3438#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
3439#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
3440#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
3441#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
3442#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
3443#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
3444#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
3445#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
3446#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
3447#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
3448#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
3449#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
3450#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
3451#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
3452#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
3453#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
3454#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
3455#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
3456#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
3457#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
3458#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
3459#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
3460#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
3461#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
3462#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
3463#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
3464#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
3465#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
3466#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
3467#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
3468#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
3469#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
3470#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
3471#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
3472#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
3473#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
3474#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
3475#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
3476#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
3477#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
3478#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
3479#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
3480#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
3481#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
3482#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
3483#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
3484#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
3485#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
3486#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
3487#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
3488#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
3489#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
3490#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
3491#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
3492#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
3493#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
3494#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
3495#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
3496#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
3497#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
3498#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
3499#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
3500#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
3501#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
3502#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
3503#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
3504#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
3505#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
3506#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
3507#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
3508#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
3509#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
3510#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
3511#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
3512#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
3513#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
3514#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
3515#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
3516#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
3517#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
3518#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
3519#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
3520#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
3521#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
3522#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
3523#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
3524#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
3525#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
3526#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
3527#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
3528#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
3529#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
3530#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
3531#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
3532#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
3533#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
3534#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
3535#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000
3536#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19
3537#define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000
3538#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b
3539#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000
3540#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19
3541#define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000
3542#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b
3543#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
3544#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
3545#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
3546#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
3547#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
3548#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
3549#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
3550#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
3551#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
3552#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
3553#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
3554#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
3555#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
3556#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
3557#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
3558#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
3559#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
3560#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
3561#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
3562#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
3563#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
3564#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
3565#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
3566#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
3567#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
3568#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
3569#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
3570#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
3571#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
3572#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
3573#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
3574#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
3575#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
3576#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
3577#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
3578#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
3579#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
3580#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
3581#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
3582#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
3583#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
3584#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
3585#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000
3586#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
3587#define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000
3588#define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b
3589#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
3590#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
3591#define CP_APPEND_DATA__DATA_MASK 0xffffffff
3592#define CP_APPEND_DATA__DATA__SHIFT 0x0
3593#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
3594#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
3595#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
3596#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
3597#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
3598#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
3599#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
3600#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
3601#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
3602#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
3603#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
3604#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
3605#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
3606#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
3607#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
3608#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
3609#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
3610#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
3611#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
3612#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
3613#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
3614#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
3615#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
3616#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
3617#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
3618#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
3619#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
3620#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
3621#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
3622#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
3623#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
3624#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
3625#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
3626#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
3627#define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000
3628#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14
3629#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000
3630#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
3631#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
3632#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
3633#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
3634#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
3635#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
3636#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
3637#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
3638#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
3639#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
3640#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
3641#define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000
3642#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14
3643#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000
3644#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
3645#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
3646#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
3647#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
3648#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
3649#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
3650#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
3651#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
3652#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
3653#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
3654#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
3655#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
3656#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
3657#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
3658#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
3659#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
3660#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
3661#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
3662#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
3663#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
3664#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
3665#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
3666#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
3667#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
3668#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
3669#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
3670#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
3671#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
3672#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
3673#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
3674#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
3675#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
3676#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
3677#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
3678#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
3679#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
3680#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
3681#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
3682#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
3683#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4
3684#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2
3685#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8
3686#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
3687#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
3688#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
3689#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
3690#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
3691#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
3692#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
3693#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
3694#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
3695#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
3696#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
3697#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
3698#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
3699#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
3700#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
3701#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
3702#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
3703#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
3704#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
3705#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
3706#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
3707#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
3708#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
3709#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
3710#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
3711#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
3712#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
3713#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
3714#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
3715#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
3716#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
3717#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
3718#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
3719#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
3720#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
3721#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
3722#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
3723#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
3724#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
3725#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
3726#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
3727#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000
3728#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
3729#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000
3730#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f
3731#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
3732#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
3733#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
3734#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
3735#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
3736#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
3737#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
3738#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
3739#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
3740#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
3741#define CP_COHER_STATUS__MEID_MASK 0x3000000
3742#define CP_COHER_STATUS__MEID__SHIFT 0x18
3743#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
3744#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
3745#define CP_COHER_STATUS__STATUS_MASK 0x80000000
3746#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
3747#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
3748#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
3749#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
3750#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
3751#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
3752#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
3753#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
3754#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
3755#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
3756#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
3757#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
3758#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
3759#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
3760#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
3761#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
3762#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
3763#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
3764#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
3765#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
3766#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
3767#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
3768#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
3769#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
3770#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
3771#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00
3772#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa
3773#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
3774#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
3775#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
3776#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
3777#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
3778#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
3779#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000
3780#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16
3781#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
3782#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
3783#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
3784#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
3785#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
3786#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
3787#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
3788#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
3789#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
3790#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
3791#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
3792#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
3793#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
3794#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
3795#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
3796#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
3797#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
3798#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
3799#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
3800#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
3801#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
3802#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
3803#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
3804#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
3805#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
3806#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
3807#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
3808#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
3809#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
3810#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
3811#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
3812#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
3813#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00
3814#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa
3815#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
3816#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
3817#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
3818#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
3819#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
3820#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
3821#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000
3822#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16
3823#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
3824#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
3825#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
3826#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
3827#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
3828#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
3829#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
3830#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
3831#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
3832#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
3833#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
3834#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
3835#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
3836#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
3837#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
3838#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
3839#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
3840#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
3841#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
3842#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
3843#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
3844#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
3845#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
3846#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
3847#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
3848#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
3849#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
3850#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
3851#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
3852#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
3853#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
3854#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
3855#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
3856#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
3857#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
3858#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
3859#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
3860#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
3861#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
3862#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
3863#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
3864#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
3865#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
3866#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
3867#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
3868#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
3869#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
3870#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
3871#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
3872#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
3873#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
3874#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
3875#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
3876#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
3877#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
3878#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
3879#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
3880#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
3881#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
3882#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
3883#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
3884#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
3885#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
3886#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
3887#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
3888#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
3889#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
3890#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
3891#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
3892#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
3893#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
3894#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
3895#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff
3896#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
3897#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3
3898#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
3899#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3
3900#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
3901#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1
3902#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
3903#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
3904#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
3905#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
3906#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
3907#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
3908#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
3909#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
3910#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
3911#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff
3912#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
3913#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
3914#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
3915#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff
3916#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
3917#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
3918#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
3919#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff
3920#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
3921#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
3922#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
3923#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3
3924#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
3925#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff
3926#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
3927#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff
3928#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
3929#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1
3930#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
3931#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2
3932#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
3933#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4
3934#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
3935#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8
3936#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
3937#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10
3938#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
3939#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20
3940#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
3941#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40
3942#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
3943#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80
3944#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
3945#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
3946#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
3947#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
3948#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
3949#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
3950#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
3951#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
3952#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
3953#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
3954#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
3955#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
3956#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
3957#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
3958#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
3959#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000
3960#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
3961#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
3962#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
3963#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
3964#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
3965#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
3966#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
3967#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
3968#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
3969#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
3970#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
3971#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
3972#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
3973#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
3974#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
3975#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
3976#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
3977#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
3978#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
3979#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
3980#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
3981#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
3982#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
3983#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
3984#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
3985#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
3986#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
3987#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
3988#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
3989#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
3990#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
3991#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
3992#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
3993#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
3994#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
3995#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
3996#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
3997#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
3998#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
3999#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
4000#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
4001#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
4002#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
4003#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
4004#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
4005#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
4006#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
4007#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
4008#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
4009#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
4010#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
4011#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
4012#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
4013#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
4014#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
4015#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
4016#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
4017#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
4018#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
4019#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
4020#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
4021#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
4022#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
4023#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
4024#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
4025#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
4026#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
4027#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
4028#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
4029#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
4030#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
4031#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
4032#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
4033#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
4034#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
4035#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
4036#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
4037#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
4038#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
4039#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
4040#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
4041#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
4042#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
4043#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
4044#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
4045#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
4046#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
4047#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
4048#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
4049#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
4050#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
4051#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
4052#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
4053#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
4054#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
4055#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
4056#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
4057#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
4058#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
4059#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
4060#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
4061#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
4062#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
4063#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000
4064#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
4065#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000
4066#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
4067#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000
4068#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12
4069#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000
4070#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13
4071#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000
4072#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14
4073#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
4074#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
4075#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
4076#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
4077#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
4078#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
4079#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
4080#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
4081#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
4082#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
4083#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
4084#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
4085#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
4086#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
4087#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
4088#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
4089#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
4090#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
4091#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
4092#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
4093#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
4094#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
4095#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
4096#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
4097#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
4098#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
4099#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
4100#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
4101#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
4102#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
4103#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
4104#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
4105#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
4106#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
4107#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
4108#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
4109#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
4110#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
4111#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
4112#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
4113#define CP_STAT__DC_BUSY_MASK 0x2000
4114#define CP_STAT__DC_BUSY__SHIFT 0xd
4115#define CP_STAT__ATCL2IU_BUSY_MASK 0x4000
4116#define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe
4117#define CP_STAT__PFP_BUSY_MASK 0x8000
4118#define CP_STAT__PFP_BUSY__SHIFT 0xf
4119#define CP_STAT__MEQ_BUSY_MASK 0x10000
4120#define CP_STAT__MEQ_BUSY__SHIFT 0x10
4121#define CP_STAT__ME_BUSY_MASK 0x20000
4122#define CP_STAT__ME_BUSY__SHIFT 0x11
4123#define CP_STAT__QUERY_BUSY_MASK 0x40000
4124#define CP_STAT__QUERY_BUSY__SHIFT 0x12
4125#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
4126#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
4127#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
4128#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
4129#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
4130#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
4131#define CP_STAT__DMA_BUSY_MASK 0x400000
4132#define CP_STAT__DMA_BUSY__SHIFT 0x16
4133#define CP_STAT__RCIU_BUSY_MASK 0x800000
4134#define CP_STAT__RCIU_BUSY__SHIFT 0x17
4135#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
4136#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
4137#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
4138#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
4139#define CP_STAT__CE_BUSY_MASK 0x4000000
4140#define CP_STAT__CE_BUSY__SHIFT 0x1a
4141#define CP_STAT__TCIU_BUSY_MASK 0x8000000
4142#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
4143#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
4144#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
4145#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
4146#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
4147#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
4148#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
4149#define CP_STAT__CP_BUSY_MASK 0x80000000
4150#define CP_STAT__CP_BUSY__SHIFT 0x1f
4151#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
4152#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
4153#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
4154#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
4155#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
4156#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
4157#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
4158#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
4159#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
4160#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
4161#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
4162#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
4163#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
4164#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
4165#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00
4166#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
4167#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
4168#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
4169#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
4170#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
4171#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
4172#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
4173#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
4174#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
4175#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000
4176#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
4177#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000
4178#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
4179#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000
4180#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
4181#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
4182#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
4183#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
4184#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
4185#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
4186#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
4187#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
4188#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
4189#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
4190#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
4191#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
4192#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
4193#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
4194#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
4195#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
4196#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
4197#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
4198#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
4199#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
4200#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
4201#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1
4202#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
4203#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
4204#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
4205#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
4206#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
4207#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
4208#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
4209#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
4210#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
4211#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
4212#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
4213#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
4214#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
4215#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
4216#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
4217#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
4218#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
4219#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
4220#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
4221#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
4222#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
4223#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
4224#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
4225#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
4226#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
4227#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
4228#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
4229#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
4230#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
4231#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
4232#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
4233#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
4234#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
4235#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
4236#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
4237#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
4238#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
4239#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
4240#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
4241#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
4242#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
4243#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
4244#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
4245#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
4246#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
4247#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
4248#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
4249#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
4250#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
4251#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
4252#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
4253#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
4254#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
4255#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
4256#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
4257#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
4258#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
4259#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
4260#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
4261#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
4262#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
4263#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
4264#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
4265#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
4266#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
4267#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
4268#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
4269#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
4270#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
4271#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
4272#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
4273#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
4274#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
4275#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
4276#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
4277#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
4278#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
4279#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
4280#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
4281#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
4282#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
4283#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
4284#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
4285#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
4286#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
4287#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
4288#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
4289#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
4290#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
4291#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
4292#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
4293#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
4294#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
4295#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
4296#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
4297#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
4298#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
4299#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
4300#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
4301#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
4302#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
4303#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
4304#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
4305#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000
4306#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
4307#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
4308#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
4309#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
4310#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
4311#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
4312#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
4313#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
4314#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
4315#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
4316#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
4317#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
4318#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
4319#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
4320#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
4321#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
4322#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
4323#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
4324#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
4325#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
4326#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
4327#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
4328#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
4329#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
4330#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
4331#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
4332#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
4333#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
4334#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
4335#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
4336#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
4337#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
4338#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
4339#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
4340#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
4341#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
4342#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
4343#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
4344#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
4345#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
4346#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
4347#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800
4348#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
4349#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
4350#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
4351#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
4352#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
4353#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000
4354#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
4355#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
4356#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
4357#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
4358#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
4359#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000
4360#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
4361#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
4362#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
4363#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
4364#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
4365#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
4366#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
4367#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
4368#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
4369#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
4370#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
4371#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
4372#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
4373#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
4374#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
4375#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
4376#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
4377#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
4378#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
4379#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
4380#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
4381#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
4382#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
4383#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
4384#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
4385#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
4386#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
4387#define CP_RINGID__RINGID_MASK 0x3
4388#define CP_RINGID__RINGID__SHIFT 0x0
4389#define CP_PIPEID__PIPE_ID_MASK 0x3
4390#define CP_PIPEID__PIPE_ID__SHIFT 0x0
4391#define CP_VMID__VMID_MASK 0xf
4392#define CP_VMID__VMID__SHIFT 0x0
4393#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
4394#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
4395#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
4396#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
4397#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
4398#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
4399#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f
4400#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
4401#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0
4402#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
4403#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00
4404#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
4405#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
4406#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
4407#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
4408#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
4409#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
4410#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
4411#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2
4412#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
4413#define CP_HQD_VMID__VMID_MASK 0xf
4414#define CP_HQD_VMID__VMID__SHIFT 0x0
4415#define CP_HQD_VMID__IB_VMID_MASK 0xf00
4416#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
4417#define CP_HQD_VMID__VQID_MASK 0x3ff0000
4418#define CP_HQD_VMID__VQID__SHIFT 0x10
4419#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
4420#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
4421#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
4422#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
4423#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000
4424#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
4425#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000
4426#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
4427#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000
4428#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
4429#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
4430#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
4431#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
4432#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
4433#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
4434#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
4435#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
4436#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
4437#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
4438#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
4439#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
4440#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
4441#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000
4442#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
4443#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
4444#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
4445#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
4446#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
4447#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
4448#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
4449#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
4450#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
4451#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
4452#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
4453#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
4454#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
4455#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
4456#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
4457#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1
4458#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
4459#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2
4460#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
4461#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
4462#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
4463#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000
4464#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17
4465#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
4466#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
4467#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
4468#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
4469#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
4470#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
4471#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
4472#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
4473#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
4474#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
4475#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
4476#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
4477#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
4478#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
4479#define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000
4480#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf
4481#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000
4482#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
4483#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
4484#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
4485#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
4486#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
4487#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000
4488#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
4489#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000
4490#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
4491#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
4492#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
4493#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
4494#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
4495#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
4496#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
4497#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
4498#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
4499#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
4500#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
4501#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
4502#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
4503#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
4504#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
4505#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
4506#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
4507#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
4508#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
4509#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
4510#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
4511#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
4512#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
4513#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000
4514#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
4515#define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000
4516#define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b
4517#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
4518#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
4519#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
4520#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
4521#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
4522#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
4523#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800
4524#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
4525#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
4526#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
4527#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000
4528#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
4529#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
4530#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
4531#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000
4532#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
4533#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
4534#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
4535#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000
4536#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
4537#define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000
4538#define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b
4539#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
4540#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
4541#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
4542#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
4543#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
4544#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
4545#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
4546#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
4547#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7
4548#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
4549#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
4550#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
4551#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
4552#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
4553#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200
4554#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
4555#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400
4556#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
4557#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
4558#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
4559#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1
4560#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
4561#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2
4562#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
4563#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10
4564#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
4565#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20
4566#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
4567#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
4568#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
4569#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
4570#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
4571#define CP_HQD_MSG_TYPE__ACTION_MASK 0x7
4572#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
4573#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70
4574#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
4575#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
4576#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
4577#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
4578#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
4579#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
4580#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
4581#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
4582#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
4583#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff
4584#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
4585#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3
4586#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
4587#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc
4588#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
4589#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70
4590#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
4591#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80
4592#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
4593#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100
4594#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
4595#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200
4596#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
4597#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00
4598#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa
4599#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
4600#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
4601#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff
4602#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
4603#define CP_MQD_CONTROL__VMID_MASK 0xf
4604#define CP_MQD_CONTROL__VMID__SHIFT 0x0
4605#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000
4606#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
4607#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000
4608#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
4609#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
4610#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
4611#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000
4612#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
4613#define CP_MQD_CONTROL__MTYPE_MASK 0x18000000
4614#define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b
4615#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff
4616#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
4617#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff
4618#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
4619#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
4620#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
4621#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
4622#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
4623#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
4624#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
4625#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
4626#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
4627#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
4628#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
4629#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
4630#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
4631#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
4632#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
4633#define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000
4634#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf
4635#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000
4636#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
4637#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000
4638#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
4639#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000
4640#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
4641#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
4642#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
4643#define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff
4644#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
4645#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000
4646#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
4647#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000
4648#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
4649#define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff
4650#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
4651#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000
4652#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
4653#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff
4654#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
4655#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000
4656#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
4657#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000
4658#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
4659#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
4660#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
4661#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1
4662#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0
4663#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6
4664#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1
4665#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8
4666#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
4667#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc
4668#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
4669#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000
4670#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
4671#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc
4672#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
4673#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000
4674#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
4675#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1
4676#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
4677#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2
4678#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
4679#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0
4680#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
4681#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000
4682#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
4683#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf
4684#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
4685#define CP_HQD_ERROR__SUA_ERROR_MASK 0x10
4686#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
4687#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff
4688#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
4689#define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff
4690#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0
4691#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
4692#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
4693#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
4694#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
4695#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
4696#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
4697#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
4698#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
4699#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
4700#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
4701#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
4702#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
4703#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
4704#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
4705#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
4706#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
4707#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
4708#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
4709#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
4710#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
4711#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
4712#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
4713#define DB_Z_INFO__FORMAT_MASK 0x3
4714#define DB_Z_INFO__FORMAT__SHIFT 0x0
4715#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
4716#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
4717#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
4718#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
4719#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
4720#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
4721#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000
4722#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
4723#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
4724#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
4725#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
4726#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
4727#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
4728#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
4729#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000
4730#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
4731#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
4732#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
4733#define DB_STENCIL_INFO__FORMAT_MASK 0x1
4734#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
4735#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
4736#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
4737#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
4738#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
4739#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
4740#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
4741#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
4742#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
4743#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000
4744#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
4745#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
4746#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
4747#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
4748#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
4749#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
4750#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
4751#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
4752#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
4753#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
4754#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
4755#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
4756#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
4757#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
4758#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
4759#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
4760#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
4761#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
4762#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
4763#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
4764#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
4765#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
4766#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
4767#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
4768#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
4769#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
4770#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
4771#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
4772#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
4773#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
4774#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
4775#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
4776#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
4777#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000
4778#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
4779#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
4780#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
4781#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
4782#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
4783#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
4784#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
4785#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
4786#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
4787#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
4788#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
4789#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
4790#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
4791#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
4792#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
4793#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
4794#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
4795#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
4796#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
4797#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
4798#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
4799#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
4800#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
4801#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
4802#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
4803#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
4804#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
4805#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
4806#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
4807#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
4808#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
4809#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
4810#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
4811#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
4812#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
4813#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
4814#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
4815#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
4816#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
4817#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
4818#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
4819#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
4820#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
4821#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
4822#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
4823#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
4824#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
4825#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
4826#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
4827#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
4828#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
4829#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
4830#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
4831#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
4832#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
4833#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
4834#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
4835#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
4836#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
4837#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
4838#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
4839#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
4840#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
4841#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
4842#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
4843#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
4844#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
4845#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
4846#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
4847#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
4848#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
4849#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
4850#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
4851#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
4852#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
4853#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
4854#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
4855#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
4856#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
4857#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
4858#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
4859#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
4860#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
4861#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
4862#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
4863#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
4864#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
4865#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
4866#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
4867#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
4868#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
4869#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
4870#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
4871#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
4872#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
4873#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
4874#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
4875#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
4876#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
4877#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
4878#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
4879#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
4880#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
4881#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
4882#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
4883#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
4884#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
4885#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
4886#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
4887#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
4888#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
4889#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
4890#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
4891#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
4892#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
4893#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
4894#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
4895#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
4896#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
4897#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
4898#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
4899#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
4900#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
4901#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
4902#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
4903#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
4904#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
4905#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
4906#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
4907#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
4908#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
4909#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
4910#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
4911#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
4912#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
4913#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
4914#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
4915#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
4916#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
4917#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
4918#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
4919#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
4920#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
4921#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x8000
4922#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf
4923#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
4924#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
4925#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
4926#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
4927#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
4928#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
4929#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
4930#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
4931#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
4932#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
4933#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
4934#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
4935#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
4936#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
4937#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
4938#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
4939#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
4940#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
4941#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
4942#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
4943#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
4944#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
4945#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
4946#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
4947#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000
4948#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11
4949#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
4950#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
4951#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
4952#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
4953#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
4954#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
4955#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
4956#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
4957#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
4958#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
4959#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
4960#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
4961#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
4962#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
4963#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
4964#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
4965#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
4966#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
4967#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
4968#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
4969#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
4970#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
4971#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
4972#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
4973#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
4974#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
4975#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
4976#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
4977#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
4978#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
4979#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
4980#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
4981#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
4982#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
4983#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
4984#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
4985#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
4986#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
4987#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
4988#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
4989#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
4990#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
4991#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
4992#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
4993#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
4994#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
4995#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
4996#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
4997#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
4998#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
4999#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
5000#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
5001#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
5002#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
5003#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
5004#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
5005#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
5006#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
5007#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
5008#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
5009#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
5010#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
5011#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
5012#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
5013#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
5014#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
5015#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
5016#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
5017#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
5018#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
5019#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
5020#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
5021#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
5022#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
5023#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
5024#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
5025#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
5026#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
5027#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
5028#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
5029#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
5030#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
5031#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
5032#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
5033#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
5034#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
5035#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
5036#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
5037#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
5038#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
5039#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
5040#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
5041#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
5042#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
5043#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
5044#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
5045#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
5046#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
5047#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
5048#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
5049#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
5050#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
5051#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
5052#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
5053#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
5054#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
5055#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
5056#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
5057#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
5058#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
5059#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
5060#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
5061#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
5062#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
5063#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
5064#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
5065#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
5066#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
5067#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
5068#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
5069#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
5070#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
5071#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
5072#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
5073#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
5074#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
5075#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
5076#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
5077#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
5078#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
5079#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
5080#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
5081#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
5082#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
5083#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
5084#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
5085#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
5086#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
5087#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
5088#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
5089#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
5090#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
5091#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
5092#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
5093#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
5094#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
5095#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
5096#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
5097#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
5098#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
5099#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
5100#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
5101#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
5102#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
5103#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
5104#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
5105#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
5106#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
5107#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
5108#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
5109#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
5110#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
5111#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
5112#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
5113#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
5114#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
5115#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
5116#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
5117#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
5118#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
5119#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
5120#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
5121#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
5122#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
5123#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
5124#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
5125#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
5126#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
5127#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
5128#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
5129#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
5130#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
5131#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
5132#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
5133#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
5134#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
5135#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
5136#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
5137#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
5138#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
5139#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
5140#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
5141#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
5142#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
5143#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
5144#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
5145#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
5146#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
5147#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
5148#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
5149#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
5150#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
5151#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
5152#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
5153#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
5154#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
5155#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
5156#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
5157#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
5158#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
5159#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
5160#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
5161#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
5162#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
5163#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
5164#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
5165#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
5166#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
5167#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
5168#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
5169#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
5170#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
5171#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
5172#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
5173#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
5174#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
5175#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
5176#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
5177#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
5178#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
5179#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
5180#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
5181#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
5182#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
5183#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
5184#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
5185#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
5186#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
5187#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
5188#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
5189#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
5190#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
5191#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
5192#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
5193#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
5194#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
5195#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
5196#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
5197#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
5198#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
5199#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
5200#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
5201#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
5202#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
5203#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
5204#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
5205#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
5206#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
5207#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
5208#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
5209#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
5210#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
5211#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
5212#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
5213#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
5214#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
5215#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
5216#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
5217#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
5218#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
5219#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
5220#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
5221#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
5222#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
5223#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
5224#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
5225#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
5226#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
5227#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
5228#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
5229#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
5230#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
5231#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
5232#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
5233#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
5234#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
5235#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
5236#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
5237#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
5238#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
5239#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
5240#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
5241#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
5242#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
5243#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
5244#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
5245#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
5246#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
5247#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
5248#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
5249#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000
5250#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
5251#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000
5252#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
5253#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
5254#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
5255#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
5256#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
5257#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
5258#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
5259#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
5260#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
5261#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x10
5262#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4
5263#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x20
5264#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5
5265#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x40
5266#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6
5267#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xffffff80
5268#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x7
5269#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
5270#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
5271#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
5272#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
5273#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
5274#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
5275#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
5276#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
5277#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
5278#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
5279#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
5280#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
5281#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
5282#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
5283#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
5284#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
5285#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
5286#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
5287#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
5288#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
5289#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
5290#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
5291#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
5292#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
5293#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
5294#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
5295#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
5296#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
5297#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
5298#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
5299#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
5300#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
5301#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
5302#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
5303#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
5304#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
5305#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
5306#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
5307#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
5308#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
5309#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
5310#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
5311#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
5312#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
5313#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
5314#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
5315#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
5316#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
5317#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
5318#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
5319#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
5320#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
5321#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
5322#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
5323#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
5324#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
5325#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
5326#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
5327#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
5328#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
5329#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
5330#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
5331#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
5332#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
5333#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
5334#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
5335#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
5336#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
5337#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
5338#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
5339#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
5340#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
5341#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
5342#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
5343#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
5344#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
5345#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
5346#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
5347#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
5348#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
5349#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
5350#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
5351#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
5352#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
5353#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
5354#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
5355#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
5356#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
5357#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
5358#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
5359#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
5360#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
5361#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
5362#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
5363#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
5364#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
5365#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
5366#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
5367#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
5368#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
5369#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
5370#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
5371#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
5372#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
5373#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
5374#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
5375#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
5376#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
5377#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
5378#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
5379#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
5380#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
5381#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
5382#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
5383#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
5384#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
5385#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
5386#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
5387#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
5388#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
5389#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
5390#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
5391#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
5392#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
5393#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
5394#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
5395#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
5396#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
5397#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
5398#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
5399#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
5400#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
5401#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
5402#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
5403#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
5404#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
5405#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
5406#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
5407#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
5408#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
5409#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
5410#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
5411#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
5412#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
5413#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
5414#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
5415#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
5416#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
5417#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
5418#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
5419#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
5420#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
5421#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
5422#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
5423#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
5424#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
5425#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
5426#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
5427#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
5428#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
5429#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
5430#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
5431#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
5432#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
5433#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
5434#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
5435#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
5436#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
5437#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
5438#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
5439#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
5440#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
5441#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
5442#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
5443#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
5444#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
5445#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
5446#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
5447#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
5448#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
5449#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
5450#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
5451#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
5452#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
5453#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
5454#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
5455#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
5456#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
5457#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
5458#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
5459#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
5460#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
5461#define GB_GPU_ID__GPU_ID_MASK 0xf
5462#define GB_GPU_ID__GPU_ID__SHIFT 0x0
5463#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
5464#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
5465#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
5466#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
5467#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
5468#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
5469#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
5470#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
5471#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
5472#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
5473#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
5474#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
5475#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
5476#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
5477#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
5478#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
5479#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
5480#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
5481#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
5482#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
5483#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
5484#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
5485#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5486#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
5487#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
5488#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
5489#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
5490#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
5491#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
5492#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
5493#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
5494#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
5495#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5496#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
5497#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
5498#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
5499#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
5500#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
5501#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
5502#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
5503#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
5504#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
5505#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5506#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
5507#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
5508#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
5509#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
5510#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
5511#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
5512#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
5513#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
5514#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
5515#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5516#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
5517#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
5518#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
5519#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
5520#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
5521#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
5522#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
5523#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
5524#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
5525#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5526#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
5527#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
5528#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
5529#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
5530#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
5531#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
5532#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
5533#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
5534#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
5535#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5536#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
5537#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
5538#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
5539#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
5540#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
5541#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
5542#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
5543#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
5544#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
5545#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5546#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
5547#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
5548#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
5549#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
5550#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
5551#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
5552#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
5553#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
5554#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
5555#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5556#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
5557#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
5558#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
5559#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
5560#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
5561#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
5562#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
5563#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
5564#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
5565#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5566#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
5567#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
5568#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
5569#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
5570#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
5571#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
5572#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
5573#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
5574#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
5575#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5576#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
5577#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
5578#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
5579#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
5580#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
5581#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
5582#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
5583#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
5584#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
5585#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5586#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
5587#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
5588#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
5589#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
5590#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
5591#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
5592#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
5593#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
5594#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
5595#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5596#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
5597#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
5598#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
5599#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
5600#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
5601#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
5602#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
5603#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
5604#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
5605#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5606#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
5607#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
5608#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
5609#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
5610#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
5611#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
5612#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
5613#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
5614#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
5615#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5616#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
5617#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
5618#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
5619#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
5620#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
5621#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
5622#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
5623#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
5624#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
5625#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5626#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
5627#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
5628#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
5629#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
5630#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
5631#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
5632#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
5633#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
5634#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
5635#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5636#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
5637#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
5638#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
5639#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
5640#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
5641#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
5642#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
5643#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
5644#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
5645#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5646#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
5647#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
5648#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
5649#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
5650#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
5651#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
5652#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
5653#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
5654#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
5655#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5656#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
5657#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
5658#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
5659#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
5660#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
5661#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
5662#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
5663#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
5664#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
5665#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5666#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
5667#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
5668#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
5669#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
5670#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
5671#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
5672#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
5673#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
5674#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
5675#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5676#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
5677#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
5678#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
5679#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
5680#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
5681#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
5682#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
5683#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
5684#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
5685#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5686#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
5687#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
5688#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
5689#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
5690#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
5691#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
5692#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
5693#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
5694#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
5695#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5696#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
5697#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
5698#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
5699#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
5700#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
5701#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
5702#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
5703#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
5704#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
5705#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5706#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
5707#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
5708#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
5709#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
5710#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
5711#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
5712#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
5713#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
5714#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
5715#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5716#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
5717#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
5718#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
5719#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
5720#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
5721#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
5722#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
5723#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
5724#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
5725#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5726#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
5727#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
5728#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
5729#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
5730#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
5731#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
5732#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
5733#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
5734#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
5735#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5736#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
5737#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
5738#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
5739#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
5740#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
5741#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
5742#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
5743#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
5744#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
5745#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5746#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
5747#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
5748#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
5749#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
5750#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
5751#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
5752#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
5753#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
5754#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
5755#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5756#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
5757#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
5758#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
5759#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
5760#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
5761#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
5762#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
5763#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
5764#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
5765#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5766#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
5767#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
5768#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
5769#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
5770#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
5771#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
5772#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
5773#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
5774#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
5775#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5776#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
5777#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
5778#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
5779#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
5780#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
5781#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
5782#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
5783#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
5784#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
5785#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5786#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
5787#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
5788#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
5789#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
5790#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
5791#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
5792#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
5793#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
5794#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
5795#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5796#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
5797#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
5798#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
5799#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
5800#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
5801#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
5802#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
5803#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
5804#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
5805#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
5806#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
5807#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
5808#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
5809#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
5810#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
5811#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
5812#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
5813#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
5814#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
5815#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
5816#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
5817#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
5818#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
5819#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30
5820#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
5821#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0
5822#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
5823#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3
5824#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
5825#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc
5826#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
5827#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30
5828#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
5829#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0
5830#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
5831#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3
5832#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
5833#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc
5834#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
5835#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30
5836#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
5837#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0
5838#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
5839#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3
5840#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
5841#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc
5842#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
5843#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30
5844#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
5845#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0
5846#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
5847#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3
5848#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
5849#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc
5850#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
5851#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30
5852#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
5853#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0
5854#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
5855#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3
5856#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
5857#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc
5858#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
5859#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30
5860#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
5861#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0
5862#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
5863#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3
5864#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
5865#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc
5866#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
5867#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30
5868#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
5869#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0
5870#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
5871#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3
5872#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
5873#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc
5874#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
5875#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30
5876#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
5877#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0
5878#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
5879#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3
5880#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
5881#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc
5882#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
5883#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30
5884#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
5885#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0
5886#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
5887#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3
5888#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
5889#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc
5890#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
5891#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30
5892#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
5893#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0
5894#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
5895#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3
5896#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
5897#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc
5898#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
5899#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30
5900#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
5901#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0
5902#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
5903#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3
5904#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
5905#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc
5906#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
5907#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30
5908#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
5909#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0
5910#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
5911#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3
5912#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
5913#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc
5914#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
5915#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30
5916#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
5917#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0
5918#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
5919#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3
5920#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
5921#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc
5922#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
5923#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30
5924#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
5925#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0
5926#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
5927#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000
5928#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10
5929#define GB_EDC_MODE__DED_MODE_MASK 0x300000
5930#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
5931#define GB_EDC_MODE__PROP_FED_MASK 0x20000000
5932#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
5933#define GB_EDC_MODE__BYPASS_MASK 0x80000000
5934#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
5935#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2
5936#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
5937#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1
5938#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
5939#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff
5940#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
5941#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5942#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
5943#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5944#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
5945#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff
5946#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
5947#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff
5948#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
5949#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5950#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
5951#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5952#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
5953#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5954#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
5955#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5956#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
5957#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5958#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
5959#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff
5960#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
5961#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff
5962#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
5963#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff
5964#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
5965#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff
5966#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
5967#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff
5968#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
5969#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff
5970#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
5971#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5972#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
5973#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5974#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
5975#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5976#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
5977#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5978#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
5979#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5980#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
5981#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5982#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
5983#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5984#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
5985#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5986#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
5987#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5988#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
5989#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5990#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
5991#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7
5992#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
5993#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
5994#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
5995#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff
5996#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
5997#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
5998#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
5999#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
6000#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
6001#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
6002#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
6003#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff
6004#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
6005#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000
6006#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
6007#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f
6008#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
6009#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0
6010#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
6011#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3
6012#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
6013#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc
6014#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
6015#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30
6016#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
6017#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0
6018#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
6019#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000
6020#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
6021#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000
6022#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
6023#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf
6024#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
6025#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20
6026#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5
6027#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80
6028#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
6029#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100
6030#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
6031#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200
6032#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
6033#define GRBM_STATUS__DB_CLEAN_MASK 0x1000
6034#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
6035#define GRBM_STATUS__CB_CLEAN_MASK 0x2000
6036#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
6037#define GRBM_STATUS__TA_BUSY_MASK 0x4000
6038#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
6039#define GRBM_STATUS__GDS_BUSY_MASK 0x8000
6040#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
6041#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000
6042#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
6043#define GRBM_STATUS__VGT_BUSY_MASK 0x20000
6044#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
6045#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000
6046#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
6047#define GRBM_STATUS__IA_BUSY_MASK 0x80000
6048#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
6049#define GRBM_STATUS__SX_BUSY_MASK 0x100000
6050#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
6051#define GRBM_STATUS__WD_BUSY_MASK 0x200000
6052#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
6053#define GRBM_STATUS__SPI_BUSY_MASK 0x400000
6054#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
6055#define GRBM_STATUS__BCI_BUSY_MASK 0x800000
6056#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
6057#define GRBM_STATUS__SC_BUSY_MASK 0x1000000
6058#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
6059#define GRBM_STATUS__PA_BUSY_MASK 0x2000000
6060#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
6061#define GRBM_STATUS__DB_BUSY_MASK 0x4000000
6062#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
6063#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000
6064#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
6065#define GRBM_STATUS__CP_BUSY_MASK 0x20000000
6066#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
6067#define GRBM_STATUS__CB_BUSY_MASK 0x40000000
6068#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
6069#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
6070#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
6071#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf
6072#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
6073#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10
6074#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
6075#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20
6076#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
6077#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40
6078#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
6079#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80
6080#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
6081#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100
6082#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
6083#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200
6084#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
6085#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400
6086#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
6087#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800
6088#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
6089#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000
6090#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
6091#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000
6092#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
6093#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000
6094#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
6095#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000
6096#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
6097#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000
6098#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
6099#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000
6100#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
6101#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000
6102#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
6103#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000
6104#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
6105#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000
6106#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
6107#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2
6108#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
6109#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4
6110#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
6111#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000
6112#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
6113#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000
6114#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
6115#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000
6116#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
6117#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000
6118#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
6119#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000
6120#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
6121#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000
6122#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
6123#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000
6124#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
6125#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000
6126#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
6127#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000
6128#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
6129#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2
6130#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
6131#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4
6132#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
6133#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000
6134#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
6135#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000
6136#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
6137#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000
6138#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
6139#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000
6140#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
6141#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000
6142#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
6143#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000
6144#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
6145#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000
6146#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
6147#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000
6148#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
6149#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000
6150#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
6151#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2
6152#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
6153#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4
6154#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
6155#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000
6156#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
6157#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000
6158#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
6159#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000
6160#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
6161#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000
6162#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
6163#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000
6164#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
6165#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000
6166#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
6167#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000
6168#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
6169#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000
6170#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
6171#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000
6172#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
6173#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2
6174#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
6175#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4
6176#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
6177#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000
6178#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
6179#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000
6180#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
6181#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000
6182#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
6183#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000
6184#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
6185#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000
6186#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
6187#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000
6188#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
6189#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000
6190#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
6191#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000
6192#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
6193#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000
6194#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
6195#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1
6196#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
6197#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4
6198#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
6199#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000
6200#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
6201#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000
6202#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
6203#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000
6204#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
6205#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000
6206#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
6207#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000
6208#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
6209#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f
6210#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0
6211#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff
6212#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0
6213#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0xf
6214#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0
6215#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0xff0
6216#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4
6217#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000
6218#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
6219#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff
6220#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
6221#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00
6222#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
6223#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000
6224#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
6225#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000
6226#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
6227#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
6228#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
6229#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000
6230#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
6231#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
6232#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
6233#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
6234#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
6235#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff
6236#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
6237#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2
6238#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1
6239#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20
6240#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5
6241#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40
6242#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6
6243#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80
6244#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7
6245#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00
6246#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8
6247#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000
6248#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc
6249#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000
6250#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd
6251#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000
6252#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f
6253#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1
6254#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0
6255#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2
6256#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1
6257#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4
6258#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2
6259#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8
6260#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3
6261#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10
6262#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4
6263#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20
6264#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5
6265#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40
6266#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6
6267#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80
6268#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7
6269#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100
6270#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8
6271#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200
6272#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9
6273#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400
6274#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa
6275#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800
6276#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb
6277#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000
6278#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc
6279#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000
6280#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd
6281#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000
6282#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe
6283#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000
6284#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf
6285#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000
6286#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10
6287#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000
6288#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11
6289#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000
6290#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12
6291#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000
6292#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13
6293#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000
6294#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
6295#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000
6296#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15
6297#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
6298#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
6299#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000
6300#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
6301#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000
6302#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
6303#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
6304#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
6305#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000
6306#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11
6307#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000
6308#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
6309#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000
6310#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
6311#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000
6312#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
6313#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000
6314#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
6315#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000
6316#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
6317#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000
6318#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
6319#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000
6320#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
6321#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000
6322#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
6323#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000
6324#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
6325#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000
6326#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
6327#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000
6328#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
6329#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000
6330#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
6331#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000
6332#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
6333#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000
6334#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
6335#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1
6336#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
6337#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000
6338#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
6339#define GRBM_TRAP_OP__RW_MASK 0x1
6340#define GRBM_TRAP_OP__RW__SHIFT 0x0
6341#define GRBM_TRAP_ADDR__DATA_MASK 0xffff
6342#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
6343#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff
6344#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
6345#define GRBM_TRAP_WD__DATA_MASK 0xffffffff
6346#define GRBM_TRAP_WD__DATA__SHIFT 0x0
6347#define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff
6348#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
6349#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3
6350#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
6351#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4
6352#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
6353#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1
6354#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
6355#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2
6356#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1
6357#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c
6358#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
6359#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0
6360#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
6361#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000
6362#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
6363#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000
6364#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
6365#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000
6366#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
6367#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000
6368#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
6369#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000
6370#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
6371#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
6372#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
6373#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
6374#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
6375#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
6376#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
6377#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
6378#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
6379#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
6380#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
6381#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
6382#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
6383#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
6384#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
6385#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
6386#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
6387#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
6388#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
6389#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
6390#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
6391#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
6392#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
6393#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
6394#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
6395#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
6396#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
6397#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
6398#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
6399#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
6400#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
6401#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
6402#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
6403#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
6404#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
6405#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
6406#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
6407#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
6408#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
6409#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
6410#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
6411#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
6412#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
6413#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
6414#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
6415#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
6416#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
6417#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
6418#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
6419#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
6420#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
6421#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
6422#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
6423#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
6424#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
6425#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
6426#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
6427#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
6428#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
6429#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
6430#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
6431#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
6432#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
6433#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
6434#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
6435#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
6436#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
6437#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
6438#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
6439#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
6440#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
6441#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
6442#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
6443#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
6444#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
6445#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
6446#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
6447#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
6448#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
6449#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
6450#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
6451#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
6452#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
6453#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
6454#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
6455#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
6456#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
6457#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
6458#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
6459#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
6460#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
6461#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
6462#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
6463#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
6464#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
6465#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
6466#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
6467#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
6468#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
6469#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
6470#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
6471#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
6472#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
6473#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
6474#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
6475#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
6476#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
6477#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
6478#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
6479#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
6480#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
6481#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
6482#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
6483#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
6484#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
6485#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
6486#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
6487#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
6488#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
6489#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
6490#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
6491#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
6492#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
6493#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
6494#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
6495#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
6496#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
6497#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
6498#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
6499#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
6500#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
6501#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
6502#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
6503#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
6504#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
6505#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
6506#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
6507#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
6508#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
6509#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
6510#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
6511#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
6512#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
6513#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
6514#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
6515#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
6516#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
6517#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
6518#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
6519#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
6520#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
6521#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
6522#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
6523#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
6524#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
6525#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
6526#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
6527#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
6528#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
6529#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
6530#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
6531#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
6532#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
6533#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
6534#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
6535#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
6536#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
6537#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
6538#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
6539#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
6540#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
6541#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
6542#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
6543#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
6544#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
6545#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
6546#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
6547#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
6548#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
6549#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
6550#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
6551#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
6552#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
6553#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
6554#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
6555#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
6556#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
6557#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
6558#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
6559#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
6560#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
6561#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
6562#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
6563#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
6564#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
6565#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
6566#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
6567#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
6568#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
6569#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
6570#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
6571#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
6572#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
6573#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
6574#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
6575#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
6576#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
6577#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
6578#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
6579#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
6580#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
6581#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
6582#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
6583#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff
6584#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0
6585#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff
6586#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0
6587#define GRBM_NOWHERE__DATA_MASK 0xffffffff
6588#define GRBM_NOWHERE__DATA__SHIFT 0x0
6589#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff
6590#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
6591#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff
6592#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
6593#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff
6594#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
6595#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff
6596#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
6597#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff
6598#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
6599#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff
6600#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
6601#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff
6602#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
6603#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff
6604#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
6605#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff
6606#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
6607#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff
6608#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
6609#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff
6610#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
6611#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff
6612#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
6613#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff
6614#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
6615#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff
6616#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
6617#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff
6618#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
6619#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff
6620#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
6621#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff
6622#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
6623#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff
6624#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
6625#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff
6626#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
6627#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff
6628#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
6629#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff
6630#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
6631#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff
6632#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
6633#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff
6634#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
6635#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff
6636#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
6637#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff
6638#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
6639#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff
6640#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
6641#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff
6642#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
6643#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff
6644#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
6645#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff
6646#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
6647#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff
6648#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
6649#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff
6650#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
6651#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff
6652#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
6653#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff
6654#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
6655#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff
6656#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
6657#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff
6658#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
6659#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff
6660#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
6661#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff
6662#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
6663#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff
6664#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
6665#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff
6666#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
6667#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff
6668#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
6669#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff
6670#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
6671#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff
6672#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
6673#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff
6674#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
6675#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff
6676#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
6677#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff
6678#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
6679#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff
6680#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
6681#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff
6682#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
6683#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff
6684#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
6685#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff
6686#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
6687#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff
6688#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
6689#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff
6690#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
6691#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff
6692#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
6693#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff
6694#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
6695#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff
6696#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
6697#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff
6698#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
6699#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff
6700#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
6701#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff
6702#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
6703#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff
6704#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
6705#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff
6706#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
6707#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff
6708#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
6709#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff
6710#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
6711#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff
6712#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
6713#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff
6714#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
6715#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff
6716#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
6717#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff
6718#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
6719#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff
6720#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
6721#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff
6722#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
6723#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff
6724#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
6725#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff
6726#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
6727#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff
6728#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
6729#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff
6730#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
6731#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff
6732#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
6733#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff
6734#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
6735#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff
6736#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
6737#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff
6738#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
6739#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff
6740#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
6741#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff
6742#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
6743#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff
6744#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
6745#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff
6746#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
6747#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff
6748#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
6749#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff
6750#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
6751#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff
6752#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
6753#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff
6754#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
6755#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff
6756#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
6757#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff
6758#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
6759#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff
6760#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
6761#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff
6762#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
6763#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff
6764#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
6765#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff
6766#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
6767#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff
6768#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
6769#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff
6770#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
6771#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff
6772#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
6773#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff
6774#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
6775#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff
6776#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
6777#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff
6778#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
6779#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff
6780#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
6781#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1
6782#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
6783#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2
6784#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
6785#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4
6786#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
6787#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8
6788#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
6789#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10
6790#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
6791#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20
6792#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
6793#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100
6794#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
6795#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200
6796#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
6797#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400
6798#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
6799#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800
6800#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
6801#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1
6802#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
6803#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2
6804#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
6805#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4
6806#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
6807#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8
6808#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
6809#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10
6810#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
6811#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20
6812#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
6813#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40
6814#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
6815#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80
6816#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
6817#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100
6818#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
6819#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200
6820#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
6821#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400
6822#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
6823#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800
6824#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
6825#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000
6826#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
6827#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000
6828#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
6829#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000
6830#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
6831#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000
6832#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
6833#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000
6834#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
6835#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000
6836#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
6837#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000
6838#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
6839#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000
6840#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
6841#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000
6842#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
6843#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000
6844#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
6845#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000
6846#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
6847#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000
6848#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
6849#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000
6850#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
6851#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000
6852#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
6853#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000
6854#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
6855#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1
6856#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
6857#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2
6858#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
6859#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4
6860#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
6861#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8
6862#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
6863#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10
6864#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
6865#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20
6866#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
6867#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40
6868#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
6869#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80
6870#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
6871#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100
6872#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
6873#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200
6874#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
6875#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400
6876#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
6877#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800
6878#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
6879#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000
6880#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
6881#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000
6882#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
6883#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000
6884#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
6885#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000
6886#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
6887#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1
6888#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
6889#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2
6890#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
6891#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4
6892#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
6893#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8
6894#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
6895#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10
6896#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
6897#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20
6898#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
6899#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000
6900#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
6901#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000
6902#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
6903#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000
6904#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
6905#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000
6906#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
6907#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000
6908#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
6909#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000
6910#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
6911#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000
6912#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
6913#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000
6914#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
6915#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000
6916#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
6917#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000
6918#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
6919#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000
6920#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
6921#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000
6922#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
6923#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000
6924#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
6925#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
6926#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
6927#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
6928#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
6929#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
6930#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
6931#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
6932#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
6933#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff
6934#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
6935#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff
6936#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
6937#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff
6938#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
6939#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff
6940#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
6941#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff
6942#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
6943#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff
6944#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
6945#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff
6946#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
6947#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff
6948#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
6949#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff
6950#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
6951#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff
6952#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
6953#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff
6954#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
6955#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff
6956#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
6957#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff
6958#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
6959#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff
6960#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
6961#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff
6962#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
6963#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff
6964#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
6965#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff
6966#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
6967#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff
6968#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
6969#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff
6970#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
6971#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff
6972#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
6973#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff
6974#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
6975#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff
6976#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
6977#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff
6978#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
6979#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff
6980#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
6981#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff
6982#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
6983#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff
6984#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
6985#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff
6986#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
6987#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff
6988#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
6989#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1
6990#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
6991#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6
6992#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
6993#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8
6994#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
6995#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10
6996#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
6997#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20
6998#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
6999#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000
7000#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
7001#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000
7002#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
7003#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000
7004#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
7005#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000
7006#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
7007#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1
7008#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
7009#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1
7010#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
7011#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6
7012#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
7013#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38
7014#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
7015#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff
7016#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
7017#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000
7018#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
7019#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff
7020#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
7021#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000
7022#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
7023#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff
7024#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
7025#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3
7026#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
7027#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4
7028#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
7029#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8
7030#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
7031#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10
7032#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
7033#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff
7034#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
7035#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1
7036#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
7037#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2
7038#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
7039#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4
7040#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
7041#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8
7042#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
7043#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10
7044#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
7045#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20
7046#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
7047#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40
7048#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
7049#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80
7050#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
7051#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00
7052#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
7053#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000
7054#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
7055#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000
7056#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
7057#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1
7058#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
7059#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2
7060#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
7061#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4
7062#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
7063#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18
7064#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
7065#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0
7066#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
7067#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700
7068#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
7069#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800
7070#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
7071#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000
7072#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
7073#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000
7074#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
7075#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000
7076#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
7077#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000
7078#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
7079#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000
7080#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
7081#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000
7082#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
7083#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff
7084#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
7085#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100
7086#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
7087#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff
7088#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
7089#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff
7090#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
7091#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff
7092#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
7093#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff
7094#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
7095#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff
7096#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
7097#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff
7098#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
7099#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000
7100#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
7101#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff
7102#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
7103#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
7104#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
7105#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
7106#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
7107#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
7108#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
7109#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
7110#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
7111#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
7112#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
7113#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
7114#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
7115#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
7116#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
7117#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
7118#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
7119#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
7120#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
7121#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
7122#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
7123#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
7124#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
7125#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
7126#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
7127#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
7128#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
7129#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
7130#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
7131#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
7132#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
7133#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff
7134#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
7135#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
7136#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
7137#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff
7138#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
7139#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
7140#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
7141#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff
7142#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
7143#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
7144#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
7145#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff
7146#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
7147#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7
7148#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
7149#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10
7150#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
7151#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000
7152#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
7153#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000
7154#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
7155#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000
7156#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
7157#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff
7158#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
7159#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000
7160#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
7161#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff
7162#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
7163#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000
7164#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
7165#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x3
7166#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0
7167#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf
7168#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
7169#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0
7170#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
7171#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00
7172#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
7173#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000
7174#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
7175#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000
7176#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
7177#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000
7178#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
7179#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000
7180#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
7181#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000
7182#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
7183#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf
7184#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
7185#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0
7186#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
7187#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00
7188#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
7189#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000
7190#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
7191#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000
7192#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
7193#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000
7194#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
7195#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000
7196#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
7197#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000
7198#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
7199#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf
7200#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
7201#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0
7202#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
7203#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00
7204#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
7205#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000
7206#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
7207#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000
7208#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
7209#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000
7210#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
7211#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000
7212#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
7213#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000
7214#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
7215#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf
7216#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
7217#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0
7218#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
7219#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00
7220#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
7221#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000
7222#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
7223#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000
7224#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
7225#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000
7226#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
7227#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000
7228#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
7229#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000
7230#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
7231#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf
7232#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
7233#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0
7234#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
7235#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00
7236#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
7237#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000
7238#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
7239#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000
7240#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
7241#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000
7242#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
7243#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000
7244#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
7245#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000
7246#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
7247#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf
7248#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
7249#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0
7250#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
7251#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00
7252#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
7253#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000
7254#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
7255#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000
7256#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
7257#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000
7258#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
7259#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000
7260#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
7261#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000
7262#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
7263#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf
7264#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
7265#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0
7266#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
7267#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00
7268#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
7269#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000
7270#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
7271#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000
7272#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
7273#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000
7274#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
7275#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000
7276#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
7277#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000
7278#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
7279#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf
7280#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
7281#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0
7282#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
7283#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00
7284#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
7285#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000
7286#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
7287#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000
7288#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
7289#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000
7290#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
7291#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000
7292#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
7293#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000
7294#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
7295#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf
7296#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
7297#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0
7298#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
7299#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00
7300#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
7301#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000
7302#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
7303#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000
7304#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
7305#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000
7306#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
7307#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000
7308#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
7309#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000
7310#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
7311#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf
7312#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
7313#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0
7314#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
7315#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00
7316#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
7317#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000
7318#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
7319#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000
7320#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
7321#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000
7322#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
7323#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000
7324#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
7325#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000
7326#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
7327#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf
7328#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
7329#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0
7330#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
7331#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00
7332#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
7333#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000
7334#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
7335#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000
7336#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
7337#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000
7338#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
7339#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000
7340#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
7341#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000
7342#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
7343#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf
7344#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
7345#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0
7346#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
7347#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00
7348#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
7349#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000
7350#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
7351#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000
7352#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
7353#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000
7354#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
7355#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000
7356#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
7357#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000
7358#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
7359#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf
7360#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
7361#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0
7362#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
7363#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00
7364#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
7365#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000
7366#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
7367#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000
7368#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
7369#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000
7370#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
7371#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000
7372#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
7373#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000
7374#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
7375#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf
7376#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
7377#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0
7378#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
7379#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00
7380#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
7381#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000
7382#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
7383#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000
7384#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
7385#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000
7386#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
7387#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000
7388#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
7389#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000
7390#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
7391#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf
7392#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
7393#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0
7394#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
7395#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00
7396#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
7397#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000
7398#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
7399#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000
7400#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
7401#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000
7402#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
7403#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000
7404#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
7405#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000
7406#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
7407#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf
7408#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
7409#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0
7410#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
7411#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00
7412#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
7413#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000
7414#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
7415#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000
7416#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
7417#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000
7418#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
7419#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000
7420#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
7421#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000
7422#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
7423#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf
7424#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
7425#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0
7426#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
7427#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00
7428#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
7429#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000
7430#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
7431#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000
7432#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
7433#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000
7434#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
7435#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000
7436#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
7437#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000
7438#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
7439#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf
7440#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
7441#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0
7442#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
7443#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00
7444#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
7445#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000
7446#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
7447#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000
7448#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
7449#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000
7450#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
7451#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000
7452#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
7453#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000
7454#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
7455#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff
7456#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
7457#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000
7458#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
7459#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff
7460#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
7461#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000
7462#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
7463#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff
7464#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
7465#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000
7466#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
7467#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff
7468#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
7469#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000
7470#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
7471#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff
7472#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
7473#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000
7474#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
7475#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff
7476#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
7477#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000
7478#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
7479#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff
7480#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
7481#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000
7482#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
7483#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff
7484#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
7485#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000
7486#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
7487#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff
7488#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
7489#define PA_SC_EDGERULE__ER_TRI_MASK 0xf
7490#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
7491#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0
7492#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
7493#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00
7494#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
7495#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000
7496#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
7497#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000
7498#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
7499#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000
7500#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
7501#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000
7502#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
7503#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200
7504#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
7505#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400
7506#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
7507#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800
7508#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
7509#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000
7510#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
7511#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff
7512#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
7513#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000
7514#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
7515#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000
7516#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
7517#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000
7518#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
7519#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1
7520#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
7521#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2
7522#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
7523#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4
7524#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
7525#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8
7526#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
7527#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1
7528#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
7529#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2
7530#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
7531#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4
7532#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
7533#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8
7534#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
7535#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70
7536#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
7537#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80
7538#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
7539#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100
7540#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
7541#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200
7542#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
7543#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400
7544#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
7545#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800
7546#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
7547#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000
7548#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
7549#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000
7550#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
7551#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000
7552#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
7553#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000
7554#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
7555#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000
7556#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
7557#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000
7558#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
7559#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000
7560#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
7561#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000
7562#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
7563#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000
7564#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
7565#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000
7566#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
7567#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000
7568#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
7569#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000
7570#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
7571#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000
7572#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
7573#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000
7574#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
7575#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3
7576#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
7577#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc
7578#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
7579#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30
7580#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
7581#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40
7582#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
7583#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80
7584#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
7585#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300
7586#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
7587#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00
7588#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
7589#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000
7590#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
7591#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000
7592#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
7593#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000
7594#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
7595#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000
7596#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
7597#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000
7598#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
7599#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000
7600#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
7601#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000
7602#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
7603#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000
7604#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
7605#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3
7606#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
7607#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc
7608#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
7609#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30
7610#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
7611#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3
7612#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
7613#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc
7614#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
7615#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff
7616#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
7617#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000
7618#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
7619#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7620#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7621#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff
7622#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
7623#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000
7624#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
7625#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff
7626#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
7627#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000
7628#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
7629#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff
7630#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
7631#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000
7632#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
7633#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff
7634#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
7635#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000
7636#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
7637#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff
7638#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
7639#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000
7640#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
7641#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7642#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7643#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff
7644#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
7645#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000
7646#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
7647#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff
7648#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
7649#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000
7650#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
7651#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7652#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7653#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff
7654#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
7655#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000
7656#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
7657#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7658#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7659#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff
7660#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
7661#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000
7662#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
7663#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7664#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7665#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff
7666#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
7667#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000
7668#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
7669#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7670#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7671#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff
7672#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
7673#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000
7674#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
7675#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7676#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7677#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff
7678#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
7679#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000
7680#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
7681#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7682#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7683#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff
7684#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
7685#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000
7686#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
7687#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7688#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7689#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff
7690#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
7691#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000
7692#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
7693#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7694#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7695#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff
7696#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
7697#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000
7698#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
7699#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7700#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7701#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff
7702#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
7703#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000
7704#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
7705#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7706#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7707#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff
7708#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
7709#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000
7710#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
7711#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7712#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7713#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff
7714#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
7715#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000
7716#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
7717#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7718#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7719#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff
7720#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
7721#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000
7722#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
7723#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7724#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7725#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff
7726#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
7727#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000
7728#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
7729#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7730#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7731#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff
7732#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
7733#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000
7734#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
7735#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7736#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7737#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff
7738#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
7739#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000
7740#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
7741#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7742#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7743#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff
7744#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
7745#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000
7746#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
7747#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff
7748#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
7749#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000
7750#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
7751#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff
7752#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
7753#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000
7754#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
7755#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff
7756#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
7757#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000
7758#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
7759#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff
7760#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
7761#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000
7762#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
7763#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff
7764#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
7765#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000
7766#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
7767#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff
7768#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
7769#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000
7770#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
7771#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff
7772#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
7773#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000
7774#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
7775#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff
7776#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
7777#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000
7778#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
7779#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff
7780#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
7781#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000
7782#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
7783#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff
7784#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
7785#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000
7786#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
7787#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff
7788#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
7789#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000
7790#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
7791#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff
7792#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
7793#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000
7794#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
7795#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff
7796#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
7797#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000
7798#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
7799#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff
7800#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
7801#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000
7802#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
7803#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff
7804#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
7805#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000
7806#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
7807#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff
7808#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
7809#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff
7810#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
7811#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff
7812#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
7813#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff
7814#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
7815#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff
7816#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
7817#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff
7818#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
7819#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff
7820#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
7821#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff
7822#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
7823#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff
7824#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
7825#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff
7826#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
7827#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff
7828#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
7829#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff
7830#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
7831#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff
7832#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
7833#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff
7834#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
7835#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff
7836#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
7837#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff
7838#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
7839#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff
7840#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
7841#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff
7842#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
7843#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff
7844#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
7845#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff
7846#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
7847#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff
7848#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
7849#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff
7850#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
7851#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff
7852#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
7853#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff
7854#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
7855#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff
7856#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
7857#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff
7858#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
7859#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff
7860#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
7861#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff
7862#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
7863#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff
7864#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
7865#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff
7866#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
7867#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff
7868#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
7869#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff
7870#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
7871#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1
7872#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
7873#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2
7874#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
7875#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4
7876#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
7877#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8
7878#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
7879#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10
7880#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
7881#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20
7882#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
7883#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0
7884#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6
7885#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100
7886#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8
7887#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200
7888#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9
7889#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
7890#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
7891#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800
7892#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb
7893#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000
7894#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc
7895#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000
7896#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd
7897#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000
7898#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe
7899#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000
7900#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf
7901#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000
7902#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10
7903#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000
7904#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11
7905#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000
7906#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12
7907#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000
7908#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13
7909#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000
7910#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
7911#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000
7912#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15
7913#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000
7914#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16
7915#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000
7916#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17
7917#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000
7918#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18
7919#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000
7920#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19
7921#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000
7922#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a
7923#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000
7924#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b
7925#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000
7926#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c
7927#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000
7928#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d
7929#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000
7930#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e
7931#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000
7932#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f
7933#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x1
7934#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
7935#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x6
7936#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
7937#define PA_SC_ENHANCE_1__ENABLE_SC_BINNING_MASK 0x8
7938#define PA_SC_ENHANCE_1__ENABLE_SC_BINNING__SHIFT 0x3
7939#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x10
7940#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x4
7941#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x20
7942#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x5
7943#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x40
7944#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x6
7945#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x80
7946#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x7
7947#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x1
7948#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
7949#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x2
7950#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
7951#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f
7952#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
7953#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0
7954#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
7955#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000
7956#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
7957#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000
7958#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17
7959#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f
7960#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
7961#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0
7962#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
7963#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000
7964#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
7965#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000
7966#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
7967#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff
7968#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
7969#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000
7970#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
7971#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf
7972#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
7973#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00
7974#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
7975#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff
7976#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
7977#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000
7978#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
7979#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff
7980#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
7981#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000
7982#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
7983#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff
7984#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
7985#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000
7986#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
7987#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff
7988#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
7989#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000
7990#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
7991#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
7992#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
7993#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
7994#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
7995#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
7996#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
7997#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
7998#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
7999#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
8000#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
8001#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
8002#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
8003#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
8004#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
8005#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
8006#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
8007#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff
8008#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
8009#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff
8010#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
8011#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff
8012#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
8013#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff
8014#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
8015#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
8016#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
8017#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
8018#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
8019#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
8020#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
8021#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
8022#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
8023#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
8024#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
8025#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
8026#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
8027#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
8028#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
8029#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
8030#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
8031#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
8032#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
8033#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
8034#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
8035#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
8036#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
8037#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
8038#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
8039#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
8040#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
8041#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
8042#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
8043#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
8044#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
8045#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
8046#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
8047#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
8048#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
8049#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
8050#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
8051#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
8052#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
8053#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
8054#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
8055#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
8056#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
8057#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
8058#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
8059#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
8060#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
8061#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
8062#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
8063#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
8064#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
8065#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
8066#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
8067#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
8068#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
8069#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
8070#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
8071#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
8072#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
8073#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
8074#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
8075#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
8076#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
8077#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
8078#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
8079#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
8080#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
8081#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
8082#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
8083#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
8084#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
8085#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
8086#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
8087#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
8088#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
8089#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000
8090#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
8091#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000
8092#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
8093#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff
8094#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
8095#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf
8096#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
8097#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
8098#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
8099#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
8100#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
8101#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
8102#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
8103#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
8104#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
8105#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
8106#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
8107#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
8108#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
8109#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000
8110#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
8111#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000
8112#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
8113#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000
8114#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
8115#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf
8116#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0
8117#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
8118#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
8119#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
8120#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
8121#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
8122#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
8123#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
8124#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
8125#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
8126#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
8127#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
8128#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
8129#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
8130#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
8131#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
8132#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
8133#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
8134#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
8135#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f
8136#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0
8137#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff
8138#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0
8139#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f
8140#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0
8141#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff
8142#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0
8143#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff
8144#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0
8145#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100
8146#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8
8147#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600
8148#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9
8149#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800
8150#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb
8151#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000
8152#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc
8153#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000
8154#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd
8155#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000
8156#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe
8157#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000
8158#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf
8159#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000
8160#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10
8161#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000
8162#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11
8163#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000
8164#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12
8165#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000
8166#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13
8167#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000
8168#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
8169#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000
8170#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15
8171#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000
8172#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16
8173#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000
8174#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17
8175#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000
8176#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18
8177#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000
8178#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19
8179#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000
8180#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a
8181#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000
8182#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b
8183#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000
8184#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c
8185#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000
8186#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d
8187#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000
8188#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e
8189#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000
8190#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f
8191#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff
8192#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0
8193#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700
8194#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8
8195#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800
8196#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb
8197#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000
8198#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe
8199#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000
8200#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11
8201#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000
8202#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
8203#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000
8204#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15
8205#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000
8206#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16
8207#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000
8208#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17
8209#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000
8210#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18
8211#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000
8212#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19
8213#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000
8214#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a
8215#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000
8216#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c
8217#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000
8218#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d
8219#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000
8220#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e
8221#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000
8222#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f
8223#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7
8224#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0
8225#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38
8226#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3
8227#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0
8228#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6
8229#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00
8230#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8
8231#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000
8232#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc
8233#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000
8234#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10
8235#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000
8236#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
8237#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000
8238#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15
8239#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000
8240#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16
8241#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000
8242#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17
8243#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000
8244#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18
8245#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000
8246#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19
8247#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000
8248#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a
8249#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000
8250#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b
8251#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000
8252#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c
8253#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000
8254#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d
8255#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000
8256#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e
8257#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000
8258#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f
8259#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff
8260#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0
8261#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000
8262#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe
8263#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000
8264#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
8265#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000
8266#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17
8267#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000
8268#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18
8269#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
8270#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
8271#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000
8272#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c
8273#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000
8274#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d
8275#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
8276#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
8277#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
8278#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
8279#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
8280#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
8281#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
8282#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
8283#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
8284#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
8285#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
8286#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
8287#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000
8288#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d
8289#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
8290#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
8291#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
8292#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
8293#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff
8294#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0
8295#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000
8296#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe
8297#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000
8298#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
8299#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000
8300#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17
8301#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000
8302#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18
8303#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
8304#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
8305#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000
8306#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c
8307#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000
8308#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d
8309#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
8310#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
8311#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
8312#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
8313#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
8314#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
8315#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
8316#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
8317#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
8318#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
8319#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
8320#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
8321#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000
8322#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d
8323#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
8324#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
8325#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
8326#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
8327#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff
8328#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0
8329#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000
8330#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe
8331#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000
8332#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
8333#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000
8334#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17
8335#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000
8336#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18
8337#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
8338#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
8339#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000
8340#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c
8341#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000
8342#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d
8343#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
8344#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
8345#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
8346#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
8347#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
8348#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
8349#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
8350#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
8351#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
8352#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
8353#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
8354#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
8355#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000
8356#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d
8357#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
8358#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
8359#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
8360#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
8361#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff
8362#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0
8363#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000
8364#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe
8365#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000
8366#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
8367#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000
8368#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17
8369#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000
8370#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18
8371#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
8372#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
8373#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000
8374#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c
8375#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000
8376#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d
8377#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
8378#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
8379#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
8380#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
8381#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
8382#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
8383#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
8384#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
8385#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
8386#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
8387#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
8388#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
8389#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000
8390#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d
8391#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
8392#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
8393#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
8394#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
8395#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1
8396#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0
8397#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2
8398#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1
8399#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4
8400#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2
8401#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8
8402#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3
8403#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10
8404#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4
8405#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20
8406#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5
8407#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40
8408#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6
8409#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80
8410#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7
8411#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00
8412#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8
8413#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000
8414#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc
8415#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000
8416#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10
8417#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000
8418#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
8419#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000
8420#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18
8421#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000
8422#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19
8423#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000
8424#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a
8425#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000
8426#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b
8427#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000
8428#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c
8429#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000
8430#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d
8431#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000
8432#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e
8433#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000
8434#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f
8435#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff
8436#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0
8437#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00
8438#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8
8439#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000
8440#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd
8441#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000
8442#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12
8443#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000
8444#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
8445#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000
8446#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16
8447#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000
8448#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18
8449#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000
8450#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19
8451#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000
8452#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a
8453#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000
8454#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b
8455#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000
8456#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c
8457#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000
8458#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d
8459#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000
8460#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e
8461#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
8462#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
8463#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7
8464#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0
8465#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8
8466#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3
8467#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10
8468#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4
8469#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20
8470#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5
8471#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40
8472#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6
8473#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80
8474#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7
8475#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00
8476#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8
8477#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000
8478#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc
8479#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000
8480#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe
8481#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000
8482#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf
8483#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000
8484#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10
8485#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000
8486#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11
8487#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000
8488#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15
8489#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000
8490#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17
8491#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000
8492#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18
8493#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000
8494#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d
8495#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000
8496#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e
8497#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000
8498#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f
8499#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f
8500#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0
8501#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0
8502#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6
8503#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000
8504#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc
8505#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000
8506#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12
8507#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000
8508#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13
8509#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000
8510#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
8511#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000
8512#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15
8513#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000
8514#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18
8515#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000
8516#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e
8517#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000
8518#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f
8519#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff
8520#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0
8521#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000
8522#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10
8523#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000
8524#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15
8525#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000
8526#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a
8527#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000
8528#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f
8529#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f
8530#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0
8531#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80
8532#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7
8533#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00
8534#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8
8535#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000
8536#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd
8537#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000
8538#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12
8539#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000
8540#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13
8541#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000
8542#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
8543#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
8544#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
8545#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000
8546#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c
8547#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000
8548#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d
8549#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000
8550#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e
8551#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000
8552#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f
8553#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f
8554#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0
8555#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80
8556#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7
8557#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00
8558#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8
8559#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000
8560#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd
8561#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000
8562#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12
8563#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000
8564#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13
8565#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000
8566#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
8567#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
8568#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
8569#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000
8570#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c
8571#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000
8572#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d
8573#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000
8574#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e
8575#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000
8576#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f
8577#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f
8578#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0
8579#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80
8580#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7
8581#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00
8582#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8
8583#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000
8584#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd
8585#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000
8586#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12
8587#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000
8588#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13
8589#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000
8590#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
8591#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
8592#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
8593#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000
8594#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c
8595#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000
8596#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d
8597#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000
8598#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e
8599#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000
8600#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f
8601#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f
8602#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0
8603#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80
8604#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7
8605#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00
8606#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8
8607#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000
8608#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd
8609#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000
8610#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12
8611#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000
8612#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13
8613#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000
8614#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
8615#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
8616#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
8617#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000
8618#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c
8619#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000
8620#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d
8621#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000
8622#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e
8623#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000
8624#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f
8625#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f
8626#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0
8627#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0
8628#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6
8629#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00
8630#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9
8631#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000
8632#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc
8633#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000
8634#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10
8635#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000
8636#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a
8637#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000
8638#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c
8639#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000
8640#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e
8641#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000
8642#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f
8643#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f
8644#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0
8645#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380
8646#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7
8647#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00
8648#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa
8649#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000
8650#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf
8651#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000
8652#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10
8653#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000
8654#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
8655#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000
8656#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16
8657#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000
8658#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17
8659#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000
8660#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18
8661#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000
8662#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c
8663#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f
8664#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0
8665#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180
8666#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7
8667#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00
8668#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9
8669#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000
8670#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf
8671#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000
8672#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10
8673#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000
8674#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17
8675#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000
8676#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a
8677#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff
8678#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0
8679#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00
8680#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8
8681#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000
8682#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc
8683#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000
8684#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd
8685#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000
8686#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe
8687#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000
8688#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15
8689#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000
8690#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17
8691#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000
8692#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18
8693#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000
8694#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19
8695#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000
8696#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a
8697#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000
8698#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b
8699#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000
8700#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c
8701#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000
8702#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d
8703#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000
8704#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e
8705#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000
8706#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f
8707#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3
8708#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0
8709#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c
8710#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2
8711#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00
8712#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8
8713#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000
8714#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe
8715#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000
8716#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf
8717#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000
8718#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10
8719#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000
8720#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12
8721#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000
8722#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13
8723#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000
8724#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
8725#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000
8726#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15
8727#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000
8728#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16
8729#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000
8730#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c
8731#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000
8732#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d
8733#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000
8734#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e
8735#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000
8736#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f
8737#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff
8738#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0
8739#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000
8740#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10
8741#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff
8742#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0
8743#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000
8744#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10
8745#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff
8746#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0
8747#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000
8748#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10
8749#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff
8750#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0
8751#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000
8752#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe
8753#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000
8754#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf
8755#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000
8756#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10
8757#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000
8758#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13
8759#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000
8760#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
8761#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000
8762#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17
8763#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000
8764#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18
8765#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000
8766#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a
8767#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000
8768#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d
8769#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000
8770#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f
8771#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff
8772#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0
8773#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000
8774#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe
8775#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000
8776#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c
8777#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000
8778#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e
8779#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000
8780#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f
8781#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3
8782#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0
8783#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc
8784#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2
8785#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3
8786#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0
8787#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc
8788#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2
8789#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1
8790#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
8791#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2
8792#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
8793#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4
8794#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
8795#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8
8796#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
8797#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10
8798#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
8799#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20
8800#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
8801#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40
8802#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
8803#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380
8804#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7
8805#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400
8806#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
8807#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800
8808#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
8809#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000
8810#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc
8811#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000
8812#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
8813#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff
8814#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
8815#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff
8816#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
8817#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff
8818#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
8819#define COMPUTE_START_X__START_MASK 0xffffffff
8820#define COMPUTE_START_X__START__SHIFT 0x0
8821#define COMPUTE_START_Y__START_MASK 0xffffffff
8822#define COMPUTE_START_Y__START__SHIFT 0x0
8823#define COMPUTE_START_Z__START_MASK 0xffffffff
8824#define COMPUTE_START_Z__START__SHIFT 0x0
8825#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff
8826#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
8827#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000
8828#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
8829#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff
8830#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
8831#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000
8832#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
8833#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff
8834#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
8835#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000
8836#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
8837#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1
8838#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
8839#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1
8840#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
8841#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff
8842#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
8843#define COMPUTE_PGM_HI__DATA_MASK 0xff
8844#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
8845#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100
8846#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8
8847#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff
8848#define COMPUTE_TBA_LO__DATA__SHIFT 0x0
8849#define COMPUTE_TBA_HI__DATA_MASK 0xff
8850#define COMPUTE_TBA_HI__DATA__SHIFT 0x0
8851#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff
8852#define COMPUTE_TMA_LO__DATA__SHIFT 0x0
8853#define COMPUTE_TMA_HI__DATA_MASK 0xff
8854#define COMPUTE_TMA_HI__DATA__SHIFT 0x0
8855#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f
8856#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
8857#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0
8858#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
8859#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00
8860#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
8861#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000
8862#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
8863#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000
8864#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
8865#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000
8866#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
8867#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000
8868#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
8869#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000
8870#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
8871#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000
8872#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
8873#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000
8874#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
8875#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1
8876#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
8877#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e
8878#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
8879#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40
8880#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
8881#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80
8882#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
8883#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100
8884#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
8885#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200
8886#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
8887#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400
8888#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
8889#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800
8890#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
8891#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000
8892#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
8893#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000
8894#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
8895#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000
8896#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
8897#define COMPUTE_VMID__DATA_MASK 0xf
8898#define COMPUTE_VMID__DATA__SHIFT 0x0
8899#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff
8900#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
8901#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000
8902#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
8903#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000
8904#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
8905#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000
8906#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
8907#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000
8908#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
8909#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000
8910#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
8911#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff
8912#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
8913#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000
8914#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
8915#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff
8916#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
8917#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000
8918#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
8919#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff
8920#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
8921#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
8922#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
8923#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff
8924#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
8925#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000
8926#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
8927#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff
8928#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
8929#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000
8930#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
8931#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff
8932#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
8933#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff
8934#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
8935#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff
8936#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
8937#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1
8938#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
8939#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3
8940#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
8941#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4
8942#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
8943#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8
8944#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
8945#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10
8946#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
8947#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0
8948#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
8949#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff
8950#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
8951#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff
8952#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
8953#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff
8954#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
8955#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000
8956#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
8957#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000
8958#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
8959#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff
8960#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
8961#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff
8962#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
8963#define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1
8964#define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0
8965#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6
8966#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1
8967#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff
8968#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
8969#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff
8970#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
8971#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff
8972#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
8973#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff
8974#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
8975#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff
8976#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
8977#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff
8978#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
8979#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff
8980#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
8981#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff
8982#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
8983#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff
8984#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
8985#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff
8986#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
8987#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff
8988#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
8989#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff
8990#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
8991#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff
8992#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
8993#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff
8994#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
8995#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff
8996#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
8997#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff
8998#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
8999#define COMPUTE_NOWHERE__DATA_MASK 0xffffffff
9000#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
9001#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff
9002#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0
9003#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000
9004#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15
9005#define CSPRIV_CONNECT__VMID_MASK 0x3c000000
9006#define CSPRIV_CONNECT__VMID__SHIFT 0x1a
9007#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000
9008#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f
9009#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff
9010#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0
9011#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff
9012#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0
9013#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff
9014#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0
9015#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff
9016#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0
9017#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000
9018#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc
9019#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000
9020#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18
9021#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000
9022#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19
9023#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000
9024#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a
9025#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000
9026#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b
9027#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000
9028#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c
9029#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f
9030#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0
9031#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1
9032#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
9033#define RLC_CNTL__FORCE_RETRY_MASK 0x2
9034#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
9035#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4
9036#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
9037#define RLC_CNTL__RLC_STEP_F32_MASK 0x8
9038#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
9039#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10
9040#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4
9041#define RLC_CNTL__RESERVED_MASK 0xffffff00
9042#define RLC_CNTL__RESERVED__SHIFT 0x8
9043#define RLC_DEBUG_SELECT__SELECT_MASK 0xff
9044#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0
9045#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00
9046#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8
9047#define RLC_DEBUG__DATA_MASK 0xffffffff
9048#define RLC_DEBUG__DATA__SHIFT 0x0
9049#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3
9050#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0
9051#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4
9052#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2
9053#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8
9054#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3
9055#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10
9056#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4
9057#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0
9058#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5
9059#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00
9060#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9
9061#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000
9062#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd
9063#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000
9064#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
9065#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000
9066#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18
9067#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000
9068#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a
9069#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000
9070#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b
9071#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000
9072#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c
9073#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000
9074#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d
9075#define RLC_STAT__RLC_BUSY_MASK 0x1
9076#define RLC_STAT__RLC_BUSY__SHIFT 0x0
9077#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2
9078#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
9079#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4
9080#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
9081#define RLC_STAT__RLC_SRM_BUSY_MASK 0x8
9082#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3
9083#define RLC_STAT__RESERVED_MASK 0xfffffff0
9084#define RLC_STAT__RESERVED__SHIFT 0x4
9085#define RLC_SAFE_MODE__CMD_MASK 0x1
9086#define RLC_SAFE_MODE__CMD__SHIFT 0x0
9087#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e
9088#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
9089#define RLC_SAFE_MODE__RESERVED1_MASK 0xe0
9090#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
9091#define RLC_SAFE_MODE__RESPONSE_MASK 0xf00
9092#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
9093#define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000
9094#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
9095#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1
9096#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
9097#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2
9098#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
9099#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c
9100#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
9101#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80
9102#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
9103#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00
9104#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
9105#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000
9106#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
9107#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
9108#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
9109#define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff
9110#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
9111#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1
9112#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
9113#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e
9114#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
9115#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0
9116#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
9117#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00
9118#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
9119#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000
9120#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
9121#define RLC_SMU_SAFE_MODE__CMD_MASK 0x1
9122#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
9123#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e
9124#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
9125#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0
9126#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
9127#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00
9128#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
9129#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000
9130#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
9131#define RLC_RLCV_COMMAND__CMD_MASK 0xf
9132#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
9133#define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0
9134#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
9135#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x1
9136#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0
9137#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x2
9138#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1
9139#define RLC_CLK_CNTL__RESERVED_MASK 0xfffffffc
9140#define RLC_CLK_CNTL__RESERVED__SHIFT 0x2
9141#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1
9142#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
9143#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7
9144#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
9145#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
9146#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
9147#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff
9148#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
9149#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff
9150#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
9151#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
9152#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
9153#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
9154#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
9155#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
9156#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
9157#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
9158#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
9159#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf
9160#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
9161#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
9162#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
9163#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
9164#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
9165#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
9166#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
9167#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1
9168#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
9169#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2
9170#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
9171#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4
9172#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
9173#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8
9174#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
9175#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0
9176#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
9177#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000
9178#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
9179#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff
9180#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
9181#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff
9182#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
9183#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff
9184#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
9185#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff
9186#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
9187#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff
9188#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
9189#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00
9190#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
9191#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000
9192#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
9193#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff
9194#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0
9195#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300
9196#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8
9197#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00
9198#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa
9199#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff
9200#define RLC_GPM_DEBUG__DATA__SHIFT 0x0
9201#define RLC_GPM_DEBUG_INST_A__INST_A_MASK 0xffffffff
9202#define RLC_GPM_DEBUG_INST_A__INST_A__SHIFT 0x0
9203#define RLC_GPM_DEBUG_INST_B__INST_B_MASK 0xffffffff
9204#define RLC_GPM_DEBUG_INST_B__INST_B__SHIFT 0x0
9205#define RLC_GPM_DEBUG_INST_ADDR__ADRR_A_MASK 0xffff
9206#define RLC_GPM_DEBUG_INST_ADDR__ADRR_A__SHIFT 0x0
9207#define RLC_GPM_DEBUG_INST_ADDR__ADDR_B_MASK 0xffff0000
9208#define RLC_GPM_DEBUG_INST_ADDR__ADDR_B__SHIFT 0x10
9209#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
9210#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
9211#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
9212#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
9213#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
9214#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
9215#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1
9216#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0
9217#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2
9218#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1
9219#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c
9220#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2
9221#define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80
9222#define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7
9223#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000
9224#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18
9225#define RLC_ROM_CNTL__USE_ROM_MASK 0x1
9226#define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0
9227#define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2
9228#define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1
9229#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4
9230#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2
9231#define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8
9232#define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3
9233#define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10
9234#define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4
9235#define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0
9236#define RLC_ROM_CNTL__RESERVED__SHIFT 0x5
9237#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff
9238#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
9239#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff
9240#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
9241#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1
9242#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
9243#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe
9244#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
9245#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff
9246#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
9247#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1
9248#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
9249#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2
9250#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
9251#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4
9252#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
9253#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8
9254#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
9255#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10
9256#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
9257#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20
9258#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
9259#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40
9260#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
9261#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80
9262#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
9263#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100
9264#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
9265#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200
9266#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
9267#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400
9268#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
9269#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800
9270#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
9271#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000
9272#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
9273#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000
9274#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
9275#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000
9276#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
9277#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000
9278#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
9279#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000
9280#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
9281#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000
9282#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
9283#define RLC_GPM_STAT__RESERVED_MASK 0xfc0000
9284#define RLC_GPM_STAT__RESERVED__SHIFT 0x12
9285#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000
9286#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
9287#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f
9288#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
9289#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0
9290#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
9291#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff
9292#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
9293#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1
9294#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
9295#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2
9296#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
9297#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4
9298#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
9299#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8
9300#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
9301#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10
9302#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
9303#define RLC_PG_CNTL__RESERVED_MASK 0x3fe0
9304#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
9305#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000
9306#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
9307#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000
9308#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
9309#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000
9310#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
9311#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000
9312#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
9313#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000
9314#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
9315#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000
9316#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
9317#define RLC_PG_CNTL__RESERVED1_MASK 0xf00000
9318#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
9319#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff
9320#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
9321#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00
9322#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
9323#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000
9324#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
9325#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000
9326#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
9327#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1
9328#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
9329#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2
9330#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
9331#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4
9332#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
9333#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8
9334#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
9335#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0
9336#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
9337#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf
9338#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0
9339#define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0
9340#define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4
9341#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700
9342#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8
9343#define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800
9344#define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb
9345#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf
9346#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0
9347#define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0
9348#define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4
9349#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700
9350#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8
9351#define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800
9352#define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb
9353#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff
9354#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0
9355#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1
9356#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
9357#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2
9358#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
9359#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc
9360#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
9361#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00
9362#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
9363#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000
9364#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
9365#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000
9366#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
9367#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000
9368#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
9369#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000
9370#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
9371#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf
9372#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
9373#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0
9374#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
9375#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00
9376#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
9377#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000
9378#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
9379#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000
9380#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
9381#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000
9382#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
9383#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
9384#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
9385#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff
9386#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
9387#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff
9388#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
9389#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00
9390#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
9391#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000
9392#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
9393#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000
9394#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
9395#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff
9396#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
9397#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff
9398#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
9399#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff
9400#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
9401#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1
9402#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
9403#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe
9404#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
9405#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00
9406#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
9407#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000
9408#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
9409#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff
9410#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
9411#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00
9412#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
9413#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000
9414#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
9415#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000
9416#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
9417#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff
9418#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
9419#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff
9420#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
9421#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00
9422#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
9423#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1
9424#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
9425#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2
9426#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
9427#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4
9428#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
9429#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8
9430#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
9431#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000
9432#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
9433#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1
9434#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
9435#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe
9436#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
9437#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf
9438#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
9439#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30
9440#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
9441#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0
9442#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
9443#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200
9444#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
9445#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400
9446#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa
9447#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800
9448#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb
9449#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000
9450#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf
9451#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000
9452#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11
9453#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff
9454#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
9455#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff
9456#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
9457#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff
9458#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
9459#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff
9460#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
9461#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff
9462#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
9463#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000
9464#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
9465#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000
9466#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
9467#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000
9468#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
9469#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000
9470#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
9471#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000
9472#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
9473#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000
9474#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
9475#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000
9476#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
9477#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000
9478#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
9479#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000
9480#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18
9481#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff
9482#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
9483#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100
9484#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
9485#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200
9486#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
9487#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400
9488#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
9489#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800
9490#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
9491#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000
9492#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
9493#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000
9494#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
9495#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000
9496#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
9497#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000
9498#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
9499#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000
9500#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
9501#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000
9502#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
9503#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000
9504#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
9505#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000
9506#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
9507#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff
9508#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
9509#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff
9510#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
9511#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff
9512#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
9513#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000
9514#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
9515#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000
9516#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
9517#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000
9518#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
9519#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000
9520#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
9521#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000
9522#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
9523#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000
9524#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
9525#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000
9526#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
9527#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000
9528#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
9529#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000
9530#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18
9531#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff
9532#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
9533#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff
9534#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
9535#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff
9536#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
9537#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff
9538#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
9539#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff
9540#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
9541#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff
9542#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
9543#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff
9544#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
9545#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff
9546#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
9547#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff
9548#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
9549#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
9550#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
9551#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff
9552#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
9553#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
9554#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
9555#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf
9556#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
9557#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0
9558#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
9559#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00
9560#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
9561#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000
9562#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
9563#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000
9564#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
9565#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000
9566#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
9567#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000
9568#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
9569#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000
9570#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
9571#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf
9572#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
9573#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0
9574#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
9575#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00
9576#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
9577#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000
9578#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
9579#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000
9580#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
9581#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000
9582#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
9583#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000
9584#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
9585#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000
9586#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
9587#define RLC_GPR_REG1__DATA_MASK 0xffffffff
9588#define RLC_GPR_REG1__DATA__SHIFT 0x0
9589#define RLC_GPR_REG2__DATA_MASK 0xffffffff
9590#define RLC_GPR_REG2__DATA__SHIFT 0x0
9591#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1
9592#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
9593#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2
9594#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
9595#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4
9596#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
9597#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78
9598#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
9599#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80
9600#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
9601#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x8000
9602#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf
9603#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x10000
9604#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10
9605#define RLC_MGCG_CTRL__SPARE_MASK 0xfffe0000
9606#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11
9607#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1
9608#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
9609#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2
9610#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
9611#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4
9612#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
9613#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8
9614#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
9615#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0
9616#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
9617#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf
9618#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0
9619#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0
9620#define RLC_SPM_VMID__RESERVED__SHIFT 0x4
9621#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1
9622#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
9623#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe
9624#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
9625#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1
9626#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
9627#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe
9628#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
9629#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff
9630#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0
9631#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00
9632#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
9633#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000
9634#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf
9635#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000
9636#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10
9637#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff
9638#define RLC_SPM_DEBUG__DATA__SHIFT 0x0
9639#define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff
9640#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
9641#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff
9642#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
9643#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff
9644#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
9645#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff
9646#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
9647#define RLC_PG_DELAY_3__RESERVED_MASK 0xffffff00
9648#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
9649#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff
9650#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
9651#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff
9652#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
9653#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff
9654#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
9655#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff
9656#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
9657#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1
9658#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
9659#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2
9660#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
9661#define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc
9662#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
9663#define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff
9664#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0
9665#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00
9666#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8
9667#define RLC_SRM_DEBUG__DATA_MASK 0xffffffff
9668#define RLC_SRM_DEBUG__DATA__SHIFT 0x0
9669#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x3ff
9670#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
9671#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xfffffc00
9672#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xa
9673#define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff
9674#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
9675#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x3ff
9676#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
9677#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00
9678#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa
9679#define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff
9680#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
9681#define RLC_SRM_GPM_COMMAND__OP_MASK 0x1
9682#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
9683#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2
9684#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
9685#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c
9686#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
9687#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0
9688#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
9689#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000
9690#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
9691#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000
9692#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
9693#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000
9694#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
9695#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
9696#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
9697#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2
9698#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
9699#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
9700#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
9701#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1
9702#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
9703#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe
9704#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
9705#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0
9706#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
9707#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000
9708#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
9709#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000
9710#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
9711#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000
9712#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
9713#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
9714#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
9715#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2
9716#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
9717#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
9718#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
9719#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff
9720#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
9721#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000
9722#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
9723#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff
9724#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
9725#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000
9726#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
9727#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff
9728#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
9729#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000
9730#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
9731#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff
9732#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
9733#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000
9734#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
9735#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff
9736#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
9737#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000
9738#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
9739#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff
9740#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
9741#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000
9742#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
9743#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff
9744#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
9745#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000
9746#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
9747#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff
9748#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
9749#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000
9750#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
9751#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff
9752#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
9753#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff
9754#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
9755#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff
9756#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
9757#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff
9758#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
9759#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff
9760#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
9761#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff
9762#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
9763#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff
9764#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
9765#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff
9766#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
9767#define RLC_SRM_STAT__SRM_STATUS_MASK 0x1
9768#define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0
9769#define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe
9770#define RLC_SRM_STAT__RESERVED__SHIFT 0x1
9771#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1
9772#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
9773#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe
9774#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
9775#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff
9776#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
9777#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff
9778#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
9779#define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff
9780#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
9781#define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff
9782#define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0
9783#define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff
9784#define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0
9785#define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff
9786#define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0
9787#define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff
9788#define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0
9789#define RLC_SMU_COMMAND__CMD_MASK 0xffffffff
9790#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
9791#define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff
9792#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
9793#define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00
9794#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
9795#define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000
9796#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
9797#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000
9798#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
9799#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xffffffff
9800#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0
9801#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xffffffff
9802#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0
9803#define RLC_GPM_GENERAL_8__DATA_MASK 0xffffffff
9804#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0
9805#define RLC_GPM_GENERAL_9__DATA_MASK 0xffffffff
9806#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0
9807#define RLC_GPM_GENERAL_10__DATA_MASK 0xffffffff
9808#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0
9809#define RLC_GPM_GENERAL_11__DATA_MASK 0xffffffff
9810#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0
9811#define RLC_GPM_GENERAL_12__DATA_MASK 0xffffffff
9812#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0
9813#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff
9814#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
9815#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000
9816#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
9817#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000
9818#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
9819#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000
9820#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
9821#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff
9822#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
9823#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff
9824#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
9825#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000
9826#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
9827#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff
9828#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
9829#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff
9830#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
9831#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700
9832#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
9833#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800
9834#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
9835#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000
9836#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
9837#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000
9838#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
9839#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000
9840#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
9841#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000
9842#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
9843#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
9844#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
9845#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
9846#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
9847#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9848#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9849#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9850#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9851#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9852#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9853#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9854#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9855#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9856#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9857#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9858#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9859#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9860#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9861#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9862#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9863#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9864#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9865#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9866#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9867#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9868#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9869#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9870#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9871#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9872#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9873#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9874#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9875#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9876#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9877#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9878#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9879#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9880#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9881#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9882#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9883#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9884#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9885#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9886#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9887#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9888#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9889#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9890#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9891#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9892#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9893#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9894#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9895#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9896#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9897#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9898#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9899#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9900#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9901#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9902#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9903#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9904#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9905#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9906#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9907#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9908#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9909#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9910#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9911#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9912#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9913#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9914#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9915#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9916#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9917#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9918#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9919#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
9920#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
9921#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
9922#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
9923#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff
9924#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
9925#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff
9926#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
9927#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1
9928#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
9929#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe
9930#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
9931#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000
9932#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
9933#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff
9934#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
9935#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf
9936#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
9937#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0
9938#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
9939#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000
9940#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
9941#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f
9942#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
9943#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300
9944#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
9945#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400
9946#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
9947#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000
9948#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
9949#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000
9950#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
9951#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000
9952#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
9953#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000
9954#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
9955#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000
9956#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
9957#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000
9958#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
9959#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9960#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9961#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000
9962#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
9963#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000
9964#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
9965#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f
9966#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
9967#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300
9968#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
9969#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400
9970#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
9971#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000
9972#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
9973#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000
9974#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
9975#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000
9976#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
9977#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000
9978#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
9979#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000
9980#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
9981#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000
9982#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
9983#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9984#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9985#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000
9986#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
9987#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000
9988#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
9989#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f
9990#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
9991#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300
9992#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
9993#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400
9994#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
9995#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000
9996#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
9997#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000
9998#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
9999#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000
10000#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
10001#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000
10002#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
10003#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000
10004#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
10005#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000
10006#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
10007#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10008#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10009#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000
10010#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
10011#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000
10012#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
10013#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f
10014#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
10015#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300
10016#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
10017#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400
10018#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
10019#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000
10020#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
10021#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000
10022#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
10023#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000
10024#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
10025#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000
10026#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
10027#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000
10028#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
10029#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000
10030#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
10031#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10032#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10033#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000
10034#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
10035#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000
10036#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
10037#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f
10038#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
10039#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300
10040#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
10041#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400
10042#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
10043#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000
10044#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
10045#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000
10046#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
10047#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000
10048#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
10049#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000
10050#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
10051#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000
10052#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
10053#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000
10054#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
10055#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10056#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10057#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000
10058#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
10059#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000
10060#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
10061#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f
10062#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
10063#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300
10064#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
10065#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400
10066#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
10067#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000
10068#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
10069#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000
10070#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
10071#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000
10072#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
10073#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000
10074#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
10075#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000
10076#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
10077#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000
10078#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
10079#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10080#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10081#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000
10082#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
10083#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000
10084#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
10085#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f
10086#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
10087#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300
10088#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
10089#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400
10090#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
10091#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000
10092#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
10093#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000
10094#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
10095#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000
10096#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
10097#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000
10098#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
10099#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000
10100#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
10101#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000
10102#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
10103#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10104#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10105#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000
10106#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
10107#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000
10108#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
10109#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f
10110#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
10111#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300
10112#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
10113#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400
10114#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
10115#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000
10116#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
10117#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000
10118#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
10119#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000
10120#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
10121#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000
10122#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
10123#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000
10124#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
10125#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000
10126#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
10127#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10128#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10129#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000
10130#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
10131#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000
10132#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
10133#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f
10134#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
10135#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300
10136#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
10137#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400
10138#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
10139#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000
10140#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
10141#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000
10142#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
10143#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000
10144#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
10145#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000
10146#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
10147#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000
10148#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
10149#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000
10150#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
10151#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10152#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10153#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000
10154#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
10155#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000
10156#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
10157#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f
10158#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
10159#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300
10160#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
10161#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400
10162#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
10163#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000
10164#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
10165#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000
10166#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
10167#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000
10168#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
10169#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000
10170#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
10171#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000
10172#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
10173#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000
10174#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
10175#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10176#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10177#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000
10178#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
10179#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000
10180#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
10181#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f
10182#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
10183#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300
10184#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
10185#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400
10186#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
10187#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000
10188#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
10189#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000
10190#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
10191#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000
10192#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
10193#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000
10194#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
10195#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000
10196#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
10197#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000
10198#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
10199#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10200#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10201#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000
10202#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
10203#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000
10204#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
10205#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f
10206#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
10207#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300
10208#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
10209#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400
10210#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
10211#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000
10212#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
10213#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000
10214#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
10215#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000
10216#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
10217#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000
10218#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
10219#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000
10220#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
10221#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000
10222#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
10223#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10224#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10225#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000
10226#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
10227#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000
10228#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
10229#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f
10230#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
10231#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300
10232#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
10233#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400
10234#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
10235#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000
10236#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
10237#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000
10238#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
10239#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000
10240#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
10241#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000
10242#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
10243#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000
10244#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
10245#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000
10246#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
10247#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10248#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10249#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000
10250#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
10251#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000
10252#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
10253#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f
10254#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
10255#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300
10256#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
10257#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400
10258#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
10259#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000
10260#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
10261#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000
10262#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
10263#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000
10264#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
10265#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000
10266#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
10267#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000
10268#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
10269#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000
10270#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
10271#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10272#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10273#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000
10274#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
10275#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000
10276#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
10277#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f
10278#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
10279#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300
10280#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
10281#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400
10282#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
10283#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000
10284#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
10285#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000
10286#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
10287#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000
10288#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
10289#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000
10290#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
10291#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000
10292#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
10293#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000
10294#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
10295#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10296#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10297#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000
10298#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
10299#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000
10300#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
10301#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f
10302#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
10303#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300
10304#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
10305#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400
10306#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
10307#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000
10308#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
10309#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000
10310#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
10311#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000
10312#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
10313#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000
10314#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
10315#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000
10316#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
10317#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000
10318#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
10319#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10320#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10321#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000
10322#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
10323#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000
10324#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
10325#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f
10326#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
10327#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300
10328#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
10329#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400
10330#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
10331#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000
10332#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
10333#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000
10334#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
10335#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000
10336#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
10337#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000
10338#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
10339#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000
10340#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
10341#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000
10342#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
10343#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10344#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10345#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000
10346#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
10347#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000
10348#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
10349#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f
10350#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
10351#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300
10352#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
10353#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400
10354#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
10355#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000
10356#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
10357#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000
10358#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
10359#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000
10360#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
10361#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000
10362#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
10363#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000
10364#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
10365#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000
10366#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
10367#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10368#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10369#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000
10370#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
10371#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000
10372#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
10373#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f
10374#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
10375#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300
10376#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
10377#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400
10378#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
10379#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000
10380#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
10381#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000
10382#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
10383#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000
10384#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
10385#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000
10386#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
10387#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000
10388#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
10389#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000
10390#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
10391#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10392#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10393#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000
10394#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
10395#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000
10396#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
10397#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f
10398#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
10399#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300
10400#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
10401#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400
10402#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
10403#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000
10404#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
10405#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000
10406#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
10407#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000
10408#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
10409#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000
10410#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
10411#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000
10412#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
10413#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000
10414#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
10415#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10416#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10417#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000
10418#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
10419#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000
10420#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
10421#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f
10422#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
10423#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300
10424#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
10425#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400
10426#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
10427#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000
10428#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
10429#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000
10430#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
10431#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000
10432#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
10433#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000
10434#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
10435#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000
10436#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
10437#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000
10438#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
10439#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f
10440#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
10441#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300
10442#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
10443#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400
10444#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
10445#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000
10446#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
10447#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000
10448#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
10449#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000
10450#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
10451#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000
10452#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
10453#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000
10454#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
10455#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000
10456#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
10457#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f
10458#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
10459#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300
10460#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
10461#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400
10462#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
10463#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000
10464#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
10465#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000
10466#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
10467#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000
10468#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
10469#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000
10470#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
10471#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000
10472#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
10473#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000
10474#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
10475#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f
10476#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
10477#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300
10478#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
10479#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400
10480#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
10481#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000
10482#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
10483#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000
10484#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
10485#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000
10486#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
10487#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000
10488#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
10489#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000
10490#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
10491#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000
10492#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
10493#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f
10494#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
10495#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300
10496#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
10497#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400
10498#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
10499#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000
10500#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
10501#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000
10502#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
10503#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000
10504#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
10505#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000
10506#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
10507#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000
10508#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
10509#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000
10510#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
10511#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f
10512#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
10513#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300
10514#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
10515#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400
10516#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
10517#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000
10518#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
10519#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000
10520#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
10521#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000
10522#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
10523#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000
10524#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
10525#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000
10526#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
10527#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000
10528#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
10529#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f
10530#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
10531#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300
10532#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
10533#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400
10534#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
10535#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000
10536#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
10537#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000
10538#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
10539#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000
10540#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
10541#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000
10542#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
10543#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000
10544#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
10545#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000
10546#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
10547#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f
10548#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
10549#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300
10550#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
10551#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400
10552#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
10553#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000
10554#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
10555#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000
10556#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
10557#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000
10558#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
10559#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000
10560#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
10561#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000
10562#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
10563#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000
10564#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
10565#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f
10566#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
10567#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300
10568#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
10569#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400
10570#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
10571#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000
10572#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
10573#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000
10574#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
10575#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000
10576#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
10577#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000
10578#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
10579#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000
10580#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
10581#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000
10582#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
10583#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f
10584#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
10585#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300
10586#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
10587#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400
10588#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
10589#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000
10590#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
10591#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000
10592#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
10593#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000
10594#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
10595#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000
10596#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
10597#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000
10598#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
10599#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000
10600#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
10601#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f
10602#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
10603#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300
10604#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
10605#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400
10606#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
10607#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000
10608#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
10609#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000
10610#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
10611#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000
10612#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
10613#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000
10614#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
10615#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000
10616#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
10617#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000
10618#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
10619#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f
10620#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
10621#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300
10622#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
10623#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400
10624#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
10625#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000
10626#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
10627#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000
10628#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
10629#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000
10630#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
10631#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000
10632#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
10633#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000
10634#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
10635#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000
10636#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
10637#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e
10638#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
10639#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40
10640#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
10641#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1
10642#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
10643#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2
10644#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
10645#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4
10646#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
10647#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8
10648#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
10649#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10
10650#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
10651#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20
10652#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
10653#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40
10654#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
10655#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80
10656#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
10657#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100
10658#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
10659#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200
10660#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
10661#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400
10662#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
10663#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800
10664#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
10665#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000
10666#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
10667#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000
10668#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
10669#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000
10670#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
10671#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000
10672#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
10673#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1
10674#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
10675#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2
10676#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
10677#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4
10678#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
10679#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8
10680#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
10681#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10
10682#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
10683#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20
10684#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
10685#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40
10686#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
10687#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80
10688#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
10689#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100
10690#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
10691#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200
10692#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
10693#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400
10694#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
10695#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800
10696#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
10697#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000
10698#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
10699#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000
10700#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
10701#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000
10702#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
10703#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000
10704#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
10705#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1
10706#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
10707#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2
10708#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
10709#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c
10710#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
10711#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0
10712#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
10713#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700
10714#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
10715#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800
10716#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
10717#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000
10718#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
10719#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
10720#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
10721#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40
10722#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
10723#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000
10724#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
10725#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1
10726#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
10727#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10
10728#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
10729#define SPI_BARYC_CNTL_