Warning: This file is not a C or C++ file. It does not have highlighting.

1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _mp_9_0_SH_MASK_HEADER
22#define _mp_9_0_SH_MASK_HEADER
23
24
25// addressBlock: mp_SmuMp0_SmnDec
26//MP0_SMN_C2PMSG_32
27#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
28#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
29//MP0_SMN_C2PMSG_33
30#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
31#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
32//MP0_SMN_C2PMSG_34
33#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
34#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
35//MP0_SMN_C2PMSG_35
36#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
37#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
38//MP0_SMN_C2PMSG_36
39#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
40#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
41//MP0_SMN_C2PMSG_37
42#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
43#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
44//MP0_SMN_C2PMSG_38
45#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
46#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
47//MP0_SMN_C2PMSG_39
48#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
49#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
50//MP0_SMN_C2PMSG_40
51#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
52#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
53//MP0_SMN_C2PMSG_41
54#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
55#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
56//MP0_SMN_C2PMSG_42
57#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
58#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
59//MP0_SMN_C2PMSG_43
60#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
61#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
62//MP0_SMN_C2PMSG_44
63#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
64#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
65//MP0_SMN_C2PMSG_45
66#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
67#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
68//MP0_SMN_C2PMSG_46
69#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
70#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
71//MP0_SMN_C2PMSG_47
72#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
73#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
74//MP0_SMN_C2PMSG_48
75#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
76#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
77//MP0_SMN_C2PMSG_49
78#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
79#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
80//MP0_SMN_C2PMSG_50
81#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
82#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
83//MP0_SMN_C2PMSG_51
84#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
85#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
86//MP0_SMN_C2PMSG_52
87#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
88#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
89//MP0_SMN_C2PMSG_53
90#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
91#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
92//MP0_SMN_C2PMSG_54
93#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
94#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
95//MP0_SMN_C2PMSG_55
96#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
97#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
98//MP0_SMN_C2PMSG_56
99#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
100#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
101//MP0_SMN_C2PMSG_57
102#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
103#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
104//MP0_SMN_C2PMSG_58
105#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
106#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
107//MP0_SMN_C2PMSG_59
108#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
109#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
110//MP0_SMN_C2PMSG_60
111#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
112#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
113//MP0_SMN_C2PMSG_61
114#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
115#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
116//MP0_SMN_C2PMSG_62
117#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
118#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
119//MP0_SMN_C2PMSG_63
120#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
121#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
122//MP0_SMN_C2PMSG_64
123#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
124#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
125//MP0_SMN_C2PMSG_65
126#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
127#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
128//MP0_SMN_C2PMSG_66
129#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
130#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
131//MP0_SMN_C2PMSG_67
132#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
133#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
134//MP0_SMN_C2PMSG_68
135#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
136#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
137//MP0_SMN_C2PMSG_69
138#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
139#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
140//MP0_SMN_C2PMSG_70
141#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
142#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
143//MP0_SMN_C2PMSG_71
144#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
145#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
146//MP0_SMN_C2PMSG_72
147#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
148#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
149//MP0_SMN_C2PMSG_73
150#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
151#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
152//MP0_SMN_C2PMSG_74
153#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
154#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
155//MP0_SMN_C2PMSG_75
156#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
157#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
158//MP0_SMN_C2PMSG_76
159#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
160#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
161//MP0_SMN_C2PMSG_77
162#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
163#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
164//MP0_SMN_C2PMSG_78
165#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
166#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
167//MP0_SMN_C2PMSG_79
168#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
169#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
170//MP0_SMN_C2PMSG_80
171#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
172#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
173//MP0_SMN_C2PMSG_81
174#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
175#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
176//MP0_SMN_C2PMSG_82
177#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
178#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
179//MP0_SMN_C2PMSG_83
180#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
181#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
182//MP0_SMN_C2PMSG_84
183#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
184#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
185//MP0_SMN_C2PMSG_85
186#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
187#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
188//MP0_SMN_C2PMSG_86
189#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
190#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
191//MP0_SMN_C2PMSG_87
192#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
193#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
194//MP0_SMN_C2PMSG_88
195#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
196#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
197//MP0_SMN_C2PMSG_89
198#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
199#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
200//MP0_SMN_C2PMSG_90
201#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
202#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
203//MP0_SMN_C2PMSG_91
204#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
205#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
206//MP0_SMN_C2PMSG_92
207#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
208#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
209//MP0_SMN_C2PMSG_93
210#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
211#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
212//MP0_SMN_C2PMSG_94
213#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
214#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
215//MP0_SMN_C2PMSG_95
216#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
217#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
218//MP0_SMN_C2PMSG_96
219#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
220#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
221//MP0_SMN_C2PMSG_97
222#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
223#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
224//MP0_SMN_C2PMSG_98
225#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
226#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
227//MP0_SMN_C2PMSG_99
228#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
229#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
230//MP0_SMN_C2PMSG_100
231#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
232#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
233//MP0_SMN_C2PMSG_101
234#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
235#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
236//MP0_SMN_C2PMSG_102
237#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
238#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
239//MP0_SMN_C2PMSG_103
240#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
241#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
242//MP0_SMN_ACTIVE_FCN_ID
243#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
244#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
245#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
246#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
247//MP0_SMN_IH_CREDIT
248#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
249#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
250#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
251#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
252//MP0_SMN_IH_SW_INT
253#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0
254#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1
255#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L
256#define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL
257//MP0_SMN_IH_SW_INT_CTRL
258#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
259#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
260#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
261#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
262
263
264// addressBlock: mp_SmuMp1_SmnDec
265//MP1_SMN_ACP2MP_RESP
266#define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0
267#define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
268//MP1_SMN_DC2MP_RESP
269#define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0
270#define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
271//MP1_SMN_UVD2MP_RESP
272#define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0
273#define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
274//MP1_SMN_VCE2MP_RESP
275#define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0
276#define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
277//MP1_SMN_RLC2MP_RESP
278#define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0
279#define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
280//MP1_SMN_C2PMSG_32
281#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
282#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
283//MP1_SMN_C2PMSG_33
284#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
285#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
286//MP1_SMN_C2PMSG_34
287#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
288#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
289//MP1_SMN_C2PMSG_35
290#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
291#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
292//MP1_SMN_C2PMSG_36
293#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
294#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
295//MP1_SMN_C2PMSG_37
296#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
297#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
298//MP1_SMN_C2PMSG_38
299#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
300#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
301//MP1_SMN_C2PMSG_39
302#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
303#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
304//MP1_SMN_C2PMSG_40
305#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
306#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
307//MP1_SMN_C2PMSG_41
308#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
309#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
310//MP1_SMN_C2PMSG_42
311#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
312#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
313//MP1_SMN_C2PMSG_43
314#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
315#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
316//MP1_SMN_C2PMSG_44
317#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
318#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
319//MP1_SMN_C2PMSG_45
320#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
321#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
322//MP1_SMN_C2PMSG_46
323#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
324#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
325//MP1_SMN_C2PMSG_47
326#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
327#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
328//MP1_SMN_C2PMSG_48
329#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
330#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
331//MP1_SMN_C2PMSG_49
332#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
333#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
334//MP1_SMN_C2PMSG_50
335#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
336#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
337//MP1_SMN_C2PMSG_51
338#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
339#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
340//MP1_SMN_C2PMSG_52
341#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
342#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
343//MP1_SMN_C2PMSG_53
344#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
345#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
346//MP1_SMN_C2PMSG_54
347#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
348#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
349//MP1_SMN_C2PMSG_55
350#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
351#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
352//MP1_SMN_C2PMSG_56
353#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
354#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
355//MP1_SMN_C2PMSG_57
356#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
357#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
358//MP1_SMN_C2PMSG_58
359#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
360#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
361//MP1_SMN_C2PMSG_59
362#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
363#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
364//MP1_SMN_C2PMSG_60
365#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
366#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
367//MP1_SMN_C2PMSG_61
368#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
369#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
370//MP1_SMN_C2PMSG_62
371#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
372#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
373//MP1_SMN_C2PMSG_63
374#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
375#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
376//MP1_SMN_C2PMSG_64
377#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
378#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
379//MP1_SMN_C2PMSG_65
380#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
381#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
382//MP1_SMN_C2PMSG_66
383#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
384#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
385//MP1_SMN_C2PMSG_67
386#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
387#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
388//MP1_SMN_C2PMSG_68
389#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
390#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
391//MP1_SMN_C2PMSG_69
392#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
393#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
394//MP1_SMN_C2PMSG_70
395#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
396#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
397//MP1_SMN_C2PMSG_71
398#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
399#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
400//MP1_SMN_C2PMSG_72
401#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
402#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
403//MP1_SMN_C2PMSG_73
404#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
405#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
406//MP1_SMN_C2PMSG_74
407#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
408#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
409//MP1_SMN_C2PMSG_75
410#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
411#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
412//MP1_SMN_C2PMSG_76
413#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
414#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
415//MP1_SMN_C2PMSG_77
416#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
417#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
418//MP1_SMN_C2PMSG_78
419#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
420#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
421//MP1_SMN_C2PMSG_79
422#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
423#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
424//MP1_SMN_C2PMSG_80
425#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
426#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
427//MP1_SMN_C2PMSG_81
428#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
429#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
430//MP1_SMN_C2PMSG_82
431#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
432#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
433//MP1_SMN_C2PMSG_83
434#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
435#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
436//MP1_SMN_C2PMSG_84
437#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
438#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
439//MP1_SMN_C2PMSG_85
440#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
441#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
442//MP1_SMN_C2PMSG_86
443#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
444#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
445//MP1_SMN_C2PMSG_87
446#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
447#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
448//MP1_SMN_C2PMSG_88
449#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
450#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
451//MP1_SMN_C2PMSG_89
452#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
453#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
454//MP1_SMN_C2PMSG_90
455#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
456#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
457//MP1_SMN_C2PMSG_91
458#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
459#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
460//MP1_SMN_C2PMSG_92
461#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
462#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
463//MP1_SMN_C2PMSG_93
464#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
465#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
466//MP1_SMN_C2PMSG_94
467#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
468#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
469//MP1_SMN_C2PMSG_95
470#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
471#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
472//MP1_SMN_C2PMSG_96
473#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
474#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
475//MP1_SMN_C2PMSG_97
476#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
477#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
478//MP1_SMN_C2PMSG_98
479#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
480#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
481//MP1_SMN_C2PMSG_99
482#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
483#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
484//MP1_SMN_C2PMSG_100
485#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
486#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
487//MP1_SMN_C2PMSG_101
488#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
489#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
490//MP1_SMN_C2PMSG_102
491#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
492#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
493//MP1_SMN_C2PMSG_103
494#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
495#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
496//MP1_SMN_ACTIVE_FCN_ID
497#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
498#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
499#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
500#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
501//MP1_SMN_IH_CREDIT
502#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
503#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
504#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
505#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
506//MP1_SMN_IH_SW_INT
507#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0
508#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1
509#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L
510#define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL
511//MP1_SMN_IH_SW_INT_CTRL
512#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
513#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
514#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
515#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
516//MP1_SMN_FPS_CNT
517#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
518#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
519//MP1_SMN_EXT_SCRATCH0
520#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
521#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
522//MP1_SMN_EXT_SCRATCH1
523#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
524#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
525//MP1_SMN_EXT_SCRATCH2
526#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
527#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
528//MP1_SMN_EXT_SCRATCH3
529#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
530#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
531//MP1_SMN_EXT_SCRATCH4
532#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
533#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
534//MP1_SMN_EXT_SCRATCH5
535#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
536#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
537//MP1_SMN_EXT_SCRATCH6
538#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
539#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
540//MP1_SMN_EXT_SCRATCH7
541#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
542#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
543//MP1_SMN_EXT_SCRATCH8
544#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0
545#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL
546
547
548
549
550// addressBlock: mp_SmuMp0Pub_CruDec
551//MP0_SOC_INFO
552#define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0
553#define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2
554#define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L
555#define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL
556//MP0_PUB_SCRATCH0
557#define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0
558#define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
559//MP0_PUB_SCRATCH1
560#define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0
561#define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
562//MP0_PUB_SCRATCH2
563#define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0
564#define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
565//MP0_PUB_SCRATCH3
566#define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0
567#define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
568//MP0_FW_INTF
569#define MP0_FW_INTF__SS_SECURE__SHIFT 0x13
570#define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L
571//MP0_C2PMSG_0
572#define MP0_C2PMSG_0__CONTENT__SHIFT 0x0
573#define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
574//MP0_C2PMSG_1
575#define MP0_C2PMSG_1__CONTENT__SHIFT 0x0
576#define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
577//MP0_C2PMSG_2
578#define MP0_C2PMSG_2__CONTENT__SHIFT 0x0
579#define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
580//MP0_C2PMSG_3
581#define MP0_C2PMSG_3__CONTENT__SHIFT 0x0
582#define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
583//MP0_C2PMSG_4
584#define MP0_C2PMSG_4__CONTENT__SHIFT 0x0
585#define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
586//MP0_C2PMSG_5
587#define MP0_C2PMSG_5__CONTENT__SHIFT 0x0
588#define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
589//MP0_C2PMSG_6
590#define MP0_C2PMSG_6__CONTENT__SHIFT 0x0
591#define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
592//MP0_C2PMSG_7
593#define MP0_C2PMSG_7__CONTENT__SHIFT 0x0
594#define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
595//MP0_C2PMSG_8
596#define MP0_C2PMSG_8__CONTENT__SHIFT 0x0
597#define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
598//MP0_C2PMSG_9
599#define MP0_C2PMSG_9__CONTENT__SHIFT 0x0
600#define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
601//MP0_C2PMSG_10
602#define MP0_C2PMSG_10__CONTENT__SHIFT 0x0
603#define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
604//MP0_C2PMSG_11
605#define MP0_C2PMSG_11__CONTENT__SHIFT 0x0
606#define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
607//MP0_C2PMSG_12
608#define MP0_C2PMSG_12__CONTENT__SHIFT 0x0
609#define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
610//MP0_C2PMSG_13
611#define MP0_C2PMSG_13__CONTENT__SHIFT 0x0
612#define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
613//MP0_C2PMSG_14
614#define MP0_C2PMSG_14__CONTENT__SHIFT 0x0
615#define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
616//MP0_C2PMSG_15
617#define MP0_C2PMSG_15__CONTENT__SHIFT 0x0
618#define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
619//MP0_C2PMSG_16
620#define MP0_C2PMSG_16__CONTENT__SHIFT 0x0
621#define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
622//MP0_C2PMSG_17
623#define MP0_C2PMSG_17__CONTENT__SHIFT 0x0
624#define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
625//MP0_C2PMSG_18
626#define MP0_C2PMSG_18__CONTENT__SHIFT 0x0
627#define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
628//MP0_C2PMSG_19
629#define MP0_C2PMSG_19__CONTENT__SHIFT 0x0
630#define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
631//MP0_C2PMSG_20
632#define MP0_C2PMSG_20__CONTENT__SHIFT 0x0
633#define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
634//MP0_C2PMSG_21
635#define MP0_C2PMSG_21__CONTENT__SHIFT 0x0
636#define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
637//MP0_C2PMSG_22
638#define MP0_C2PMSG_22__CONTENT__SHIFT 0x0
639#define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
640//MP0_C2PMSG_23
641#define MP0_C2PMSG_23__CONTENT__SHIFT 0x0
642#define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
643//MP0_C2PMSG_24
644#define MP0_C2PMSG_24__CONTENT__SHIFT 0x0
645#define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
646//MP0_C2PMSG_25
647#define MP0_C2PMSG_25__CONTENT__SHIFT 0x0
648#define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
649//MP0_C2PMSG_26
650#define MP0_C2PMSG_26__CONTENT__SHIFT 0x0
651#define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
652//MP0_C2PMSG_27
653#define MP0_C2PMSG_27__CONTENT__SHIFT 0x0
654#define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
655//MP0_C2PMSG_28
656#define MP0_C2PMSG_28__CONTENT__SHIFT 0x0
657#define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
658//MP0_C2PMSG_29
659#define MP0_C2PMSG_29__CONTENT__SHIFT 0x0
660#define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
661//MP0_C2PMSG_30
662#define MP0_C2PMSG_30__CONTENT__SHIFT 0x0
663#define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
664//MP0_C2PMSG_31
665#define MP0_C2PMSG_31__CONTENT__SHIFT 0x0
666#define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
667//MP0_P2CMSG_0
668#define MP0_P2CMSG_0__CONTENT__SHIFT 0x0
669#define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
670//MP0_P2CMSG_1
671#define MP0_P2CMSG_1__CONTENT__SHIFT 0x0
672#define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
673//MP0_P2CMSG_2
674#define MP0_P2CMSG_2__CONTENT__SHIFT 0x0
675#define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
676//MP0_P2CMSG_3
677#define MP0_P2CMSG_3__CONTENT__SHIFT 0x0
678#define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
679//MP0_P2CMSG_INTEN
680#define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0
681#define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
682//MP0_P2CMSG_INTSTS
683#define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
684#define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
685#define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
686#define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
687#define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
688#define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
689#define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
690#define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
691//MP0_C2PMSG_ATTR_0
692#define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0
693#define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL
694//MP0_C2PMSG_ATTR_1
695#define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0
696#define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL
697//MP0_C2PMSG_ATTR_2
698#define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0
699#define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL
700//MP0_C2PMSG_ATTR_3
701#define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0
702#define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL
703//MP0_C2PMSG_ATTR_4
704#define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0
705#define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL
706//MP0_C2PMSG_ATTR_5
707#define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0
708#define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL
709//MP0_C2PMSG_ATTR_6
710#define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0
711#define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL
712//MP0_P2CMSG_ATTR
713#define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0
714#define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL
715//MP0_P2SMSG_0
716#define MP0_P2SMSG_0__CONTENT__SHIFT 0x0
717#define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
718//MP0_P2SMSG_1
719#define MP0_P2SMSG_1__CONTENT__SHIFT 0x0
720#define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
721//MP0_P2SMSG_2
722#define MP0_P2SMSG_2__CONTENT__SHIFT 0x0
723#define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
724//MP0_P2SMSG_3
725#define MP0_P2SMSG_3__CONTENT__SHIFT 0x0
726#define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
727//MP0_P2SMSG_ATTR
728#define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0
729#define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL
730//MP0_S2PMSG_ATTR
731#define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0
732#define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L
733//MP0_P2SMSG_INTSTS
734#define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
735#define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
736#define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
737#define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
738#define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
739#define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
740#define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
741#define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
742//MP0_S2PMSG_0
743#define MP0_S2PMSG_0__CONTENT__SHIFT 0x0
744#define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
745//MP0_C2PMSG_32
746#define MP0_C2PMSG_32__CONTENT__SHIFT 0x0
747#define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
748//MP0_C2PMSG_33
749#define MP0_C2PMSG_33__CONTENT__SHIFT 0x0
750#define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
751//MP0_C2PMSG_34
752#define MP0_C2PMSG_34__CONTENT__SHIFT 0x0
753#define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
754//MP0_C2PMSG_35
755#define MP0_C2PMSG_35__CONTENT__SHIFT 0x0
756#define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
757//MP0_C2PMSG_36
758#define MP0_C2PMSG_36__CONTENT__SHIFT 0x0
759#define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
760//MP0_C2PMSG_37
761#define MP0_C2PMSG_37__CONTENT__SHIFT 0x0
762#define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
763//MP0_C2PMSG_38
764#define MP0_C2PMSG_38__CONTENT__SHIFT 0x0
765#define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
766//MP0_C2PMSG_39
767#define MP0_C2PMSG_39__CONTENT__SHIFT 0x0
768#define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
769//MP0_C2PMSG_40
770#define MP0_C2PMSG_40__CONTENT__SHIFT 0x0
771#define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
772//MP0_C2PMSG_41
773#define MP0_C2PMSG_41__CONTENT__SHIFT 0x0
774#define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
775//MP0_C2PMSG_42
776#define MP0_C2PMSG_42__CONTENT__SHIFT 0x0
777#define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
778//MP0_C2PMSG_43
779#define MP0_C2PMSG_43__CONTENT__SHIFT 0x0
780#define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
781//MP0_C2PMSG_44
782#define MP0_C2PMSG_44__CONTENT__SHIFT 0x0
783#define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
784//MP0_C2PMSG_45
785#define MP0_C2PMSG_45__CONTENT__SHIFT 0x0
786#define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
787//MP0_C2PMSG_46
788#define MP0_C2PMSG_46__CONTENT__SHIFT 0x0
789#define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
790//MP0_C2PMSG_47
791#define MP0_C2PMSG_47__CONTENT__SHIFT 0x0
792#define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
793//MP0_C2PMSG_48
794#define MP0_C2PMSG_48__CONTENT__SHIFT 0x0
795#define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
796//MP0_C2PMSG_49
797#define MP0_C2PMSG_49__CONTENT__SHIFT 0x0
798#define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
799//MP0_C2PMSG_50
800#define MP0_C2PMSG_50__CONTENT__SHIFT 0x0
801#define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
802//MP0_C2PMSG_51
803#define MP0_C2PMSG_51__CONTENT__SHIFT 0x0
804#define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
805//MP0_C2PMSG_52
806#define MP0_C2PMSG_52__CONTENT__SHIFT 0x0
807#define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
808//MP0_C2PMSG_53
809#define MP0_C2PMSG_53__CONTENT__SHIFT 0x0
810#define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
811//MP0_C2PMSG_54
812#define MP0_C2PMSG_54__CONTENT__SHIFT 0x0
813#define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
814//MP0_C2PMSG_55
815#define MP0_C2PMSG_55__CONTENT__SHIFT 0x0
816#define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
817//MP0_C2PMSG_56
818#define MP0_C2PMSG_56__CONTENT__SHIFT 0x0
819#define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
820//MP0_C2PMSG_57
821#define MP0_C2PMSG_57__CONTENT__SHIFT 0x0
822#define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
823//MP0_C2PMSG_58
824#define MP0_C2PMSG_58__CONTENT__SHIFT 0x0
825#define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
826//MP0_C2PMSG_59
827#define MP0_C2PMSG_59__CONTENT__SHIFT 0x0
828#define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
829//MP0_C2PMSG_60
830#define MP0_C2PMSG_60__CONTENT__SHIFT 0x0
831#define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
832//MP0_C2PMSG_61
833#define MP0_C2PMSG_61__CONTENT__SHIFT 0x0
834#define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
835//MP0_C2PMSG_62
836#define MP0_C2PMSG_62__CONTENT__SHIFT 0x0
837#define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
838//MP0_C2PMSG_63
839#define MP0_C2PMSG_63__CONTENT__SHIFT 0x0
840#define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
841//MP0_C2PMSG_64
842#define MP0_C2PMSG_64__CONTENT__SHIFT 0x0
843#define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
844//MP0_C2PMSG_65
845#define MP0_C2PMSG_65__CONTENT__SHIFT 0x0
846#define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
847//MP0_C2PMSG_66
848#define MP0_C2PMSG_66__CONTENT__SHIFT 0x0
849#define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
850//MP0_C2PMSG_67
851#define MP0_C2PMSG_67__CONTENT__SHIFT 0x0
852#define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
853//MP0_C2PMSG_68
854#define MP0_C2PMSG_68__CONTENT__SHIFT 0x0
855#define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
856//MP0_C2PMSG_69
857#define MP0_C2PMSG_69__CONTENT__SHIFT 0x0
858#define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
859//MP0_C2PMSG_70
860#define MP0_C2PMSG_70__CONTENT__SHIFT 0x0
861#define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
862//MP0_C2PMSG_71
863#define MP0_C2PMSG_71__CONTENT__SHIFT 0x0
864#define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
865//MP0_C2PMSG_72
866#define MP0_C2PMSG_72__CONTENT__SHIFT 0x0
867#define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
868//MP0_C2PMSG_73
869#define MP0_C2PMSG_73__CONTENT__SHIFT 0x0
870#define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
871//MP0_C2PMSG_74
872#define MP0_C2PMSG_74__CONTENT__SHIFT 0x0
873#define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
874//MP0_C2PMSG_75
875#define MP0_C2PMSG_75__CONTENT__SHIFT 0x0
876#define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
877//MP0_C2PMSG_76
878#define MP0_C2PMSG_76__CONTENT__SHIFT 0x0
879#define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
880//MP0_C2PMSG_77
881#define MP0_C2PMSG_77__CONTENT__SHIFT 0x0
882#define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
883//MP0_C2PMSG_78
884#define MP0_C2PMSG_78__CONTENT__SHIFT 0x0
885#define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
886//MP0_C2PMSG_79
887#define MP0_C2PMSG_79__CONTENT__SHIFT 0x0
888#define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
889//MP0_C2PMSG_80
890#define MP0_C2PMSG_80__CONTENT__SHIFT 0x0
891#define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
892//MP0_C2PMSG_81
893#define MP0_C2PMSG_81__CONTENT__SHIFT 0x0
894#define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
895//MP0_C2PMSG_82
896#define MP0_C2PMSG_82__CONTENT__SHIFT 0x0
897#define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
898//MP0_C2PMSG_83
899#define MP0_C2PMSG_83__CONTENT__SHIFT 0x0
900#define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
901//MP0_C2PMSG_84
902#define MP0_C2PMSG_84__CONTENT__SHIFT 0x0
903#define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
904//MP0_C2PMSG_85
905#define MP0_C2PMSG_85__CONTENT__SHIFT 0x0
906#define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
907//MP0_C2PMSG_86
908#define MP0_C2PMSG_86__CONTENT__SHIFT 0x0
909#define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
910//MP0_C2PMSG_87
911#define MP0_C2PMSG_87__CONTENT__SHIFT 0x0
912#define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
913//MP0_C2PMSG_88
914#define MP0_C2PMSG_88__CONTENT__SHIFT 0x0
915#define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
916//MP0_C2PMSG_89
917#define MP0_C2PMSG_89__CONTENT__SHIFT 0x0
918#define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
919//MP0_C2PMSG_90
920#define MP0_C2PMSG_90__CONTENT__SHIFT 0x0
921#define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
922//MP0_C2PMSG_91
923#define MP0_C2PMSG_91__CONTENT__SHIFT 0x0
924#define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
925//MP0_C2PMSG_92
926#define MP0_C2PMSG_92__CONTENT__SHIFT 0x0
927#define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
928//MP0_C2PMSG_93
929#define MP0_C2PMSG_93__CONTENT__SHIFT 0x0
930#define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
931//MP0_C2PMSG_94
932#define MP0_C2PMSG_94__CONTENT__SHIFT 0x0
933#define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
934//MP0_C2PMSG_95
935#define MP0_C2PMSG_95__CONTENT__SHIFT 0x0
936#define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
937//MP0_C2PMSG_96
938#define MP0_C2PMSG_96__CONTENT__SHIFT 0x0
939#define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
940//MP0_C2PMSG_97
941#define MP0_C2PMSG_97__CONTENT__SHIFT 0x0
942#define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
943//MP0_C2PMSG_98
944#define MP0_C2PMSG_98__CONTENT__SHIFT 0x0
945#define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
946//MP0_C2PMSG_99
947#define MP0_C2PMSG_99__CONTENT__SHIFT 0x0
948#define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
949//MP0_C2PMSG_100
950#define MP0_C2PMSG_100__CONTENT__SHIFT 0x0
951#define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
952//MP0_C2PMSG_101
953#define MP0_C2PMSG_101__CONTENT__SHIFT 0x0
954#define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
955//MP0_C2PMSG_102
956#define MP0_C2PMSG_102__CONTENT__SHIFT 0x0
957#define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
958//MP0_C2PMSG_103
959#define MP0_C2PMSG_103__CONTENT__SHIFT 0x0
960#define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
961//MP0_ACTIVE_FCN_ID
962#define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
963#define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
964#define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
965#define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
966//MP0_IH_CREDIT
967#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
968#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10
969#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
970#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
971//MP0_IH_SW_INT
972#define MP0_IH_SW_INT__ID__SHIFT 0x0
973#define MP0_IH_SW_INT__VALID__SHIFT 0x8
974#define MP0_IH_SW_INT__ID_MASK 0x000000FFL
975#define MP0_IH_SW_INT__VALID_MASK 0x00000100L
976//MP0_IH_SW_INT_CTRL
977#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
978#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
979#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
980#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
981
982
983//CGTT_DRM_CLK_CTRL0
984#define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
985#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
986#define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc
987#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15
988#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16
989#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
990#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
991#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
992#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
993#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
994#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
995#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
996#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
997#define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
998#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
999#define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L
1000#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L
1001#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L
1002#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
1003#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
1004#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
1005#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
1006#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
1007#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
1008#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
1009#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
1010//DRM_LIGHT_SLEEP_CTRL
1011#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0
1012#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L
1013
1014
1015// addressBlock: mp_SmuMp1Pub_CruDec
1016//MP1_SMN_PUB_CTRL
1017#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0
1018#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L
1019//MP1_FIRMWARE_FLAGS
1020#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
1021#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
1022#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
1023#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
1024//MP1_PUB_SCRATCH0
1025#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0
1026#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
1027//MP1_PUB_SCRATCH1
1028#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0
1029#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
1030//MP1_PUB_SCRATCH2
1031#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0
1032#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
1033//MP1_PUB_SCRATCH3
1034#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0
1035#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
1036//MP1_C2PMSG_0
1037#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0
1038#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
1039//MP1_C2PMSG_1
1040#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0
1041#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
1042//MP1_C2PMSG_2
1043#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0
1044#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
1045//MP1_C2PMSG_3
1046#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0
1047#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
1048//MP1_C2PMSG_4
1049#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0
1050#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
1051//MP1_C2PMSG_5
1052#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0
1053#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
1054//MP1_C2PMSG_6
1055#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0
1056#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
1057//MP1_C2PMSG_7
1058#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0
1059#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
1060//MP1_C2PMSG_8
1061#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0
1062#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
1063//MP1_C2PMSG_9
1064#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0
1065#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
1066//MP1_C2PMSG_10
1067#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0
1068#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
1069//MP1_C2PMSG_11
1070#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0
1071#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
1072//MP1_C2PMSG_12
1073#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0
1074#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
1075//MP1_C2PMSG_13
1076#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0
1077#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
1078//MP1_C2PMSG_14
1079#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0
1080#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
1081//MP1_C2PMSG_15
1082#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0
1083#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
1084//MP1_C2PMSG_16
1085#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0
1086#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
1087//MP1_C2PMSG_17
1088#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0
1089#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
1090//MP1_C2PMSG_18
1091#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0
1092#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
1093//MP1_C2PMSG_19
1094#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0
1095#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
1096//MP1_C2PMSG_20
1097#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0
1098#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
1099//MP1_C2PMSG_21
1100#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0
1101#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
1102//MP1_C2PMSG_22
1103#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0
1104#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
1105//MP1_C2PMSG_23
1106#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0
1107#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
1108//MP1_C2PMSG_24
1109#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0
1110#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
1111//MP1_C2PMSG_25
1112#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0
1113#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
1114//MP1_C2PMSG_26
1115#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0
1116#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
1117//MP1_C2PMSG_27
1118#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0
1119#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
1120//MP1_C2PMSG_28
1121#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0
1122#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
1123//MP1_C2PMSG_29
1124#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0
1125#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
1126//MP1_C2PMSG_30
1127#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0
1128#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
1129//MP1_C2PMSG_31
1130#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0
1131#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
1132//MP1_P2CMSG_0
1133#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0
1134#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
1135//MP1_P2CMSG_1
1136#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0
1137#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
1138//MP1_P2CMSG_2
1139#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0
1140#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
1141//MP1_P2CMSG_3
1142#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0
1143#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
1144//MP1_P2CMSG_INTEN
1145#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0
1146#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
1147//MP1_P2CMSG_INTSTS
1148#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
1149#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
1150#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
1151#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
1152#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
1153#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
1154#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
1155#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
1156//MP1_P2SMSG_0
1157#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0
1158#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
1159//MP1_P2SMSG_1
1160#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0
1161#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
1162//MP1_P2SMSG_2
1163#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0
1164#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
1165//MP1_P2SMSG_3
1166#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0
1167#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
1168//MP1_P2SMSG_INTSTS
1169#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
1170#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
1171#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
1172#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
1173#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
1174#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
1175#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
1176#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
1177//MP1_S2PMSG_0
1178#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0
1179#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
1180//MP1_ACP2MP_RESP
1181#define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0
1182#define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
1183//MP1_DC2MP_RESP
1184#define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0
1185#define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
1186//MP1_UVD2MP_RESP
1187#define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0
1188#define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
1189//MP1_VCE2MP_RESP
1190#define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0
1191#define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
1192//MP1_RLC2MP_RESP
1193#define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0
1194#define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL
1195//MP1_C2PMSG_32
1196#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0
1197#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
1198//MP1_C2PMSG_33
1199#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0
1200#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
1201//MP1_C2PMSG_34
1202#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0
1203#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
1204//MP1_C2PMSG_35
1205#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0
1206#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
1207//MP1_C2PMSG_36
1208#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0
1209#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
1210//MP1_C2PMSG_37
1211#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0
1212#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
1213//MP1_C2PMSG_38
1214#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0
1215#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
1216//MP1_C2PMSG_39
1217#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0
1218#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
1219//MP1_C2PMSG_40
1220#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0
1221#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
1222//MP1_C2PMSG_41
1223#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0
1224#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
1225//MP1_C2PMSG_42
1226#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0
1227#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
1228//MP1_C2PMSG_43
1229#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0
1230#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
1231//MP1_C2PMSG_44
1232#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0
1233#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
1234//MP1_C2PMSG_45
1235#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0
1236#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
1237//MP1_C2PMSG_46
1238#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0
1239#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
1240//MP1_C2PMSG_47
1241#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0
1242#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
1243//MP1_C2PMSG_48
1244#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0
1245#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
1246//MP1_C2PMSG_49
1247#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0
1248#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
1249//MP1_C2PMSG_50
1250#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0
1251#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
1252//MP1_C2PMSG_51
1253#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0
1254#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
1255//MP1_C2PMSG_52
1256#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0
1257#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
1258//MP1_C2PMSG_53
1259#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0
1260#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
1261//MP1_C2PMSG_54
1262#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0
1263#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
1264//MP1_C2PMSG_55
1265#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0
1266#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
1267//MP1_C2PMSG_56
1268#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0
1269#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
1270//MP1_C2PMSG_57
1271#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0
1272#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
1273//MP1_C2PMSG_58
1274#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0
1275#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
1276//MP1_C2PMSG_59
1277#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0
1278#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
1279//MP1_C2PMSG_60
1280#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0
1281#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
1282//MP1_C2PMSG_61
1283#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0
1284#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
1285//MP1_C2PMSG_62
1286#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0
1287#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
1288//MP1_C2PMSG_63
1289#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0
1290#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
1291//MP1_C2PMSG_64
1292#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0
1293#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
1294//MP1_C2PMSG_65
1295#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0
1296#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
1297//MP1_C2PMSG_66
1298#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0
1299#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
1300//MP1_C2PMSG_67
1301#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0
1302#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
1303//MP1_C2PMSG_68
1304#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0
1305#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
1306//MP1_C2PMSG_69
1307#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0
1308#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
1309//MP1_C2PMSG_70
1310#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0
1311#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
1312//MP1_C2PMSG_71
1313#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0
1314#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
1315//MP1_C2PMSG_72
1316#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0
1317#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
1318//MP1_C2PMSG_73
1319#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0
1320#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
1321//MP1_C2PMSG_74
1322#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0
1323#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
1324//MP1_C2PMSG_75
1325#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0
1326#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
1327//MP1_C2PMSG_76
1328#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0
1329#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
1330//MP1_C2PMSG_77
1331#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0
1332#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
1333//MP1_C2PMSG_78
1334#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0
1335#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
1336//MP1_C2PMSG_79
1337#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0
1338#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
1339//MP1_C2PMSG_80
1340#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0
1341#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
1342//MP1_C2PMSG_81
1343#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0
1344#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
1345//MP1_C2PMSG_82
1346#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0
1347#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
1348//MP1_C2PMSG_83
1349#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0
1350#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
1351//MP1_C2PMSG_84
1352#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0
1353#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
1354//MP1_C2PMSG_85
1355#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0
1356#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
1357//MP1_C2PMSG_86
1358#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0
1359#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
1360//MP1_C2PMSG_87
1361#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0
1362#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
1363//MP1_C2PMSG_88
1364#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0
1365#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
1366//MP1_C2PMSG_89
1367#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0
1368#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
1369//MP1_C2PMSG_90
1370#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0
1371#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
1372//MP1_C2PMSG_91
1373#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0
1374#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
1375//MP1_C2PMSG_92
1376#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0
1377#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
1378//MP1_C2PMSG_93
1379#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0
1380#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
1381//MP1_C2PMSG_94
1382#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0
1383#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
1384//MP1_C2PMSG_95
1385#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0
1386#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
1387//MP1_C2PMSG_96
1388#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0
1389#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
1390//MP1_C2PMSG_97
1391#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0
1392#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
1393//MP1_C2PMSG_98
1394#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0
1395#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
1396//MP1_C2PMSG_99
1397#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0
1398#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
1399//MP1_C2PMSG_100
1400#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0
1401#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
1402//MP1_C2PMSG_101
1403#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0
1404#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
1405//MP1_C2PMSG_102
1406#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0
1407#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
1408//MP1_C2PMSG_103
1409#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0
1410#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
1411//MP1_ACTIVE_FCN_ID
1412#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
1413#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
1414#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
1415#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
1416//MP1_IH_CREDIT
1417#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
1418#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10
1419#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
1420#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
1421//MP1_IH_SW_INT
1422#define MP1_IH_SW_INT__ID__SHIFT 0x0
1423#define MP1_IH_SW_INT__VALID__SHIFT 0x8
1424#define MP1_IH_SW_INT__ID_MASK 0x000000FFL
1425#define MP1_IH_SW_INT__VALID_MASK 0x00000100L
1426//MP1_IH_SW_INT_CTRL
1427#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
1428#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
1429#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
1430#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
1431//MP1_FPS_CNT
1432#define MP1_FPS_CNT__COUNT__SHIFT 0x0
1433#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
1434//MP1_PUB_CTRL
1435#define MP1_PUB_CTRL__RESET__SHIFT 0x0
1436#define MP1_PUB_CTRL__RESET_MASK 0x00000001L
1437//MP1_EXT_SCRATCH0
1438#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0
1439#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
1440//MP1_EXT_SCRATCH1
1441#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0
1442#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
1443//MP1_EXT_SCRATCH2
1444#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0
1445#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
1446//MP1_EXT_SCRATCH3
1447#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0
1448#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
1449//MP1_EXT_SCRATCH4
1450#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0
1451#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
1452//MP1_EXT_SCRATCH5
1453#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0
1454#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
1455//MP1_EXT_SCRATCH6
1456#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0
1457#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
1458//MP1_EXT_SCRATCH7
1459#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0
1460#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
1461
1462
1463#endif
1464

Warning: This file is not a C or C++ file. It does not have highlighting.

source code of linux/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h