| 1 | /* |
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| 2 | * UVD_5_0 Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included |
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| 14 | * in all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef UVD_5_0_D_H |
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| 25 | #define UVD_5_0_D_H |
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| 26 | |
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| 27 | #define mmUVD_SEMA_ADDR_LOW 0x3bc0 |
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| 28 | #define mmUVD_SEMA_ADDR_HIGH 0x3bc1 |
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| 29 | #define mmUVD_SEMA_CMD 0x3bc2 |
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| 30 | #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 |
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| 31 | #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 |
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| 32 | #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 |
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| 33 | #define mmUVD_ENGINE_CNTL 0x3bc6 |
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| 34 | #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 |
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| 35 | #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 |
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| 36 | #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 |
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| 37 | #define mmUVD_NO_OP 0x3bff |
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| 38 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 |
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| 39 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 |
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| 40 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67 |
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| 41 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66 |
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| 42 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f |
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| 43 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e |
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| 44 | #define mmUVD_SEMA_CNTL 0x3d00 |
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| 45 | #define mmUVD_LMI_EXT40_ADDR 0x3d26 |
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| 46 | #define mmUVD_CTX_INDEX 0x3d28 |
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| 47 | #define mmUVD_CTX_DATA 0x3d29 |
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| 48 | #define mmUVD_CGC_GATE 0x3d2a |
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| 49 | #define mmUVD_CGC_STATUS 0x3d2b |
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| 50 | #define mmUVD_CGC_CTRL 0x3d2c |
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| 51 | #define mmUVD_CGC_UDEC_STATUS 0x3d2d |
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| 52 | #define mmUVD_LMI_CTRL2 0x3d3d |
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| 53 | #define mmUVD_MASTINT_EN 0x3d40 |
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| 54 | #define mmUVD_LMI_ADDR_EXT 0x3d65 |
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| 55 | #define mmUVD_LMI_CTRL 0x3d66 |
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| 56 | #define mmUVD_LMI_STATUS 0x3d67 |
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| 57 | #define mmUVD_LMI_SWAP_CNTL 0x3d6d |
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| 58 | #define mmUVD_MP_SWAP_CNTL 0x3d6f |
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| 59 | #define mmUVD_MPC_CNTL 0x3d77 |
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| 60 | #define mmUVD_MPC_SET_MUXA0 0x3d79 |
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| 61 | #define mmUVD_MPC_SET_MUXA1 0x3d7a |
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| 62 | #define mmUVD_MPC_SET_MUXB0 0x3d7b |
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| 63 | #define mmUVD_MPC_SET_MUXB1 0x3d7c |
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| 64 | #define mmUVD_MPC_SET_MUX 0x3d7d |
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| 65 | #define mmUVD_MPC_SET_ALU 0x3d7e |
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| 66 | #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 |
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| 67 | #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 |
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| 68 | #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 |
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| 69 | #define mmUVD_VCPU_CACHE_SIZE1 0x3d85 |
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| 70 | #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 |
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| 71 | #define mmUVD_VCPU_CACHE_SIZE2 0x3d87 |
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| 72 | #define mmUVD_VCPU_CNTL 0x3d98 |
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| 73 | #define mmUVD_SOFT_RESET 0x3da0 |
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| 74 | #define mmUVD_LMI_RBC_IB_VMID 0x3da1 |
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| 75 | #define mmUVD_RBC_IB_SIZE 0x3da2 |
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| 76 | #define mmUVD_LMI_RBC_RB_VMID 0x3da3 |
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| 77 | #define mmUVD_RBC_RB_RPTR 0x3da4 |
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| 78 | #define mmUVD_RBC_RB_WPTR 0x3da5 |
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| 79 | #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 |
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| 80 | #define mmUVD_RBC_RB_CNTL 0x3da9 |
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| 81 | #define mmUVD_RBC_RB_RPTR_ADDR 0x3daa |
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| 82 | #define mmUVD_STATUS 0x3daf |
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| 83 | #define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 |
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| 84 | #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1 |
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| 85 | #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2 |
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| 86 | #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 |
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| 87 | #define mmUVD_CONTEXT_ID 0x3dbd |
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| 88 | #define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1 |
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| 89 | #define mmUVD_SUVD_CGC_GATE 0x3be4 |
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| 90 | #define mmUVD_SUVD_CGC_STATUS 0x3be5 |
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| 91 | #define mmUVD_SUVD_CGC_CTRL 0x3be6 |
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| 92 | #define ixUVD_LMI_VMID_INTERNAL 0x99 |
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| 93 | #define ixUVD_LMI_VMID_INTERNAL2 0x9a |
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| 94 | #define ixUVD_LMI_CACHE_CTRL 0x9b |
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| 95 | #define ixUVD_LMI_SWAP_CNTL2 0xaa |
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| 96 | #define ixUVD_LMI_ADDR_EXT2 0xab |
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| 97 | #define ixUVD_CGC_MEM_CTRL 0xc0 |
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| 98 | #define ixUVD_CGC_CTRL2 0xc1 |
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| 99 | #define ixUVD_LMI_VMID_INTERNAL3 0x162 |
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| 100 | #define mmUVD_PGFSM_CONFIG 0x38c0 |
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| 101 | #define mmUVD_PGFSM_READ_TILE1 0x38c2 |
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| 102 | #define mmUVD_PGFSM_READ_TILE2 0x38c3 |
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| 103 | #define mmUVD_POWER_STATUS 0x38c4 |
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| 104 | #define mmUVD_PGFSM_READ_TILE3 0x38c5 |
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| 105 | #define mmUVD_PGFSM_READ_TILE4 0x38c6 |
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| 106 | #define mmUVD_PGFSM_READ_TILE5 0x38c8 |
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| 107 | #define mmUVD_PGFSM_READ_TILE6 0x38ee |
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| 108 | #define mmUVD_PGFSM_READ_TILE7 0x38ef |
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| 109 | #define mmUVD_MIF_CURR_ADDR_CONFIG 0x3992 |
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| 110 | #define mmUVD_MIF_REF_ADDR_CONFIG 0x3993 |
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| 111 | #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5 |
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| 112 | #define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4 |
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| 113 | #define mmUVD_JPEG_ADDR_CONFIG 0x3a1f |
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| 114 | |
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| 115 | #endif /* UVD_5_0_D_H */ |
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| 116 | |
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