| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | |
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| 3 | /* |
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| 4 | * Copyright 2024 Advanced Micro Devices, Inc. All rights reserved. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | */ |
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| 24 | |
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| 25 | #ifndef __IRQSRCS_VCN_5_0_H__ |
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| 26 | #define __IRQSRCS_VCN_5_0_H__ |
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| 27 | |
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| 28 | #define VCN_5_0__SRCID__UVD_TRAP 114 // 0x72 UVD_TRAP |
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| 29 | #define VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE 119 // 0x77 Encoder General Purpose |
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| 30 | #define VCN_5_0__SRCID__UVD_ENC_LOW_LATENCY 120 // 0x78 Encoder Low Latency |
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| 31 | #define VCN_5_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT 124 // 0x7c UVD system message interrupt |
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| 32 | #define VCN_5_0__SRCID__JPEG_ENCODE 151 // 0x97 JRBC Encode interrupt |
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| 33 | #define VCN_5_0__SRCID__JPEG_DECODE 153 // 0x99 JRBC Decode interrupt |
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| 34 | #define VCN_5_0__SRCID__JPEG1_DECODE 149 // 0x95 JRBC1 Decode interrupt |
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| 35 | #define VCN_5_0__SRCID__JPEG2_DECODE 151 // 0x97 JRBC2 Decode interrupt |
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| 36 | #define VCN_5_0__SRCID__JPEG3_DECODE 171 // 0xab JRBC3 Decode interrupt |
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| 37 | #define VCN_5_0__SRCID__JPEG4_DECODE 172 // 0xac JRBC4 Decode interrupt |
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| 38 | #define VCN_5_0__SRCID__JPEG5_DECODE 173 // 0xad JRBC5 Decode interrupt |
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| 39 | #define VCN_5_0__SRCID__JPEG6_DECODE 174 // 0xae JRBC6 Decode interrupt |
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| 40 | #define VCN_5_0__SRCID__JPEG7_DECODE 175 // 0xaf JRBC7 Decode interrupt |
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| 41 | #define VCN_5_0__SRCID__JPEG8_DECODE 177 // 0xb1 JRBC8 Decode interrupt |
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| 42 | #define VCN_5_0__SRCID__JPEG9_DECODE 178 // 0xb2 JRBC9 Decode interrupt |
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| 43 | |
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| 44 | #define VCN_5_0__SRCID_UVD_POISON 160 |
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| 45 | #define VCN_5_0__SRCID_DJPEG0_POISON 161 |
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| 46 | #define VCN_5_0__SRCID_EJPEG0_POISON 162 |
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| 47 | #endif |
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| 48 | |
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