| 1 | /* |
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| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 28 | #ifndef __R600_REG_H__ |
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| 29 | #define __R600_REG_H__ |
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| 30 | |
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| 31 | #define R600_PCIE_PORT_INDEX 0x0038 |
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| 32 | #define R600_PCIE_PORT_DATA 0x003c |
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| 33 | |
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| 34 | #define R600_RCU_INDEX 0x0100 |
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| 35 | #define R600_RCU_DATA 0x0104 |
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| 36 | |
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| 37 | #define R600_UVD_CTX_INDEX 0xf4a0 |
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| 38 | #define R600_UVD_CTX_DATA 0xf4a4 |
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| 39 | |
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| 40 | #define R600_MC_VM_FB_LOCATION 0x2180 |
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| 41 | #define R600_MC_FB_BASE_MASK 0x0000FFFF |
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| 42 | #define R600_MC_FB_BASE_SHIFT 0 |
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| 43 | #define R600_MC_FB_TOP_MASK 0xFFFF0000 |
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| 44 | #define R600_MC_FB_TOP_SHIFT 16 |
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| 45 | #define R600_MC_VM_AGP_TOP 0x2184 |
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| 46 | #define R600_MC_AGP_TOP_MASK 0x0003FFFF |
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| 47 | #define R600_MC_AGP_TOP_SHIFT 0 |
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| 48 | #define R600_MC_VM_AGP_BOT 0x2188 |
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| 49 | #define R600_MC_AGP_BOT_MASK 0x0003FFFF |
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| 50 | #define R600_MC_AGP_BOT_SHIFT 0 |
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| 51 | #define R600_MC_VM_AGP_BASE 0x218c |
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| 52 | #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 |
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| 53 | #define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
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| 54 | #define R600_LOGICAL_PAGE_NUMBER_SHIFT 0 |
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| 55 | #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 |
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| 56 | #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 |
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| 57 | |
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| 58 | #define R700_MC_VM_FB_LOCATION 0x2024 |
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| 59 | #define R700_MC_FB_BASE_MASK 0x0000FFFF |
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| 60 | #define R700_MC_FB_BASE_SHIFT 0 |
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| 61 | #define R700_MC_FB_TOP_MASK 0xFFFF0000 |
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| 62 | #define R700_MC_FB_TOP_SHIFT 16 |
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| 63 | #define R700_MC_VM_AGP_TOP 0x2028 |
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| 64 | #define R700_MC_AGP_TOP_MASK 0x0003FFFF |
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| 65 | #define R700_MC_AGP_TOP_SHIFT 0 |
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| 66 | #define R700_MC_VM_AGP_BOT 0x202c |
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| 67 | #define R700_MC_AGP_BOT_MASK 0x0003FFFF |
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| 68 | #define R700_MC_AGP_BOT_SHIFT 0 |
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| 69 | #define R700_MC_VM_AGP_BASE 0x2030 |
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| 70 | #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 |
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| 71 | #define R700_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
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| 72 | #define R700_LOGICAL_PAGE_NUMBER_SHIFT 0 |
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| 73 | #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 |
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| 74 | #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c |
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| 75 | |
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| 76 | #define R600_RAMCFG 0x2408 |
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| 77 | # define R600_CHANSIZE (1 << 7) |
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| 78 | # define R600_CHANSIZE_OVERRIDE (1 << 10) |
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| 79 | |
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| 80 | |
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| 81 | #define R600_GENERAL_PWRMGT 0x618 |
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| 82 | # define R600_OPEN_DRAIN_PADS (1 << 11) |
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| 83 | |
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| 84 | #define R600_LOWER_GPIO_ENABLE 0x710 |
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| 85 | #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 |
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| 86 | #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c |
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| 87 | #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 |
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| 88 | #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 |
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| 89 | |
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| 90 | #define R600_D1GRPH_SWAP_CONTROL 0x610C |
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| 91 | # define R600_D1GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) |
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| 92 | # define R600_D1GRPH_SWAP_ENDIAN_NONE 0 |
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| 93 | # define R600_D1GRPH_SWAP_ENDIAN_16BIT 1 |
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| 94 | # define R600_D1GRPH_SWAP_ENDIAN_32BIT 2 |
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| 95 | # define R600_D1GRPH_SWAP_ENDIAN_64BIT 3 |
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| 96 | # define R600_D1GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) |
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| 97 | # define R600_D1GRPH_RED_SEL_R 0 |
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| 98 | # define R600_D1GRPH_RED_SEL_G 1 |
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| 99 | # define R600_D1GRPH_RED_SEL_B 2 |
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| 100 | # define R600_D1GRPH_RED_SEL_A 3 |
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| 101 | # define R600_D1GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) |
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| 102 | # define R600_D1GRPH_GREEN_SEL_G 0 |
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| 103 | # define R600_D1GRPH_GREEN_SEL_B 1 |
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| 104 | # define R600_D1GRPH_GREEN_SEL_A 2 |
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| 105 | # define R600_D1GRPH_GREEN_SEL_R 3 |
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| 106 | # define R600_D1GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) |
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| 107 | # define R600_D1GRPH_BLUE_SEL_B 0 |
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| 108 | # define R600_D1GRPH_BLUE_SEL_A 1 |
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| 109 | # define R600_D1GRPH_BLUE_SEL_R 2 |
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| 110 | # define R600_D1GRPH_BLUE_SEL_G 3 |
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| 111 | # define R600_D1GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) |
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| 112 | # define R600_D1GRPH_ALPHA_SEL_A 0 |
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| 113 | # define R600_D1GRPH_ALPHA_SEL_R 1 |
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| 114 | # define R600_D1GRPH_ALPHA_SEL_G 2 |
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| 115 | # define R600_D1GRPH_ALPHA_SEL_B 3 |
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| 116 | |
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| 117 | #define R600_HDP_NONSURFACE_BASE 0x2c04 |
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| 118 | |
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| 119 | #define R600_BUS_CNTL 0x5420 |
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| 120 | # define R600_BIOS_ROM_DIS (1 << 1) |
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| 121 | #define R600_CONFIG_CNTL 0x5424 |
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| 122 | #define R600_CONFIG_MEMSIZE 0x5428 |
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| 123 | #define R600_CONFIG_F0_BASE 0x542C |
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| 124 | #define R600_CONFIG_APER_SIZE 0x5430 |
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| 125 | |
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| 126 | #define R600_BIF_FB_EN 0x5490 |
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| 127 | #define R600_FB_READ_EN (1 << 0) |
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| 128 | #define R600_FB_WRITE_EN (1 << 1) |
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| 129 | |
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| 130 | #define R600_CITF_CNTL 0x200c |
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| 131 | #define R600_BLACKOUT_MASK 0x00000003 |
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| 132 | |
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| 133 | #define R700_MC_CITF_CNTL 0x25c0 |
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| 134 | |
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| 135 | #define R600_ROM_CNTL 0x1600 |
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| 136 | # define R600_SCK_OVERWRITE (1 << 1) |
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| 137 | # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 |
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| 138 | # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) |
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| 139 | |
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| 140 | #define R600_CG_SPLL_FUNC_CNTL 0x600 |
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| 141 | # define R600_SPLL_BYPASS_EN (1 << 3) |
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| 142 | #define R600_CG_SPLL_STATUS 0x60c |
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| 143 | # define R600_SPLL_CHG_STATUS (1 << 1) |
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| 144 | |
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| 145 | #define R600_BIOS_0_SCRATCH 0x1724 |
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| 146 | #define R600_BIOS_1_SCRATCH 0x1728 |
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| 147 | #define R600_BIOS_2_SCRATCH 0x172c |
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| 148 | #define R600_BIOS_3_SCRATCH 0x1730 |
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| 149 | #define R600_BIOS_4_SCRATCH 0x1734 |
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| 150 | #define R600_BIOS_5_SCRATCH 0x1738 |
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| 151 | #define R600_BIOS_6_SCRATCH 0x173c |
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| 152 | #define R600_BIOS_7_SCRATCH 0x1740 |
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| 153 | |
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| 154 | /* Audio, these regs were reverse enginered, |
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| 155 | * so the chance is high that the naming is wrong |
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| 156 | * R6xx+ ??? */ |
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| 157 | |
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| 158 | /* Audio clocks */ |
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| 159 | #define R600_AUDIO_PLL1_MUL 0x0514 |
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| 160 | #define R600_AUDIO_PLL1_DIV 0x0518 |
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| 161 | #define R600_AUDIO_PLL2_MUL 0x0524 |
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| 162 | #define R600_AUDIO_PLL2_DIV 0x0528 |
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| 163 | #define R600_AUDIO_CLK_SRCSEL 0x0534 |
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| 164 | |
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| 165 | /* Audio general */ |
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| 166 | #define R600_AUDIO_ENABLE 0x7300 |
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| 167 | #define R600_AUDIO_TIMING 0x7344 |
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| 168 | |
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| 169 | /* Audio params */ |
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| 170 | #define R600_AUDIO_VENDOR_ID 0x7380 |
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| 171 | #define R600_AUDIO_REVISION_ID 0x7384 |
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| 172 | #define R600_AUDIO_ROOT_NODE_COUNT 0x7388 |
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| 173 | #define R600_AUDIO_NID1_NODE_COUNT 0x738c |
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| 174 | #define R600_AUDIO_NID1_TYPE 0x7390 |
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| 175 | #define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394 |
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| 176 | #define R600_AUDIO_SUPPORTED_CODEC 0x7398 |
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| 177 | #define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c |
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| 178 | #define R600_AUDIO_NID2_CAPS 0x73a0 |
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| 179 | #define R600_AUDIO_NID3_CAPS 0x73a4 |
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| 180 | #define R600_AUDIO_NID3_PIN_CAPS 0x73a8 |
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| 181 | |
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| 182 | /* Audio conn list */ |
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| 183 | #define R600_AUDIO_CONN_LIST_LEN 0x73ac |
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| 184 | #define R600_AUDIO_CONN_LIST 0x73b0 |
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| 185 | |
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| 186 | /* Audio verbs */ |
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| 187 | #define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0 |
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| 188 | #define R600_AUDIO_PLAYING 0x73c4 |
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| 189 | #define R600_AUDIO_IMPLEMENTATION_ID 0x73c8 |
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| 190 | #define R600_AUDIO_CONFIG_DEFAULT 0x73cc |
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| 191 | #define R600_AUDIO_PIN_SENSE 0x73d0 |
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| 192 | #define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4 |
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| 193 | #define R600_AUDIO_STATUS_BITS 0x73d8 |
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| 194 | |
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| 195 | #define DCE2_HDMI_OFFSET0 (0x7400 - 0x7400) |
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| 196 | #define DCE2_HDMI_OFFSET1 (0x7700 - 0x7400) |
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| 197 | /* DCE3.2 second instance starts at 0x7800 */ |
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| 198 | #define DCE3_HDMI_OFFSET0 (0x7400 - 0x7400) |
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| 199 | #define DCE3_HDMI_OFFSET1 (0x7800 - 0x7400) |
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| 200 | |
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| 201 | #endif |
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| 202 | |
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