1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm/display/drm_dp_helper.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_encoder.h>
36#include <drm/drm_fixed.h>
37#include <drm/drm_modeset_helper_vtables.h>
38#include <linux/i2c.h>
39#include <linux/i2c-algo-bit.h>
40
41struct drm_fb_helper;
42struct drm_fb_helper_surface_size;
43
44struct edid;
45struct drm_edid;
46struct radeon_bo;
47struct radeon_device;
48
49#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
50#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
51#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
52
53#define RADEON_MAX_HPD_PINS 7
54#define RADEON_MAX_CRTCS 6
55#define RADEON_MAX_AFMT_BLOCKS 7
56
57enum radeon_rmx_type {
58 RMX_OFF,
59 RMX_FULL,
60 RMX_CENTER,
61 RMX_ASPECT
62};
63
64enum radeon_tv_std {
65 TV_STD_NTSC,
66 TV_STD_PAL,
67 TV_STD_PAL_M,
68 TV_STD_PAL_60,
69 TV_STD_NTSC_J,
70 TV_STD_SCART_PAL,
71 TV_STD_SECAM,
72 TV_STD_PAL_CN,
73 TV_STD_PAL_N,
74};
75
76enum radeon_underscan_type {
77 UNDERSCAN_OFF,
78 UNDERSCAN_ON,
79 UNDERSCAN_AUTO,
80};
81
82enum radeon_hpd_id {
83 RADEON_HPD_1 = 0,
84 RADEON_HPD_2,
85 RADEON_HPD_3,
86 RADEON_HPD_4,
87 RADEON_HPD_5,
88 RADEON_HPD_6,
89 RADEON_HPD_NONE = 0xff,
90};
91
92enum radeon_output_csc {
93 RADEON_OUTPUT_CSC_BYPASS = 0,
94 RADEON_OUTPUT_CSC_TVRGB = 1,
95 RADEON_OUTPUT_CSC_YCBCR601 = 2,
96 RADEON_OUTPUT_CSC_YCBCR709 = 3,
97};
98
99#define RADEON_MAX_I2C_BUS 16
100
101/* radeon gpio-based i2c
102 * 1. "mask" reg and bits
103 * grabs the gpio pins for software use
104 * 0=not held 1=held
105 * 2. "a" reg and bits
106 * output pin value
107 * 0=low 1=high
108 * 3. "en" reg and bits
109 * sets the pin direction
110 * 0=input 1=output
111 * 4. "y" reg and bits
112 * input pin value
113 * 0=low 1=high
114 */
115struct radeon_i2c_bus_rec {
116 bool valid;
117 /* id used by atom */
118 uint8_t i2c_id;
119 /* id used by atom */
120 enum radeon_hpd_id hpd;
121 /* can be used with hw i2c engine */
122 bool hw_capable;
123 /* uses multi-media i2c engine */
124 bool mm_i2c;
125 /* regs and bits */
126 uint32_t mask_clk_reg;
127 uint32_t mask_data_reg;
128 uint32_t a_clk_reg;
129 uint32_t a_data_reg;
130 uint32_t en_clk_reg;
131 uint32_t en_data_reg;
132 uint32_t y_clk_reg;
133 uint32_t y_data_reg;
134 uint32_t mask_clk_mask;
135 uint32_t mask_data_mask;
136 uint32_t a_clk_mask;
137 uint32_t a_data_mask;
138 uint32_t en_clk_mask;
139 uint32_t en_data_mask;
140 uint32_t y_clk_mask;
141 uint32_t y_data_mask;
142};
143
144struct radeon_tmds_pll {
145 uint32_t freq;
146 uint32_t value;
147};
148
149#define RADEON_MAX_BIOS_CONNECTOR 16
150
151/* pll flags */
152#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
153#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
154#define RADEON_PLL_USE_REF_DIV (1 << 2)
155#define RADEON_PLL_LEGACY (1 << 3)
156#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
157#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
158#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
159#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
160#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
161#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
162#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
163#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
164#define RADEON_PLL_USE_POST_DIV (1 << 12)
165#define RADEON_PLL_IS_LCD (1 << 13)
166#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
167
168struct radeon_pll {
169 /* reference frequency */
170 uint32_t reference_freq;
171
172 /* fixed dividers */
173 uint32_t reference_div;
174 uint32_t post_div;
175
176 /* pll in/out limits */
177 uint32_t pll_in_min;
178 uint32_t pll_in_max;
179 uint32_t pll_out_min;
180 uint32_t pll_out_max;
181 uint32_t lcd_pll_out_min;
182 uint32_t lcd_pll_out_max;
183 uint32_t best_vco;
184
185 /* divider limits */
186 uint32_t min_ref_div;
187 uint32_t max_ref_div;
188 uint32_t min_post_div;
189 uint32_t max_post_div;
190 uint32_t min_feedback_div;
191 uint32_t max_feedback_div;
192 uint32_t min_frac_feedback_div;
193 uint32_t max_frac_feedback_div;
194
195 /* flags for the current clock */
196 uint32_t flags;
197
198 /* pll id */
199 uint32_t id;
200};
201
202struct radeon_i2c_chan {
203 struct i2c_adapter adapter;
204 struct drm_device *dev;
205 struct i2c_algo_bit_data bit;
206 struct radeon_i2c_bus_rec rec;
207 struct drm_dp_aux aux;
208 bool has_aux;
209 struct mutex mutex;
210};
211
212/* mostly for macs, but really any system without connector tables */
213enum radeon_connector_table {
214 CT_NONE = 0,
215 CT_GENERIC,
216 CT_IBOOK,
217 CT_POWERBOOK_EXTERNAL,
218 CT_POWERBOOK_INTERNAL,
219 CT_POWERBOOK_VGA,
220 CT_MINI_EXTERNAL,
221 CT_MINI_INTERNAL,
222 CT_IMAC_G5_ISIGHT,
223 CT_EMAC,
224 CT_RN50_POWER,
225 CT_MAC_X800,
226 CT_MAC_G5_9600,
227 CT_SAM440EP,
228 CT_MAC_G4_SILVER
229};
230
231enum radeon_dvo_chip {
232 DVO_SIL164,
233 DVO_SIL1178,
234};
235
236struct radeon_afmt {
237 bool enabled;
238 int offset;
239 bool last_buffer_filled_status;
240 int id;
241};
242
243struct radeon_mode_info {
244 struct atom_context *atom_context;
245 struct card_info *atom_card_info;
246 enum radeon_connector_table connector_table;
247 bool mode_config_initialized;
248 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
249 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
250 /* DVI-I properties */
251 struct drm_property *coherent_mode_property;
252 /* DAC enable load detect */
253 struct drm_property *load_detect_property;
254 /* TV standard */
255 struct drm_property *tv_std_property;
256 /* legacy TMDS PLL detect */
257 struct drm_property *tmds_pll_property;
258 /* underscan */
259 struct drm_property *underscan_property;
260 struct drm_property *underscan_hborder_property;
261 struct drm_property *underscan_vborder_property;
262 /* audio */
263 struct drm_property *audio_property;
264 /* FMT dithering */
265 struct drm_property *dither_property;
266 /* Output CSC */
267 struct drm_property *output_csc_property;
268 /* hardcoded DFP edid from BIOS */
269 const struct drm_edid *bios_hardcoded_edid;
270
271 /* firmware flags */
272 u16 firmware_flags;
273 /* pointer to backlight encoder */
274 struct radeon_encoder *bl_encoder;
275
276 /* bitmask for active encoder frontends */
277 uint32_t active_encoders;
278};
279
280#define RADEON_MAX_BL_LEVEL 0xFF
281
282struct radeon_backlight_privdata {
283 struct radeon_encoder *encoder;
284 uint8_t negative;
285};
286
287#define MAX_H_CODE_TIMING_LEN 32
288#define MAX_V_CODE_TIMING_LEN 32
289
290/* need to store these as reading
291 back code tables is excessive */
292struct radeon_tv_regs {
293 uint32_t tv_uv_adr;
294 uint32_t timing_cntl;
295 uint32_t hrestart;
296 uint32_t vrestart;
297 uint32_t frestart;
298 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
299 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
300};
301
302struct radeon_atom_ss {
303 uint16_t percentage;
304 uint16_t percentage_divider;
305 uint8_t type;
306 uint16_t step;
307 uint8_t delay;
308 uint8_t range;
309 uint8_t refdiv;
310 /* asic_ss */
311 uint16_t rate;
312 uint16_t amount;
313};
314
315enum radeon_flip_status {
316 RADEON_FLIP_NONE,
317 RADEON_FLIP_PENDING,
318 RADEON_FLIP_SUBMITTED
319};
320
321struct radeon_crtc {
322 struct drm_crtc base;
323 int crtc_id;
324 bool enabled;
325 bool can_tile;
326 bool cursor_out_of_bounds;
327 uint32_t crtc_offset;
328 struct drm_gem_object *cursor_bo;
329 uint64_t cursor_addr;
330 int cursor_x;
331 int cursor_y;
332 int cursor_hot_x;
333 int cursor_hot_y;
334 int cursor_width;
335 int cursor_height;
336 int max_cursor_width;
337 int max_cursor_height;
338 uint32_t legacy_display_base_addr;
339 enum radeon_rmx_type rmx_type;
340 u8 h_border;
341 u8 v_border;
342 fixed20_12 vsc;
343 fixed20_12 hsc;
344 struct drm_display_mode native_mode;
345 int pll_id;
346 /* page flipping */
347 struct workqueue_struct *flip_queue;
348 struct radeon_flip_work *flip_work;
349 enum radeon_flip_status flip_status;
350 /* pll sharing */
351 struct radeon_atom_ss ss;
352 bool ss_enabled;
353 u32 adjusted_clock;
354 int bpc;
355 u32 pll_reference_div;
356 u32 pll_post_div;
357 u32 pll_flags;
358 struct drm_encoder *encoder;
359 struct drm_connector *connector;
360 /* for dpm */
361 u32 line_time;
362 u32 wm_low;
363 u32 wm_high;
364 u32 lb_vblank_lead_lines;
365 struct drm_display_mode hw_mode;
366 enum radeon_output_csc output_csc;
367};
368
369struct radeon_encoder_primary_dac {
370 /* legacy primary dac */
371 uint32_t ps2_pdac_adj;
372};
373
374struct radeon_encoder_lvds {
375 /* legacy lvds */
376 uint16_t panel_vcc_delay;
377 uint8_t panel_pwr_delay;
378 uint8_t panel_digon_delay;
379 uint8_t panel_blon_delay;
380 uint16_t panel_ref_divider;
381 uint8_t panel_post_divider;
382 uint16_t panel_fb_divider;
383 bool use_bios_dividers;
384 uint32_t lvds_gen_cntl;
385 /* panel mode */
386 struct drm_display_mode native_mode;
387 struct backlight_device *bl_dev;
388 int dpms_mode;
389 uint8_t backlight_level;
390};
391
392struct radeon_encoder_tv_dac {
393 /* legacy tv dac */
394 uint32_t ps2_tvdac_adj;
395 uint32_t ntsc_tvdac_adj;
396 uint32_t pal_tvdac_adj;
397
398 int h_pos;
399 int v_pos;
400 int h_size;
401 int supported_tv_stds;
402 bool tv_on;
403 enum radeon_tv_std tv_std;
404 struct radeon_tv_regs tv;
405};
406
407struct radeon_encoder_int_tmds {
408 /* legacy int tmds */
409 struct radeon_tmds_pll tmds_pll[4];
410};
411
412struct radeon_encoder_ext_tmds {
413 /* tmds over dvo */
414 struct radeon_i2c_chan *i2c_bus;
415 uint8_t slave_addr;
416 enum radeon_dvo_chip dvo_chip;
417};
418
419/* spread spectrum */
420struct radeon_encoder_atom_dig {
421 bool linkb;
422 /* atom dig */
423 bool coherent_mode;
424 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
425 /* atom lvds/edp */
426 uint32_t lcd_misc;
427 uint16_t panel_pwr_delay;
428 uint32_t lcd_ss_id;
429 /* panel mode */
430 struct drm_display_mode native_mode;
431 struct backlight_device *bl_dev;
432 int dpms_mode;
433 uint8_t backlight_level;
434 int panel_mode;
435 struct radeon_afmt *afmt;
436 struct r600_audio_pin *pin;
437};
438
439struct radeon_encoder_atom_dac {
440 enum radeon_tv_std tv_std;
441};
442
443struct radeon_encoder {
444 struct drm_encoder base;
445 uint32_t encoder_enum;
446 uint32_t encoder_id;
447 uint32_t devices;
448 uint32_t active_device;
449 uint32_t flags;
450 uint32_t pixel_clock;
451 enum radeon_rmx_type rmx_type;
452 enum radeon_underscan_type underscan_type;
453 uint32_t underscan_hborder;
454 uint32_t underscan_vborder;
455 struct drm_display_mode native_mode;
456 void *enc_priv;
457 int audio_polling_active;
458 bool is_ext_encoder;
459 u16 caps;
460 struct radeon_audio_funcs *audio;
461 enum radeon_output_csc output_csc;
462 bool can_mst;
463 uint32_t offset;
464};
465
466struct radeon_connector_atom_dig {
467 uint32_t igp_lane_info;
468 /* displayport */
469 u8 dpcd[DP_RECEIVER_CAP_SIZE];
470 u8 dp_sink_type;
471 int dp_clock;
472 int dp_lane_count;
473 bool edp_on;
474};
475
476struct radeon_gpio_rec {
477 bool valid;
478 u8 id;
479 u32 reg;
480 u32 mask;
481 u32 shift;
482};
483
484struct radeon_hpd {
485 enum radeon_hpd_id hpd;
486 u8 plugged_state;
487 struct radeon_gpio_rec gpio;
488};
489
490struct radeon_router {
491 u32 router_id;
492 struct radeon_i2c_bus_rec i2c_info;
493 u8 i2c_addr;
494 /* i2c mux */
495 bool ddc_valid;
496 u8 ddc_mux_type;
497 u8 ddc_mux_control_pin;
498 u8 ddc_mux_state;
499 /* clock/data mux */
500 bool cd_valid;
501 u8 cd_mux_type;
502 u8 cd_mux_control_pin;
503 u8 cd_mux_state;
504};
505
506enum radeon_connector_audio {
507 RADEON_AUDIO_DISABLE = 0,
508 RADEON_AUDIO_ENABLE = 1,
509 RADEON_AUDIO_AUTO = 2
510};
511
512enum radeon_connector_dither {
513 RADEON_FMT_DITHER_DISABLE = 0,
514 RADEON_FMT_DITHER_ENABLE = 1,
515};
516
517struct radeon_connector {
518 struct drm_connector base;
519 uint32_t connector_id;
520 uint32_t devices;
521 struct radeon_i2c_chan *ddc_bus;
522 /* some systems have an hdmi and vga port with a shared ddc line */
523 bool shared_ddc;
524 bool use_digital;
525 /* we need to mind the EDID between detect
526 and get modes due to analog/digital/tvencoder */
527 struct edid *edid;
528 void *con_priv;
529 bool dac_load_detect;
530 bool detected_by_load; /* if the connection status was determined by load */
531 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
532 uint16_t connector_object_id;
533 struct radeon_hpd hpd;
534 struct radeon_router router;
535 struct radeon_i2c_chan *router_bus;
536 enum radeon_connector_audio audio;
537 enum radeon_connector_dither dither;
538 int pixelclock_for_modeset;
539};
540
541#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
542 ((em) == ATOM_ENCODER_MODE_DP_MST))
543
544struct atom_clock_dividers {
545 u32 post_div;
546 union {
547 struct {
548#ifdef __BIG_ENDIAN
549 u32 reserved : 6;
550 u32 whole_fb_div : 12;
551 u32 frac_fb_div : 14;
552#else
553 u32 frac_fb_div : 14;
554 u32 whole_fb_div : 12;
555 u32 reserved : 6;
556#endif
557 };
558 u32 fb_div;
559 };
560 u32 ref_div;
561 bool enable_post_div;
562 bool enable_dithen;
563 u32 vco_mode;
564 u32 real_clock;
565 /* added for CI */
566 u32 post_divider;
567 u32 flags;
568};
569
570struct atom_mpll_param {
571 union {
572 struct {
573#ifdef __BIG_ENDIAN
574 u32 reserved : 8;
575 u32 clkfrac : 12;
576 u32 clkf : 12;
577#else
578 u32 clkf : 12;
579 u32 clkfrac : 12;
580 u32 reserved : 8;
581#endif
582 };
583 u32 fb_div;
584 };
585 u32 post_div;
586 u32 bwcntl;
587 u32 dll_speed;
588 u32 vco_mode;
589 u32 yclk_sel;
590 u32 qdr;
591 u32 half_rate;
592};
593
594#define MEM_TYPE_GDDR5 0x50
595#define MEM_TYPE_GDDR4 0x40
596#define MEM_TYPE_GDDR3 0x30
597#define MEM_TYPE_DDR2 0x20
598#define MEM_TYPE_GDDR1 0x10
599#define MEM_TYPE_DDR3 0xb0
600#define MEM_TYPE_MASK 0xf0
601
602struct atom_memory_info {
603 u8 mem_vendor;
604 u8 mem_type;
605};
606
607#define MAX_AC_TIMING_ENTRIES 16
608
609struct atom_memory_clock_range_table {
610 u8 num_entries;
611 u8 rsv[3];
612 u32 mclk[MAX_AC_TIMING_ENTRIES];
613};
614
615#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
616#define VBIOS_MAX_AC_TIMING_ENTRIES 20
617
618struct atom_mc_reg_entry {
619 u32 mclk_max;
620 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
621};
622
623struct atom_mc_register_address {
624 u16 s1;
625 u8 pre_reg_data;
626};
627
628struct atom_mc_reg_table {
629 u8 last;
630 u8 num_entries;
631 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
632 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
633};
634
635#define MAX_VOLTAGE_ENTRIES 32
636
637struct atom_voltage_table_entry {
638 u16 value;
639 u32 smio_low;
640};
641
642struct atom_voltage_table {
643 u32 count;
644 u32 mask_low;
645 u32 phase_delay;
646 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
647};
648
649/* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
650#define DRM_SCANOUTPOS_VALID (1 << 0)
651#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
652#define DRM_SCANOUTPOS_ACCURATE (1 << 2)
653#define USE_REAL_VBLANKSTART (1 << 30)
654#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
655
656extern void
657radeon_add_atom_connector(struct drm_device *dev,
658 uint32_t connector_id,
659 uint32_t supported_device,
660 int connector_type,
661 struct radeon_i2c_bus_rec *i2c_bus,
662 uint32_t igp_lane_info,
663 uint16_t connector_object_id,
664 struct radeon_hpd *hpd,
665 struct radeon_router *router);
666extern void
667radeon_add_legacy_connector(struct drm_device *dev,
668 uint32_t connector_id,
669 uint32_t supported_device,
670 int connector_type,
671 struct radeon_i2c_bus_rec *i2c_bus,
672 uint16_t connector_object_id,
673 struct radeon_hpd *hpd);
674extern uint32_t
675radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
676 uint8_t dac);
677extern void radeon_link_encoder_connector(struct drm_device *dev);
678
679extern enum radeon_tv_std
680radeon_combios_get_tv_info(struct radeon_device *rdev);
681extern enum radeon_tv_std
682radeon_atombios_get_tv_info(struct radeon_device *rdev);
683extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
684 u16 *vddc, u16 *vddci, u16 *mvdd);
685
686extern void
687radeon_combios_connected_scratch_regs(struct drm_connector *connector,
688 struct drm_encoder *encoder,
689 bool connected);
690extern void
691radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
692 struct drm_encoder *encoder,
693 bool connected);
694
695extern struct drm_connector *
696radeon_get_connector_for_encoder(struct drm_encoder *encoder);
697extern struct drm_connector *
698radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
699extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
700 u32 pixel_clock);
701
702extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
703extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
704extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
705extern int radeon_get_monitor_bpc(struct drm_connector *connector);
706
707extern void radeon_connector_hotplug(struct drm_connector *connector);
708extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
709 const struct drm_display_mode *mode);
710extern void radeon_dp_set_link_config(struct drm_connector *connector,
711 const struct drm_display_mode *mode);
712extern void radeon_dp_link_train(struct drm_encoder *encoder,
713 struct drm_connector *connector);
714extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
715extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
716extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
717extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
718 struct drm_connector *connector);
719extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
720 u8 power_state);
721extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
722extern ssize_t
723radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
724
725extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
726extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
727extern void radeon_atom_encoder_init(struct radeon_device *rdev);
728extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
729extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
730 int action, uint8_t lane_num,
731 uint8_t lane_set);
732extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
733 int action, uint8_t lane_num,
734 uint8_t lane_set, int fe);
735extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
736extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
737void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
738
739extern void radeon_i2c_init(struct radeon_device *rdev);
740extern void radeon_i2c_fini(struct radeon_device *rdev);
741extern void radeon_combios_i2c_init(struct radeon_device *rdev);
742extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
743extern void radeon_i2c_add(struct radeon_device *rdev,
744 struct radeon_i2c_bus_rec *rec,
745 const char *name);
746extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
747 struct radeon_i2c_bus_rec *i2c_bus);
748extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
749 struct radeon_i2c_bus_rec *rec,
750 const char *name);
751extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
752extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
753 u8 slave_addr,
754 u8 addr,
755 u8 *val);
756extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
757 u8 slave_addr,
758 u8 addr,
759 u8 val);
760extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
761extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
762extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
763
764extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
765 struct radeon_atom_ss *ss,
766 int id);
767extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
768 struct radeon_atom_ss *ss,
769 int id, u32 clock);
770extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
771 u8 id);
772
773extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
774 uint64_t freq,
775 uint32_t *dot_clock_p,
776 uint32_t *fb_div_p,
777 uint32_t *frac_fb_div_p,
778 uint32_t *ref_div_p,
779 uint32_t *post_div_p);
780
781extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
782 u32 freq,
783 u32 *dot_clock_p,
784 u32 *fb_div_p,
785 u32 *frac_fb_div_p,
786 u32 *ref_div_p,
787 u32 *post_div_p);
788
789extern void radeon_setup_encoder_clones(struct drm_device *dev);
790
791struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
792struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
793struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
794struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
795struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
796extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
797extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
798extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
799extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
800extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
801extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
802
803extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
804extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
805 struct drm_framebuffer *old_fb);
806extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
807 struct drm_framebuffer *fb,
808 int x, int y,
809 enum mode_set_atomic state);
810extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
811 struct drm_display_mode *mode,
812 struct drm_display_mode *adjusted_mode,
813 int x, int y,
814 struct drm_framebuffer *old_fb);
815extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
816
817extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
818 struct drm_framebuffer *old_fb);
819extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
820 struct drm_framebuffer *fb,
821 int x, int y,
822 enum mode_set_atomic state);
823extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
824 struct drm_framebuffer *fb,
825 int x, int y, int atomic);
826extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
827 struct drm_file *file_priv,
828 uint32_t handle,
829 uint32_t width,
830 uint32_t height,
831 int32_t hot_x,
832 int32_t hot_y);
833extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
834 int x, int y);
835extern void radeon_cursor_reset(struct drm_crtc *crtc);
836
837extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
838 unsigned int flags, int *vpos, int *hpos,
839 ktime_t *stime, ktime_t *etime,
840 const struct drm_display_mode *mode);
841
842extern bool
843radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq,
844 int *vpos, int *hpos,
845 ktime_t *stime, ktime_t *etime,
846 const struct drm_display_mode *mode);
847
848extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
849extern struct edid *
850radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
851extern bool radeon_atom_get_clock_info(struct drm_device *dev);
852extern bool radeon_combios_get_clock_info(struct drm_device *dev);
853extern struct radeon_encoder_atom_dig *
854radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
855extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
856 struct radeon_encoder_int_tmds *tmds);
857extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
858 struct radeon_encoder_int_tmds *tmds);
859extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
860 struct radeon_encoder_int_tmds *tmds);
861extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
862 struct radeon_encoder_ext_tmds *tmds);
863extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
864 struct radeon_encoder_ext_tmds *tmds);
865extern struct radeon_encoder_primary_dac *
866radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
867extern struct radeon_encoder_tv_dac *
868radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
869extern struct radeon_encoder_lvds *
870radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
871extern struct radeon_encoder_tv_dac *
872radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
873extern struct radeon_encoder_primary_dac *
874radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
875extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
876extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
877extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
878extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
879extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
880extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
881extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
882extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
883extern void
884radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
885extern void
886radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
887extern void
888radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
889extern void
890radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
891int radeon_framebuffer_init(struct drm_device *dev,
892 struct drm_framebuffer *rfb,
893 const struct drm_mode_fb_cmd2 *mode_cmd,
894 struct drm_gem_object *obj);
895
896int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
897bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
898bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
899void radeon_atombios_init_crtc(struct drm_device *dev,
900 struct radeon_crtc *radeon_crtc);
901void radeon_legacy_init_crtc(struct drm_device *dev,
902 struct radeon_crtc *radeon_crtc);
903
904void radeon_get_clock_info(struct drm_device *dev);
905
906extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
907extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
908
909void radeon_enc_destroy(struct drm_encoder *encoder);
910void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
911void radeon_combios_asic_init(struct drm_device *dev);
912bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
913 const struct drm_display_mode *mode,
914 struct drm_display_mode *adjusted_mode);
915void radeon_panel_mode_fixup(struct drm_encoder *encoder,
916 struct drm_display_mode *adjusted_mode);
917void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
918
919/* legacy tv */
920void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
921 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
922 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
923void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
924 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
925 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
926void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
927 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
928 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
929void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
930 struct drm_display_mode *mode,
931 struct drm_display_mode *adjusted_mode);
932
933/* fmt blocks */
934void avivo_program_fmt(struct drm_encoder *encoder);
935void dce3_program_fmt(struct drm_encoder *encoder);
936void dce4_program_fmt(struct drm_encoder *encoder);
937void dce8_program_fmt(struct drm_encoder *encoder);
938
939/* fbdev layer */
940#if defined(CONFIG_DRM_FBDEV_EMULATION)
941int radeon_fbdev_driver_fbdev_probe(struct drm_fb_helper *fb_helper,
942 struct drm_fb_helper_surface_size *sizes);
943#define RADEON_FBDEV_DRIVER_OPS \
944 .fbdev_probe = radeon_fbdev_driver_fbdev_probe
945bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
946#else
947#define RADEON_FBDEV_DRIVER_OPS \
948 .fbdev_probe = NULL
949static inline bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
950{
951 return false;
952}
953#endif
954
955void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
956
957void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
958
959int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
960void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
961#endif
962

source code of linux/drivers/gpu/drm/radeon/radeon_mode.h