1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright(c) 2015, 2016 Intel Corporation.
4 */
5
6#include <linux/delay.h>
7#include <linux/pci.h>
8#include <linux/vmalloc.h>
9
10#include "hfi.h"
11
12/* for the given bus number, return the CSR for reading an i2c line */
13static inline u32 i2c_in_csr(u32 bus_num)
14{
15 return bus_num ? ASIC_QSFP2_IN : ASIC_QSFP1_IN;
16}
17
18/* for the given bus number, return the CSR for writing an i2c line */
19static inline u32 i2c_oe_csr(u32 bus_num)
20{
21 return bus_num ? ASIC_QSFP2_OE : ASIC_QSFP1_OE;
22}
23
24static void hfi1_setsda(void *data, int state)
25{
26 struct hfi1_i2c_bus *bus = (struct hfi1_i2c_bus *)data;
27 struct hfi1_devdata *dd = bus->controlling_dd;
28 u64 reg;
29 u32 target_oe;
30
31 target_oe = i2c_oe_csr(bus_num: bus->num);
32 reg = read_csr(dd, offset: target_oe);
33 /*
34 * The OE bit value is inverted and connected to the pin. When
35 * OE is 0 the pin is left to be pulled up, when the OE is 1
36 * the pin is driven low. This matches the "open drain" or "open
37 * collector" convention.
38 */
39 if (state)
40 reg &= ~QSFP_HFI0_I2CDAT;
41 else
42 reg |= QSFP_HFI0_I2CDAT;
43 write_csr(dd, offset: target_oe, value: reg);
44 /* do a read to force the write into the chip */
45 (void)read_csr(dd, offset: target_oe);
46}
47
48static void hfi1_setscl(void *data, int state)
49{
50 struct hfi1_i2c_bus *bus = (struct hfi1_i2c_bus *)data;
51 struct hfi1_devdata *dd = bus->controlling_dd;
52 u64 reg;
53 u32 target_oe;
54
55 target_oe = i2c_oe_csr(bus_num: bus->num);
56 reg = read_csr(dd, offset: target_oe);
57 /*
58 * The OE bit value is inverted and connected to the pin. When
59 * OE is 0 the pin is left to be pulled up, when the OE is 1
60 * the pin is driven low. This matches the "open drain" or "open
61 * collector" convention.
62 */
63 if (state)
64 reg &= ~QSFP_HFI0_I2CCLK;
65 else
66 reg |= QSFP_HFI0_I2CCLK;
67 write_csr(dd, offset: target_oe, value: reg);
68 /* do a read to force the write into the chip */
69 (void)read_csr(dd, offset: target_oe);
70}
71
72static int hfi1_getsda(void *data)
73{
74 struct hfi1_i2c_bus *bus = (struct hfi1_i2c_bus *)data;
75 u64 reg;
76 u32 target_in;
77
78 hfi1_setsda(data, state: 1); /* clear OE so we do not pull line down */
79 udelay(usec: 2); /* 1us pull up + 250ns hold */
80
81 target_in = i2c_in_csr(bus_num: bus->num);
82 reg = read_csr(dd: bus->controlling_dd, offset: target_in);
83 return !!(reg & QSFP_HFI0_I2CDAT);
84}
85
86static int hfi1_getscl(void *data)
87{
88 struct hfi1_i2c_bus *bus = (struct hfi1_i2c_bus *)data;
89 u64 reg;
90 u32 target_in;
91
92 hfi1_setscl(data, state: 1); /* clear OE so we do not pull line down */
93 udelay(usec: 2); /* 1us pull up + 250ns hold */
94
95 target_in = i2c_in_csr(bus_num: bus->num);
96 reg = read_csr(dd: bus->controlling_dd, offset: target_in);
97 return !!(reg & QSFP_HFI0_I2CCLK);
98}
99
100/*
101 * Allocate and initialize the given i2c bus number.
102 * Returns NULL on failure.
103 */
104static struct hfi1_i2c_bus *init_i2c_bus(struct hfi1_devdata *dd,
105 struct hfi1_asic_data *ad, int num)
106{
107 struct hfi1_i2c_bus *bus;
108 int ret;
109
110 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
111 if (!bus)
112 return NULL;
113
114 bus->controlling_dd = dd;
115 bus->num = num; /* our bus number */
116
117 bus->algo.setsda = hfi1_setsda;
118 bus->algo.setscl = hfi1_setscl;
119 bus->algo.getsda = hfi1_getsda;
120 bus->algo.getscl = hfi1_getscl;
121 bus->algo.udelay = 5;
122 bus->algo.timeout = usecs_to_jiffies(u: 100000);
123 bus->algo.data = bus;
124
125 bus->adapter.owner = THIS_MODULE;
126 bus->adapter.algo_data = &bus->algo;
127 bus->adapter.dev.parent = &dd->pcidev->dev;
128 snprintf(buf: bus->adapter.name, size: sizeof(bus->adapter.name),
129 fmt: "hfi1_i2c%d", num);
130
131 ret = i2c_bit_add_bus(&bus->adapter);
132 if (ret) {
133 dd_dev_info(dd, "%s: unable to add i2c bus %d, err %d\n",
134 __func__, num, ret);
135 kfree(objp: bus);
136 return NULL;
137 }
138
139 return bus;
140}
141
142/*
143 * Initialize i2c buses.
144 * Return 0 on success, -errno on error.
145 */
146int set_up_i2c(struct hfi1_devdata *dd, struct hfi1_asic_data *ad)
147{
148 ad->i2c_bus0 = init_i2c_bus(dd, ad, num: 0);
149 ad->i2c_bus1 = init_i2c_bus(dd, ad, num: 1);
150 if (!ad->i2c_bus0 || !ad->i2c_bus1)
151 return -ENOMEM;
152 return 0;
153};
154
155static void clean_i2c_bus(struct hfi1_i2c_bus *bus)
156{
157 if (bus) {
158 i2c_del_adapter(adap: &bus->adapter);
159 kfree(objp: bus);
160 }
161}
162
163void clean_up_i2c(struct hfi1_devdata *dd, struct hfi1_asic_data *ad)
164{
165 if (!ad)
166 return;
167 clean_i2c_bus(bus: ad->i2c_bus0);
168 ad->i2c_bus0 = NULL;
169 clean_i2c_bus(bus: ad->i2c_bus1);
170 ad->i2c_bus1 = NULL;
171}
172
173static int i2c_bus_write(struct hfi1_devdata *dd, struct hfi1_i2c_bus *i2c,
174 u8 slave_addr, int offset, int offset_size,
175 u8 *data, u16 len)
176{
177 int ret;
178 int num_msgs;
179 u8 offset_bytes[2];
180 struct i2c_msg msgs[2];
181
182 switch (offset_size) {
183 case 0:
184 num_msgs = 1;
185 msgs[0].addr = slave_addr;
186 msgs[0].flags = 0;
187 msgs[0].len = len;
188 msgs[0].buf = data;
189 break;
190 case 2:
191 offset_bytes[1] = (offset >> 8) & 0xff;
192 fallthrough;
193 case 1:
194 num_msgs = 2;
195 offset_bytes[0] = offset & 0xff;
196
197 msgs[0].addr = slave_addr;
198 msgs[0].flags = 0;
199 msgs[0].len = offset_size;
200 msgs[0].buf = offset_bytes;
201
202 msgs[1].addr = slave_addr;
203 msgs[1].flags = I2C_M_NOSTART;
204 msgs[1].len = len;
205 msgs[1].buf = data;
206 break;
207 default:
208 return -EINVAL;
209 }
210
211 i2c->controlling_dd = dd;
212 ret = i2c_transfer(adap: &i2c->adapter, msgs, num: num_msgs);
213 if (ret != num_msgs) {
214 dd_dev_err(dd, "%s: bus %d, i2c slave 0x%x, offset 0x%x, len 0x%x; write failed, ret %d\n",
215 __func__, i2c->num, slave_addr, offset, len, ret);
216 return ret < 0 ? ret : -EIO;
217 }
218 return 0;
219}
220
221static int i2c_bus_read(struct hfi1_devdata *dd, struct hfi1_i2c_bus *bus,
222 u8 slave_addr, int offset, int offset_size,
223 u8 *data, u16 len)
224{
225 int ret;
226 int num_msgs;
227 u8 offset_bytes[2];
228 struct i2c_msg msgs[2];
229
230 switch (offset_size) {
231 case 0:
232 num_msgs = 1;
233 msgs[0].addr = slave_addr;
234 msgs[0].flags = I2C_M_RD;
235 msgs[0].len = len;
236 msgs[0].buf = data;
237 break;
238 case 2:
239 offset_bytes[1] = (offset >> 8) & 0xff;
240 fallthrough;
241 case 1:
242 num_msgs = 2;
243 offset_bytes[0] = offset & 0xff;
244
245 msgs[0].addr = slave_addr;
246 msgs[0].flags = 0;
247 msgs[0].len = offset_size;
248 msgs[0].buf = offset_bytes;
249
250 msgs[1].addr = slave_addr;
251 msgs[1].flags = I2C_M_RD;
252 msgs[1].len = len;
253 msgs[1].buf = data;
254 break;
255 default:
256 return -EINVAL;
257 }
258
259 bus->controlling_dd = dd;
260 ret = i2c_transfer(adap: &bus->adapter, msgs, num: num_msgs);
261 if (ret != num_msgs) {
262 dd_dev_err(dd, "%s: bus %d, i2c slave 0x%x, offset 0x%x, len 0x%x; read failed, ret %d\n",
263 __func__, bus->num, slave_addr, offset, len, ret);
264 return ret < 0 ? ret : -EIO;
265 }
266 return 0;
267}
268
269/*
270 * Raw i2c write. No set-up or lock checking.
271 *
272 * Return 0 on success, -errno on error.
273 */
274static int __i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr,
275 int offset, void *bp, int len)
276{
277 struct hfi1_devdata *dd = ppd->dd;
278 struct hfi1_i2c_bus *bus;
279 u8 slave_addr;
280 int offset_size;
281
282 bus = target ? dd->asic_data->i2c_bus1 : dd->asic_data->i2c_bus0;
283 slave_addr = (i2c_addr & 0xff) >> 1; /* convert to 7-bit addr */
284 offset_size = (i2c_addr >> 8) & 0x3;
285 return i2c_bus_write(dd, i2c: bus, slave_addr, offset, offset_size, data: bp, len);
286}
287
288/*
289 * Caller must hold the i2c chain resource.
290 *
291 * Return number of bytes written, or -errno.
292 */
293int i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset,
294 void *bp, int len)
295{
296 int ret;
297
298 if (!check_chip_resource(dd: ppd->dd, resource: i2c_target(target), func: __func__))
299 return -EACCES;
300
301 ret = __i2c_write(ppd, target, i2c_addr, offset, bp, len);
302 if (ret)
303 return ret;
304
305 return len;
306}
307
308/*
309 * Raw i2c read. No set-up or lock checking.
310 *
311 * Return 0 on success, -errno on error.
312 */
313static int __i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr,
314 int offset, void *bp, int len)
315{
316 struct hfi1_devdata *dd = ppd->dd;
317 struct hfi1_i2c_bus *bus;
318 u8 slave_addr;
319 int offset_size;
320
321 bus = target ? dd->asic_data->i2c_bus1 : dd->asic_data->i2c_bus0;
322 slave_addr = (i2c_addr & 0xff) >> 1; /* convert to 7-bit addr */
323 offset_size = (i2c_addr >> 8) & 0x3;
324 return i2c_bus_read(dd, bus, slave_addr, offset, offset_size, data: bp, len);
325}
326
327/*
328 * Caller must hold the i2c chain resource.
329 *
330 * Return number of bytes read, or -errno.
331 */
332int i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset,
333 void *bp, int len)
334{
335 int ret;
336
337 if (!check_chip_resource(dd: ppd->dd, resource: i2c_target(target), func: __func__))
338 return -EACCES;
339
340 ret = __i2c_read(ppd, target, i2c_addr, offset, bp, len);
341 if (ret)
342 return ret;
343
344 return len;
345}
346
347/*
348 * Write page n, offset m of QSFP memory as defined by SFF 8636
349 * by writing @addr = ((256 * n) + m)
350 *
351 * Caller must hold the i2c chain resource.
352 *
353 * Return number of bytes written or -errno.
354 */
355int qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
356 int len)
357{
358 int count = 0;
359 int offset;
360 int nwrite;
361 int ret = 0;
362 u8 page;
363
364 if (!check_chip_resource(dd: ppd->dd, resource: i2c_target(target), func: __func__))
365 return -EACCES;
366
367 while (count < len) {
368 /*
369 * Set the qsfp page based on a zero-based address
370 * and a page size of QSFP_PAGESIZE bytes.
371 */
372 page = (u8)(addr / QSFP_PAGESIZE);
373
374 ret = __i2c_write(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
375 QSFP_PAGE_SELECT_BYTE_OFFS, bp: &page, len: 1);
376 /* QSFPs require a 5-10msec delay after write operations */
377 mdelay(5);
378 if (ret) {
379 hfi1_dev_porterr(ppd->dd, ppd->port,
380 "QSFP chain %d can't write QSFP_PAGE_SELECT_BYTE: %d\n",
381 target, ret);
382 break;
383 }
384
385 offset = addr % QSFP_PAGESIZE;
386 nwrite = len - count;
387 /* truncate write to boundary if crossing boundary */
388 if (((addr % QSFP_RW_BOUNDARY) + nwrite) > QSFP_RW_BOUNDARY)
389 nwrite = QSFP_RW_BOUNDARY - (addr % QSFP_RW_BOUNDARY);
390
391 ret = __i2c_write(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
392 offset, bp: bp + count, len: nwrite);
393 /* QSFPs require a 5-10msec delay after write operations */
394 mdelay(5);
395 if (ret) /* stop on error */
396 break;
397
398 count += nwrite;
399 addr += nwrite;
400 }
401
402 if (ret < 0)
403 return ret;
404 return count;
405}
406
407/*
408 * Access page n, offset m of QSFP memory as defined by SFF 8636
409 * by reading @addr = ((256 * n) + m)
410 *
411 * Caller must hold the i2c chain resource.
412 *
413 * Return the number of bytes read or -errno.
414 */
415int qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
416 int len)
417{
418 int count = 0;
419 int offset;
420 int nread;
421 int ret = 0;
422 u8 page;
423
424 if (!check_chip_resource(dd: ppd->dd, resource: i2c_target(target), func: __func__))
425 return -EACCES;
426
427 while (count < len) {
428 /*
429 * Set the qsfp page based on a zero-based address
430 * and a page size of QSFP_PAGESIZE bytes.
431 */
432 page = (u8)(addr / QSFP_PAGESIZE);
433 ret = __i2c_write(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
434 QSFP_PAGE_SELECT_BYTE_OFFS, bp: &page, len: 1);
435 /* QSFPs require a 5-10msec delay after write operations */
436 mdelay(5);
437 if (ret) {
438 hfi1_dev_porterr(ppd->dd, ppd->port,
439 "QSFP chain %d can't write QSFP_PAGE_SELECT_BYTE: %d\n",
440 target, ret);
441 break;
442 }
443
444 offset = addr % QSFP_PAGESIZE;
445 nread = len - count;
446 /* truncate read to boundary if crossing boundary */
447 if (((addr % QSFP_RW_BOUNDARY) + nread) > QSFP_RW_BOUNDARY)
448 nread = QSFP_RW_BOUNDARY - (addr % QSFP_RW_BOUNDARY);
449
450 ret = __i2c_read(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
451 offset, bp: bp + count, len: nread);
452 if (ret) /* stop on error */
453 break;
454
455 count += nread;
456 addr += nread;
457 }
458
459 if (ret < 0)
460 return ret;
461 return count;
462}
463
464/*
465 * Perform a stand-alone single QSFP read. Acquire the resource, do the
466 * read, then release the resource.
467 */
468int one_qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
469 int len)
470{
471 struct hfi1_devdata *dd = ppd->dd;
472 u32 resource = qsfp_resource(dd);
473 int ret;
474
475 ret = acquire_chip_resource(dd, resource, QSFP_WAIT);
476 if (ret)
477 return ret;
478 ret = qsfp_read(ppd, target, addr, bp, len);
479 release_chip_resource(dd, resource);
480
481 return ret;
482}
483
484/*
485 * This function caches the QSFP memory range in 128 byte chunks.
486 * As an example, the next byte after address 255 is byte 128 from
487 * upper page 01H (if existing) rather than byte 0 from lower page 00H.
488 * Access page n, offset m of QSFP memory as defined by SFF 8636
489 * in the cache by reading byte ((128 * n) + m)
490 * The calls to qsfp_{read,write} in this function correctly handle the
491 * address map difference between this mapping and the mapping implemented
492 * by those functions
493 *
494 * The caller must be holding the QSFP i2c chain resource.
495 */
496int refresh_qsfp_cache(struct hfi1_pportdata *ppd, struct qsfp_data *cp)
497{
498 u32 target = ppd->dd->hfi1_id;
499 int ret;
500 unsigned long flags;
501 u8 *cache = &cp->cache[0];
502
503 /* ensure sane contents on invalid reads, for cable swaps */
504 memset(cache, 0, (QSFP_MAX_NUM_PAGES * 128));
505 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
506 ppd->qsfp_info.cache_valid = 0;
507 spin_unlock_irqrestore(lock: &ppd->qsfp_info.qsfp_lock, flags);
508
509 if (!qsfp_mod_present(ppd)) {
510 ret = -ENODEV;
511 goto bail;
512 }
513
514 ret = qsfp_read(ppd, target, addr: 0, bp: cache, QSFP_PAGESIZE);
515 if (ret != QSFP_PAGESIZE) {
516 dd_dev_info(ppd->dd,
517 "%s: Page 0 read failed, expected %d, got %d\n",
518 __func__, QSFP_PAGESIZE, ret);
519 goto bail;
520 }
521
522 /* Is paging enabled? */
523 if (!(cache[2] & 4)) {
524 /* Paging enabled, page 03 required */
525 if ((cache[195] & 0xC0) == 0xC0) {
526 /* all */
527 ret = qsfp_read(ppd, target, addr: 384, bp: cache + 256, len: 128);
528 if (ret <= 0 || ret != 128) {
529 dd_dev_info(ppd->dd, "%s failed\n", __func__);
530 goto bail;
531 }
532 ret = qsfp_read(ppd, target, addr: 640, bp: cache + 384, len: 128);
533 if (ret <= 0 || ret != 128) {
534 dd_dev_info(ppd->dd, "%s failed\n", __func__);
535 goto bail;
536 }
537 ret = qsfp_read(ppd, target, addr: 896, bp: cache + 512, len: 128);
538 if (ret <= 0 || ret != 128) {
539 dd_dev_info(ppd->dd, "%s failed\n", __func__);
540 goto bail;
541 }
542 } else if ((cache[195] & 0x80) == 0x80) {
543 /* only page 2 and 3 */
544 ret = qsfp_read(ppd, target, addr: 640, bp: cache + 384, len: 128);
545 if (ret <= 0 || ret != 128) {
546 dd_dev_info(ppd->dd, "%s failed\n", __func__);
547 goto bail;
548 }
549 ret = qsfp_read(ppd, target, addr: 896, bp: cache + 512, len: 128);
550 if (ret <= 0 || ret != 128) {
551 dd_dev_info(ppd->dd, "%s failed\n", __func__);
552 goto bail;
553 }
554 } else if ((cache[195] & 0x40) == 0x40) {
555 /* only page 1 and 3 */
556 ret = qsfp_read(ppd, target, addr: 384, bp: cache + 256, len: 128);
557 if (ret <= 0 || ret != 128) {
558 dd_dev_info(ppd->dd, "%s failed\n", __func__);
559 goto bail;
560 }
561 ret = qsfp_read(ppd, target, addr: 896, bp: cache + 512, len: 128);
562 if (ret <= 0 || ret != 128) {
563 dd_dev_info(ppd->dd, "%s failed\n", __func__);
564 goto bail;
565 }
566 } else {
567 /* only page 3 */
568 ret = qsfp_read(ppd, target, addr: 896, bp: cache + 512, len: 128);
569 if (ret <= 0 || ret != 128) {
570 dd_dev_info(ppd->dd, "%s failed\n", __func__);
571 goto bail;
572 }
573 }
574 }
575
576 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
577 ppd->qsfp_info.cache_valid = 1;
578 ppd->qsfp_info.cache_refresh_required = 0;
579 spin_unlock_irqrestore(lock: &ppd->qsfp_info.qsfp_lock, flags);
580
581 return 0;
582
583bail:
584 memset(cache, 0, (QSFP_MAX_NUM_PAGES * 128));
585 return ret;
586}
587
588const char * const hfi1_qsfp_devtech[16] = {
589 "850nm VCSEL", "1310nm VCSEL", "1550nm VCSEL", "1310nm FP",
590 "1310nm DFB", "1550nm DFB", "1310nm EML", "1550nm EML",
591 "Cu Misc", "1490nm DFB", "Cu NoEq", "Cu Eq",
592 "Undef", "Cu Active BothEq", "Cu FarEq", "Cu NearEq"
593};
594
595#define QSFP_DUMP_CHUNK 16 /* Holds longest string */
596#define QSFP_DEFAULT_HDR_CNT 224
597
598#define QSFP_PWR(pbyte) (((pbyte) >> 6) & 3)
599#define QSFP_HIGH_PWR(pbyte) ((pbyte) & 3)
600/* For use with QSFP_HIGH_PWR macro */
601#define QSFP_HIGH_PWR_UNUSED 0 /* Bits [1:0] = 00 implies low power module */
602
603/*
604 * Takes power class byte [Page 00 Byte 129] in SFF 8636
605 * Returns power class as integer (1 through 7, per SFF 8636 rev 2.4)
606 */
607int get_qsfp_power_class(u8 power_byte)
608{
609 if (QSFP_HIGH_PWR(power_byte) == QSFP_HIGH_PWR_UNUSED)
610 /* power classes count from 1, their bit encodings from 0 */
611 return (QSFP_PWR(power_byte) + 1);
612 /*
613 * 00 in the high power classes stands for unused, bringing
614 * balance to the off-by-1 offset above, we add 4 here to
615 * account for the difference between the low and high power
616 * groups
617 */
618 return (QSFP_HIGH_PWR(power_byte) + 4);
619}
620
621int qsfp_mod_present(struct hfi1_pportdata *ppd)
622{
623 struct hfi1_devdata *dd = ppd->dd;
624 u64 reg;
625
626 reg = read_csr(dd, offset: dd->hfi1_id ? ASIC_QSFP2_IN : ASIC_QSFP1_IN);
627 return !(reg & QSFP_HFI0_MODPRST_N);
628}
629
630/*
631 * This function maps QSFP memory addresses in 128 byte chunks in the following
632 * fashion per the CableInfo SMA query definition in the IBA 1.3 spec/OPA Gen 1
633 * spec
634 * For addr 000-127, lower page 00h
635 * For addr 128-255, upper page 00h
636 * For addr 256-383, upper page 01h
637 * For addr 384-511, upper page 02h
638 * For addr 512-639, upper page 03h
639 *
640 * For addresses beyond this range, it returns the invalid range of data buffer
641 * set to 0.
642 * For upper pages that are optional, if they are not valid, returns the
643 * particular range of bytes in the data buffer set to 0.
644 */
645int get_cable_info(struct hfi1_devdata *dd, u32 port_num, u32 addr, u32 len,
646 u8 *data)
647{
648 struct hfi1_pportdata *ppd;
649 u32 excess_len = len;
650 int ret = 0, offset = 0;
651
652 if (port_num > dd->num_pports || port_num < 1) {
653 dd_dev_info(dd, "%s: Invalid port number %d\n",
654 __func__, port_num);
655 ret = -EINVAL;
656 goto set_zeroes;
657 }
658
659 ppd = dd->pport + (port_num - 1);
660 if (!qsfp_mod_present(ppd)) {
661 ret = -ENODEV;
662 goto set_zeroes;
663 }
664
665 if (!ppd->qsfp_info.cache_valid) {
666 ret = -EINVAL;
667 goto set_zeroes;
668 }
669
670 if (addr >= (QSFP_MAX_NUM_PAGES * 128)) {
671 ret = -ERANGE;
672 goto set_zeroes;
673 }
674
675 if ((addr + len) > (QSFP_MAX_NUM_PAGES * 128)) {
676 excess_len = (addr + len) - (QSFP_MAX_NUM_PAGES * 128);
677 memcpy(data, &ppd->qsfp_info.cache[addr], (len - excess_len));
678 data += (len - excess_len);
679 goto set_zeroes;
680 }
681
682 memcpy(data, &ppd->qsfp_info.cache[addr], len);
683
684 if (addr <= QSFP_MONITOR_VAL_END &&
685 (addr + len) >= QSFP_MONITOR_VAL_START) {
686 /* Overlap with the dynamic channel monitor range */
687 if (addr < QSFP_MONITOR_VAL_START) {
688 if (addr + len <= QSFP_MONITOR_VAL_END)
689 len = addr + len - QSFP_MONITOR_VAL_START;
690 else
691 len = QSFP_MONITOR_RANGE;
692 offset = QSFP_MONITOR_VAL_START - addr;
693 addr = QSFP_MONITOR_VAL_START;
694 } else if (addr == QSFP_MONITOR_VAL_START) {
695 offset = 0;
696 if (addr + len > QSFP_MONITOR_VAL_END)
697 len = QSFP_MONITOR_RANGE;
698 } else {
699 offset = 0;
700 if (addr + len > QSFP_MONITOR_VAL_END)
701 len = QSFP_MONITOR_VAL_END - addr + 1;
702 }
703 /* Refresh the values of the dynamic monitors from the cable */
704 ret = one_qsfp_read(ppd, target: dd->hfi1_id, addr, bp: data + offset, len);
705 if (ret != len) {
706 ret = -EAGAIN;
707 goto set_zeroes;
708 }
709 }
710
711 return 0;
712
713set_zeroes:
714 memset(data, 0, excess_len);
715 return ret;
716}
717
718static const char *pwr_codes[8] = {"N/AW",
719 "1.5W",
720 "2.0W",
721 "2.5W",
722 "3.5W",
723 "4.0W",
724 "4.5W",
725 "5.0W"
726 };
727
728int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len)
729{
730 u8 *cache = &ppd->qsfp_info.cache[0];
731 u8 bin_buff[QSFP_DUMP_CHUNK];
732 char lenstr[6];
733 int sofar;
734 int bidx = 0;
735 u8 *atten = &cache[QSFP_ATTEN_OFFS];
736 u8 *vendor_oui = &cache[QSFP_VOUI_OFFS];
737 u8 power_byte = 0;
738
739 sofar = 0;
740 lenstr[0] = ' ';
741 lenstr[1] = '\0';
742
743 if (ppd->qsfp_info.cache_valid) {
744 if (QSFP_IS_CU(cache[QSFP_MOD_TECH_OFFS]))
745 snprintf(buf: lenstr, size: sizeof(lenstr), fmt: "%dM ",
746 cache[QSFP_MOD_LEN_OFFS]);
747
748 power_byte = cache[QSFP_MOD_PWR_OFFS];
749 sofar += scnprintf(buf: buf + sofar, size: len - sofar, fmt: "PWR:%.3sW\n",
750 pwr_codes[get_qsfp_power_class(power_byte)]);
751
752 sofar += scnprintf(buf: buf + sofar, size: len - sofar, fmt: "TECH:%s%s\n",
753 lenstr,
754 hfi1_qsfp_devtech[(cache[QSFP_MOD_TECH_OFFS]) >> 4]);
755
756 sofar += scnprintf(buf: buf + sofar, size: len - sofar, fmt: "Vendor:%.*s\n",
757 QSFP_VEND_LEN, &cache[QSFP_VEND_OFFS]);
758
759 sofar += scnprintf(buf: buf + sofar, size: len - sofar, fmt: "OUI:%06X\n",
760 QSFP_OUI(vendor_oui));
761
762 sofar += scnprintf(buf: buf + sofar, size: len - sofar, fmt: "Part#:%.*s\n",
763 QSFP_PN_LEN, &cache[QSFP_PN_OFFS]);
764
765 sofar += scnprintf(buf: buf + sofar, size: len - sofar, fmt: "Rev:%.*s\n",
766 QSFP_REV_LEN, &cache[QSFP_REV_OFFS]);
767
768 if (QSFP_IS_CU(cache[QSFP_MOD_TECH_OFFS]))
769 sofar += scnprintf(buf: buf + sofar, size: len - sofar,
770 fmt: "Atten:%d, %d\n",
771 QSFP_ATTEN_SDR(atten),
772 QSFP_ATTEN_DDR(atten));
773
774 sofar += scnprintf(buf: buf + sofar, size: len - sofar, fmt: "Serial:%.*s\n",
775 QSFP_SN_LEN, &cache[QSFP_SN_OFFS]);
776
777 sofar += scnprintf(buf: buf + sofar, size: len - sofar, fmt: "Date:%.*s\n",
778 QSFP_DATE_LEN, &cache[QSFP_DATE_OFFS]);
779
780 sofar += scnprintf(buf: buf + sofar, size: len - sofar, fmt: "Lot:%.*s\n",
781 QSFP_LOT_LEN, &cache[QSFP_LOT_OFFS]);
782
783 while (bidx < QSFP_DEFAULT_HDR_CNT) {
784 int iidx;
785
786 memcpy(bin_buff, &cache[bidx], QSFP_DUMP_CHUNK);
787 for (iidx = 0; iidx < QSFP_DUMP_CHUNK; ++iidx) {
788 sofar += scnprintf(buf: buf + sofar, size: len - sofar,
789 fmt: " %02X", bin_buff[iidx]);
790 }
791 sofar += scnprintf(buf: buf + sofar, size: len - sofar, fmt: "\n");
792 bidx += QSFP_DUMP_CHUNK;
793 }
794 }
795 return sofar;
796}
797

source code of linux/drivers/infiniband/hw/hfi1/qsfp.c