| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* $Date: 2005/03/07 23:59:05 $ $RCSfile: mv88e1xxx.h,v $ $Revision: 1.13 $ */ |
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| 3 | #ifndef CHELSIO_MV8E1XXX_H |
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| 4 | #define CHELSIO_MV8E1XXX_H |
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| 5 | |
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| 6 | #ifndef BMCR_SPEED1000 |
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| 7 | # define BMCR_SPEED1000 0x40 |
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| 8 | #endif |
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| 9 | |
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| 10 | #ifndef ADVERTISE_PAUSE |
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| 11 | # define ADVERTISE_PAUSE 0x400 |
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| 12 | #endif |
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| 13 | #ifndef ADVERTISE_PAUSE_ASYM |
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| 14 | # define ADVERTISE_PAUSE_ASYM 0x800 |
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| 15 | #endif |
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| 16 | |
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| 17 | /* Gigabit MII registers */ |
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| 18 | #define MII_GBCR 9 /* 1000Base-T control register */ |
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| 19 | #define MII_GBSR 10 /* 1000Base-T status register */ |
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| 20 | |
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| 21 | /* 1000Base-T control register fields */ |
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| 22 | #define GBCR_ADV_1000HALF 0x100 |
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| 23 | #define GBCR_ADV_1000FULL 0x200 |
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| 24 | #define GBCR_PREFER_MASTER 0x400 |
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| 25 | #define GBCR_MANUAL_AS_MASTER 0x800 |
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| 26 | #define GBCR_MANUAL_CONFIG_ENABLE 0x1000 |
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| 27 | |
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| 28 | /* 1000Base-T status register fields */ |
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| 29 | #define GBSR_LP_1000HALF 0x400 |
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| 30 | #define GBSR_LP_1000FULL 0x800 |
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| 31 | #define GBSR_REMOTE_OK 0x1000 |
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| 32 | #define GBSR_LOCAL_OK 0x2000 |
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| 33 | #define GBSR_LOCAL_MASTER 0x4000 |
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| 34 | #define GBSR_MASTER_FAULT 0x8000 |
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| 35 | |
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| 36 | /* Marvell PHY interrupt status bits. */ |
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| 37 | #define MV88E1XXX_INTR_JABBER 0x0001 |
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| 38 | #define MV88E1XXX_INTR_POLARITY_CHNG 0x0002 |
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| 39 | #define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010 |
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| 40 | #define MV88E1XXX_INTR_DOWNSHIFT 0x0020 |
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| 41 | #define MV88E1XXX_INTR_MDI_XOVER_CHNG 0x0040 |
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| 42 | #define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080 |
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| 43 | #define MV88E1XXX_INTR_FALSE_CARRIER 0x0100 |
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| 44 | #define MV88E1XXX_INTR_SYMBOL_ERROR 0x0200 |
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| 45 | #define MV88E1XXX_INTR_LINK_CHNG 0x0400 |
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| 46 | #define MV88E1XXX_INTR_AUTONEG_DONE 0x0800 |
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| 47 | #define MV88E1XXX_INTR_PAGE_RECV 0x1000 |
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| 48 | #define MV88E1XXX_INTR_DUPLEX_CHNG 0x2000 |
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| 49 | #define MV88E1XXX_INTR_SPEED_CHNG 0x4000 |
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| 50 | #define MV88E1XXX_INTR_AUTONEG_ERR 0x8000 |
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| 51 | |
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| 52 | /* Marvell PHY specific registers. */ |
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| 53 | #define MV88E1XXX_SPECIFIC_CNTRL_REGISTER 16 |
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| 54 | #define MV88E1XXX_SPECIFIC_STATUS_REGISTER 17 |
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| 55 | #define MV88E1XXX_INTERRUPT_ENABLE_REGISTER 18 |
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| 56 | #define MV88E1XXX_INTERRUPT_STATUS_REGISTER 19 |
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| 57 | #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER 20 |
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| 58 | #define MV88E1XXX_RECV_ERR_CNTR_REGISTER 21 |
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| 59 | #define MV88E1XXX_RES_REGISTER 22 |
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| 60 | #define MV88E1XXX_GLOBAL_STATUS_REGISTER 23 |
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| 61 | #define MV88E1XXX_LED_CONTROL_REGISTER 24 |
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| 62 | #define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER 25 |
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| 63 | #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER 26 |
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| 64 | #define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER 27 |
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| 65 | #define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER 28 |
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| 66 | #define MV88E1XXX_EXTENDED_ADDR_REGISTER 29 |
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| 67 | #define MV88E1XXX_EXTENDED_REGISTER 30 |
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| 68 | |
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| 69 | /* PHY specific control register fields */ |
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| 70 | #define S_PSCR_MDI_XOVER_MODE 5 |
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| 71 | #define M_PSCR_MDI_XOVER_MODE 0x3 |
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| 72 | #define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE) |
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| 73 | #define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE) |
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| 74 | |
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| 75 | /* Extended PHY specific control register fields */ |
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| 76 | #define S_DOWNSHIFT_ENABLE 8 |
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| 77 | #define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE) |
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| 78 | |
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| 79 | #define S_DOWNSHIFT_CNT 9 |
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| 80 | #define M_DOWNSHIFT_CNT 0x7 |
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| 81 | #define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT) |
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| 82 | #define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT) |
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| 83 | |
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| 84 | /* PHY specific status register fields */ |
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| 85 | #define S_PSSR_JABBER 0 |
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| 86 | #define V_PSSR_JABBER (1 << S_PSSR_JABBER) |
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| 87 | |
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| 88 | #define S_PSSR_POLARITY 1 |
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| 89 | #define V_PSSR_POLARITY (1 << S_PSSR_POLARITY) |
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| 90 | |
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| 91 | #define S_PSSR_RX_PAUSE 2 |
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| 92 | #define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE) |
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| 93 | |
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| 94 | #define S_PSSR_TX_PAUSE 3 |
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| 95 | #define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE) |
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| 96 | |
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| 97 | #define S_PSSR_ENERGY_DETECT 4 |
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| 98 | #define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT) |
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| 99 | |
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| 100 | #define S_PSSR_DOWNSHIFT_STATUS 5 |
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| 101 | #define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS) |
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| 102 | |
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| 103 | #define S_PSSR_MDI 6 |
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| 104 | #define V_PSSR_MDI (1 << S_PSSR_MDI) |
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| 105 | |
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| 106 | #define S_PSSR_CABLE_LEN 7 |
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| 107 | #define M_PSSR_CABLE_LEN 0x7 |
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| 108 | #define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN) |
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| 109 | #define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN) |
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| 110 | |
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| 111 | #define S_PSSR_LINK 10 |
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| 112 | #define V_PSSR_LINK (1 << S_PSSR_LINK) |
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| 113 | |
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| 114 | #define S_PSSR_STATUS_RESOLVED 11 |
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| 115 | #define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED) |
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| 116 | |
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| 117 | #define S_PSSR_PAGE_RECEIVED 12 |
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| 118 | #define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED) |
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| 119 | |
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| 120 | #define S_PSSR_DUPLEX 13 |
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| 121 | #define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX) |
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| 122 | |
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| 123 | #define S_PSSR_SPEED 14 |
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| 124 | #define M_PSSR_SPEED 0x3 |
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| 125 | #define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED) |
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| 126 | #define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED) |
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| 127 | |
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| 128 | #endif |
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| 129 | |
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