1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #define A_SG_CONTROL 0x0 |
3 | |
4 | #define S_CONGMODE 29 |
5 | #define V_CONGMODE(x) ((x) << S_CONGMODE) |
6 | #define F_CONGMODE V_CONGMODE(1U) |
7 | |
8 | #define S_TNLFLMODE 28 |
9 | #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) |
10 | #define F_TNLFLMODE V_TNLFLMODE(1U) |
11 | |
12 | #define S_FATLPERREN 27 |
13 | #define V_FATLPERREN(x) ((x) << S_FATLPERREN) |
14 | #define F_FATLPERREN V_FATLPERREN(1U) |
15 | |
16 | #define S_DROPPKT 20 |
17 | #define V_DROPPKT(x) ((x) << S_DROPPKT) |
18 | #define F_DROPPKT V_DROPPKT(1U) |
19 | |
20 | #define S_EGRGENCTRL 19 |
21 | #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL) |
22 | #define F_EGRGENCTRL V_EGRGENCTRL(1U) |
23 | |
24 | #define S_USERSPACESIZE 14 |
25 | #define M_USERSPACESIZE 0x1f |
26 | #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) |
27 | |
28 | #define S_HOSTPAGESIZE 11 |
29 | #define M_HOSTPAGESIZE 0x7 |
30 | #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) |
31 | |
32 | #define S_FLMODE 9 |
33 | #define V_FLMODE(x) ((x) << S_FLMODE) |
34 | #define F_FLMODE V_FLMODE(1U) |
35 | |
36 | #define S_PKTSHIFT 6 |
37 | #define M_PKTSHIFT 0x7 |
38 | #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) |
39 | |
40 | #define S_ONEINTMULTQ 5 |
41 | #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) |
42 | #define F_ONEINTMULTQ V_ONEINTMULTQ(1U) |
43 | |
44 | #define S_BIGENDIANINGRESS 2 |
45 | #define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS) |
46 | #define F_BIGENDIANINGRESS V_BIGENDIANINGRESS(1U) |
47 | |
48 | #define S_ISCSICOALESCING 1 |
49 | #define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING) |
50 | #define F_ISCSICOALESCING V_ISCSICOALESCING(1U) |
51 | |
52 | #define S_GLOBALENABLE 0 |
53 | #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE) |
54 | #define F_GLOBALENABLE V_GLOBALENABLE(1U) |
55 | |
56 | #define S_AVOIDCQOVFL 24 |
57 | #define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL) |
58 | #define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U) |
59 | |
60 | #define S_OPTONEINTMULTQ 23 |
61 | #define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ) |
62 | #define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U) |
63 | |
64 | #define S_CQCRDTCTRL 22 |
65 | #define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL) |
66 | #define F_CQCRDTCTRL V_CQCRDTCTRL(1U) |
67 | |
68 | #define A_SG_KDOORBELL 0x4 |
69 | |
70 | #define S_SELEGRCNTX 31 |
71 | #define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX) |
72 | #define F_SELEGRCNTX V_SELEGRCNTX(1U) |
73 | |
74 | #define S_EGRCNTX 0 |
75 | #define M_EGRCNTX 0xffff |
76 | #define V_EGRCNTX(x) ((x) << S_EGRCNTX) |
77 | |
78 | #define A_SG_GTS 0x8 |
79 | |
80 | #define S_RSPQ 29 |
81 | #define M_RSPQ 0x7 |
82 | #define V_RSPQ(x) ((x) << S_RSPQ) |
83 | #define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ) |
84 | |
85 | #define S_NEWTIMER 16 |
86 | #define M_NEWTIMER 0x1fff |
87 | #define V_NEWTIMER(x) ((x) << S_NEWTIMER) |
88 | |
89 | #define S_NEWINDEX 0 |
90 | #define M_NEWINDEX 0xffff |
91 | #define V_NEWINDEX(x) ((x) << S_NEWINDEX) |
92 | |
93 | #define A_SG_CONTEXT_CMD 0xc |
94 | |
95 | #define S_CONTEXT_CMD_OPCODE 28 |
96 | #define M_CONTEXT_CMD_OPCODE 0xf |
97 | #define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE) |
98 | |
99 | #define S_CONTEXT_CMD_BUSY 27 |
100 | #define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY) |
101 | #define F_CONTEXT_CMD_BUSY V_CONTEXT_CMD_BUSY(1U) |
102 | |
103 | #define S_CQ_CREDIT 20 |
104 | |
105 | #define M_CQ_CREDIT 0x7f |
106 | |
107 | #define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT) |
108 | |
109 | #define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT) |
110 | |
111 | #define S_CQ 19 |
112 | |
113 | #define V_CQ(x) ((x) << S_CQ) |
114 | #define F_CQ V_CQ(1U) |
115 | |
116 | #define S_RESPONSEQ 18 |
117 | #define V_RESPONSEQ(x) ((x) << S_RESPONSEQ) |
118 | #define F_RESPONSEQ V_RESPONSEQ(1U) |
119 | |
120 | #define S_EGRESS 17 |
121 | #define V_EGRESS(x) ((x) << S_EGRESS) |
122 | #define F_EGRESS V_EGRESS(1U) |
123 | |
124 | #define S_FREELIST 16 |
125 | #define V_FREELIST(x) ((x) << S_FREELIST) |
126 | #define F_FREELIST V_FREELIST(1U) |
127 | |
128 | #define S_CONTEXT 0 |
129 | #define M_CONTEXT 0xffff |
130 | #define V_CONTEXT(x) ((x) << S_CONTEXT) |
131 | |
132 | #define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT) |
133 | |
134 | #define A_SG_CONTEXT_DATA0 0x10 |
135 | |
136 | #define A_SG_CONTEXT_DATA1 0x14 |
137 | |
138 | #define A_SG_CONTEXT_DATA2 0x18 |
139 | |
140 | #define A_SG_CONTEXT_DATA3 0x1c |
141 | |
142 | #define A_SG_CONTEXT_MASK0 0x20 |
143 | |
144 | #define A_SG_CONTEXT_MASK1 0x24 |
145 | |
146 | #define A_SG_CONTEXT_MASK2 0x28 |
147 | |
148 | #define A_SG_CONTEXT_MASK3 0x2c |
149 | |
150 | #define A_SG_RSPQ_CREDIT_RETURN 0x30 |
151 | |
152 | #define S_CREDITS 0 |
153 | #define M_CREDITS 0xffff |
154 | #define V_CREDITS(x) ((x) << S_CREDITS) |
155 | |
156 | #define A_SG_DATA_INTR 0x34 |
157 | |
158 | #define S_ERRINTR 31 |
159 | #define V_ERRINTR(x) ((x) << S_ERRINTR) |
160 | #define F_ERRINTR V_ERRINTR(1U) |
161 | |
162 | #define A_SG_HI_DRB_HI_THRSH 0x38 |
163 | |
164 | #define A_SG_HI_DRB_LO_THRSH 0x3c |
165 | |
166 | #define A_SG_LO_DRB_HI_THRSH 0x40 |
167 | |
168 | #define A_SG_LO_DRB_LO_THRSH 0x44 |
169 | |
170 | #define A_SG_RSPQ_FL_STATUS 0x4c |
171 | |
172 | #define S_RSPQ0DISABLED 8 |
173 | |
174 | #define S_FL0EMPTY 16 |
175 | #define V_FL0EMPTY(x) ((x) << S_FL0EMPTY) |
176 | #define F_FL0EMPTY V_FL0EMPTY(1U) |
177 | |
178 | #define A_SG_EGR_RCQ_DRB_THRSH 0x54 |
179 | |
180 | #define S_HIRCQDRBTHRSH 16 |
181 | #define M_HIRCQDRBTHRSH 0x7ff |
182 | #define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH) |
183 | |
184 | #define S_LORCQDRBTHRSH 0 |
185 | #define M_LORCQDRBTHRSH 0x7ff |
186 | #define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH) |
187 | |
188 | #define A_SG_EGR_CNTX_BADDR 0x58 |
189 | |
190 | #define A_SG_INT_CAUSE 0x5c |
191 | |
192 | #define S_HIRCQPARITYERROR 31 |
193 | #define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR) |
194 | #define F_HIRCQPARITYERROR V_HIRCQPARITYERROR(1U) |
195 | |
196 | #define S_LORCQPARITYERROR 30 |
197 | #define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR) |
198 | #define F_LORCQPARITYERROR V_LORCQPARITYERROR(1U) |
199 | |
200 | #define S_HIDRBPARITYERROR 29 |
201 | #define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR) |
202 | #define F_HIDRBPARITYERROR V_HIDRBPARITYERROR(1U) |
203 | |
204 | #define S_LODRBPARITYERROR 28 |
205 | #define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR) |
206 | #define F_LODRBPARITYERROR V_LODRBPARITYERROR(1U) |
207 | |
208 | #define S_FLPARITYERROR 22 |
209 | #define M_FLPARITYERROR 0x3f |
210 | #define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR) |
211 | #define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR) |
212 | |
213 | #define S_ITPARITYERROR 20 |
214 | #define M_ITPARITYERROR 0x3 |
215 | #define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR) |
216 | #define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR) |
217 | |
218 | #define S_IRPARITYERROR 19 |
219 | #define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR) |
220 | #define F_IRPARITYERROR V_IRPARITYERROR(1U) |
221 | |
222 | #define S_RCPARITYERROR 18 |
223 | #define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR) |
224 | #define F_RCPARITYERROR V_RCPARITYERROR(1U) |
225 | |
226 | #define S_OCPARITYERROR 17 |
227 | #define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR) |
228 | #define F_OCPARITYERROR V_OCPARITYERROR(1U) |
229 | |
230 | #define S_CPPARITYERROR 16 |
231 | #define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR) |
232 | #define F_CPPARITYERROR V_CPPARITYERROR(1U) |
233 | |
234 | #define S_R_REQ_FRAMINGERROR 15 |
235 | #define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR) |
236 | #define F_R_REQ_FRAMINGERROR V_R_REQ_FRAMINGERROR(1U) |
237 | |
238 | #define S_UC_REQ_FRAMINGERROR 14 |
239 | #define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR) |
240 | #define F_UC_REQ_FRAMINGERROR V_UC_REQ_FRAMINGERROR(1U) |
241 | |
242 | #define S_HICTLDRBDROPERR 13 |
243 | #define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR) |
244 | #define F_HICTLDRBDROPERR V_HICTLDRBDROPERR(1U) |
245 | |
246 | #define S_LOCTLDRBDROPERR 12 |
247 | #define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR) |
248 | #define F_LOCTLDRBDROPERR V_LOCTLDRBDROPERR(1U) |
249 | |
250 | #define S_HIPIODRBDROPERR 11 |
251 | #define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR) |
252 | #define F_HIPIODRBDROPERR V_HIPIODRBDROPERR(1U) |
253 | |
254 | #define S_LOPIODRBDROPERR 10 |
255 | #define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR) |
256 | #define F_LOPIODRBDROPERR V_LOPIODRBDROPERR(1U) |
257 | |
258 | #define S_HIPRIORITYDBFULL 7 |
259 | #define V_HIPRIORITYDBFULL(x) ((x) << S_HIPRIORITYDBFULL) |
260 | #define F_HIPRIORITYDBFULL V_HIPRIORITYDBFULL(1U) |
261 | |
262 | #define S_HIPRIORITYDBEMPTY 6 |
263 | #define V_HIPRIORITYDBEMPTY(x) ((x) << S_HIPRIORITYDBEMPTY) |
264 | #define F_HIPRIORITYDBEMPTY V_HIPRIORITYDBEMPTY(1U) |
265 | |
266 | #define S_LOPRIORITYDBFULL 5 |
267 | #define V_LOPRIORITYDBFULL(x) ((x) << S_LOPRIORITYDBFULL) |
268 | #define F_LOPRIORITYDBFULL V_LOPRIORITYDBFULL(1U) |
269 | |
270 | #define S_LOPRIORITYDBEMPTY 4 |
271 | #define V_LOPRIORITYDBEMPTY(x) ((x) << S_LOPRIORITYDBEMPTY) |
272 | #define F_LOPRIORITYDBEMPTY V_LOPRIORITYDBEMPTY(1U) |
273 | |
274 | #define S_RSPQDISABLED 3 |
275 | #define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED) |
276 | #define F_RSPQDISABLED V_RSPQDISABLED(1U) |
277 | |
278 | #define S_RSPQCREDITOVERFOW 2 |
279 | #define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW) |
280 | #define F_RSPQCREDITOVERFOW V_RSPQCREDITOVERFOW(1U) |
281 | |
282 | #define S_FLEMPTY 1 |
283 | #define V_FLEMPTY(x) ((x) << S_FLEMPTY) |
284 | #define F_FLEMPTY V_FLEMPTY(1U) |
285 | |
286 | #define A_SG_INT_ENABLE 0x60 |
287 | |
288 | #define A_SG_CMDQ_CREDIT_TH 0x64 |
289 | |
290 | #define S_TIMEOUT 8 |
291 | #define M_TIMEOUT 0xffffff |
292 | #define V_TIMEOUT(x) ((x) << S_TIMEOUT) |
293 | |
294 | #define S_THRESHOLD 0 |
295 | #define M_THRESHOLD 0xff |
296 | #define V_THRESHOLD(x) ((x) << S_THRESHOLD) |
297 | |
298 | #define A_SG_TIMER_TICK 0x68 |
299 | |
300 | #define A_SG_CQ_CONTEXT_BADDR 0x6c |
301 | |
302 | #define A_SG_OCO_BASE 0x70 |
303 | |
304 | #define S_BASE1 16 |
305 | #define M_BASE1 0xffff |
306 | #define V_BASE1(x) ((x) << S_BASE1) |
307 | |
308 | #define A_SG_DRB_PRI_THRESH 0x74 |
309 | |
310 | #define A_PCIX_INT_ENABLE 0x80 |
311 | |
312 | #define S_MSIXPARERR 22 |
313 | #define M_MSIXPARERR 0x7 |
314 | |
315 | #define V_MSIXPARERR(x) ((x) << S_MSIXPARERR) |
316 | |
317 | #define S_CFPARERR 18 |
318 | #define M_CFPARERR 0xf |
319 | |
320 | #define V_CFPARERR(x) ((x) << S_CFPARERR) |
321 | |
322 | #define S_RFPARERR 14 |
323 | #define M_RFPARERR 0xf |
324 | |
325 | #define V_RFPARERR(x) ((x) << S_RFPARERR) |
326 | |
327 | #define S_WFPARERR 12 |
328 | #define M_WFPARERR 0x3 |
329 | |
330 | #define V_WFPARERR(x) ((x) << S_WFPARERR) |
331 | |
332 | #define S_PIOPARERR 11 |
333 | #define V_PIOPARERR(x) ((x) << S_PIOPARERR) |
334 | #define F_PIOPARERR V_PIOPARERR(1U) |
335 | |
336 | #define S_DETUNCECCERR 10 |
337 | #define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR) |
338 | #define F_DETUNCECCERR V_DETUNCECCERR(1U) |
339 | |
340 | #define S_DETCORECCERR 9 |
341 | #define V_DETCORECCERR(x) ((x) << S_DETCORECCERR) |
342 | #define F_DETCORECCERR V_DETCORECCERR(1U) |
343 | |
344 | #define S_RCVSPLCMPERR 8 |
345 | #define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR) |
346 | #define F_RCVSPLCMPERR V_RCVSPLCMPERR(1U) |
347 | |
348 | #define S_UNXSPLCMP 7 |
349 | #define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP) |
350 | #define F_UNXSPLCMP V_UNXSPLCMP(1U) |
351 | |
352 | #define S_SPLCMPDIS 6 |
353 | #define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS) |
354 | #define F_SPLCMPDIS V_SPLCMPDIS(1U) |
355 | |
356 | #define S_DETPARERR 5 |
357 | #define V_DETPARERR(x) ((x) << S_DETPARERR) |
358 | #define F_DETPARERR V_DETPARERR(1U) |
359 | |
360 | #define S_SIGSYSERR 4 |
361 | #define V_SIGSYSERR(x) ((x) << S_SIGSYSERR) |
362 | #define F_SIGSYSERR V_SIGSYSERR(1U) |
363 | |
364 | #define S_RCVMSTABT 3 |
365 | #define V_RCVMSTABT(x) ((x) << S_RCVMSTABT) |
366 | #define F_RCVMSTABT V_RCVMSTABT(1U) |
367 | |
368 | #define S_RCVTARABT 2 |
369 | #define V_RCVTARABT(x) ((x) << S_RCVTARABT) |
370 | #define F_RCVTARABT V_RCVTARABT(1U) |
371 | |
372 | #define S_SIGTARABT 1 |
373 | #define V_SIGTARABT(x) ((x) << S_SIGTARABT) |
374 | #define F_SIGTARABT V_SIGTARABT(1U) |
375 | |
376 | #define S_MSTDETPARERR 0 |
377 | #define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR) |
378 | #define F_MSTDETPARERR V_MSTDETPARERR(1U) |
379 | |
380 | #define A_PCIX_INT_CAUSE 0x84 |
381 | |
382 | #define A_PCIX_CFG 0x88 |
383 | |
384 | #define S_DMASTOPEN 19 |
385 | #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN) |
386 | #define F_DMASTOPEN V_DMASTOPEN(1U) |
387 | |
388 | #define S_CLIDECEN 18 |
389 | #define V_CLIDECEN(x) ((x) << S_CLIDECEN) |
390 | #define F_CLIDECEN V_CLIDECEN(1U) |
391 | |
392 | #define A_PCIX_MODE 0x8c |
393 | |
394 | #define S_PCLKRANGE 6 |
395 | #define M_PCLKRANGE 0x3 |
396 | #define V_PCLKRANGE(x) ((x) << S_PCLKRANGE) |
397 | #define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE) |
398 | |
399 | #define S_PCIXINITPAT 2 |
400 | #define M_PCIXINITPAT 0xf |
401 | #define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT) |
402 | #define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT) |
403 | |
404 | #define S_64BIT 0 |
405 | #define V_64BIT(x) ((x) << S_64BIT) |
406 | #define F_64BIT V_64BIT(1U) |
407 | |
408 | #define A_PCIE_INT_ENABLE 0x80 |
409 | |
410 | #define S_BISTERR 15 |
411 | #define M_BISTERR 0xff |
412 | |
413 | #define V_BISTERR(x) ((x) << S_BISTERR) |
414 | |
415 | #define S_TXPARERR 18 |
416 | #define V_TXPARERR(x) ((x) << S_TXPARERR) |
417 | #define F_TXPARERR V_TXPARERR(1U) |
418 | |
419 | #define S_RXPARERR 17 |
420 | #define V_RXPARERR(x) ((x) << S_RXPARERR) |
421 | #define F_RXPARERR V_RXPARERR(1U) |
422 | |
423 | #define S_RETRYLUTPARERR 16 |
424 | #define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR) |
425 | #define F_RETRYLUTPARERR V_RETRYLUTPARERR(1U) |
426 | |
427 | #define S_RETRYBUFPARERR 15 |
428 | #define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR) |
429 | #define F_RETRYBUFPARERR V_RETRYBUFPARERR(1U) |
430 | |
431 | #define S_PCIE_MSIXPARERR 12 |
432 | #define M_PCIE_MSIXPARERR 0x7 |
433 | |
434 | #define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR) |
435 | |
436 | #define S_PCIE_CFPARERR 11 |
437 | #define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR) |
438 | #define F_PCIE_CFPARERR V_PCIE_CFPARERR(1U) |
439 | |
440 | #define S_PCIE_RFPARERR 10 |
441 | #define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR) |
442 | #define F_PCIE_RFPARERR V_PCIE_RFPARERR(1U) |
443 | |
444 | #define S_PCIE_WFPARERR 9 |
445 | #define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR) |
446 | #define F_PCIE_WFPARERR V_PCIE_WFPARERR(1U) |
447 | |
448 | #define S_PCIE_PIOPARERR 8 |
449 | #define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR) |
450 | #define F_PCIE_PIOPARERR V_PCIE_PIOPARERR(1U) |
451 | |
452 | #define S_UNXSPLCPLERRC 7 |
453 | #define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC) |
454 | #define F_UNXSPLCPLERRC V_UNXSPLCPLERRC(1U) |
455 | |
456 | #define S_UNXSPLCPLERRR 6 |
457 | #define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR) |
458 | #define F_UNXSPLCPLERRR V_UNXSPLCPLERRR(1U) |
459 | |
460 | #define S_PEXERR 0 |
461 | #define V_PEXERR(x) ((x) << S_PEXERR) |
462 | #define F_PEXERR V_PEXERR(1U) |
463 | |
464 | #define A_PCIE_INT_CAUSE 0x84 |
465 | |
466 | #define S_PCIE_DMASTOPEN 24 |
467 | #define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN) |
468 | #define F_PCIE_DMASTOPEN V_PCIE_DMASTOPEN(1U) |
469 | |
470 | #define A_PCIE_CFG 0x88 |
471 | |
472 | #define S_ENABLELINKDWNDRST 21 |
473 | #define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST) |
474 | #define F_ENABLELINKDWNDRST V_ENABLELINKDWNDRST(1U) |
475 | |
476 | #define S_ENABLELINKDOWNRST 20 |
477 | #define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST) |
478 | #define F_ENABLELINKDOWNRST V_ENABLELINKDOWNRST(1U) |
479 | |
480 | #define S_PCIE_CLIDECEN 16 |
481 | #define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN) |
482 | #define F_PCIE_CLIDECEN V_PCIE_CLIDECEN(1U) |
483 | |
484 | #define S_CRSTWRMMODE 0 |
485 | #define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE) |
486 | #define F_CRSTWRMMODE V_CRSTWRMMODE(1U) |
487 | |
488 | #define A_PCIE_MODE 0x8c |
489 | |
490 | #define S_NUMFSTTRNSEQRX 10 |
491 | #define M_NUMFSTTRNSEQRX 0xff |
492 | #define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX) |
493 | #define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX) |
494 | |
495 | #define A_PCIE_PEX_CTRL0 0x98 |
496 | |
497 | #define S_NUMFSTTRNSEQ 22 |
498 | #define M_NUMFSTTRNSEQ 0xff |
499 | #define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ) |
500 | #define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ) |
501 | |
502 | #define S_REPLAYLMT 2 |
503 | #define M_REPLAYLMT 0xfffff |
504 | |
505 | #define V_REPLAYLMT(x) ((x) << S_REPLAYLMT) |
506 | |
507 | #define A_PCIE_PEX_CTRL1 0x9c |
508 | |
509 | #define S_T3A_ACKLAT 0 |
510 | #define M_T3A_ACKLAT 0x7ff |
511 | |
512 | #define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT) |
513 | |
514 | #define S_ACKLAT 0 |
515 | #define M_ACKLAT 0x1fff |
516 | |
517 | #define V_ACKLAT(x) ((x) << S_ACKLAT) |
518 | |
519 | #define A_PCIE_PEX_ERR 0xa4 |
520 | |
521 | #define A_T3DBG_GPIO_EN 0xd0 |
522 | |
523 | #define S_GPIO11_OEN 27 |
524 | #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN) |
525 | #define F_GPIO11_OEN V_GPIO11_OEN(1U) |
526 | |
527 | #define S_GPIO10_OEN 26 |
528 | #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN) |
529 | #define F_GPIO10_OEN V_GPIO10_OEN(1U) |
530 | |
531 | #define S_GPIO7_OEN 23 |
532 | #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN) |
533 | #define F_GPIO7_OEN V_GPIO7_OEN(1U) |
534 | |
535 | #define S_GPIO6_OEN 22 |
536 | #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN) |
537 | #define F_GPIO6_OEN V_GPIO6_OEN(1U) |
538 | |
539 | #define S_GPIO5_OEN 21 |
540 | #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN) |
541 | #define F_GPIO5_OEN V_GPIO5_OEN(1U) |
542 | |
543 | #define S_GPIO4_OEN 20 |
544 | #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN) |
545 | #define F_GPIO4_OEN V_GPIO4_OEN(1U) |
546 | |
547 | #define S_GPIO2_OEN 18 |
548 | #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN) |
549 | #define F_GPIO2_OEN V_GPIO2_OEN(1U) |
550 | |
551 | #define S_GPIO1_OEN 17 |
552 | #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN) |
553 | #define F_GPIO1_OEN V_GPIO1_OEN(1U) |
554 | |
555 | #define S_GPIO0_OEN 16 |
556 | #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN) |
557 | #define F_GPIO0_OEN V_GPIO0_OEN(1U) |
558 | |
559 | #define S_GPIO10_OUT_VAL 10 |
560 | #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL) |
561 | #define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U) |
562 | |
563 | #define S_GPIO7_OUT_VAL 7 |
564 | #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL) |
565 | #define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U) |
566 | |
567 | #define S_GPIO6_OUT_VAL 6 |
568 | #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL) |
569 | #define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U) |
570 | |
571 | #define S_GPIO5_OUT_VAL 5 |
572 | #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL) |
573 | #define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U) |
574 | |
575 | #define S_GPIO4_OUT_VAL 4 |
576 | #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL) |
577 | #define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U) |
578 | |
579 | #define S_GPIO2_OUT_VAL 2 |
580 | #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL) |
581 | #define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U) |
582 | |
583 | #define S_GPIO1_OUT_VAL 1 |
584 | #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL) |
585 | #define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U) |
586 | |
587 | #define S_GPIO0_OUT_VAL 0 |
588 | #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL) |
589 | #define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U) |
590 | |
591 | #define A_T3DBG_INT_ENABLE 0xd8 |
592 | |
593 | #define S_GPIO11 11 |
594 | #define V_GPIO11(x) ((x) << S_GPIO11) |
595 | #define F_GPIO11 V_GPIO11(1U) |
596 | |
597 | #define S_GPIO10 10 |
598 | #define V_GPIO10(x) ((x) << S_GPIO10) |
599 | #define F_GPIO10 V_GPIO10(1U) |
600 | |
601 | #define S_GPIO9 9 |
602 | #define V_GPIO9(x) ((x) << S_GPIO9) |
603 | #define F_GPIO9 V_GPIO9(1U) |
604 | |
605 | #define S_GPIO7 7 |
606 | #define V_GPIO7(x) ((x) << S_GPIO7) |
607 | #define F_GPIO7 V_GPIO7(1U) |
608 | |
609 | #define S_GPIO6 6 |
610 | #define V_GPIO6(x) ((x) << S_GPIO6) |
611 | #define F_GPIO6 V_GPIO6(1U) |
612 | |
613 | #define S_GPIO5 5 |
614 | #define V_GPIO5(x) ((x) << S_GPIO5) |
615 | #define F_GPIO5 V_GPIO5(1U) |
616 | |
617 | #define S_GPIO4 4 |
618 | #define V_GPIO4(x) ((x) << S_GPIO4) |
619 | #define F_GPIO4 V_GPIO4(1U) |
620 | |
621 | #define S_GPIO3 3 |
622 | #define V_GPIO3(x) ((x) << S_GPIO3) |
623 | #define F_GPIO3 V_GPIO3(1U) |
624 | |
625 | #define S_GPIO2 2 |
626 | #define V_GPIO2(x) ((x) << S_GPIO2) |
627 | #define F_GPIO2 V_GPIO2(1U) |
628 | |
629 | #define S_GPIO1 1 |
630 | #define V_GPIO1(x) ((x) << S_GPIO1) |
631 | #define F_GPIO1 V_GPIO1(1U) |
632 | |
633 | #define S_GPIO0 0 |
634 | #define V_GPIO0(x) ((x) << S_GPIO0) |
635 | #define F_GPIO0 V_GPIO0(1U) |
636 | |
637 | #define A_T3DBG_INT_CAUSE 0xdc |
638 | |
639 | #define A_T3DBG_GPIO_ACT_LOW 0xf0 |
640 | |
641 | #define MC7_PMRX_BASE_ADDR 0x100 |
642 | |
643 | #define A_MC7_CFG 0x100 |
644 | |
645 | #define S_IFEN 13 |
646 | #define V_IFEN(x) ((x) << S_IFEN) |
647 | #define F_IFEN V_IFEN(1U) |
648 | |
649 | #define S_TERM150 11 |
650 | #define V_TERM150(x) ((x) << S_TERM150) |
651 | #define F_TERM150 V_TERM150(1U) |
652 | |
653 | #define S_SLOW 10 |
654 | #define V_SLOW(x) ((x) << S_SLOW) |
655 | #define F_SLOW V_SLOW(1U) |
656 | |
657 | #define S_WIDTH 8 |
658 | #define M_WIDTH 0x3 |
659 | #define V_WIDTH(x) ((x) << S_WIDTH) |
660 | #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH) |
661 | |
662 | #define S_BKS 6 |
663 | #define V_BKS(x) ((x) << S_BKS) |
664 | #define F_BKS V_BKS(1U) |
665 | |
666 | #define S_ORG 5 |
667 | #define V_ORG(x) ((x) << S_ORG) |
668 | #define F_ORG V_ORG(1U) |
669 | |
670 | #define S_DEN 2 |
671 | #define M_DEN 0x7 |
672 | #define V_DEN(x) ((x) << S_DEN) |
673 | #define G_DEN(x) (((x) >> S_DEN) & M_DEN) |
674 | |
675 | #define S_RDY 1 |
676 | #define V_RDY(x) ((x) << S_RDY) |
677 | #define F_RDY V_RDY(1U) |
678 | |
679 | #define S_CLKEN 0 |
680 | #define V_CLKEN(x) ((x) << S_CLKEN) |
681 | #define F_CLKEN V_CLKEN(1U) |
682 | |
683 | #define A_MC7_MODE 0x104 |
684 | |
685 | #define S_BUSY 31 |
686 | #define V_BUSY(x) ((x) << S_BUSY) |
687 | #define F_BUSY V_BUSY(1U) |
688 | |
689 | #define A_MC7_EXT_MODE1 0x108 |
690 | |
691 | #define A_MC7_EXT_MODE2 0x10c |
692 | |
693 | #define A_MC7_EXT_MODE3 0x110 |
694 | |
695 | #define A_MC7_PRE 0x114 |
696 | |
697 | #define A_MC7_REF 0x118 |
698 | |
699 | #define S_PREREFDIV 1 |
700 | #define M_PREREFDIV 0x3fff |
701 | #define V_PREREFDIV(x) ((x) << S_PREREFDIV) |
702 | |
703 | #define S_PERREFEN 0 |
704 | #define V_PERREFEN(x) ((x) << S_PERREFEN) |
705 | #define F_PERREFEN V_PERREFEN(1U) |
706 | |
707 | #define A_MC7_DLL 0x11c |
708 | |
709 | #define S_DLLENB 1 |
710 | #define V_DLLENB(x) ((x) << S_DLLENB) |
711 | #define F_DLLENB V_DLLENB(1U) |
712 | |
713 | #define S_DLLRST 0 |
714 | #define V_DLLRST(x) ((x) << S_DLLRST) |
715 | #define F_DLLRST V_DLLRST(1U) |
716 | |
717 | #define A_MC7_PARM 0x120 |
718 | |
719 | #define S_ACTTOPREDLY 26 |
720 | #define M_ACTTOPREDLY 0xf |
721 | #define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY) |
722 | |
723 | #define S_ACTTORDWRDLY 23 |
724 | #define M_ACTTORDWRDLY 0x7 |
725 | #define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY) |
726 | |
727 | #define S_PRECYC 20 |
728 | #define M_PRECYC 0x7 |
729 | #define V_PRECYC(x) ((x) << S_PRECYC) |
730 | |
731 | #define S_REFCYC 13 |
732 | #define M_REFCYC 0x7f |
733 | #define V_REFCYC(x) ((x) << S_REFCYC) |
734 | |
735 | #define S_BKCYC 8 |
736 | #define M_BKCYC 0x1f |
737 | #define V_BKCYC(x) ((x) << S_BKCYC) |
738 | |
739 | #define S_WRTORDDLY 4 |
740 | #define M_WRTORDDLY 0xf |
741 | #define V_WRTORDDLY(x) ((x) << S_WRTORDDLY) |
742 | |
743 | #define S_RDTOWRDLY 0 |
744 | #define M_RDTOWRDLY 0xf |
745 | #define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY) |
746 | |
747 | #define A_MC7_CAL 0x128 |
748 | |
749 | #define S_CAL_FAULT 30 |
750 | #define V_CAL_FAULT(x) ((x) << S_CAL_FAULT) |
751 | #define F_CAL_FAULT V_CAL_FAULT(1U) |
752 | |
753 | #define S_SGL_CAL_EN 20 |
754 | #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN) |
755 | #define F_SGL_CAL_EN V_SGL_CAL_EN(1U) |
756 | |
757 | #define A_MC7_ERR_ADDR 0x12c |
758 | |
759 | #define A_MC7_ECC 0x130 |
760 | |
761 | #define S_ECCCHKEN 1 |
762 | #define V_ECCCHKEN(x) ((x) << S_ECCCHKEN) |
763 | #define F_ECCCHKEN V_ECCCHKEN(1U) |
764 | |
765 | #define S_ECCGENEN 0 |
766 | #define V_ECCGENEN(x) ((x) << S_ECCGENEN) |
767 | #define F_ECCGENEN V_ECCGENEN(1U) |
768 | |
769 | #define A_MC7_CE_ADDR 0x134 |
770 | |
771 | #define A_MC7_CE_DATA0 0x138 |
772 | |
773 | #define A_MC7_CE_DATA1 0x13c |
774 | |
775 | #define A_MC7_CE_DATA2 0x140 |
776 | |
777 | #define S_DATA 0 |
778 | #define M_DATA 0xff |
779 | |
780 | #define G_DATA(x) (((x) >> S_DATA) & M_DATA) |
781 | |
782 | #define A_MC7_UE_ADDR 0x144 |
783 | |
784 | #define A_MC7_UE_DATA0 0x148 |
785 | |
786 | #define A_MC7_UE_DATA1 0x14c |
787 | |
788 | #define A_MC7_UE_DATA2 0x150 |
789 | |
790 | #define A_MC7_BD_ADDR 0x154 |
791 | |
792 | #define S_ADDR 3 |
793 | |
794 | #define M_ADDR 0x1fffffff |
795 | |
796 | #define A_MC7_BD_DATA0 0x158 |
797 | |
798 | #define A_MC7_BD_DATA1 0x15c |
799 | |
800 | #define A_MC7_BD_OP 0x164 |
801 | |
802 | #define S_OP 0 |
803 | |
804 | #define V_OP(x) ((x) << S_OP) |
805 | #define F_OP V_OP(1U) |
806 | |
807 | #define A_MC7_BIST_ADDR_BEG 0x168 |
808 | |
809 | #define A_MC7_BIST_ADDR_END 0x16c |
810 | |
811 | #define A_MC7_BIST_DATA 0x170 |
812 | |
813 | #define A_MC7_BIST_OP 0x174 |
814 | |
815 | #define S_CONT 3 |
816 | #define V_CONT(x) ((x) << S_CONT) |
817 | #define F_CONT V_CONT(1U) |
818 | |
819 | #define A_MC7_INT_ENABLE 0x178 |
820 | |
821 | #define S_AE 17 |
822 | #define V_AE(x) ((x) << S_AE) |
823 | #define F_AE V_AE(1U) |
824 | |
825 | #define S_PE 2 |
826 | #define M_PE 0x7fff |
827 | |
828 | #define V_PE(x) ((x) << S_PE) |
829 | |
830 | #define G_PE(x) (((x) >> S_PE) & M_PE) |
831 | |
832 | #define S_UE 1 |
833 | #define V_UE(x) ((x) << S_UE) |
834 | #define F_UE V_UE(1U) |
835 | |
836 | #define S_CE 0 |
837 | #define V_CE(x) ((x) << S_CE) |
838 | #define F_CE V_CE(1U) |
839 | |
840 | #define A_MC7_INT_CAUSE 0x17c |
841 | |
842 | #define MC7_PMTX_BASE_ADDR 0x180 |
843 | |
844 | #define MC7_CM_BASE_ADDR 0x200 |
845 | |
846 | #define A_CIM_BOOT_CFG 0x280 |
847 | |
848 | #define S_BOOTADDR 2 |
849 | #define M_BOOTADDR 0x3fffffff |
850 | #define V_BOOTADDR(x) ((x) << S_BOOTADDR) |
851 | |
852 | #define A_CIM_SDRAM_BASE_ADDR 0x28c |
853 | |
854 | #define A_CIM_SDRAM_ADDR_SIZE 0x290 |
855 | |
856 | #define A_CIM_HOST_INT_ENABLE 0x298 |
857 | |
858 | #define S_DTAGPARERR 28 |
859 | #define V_DTAGPARERR(x) ((x) << S_DTAGPARERR) |
860 | #define F_DTAGPARERR V_DTAGPARERR(1U) |
861 | |
862 | #define S_ITAGPARERR 27 |
863 | #define V_ITAGPARERR(x) ((x) << S_ITAGPARERR) |
864 | #define F_ITAGPARERR V_ITAGPARERR(1U) |
865 | |
866 | #define S_IBQTPPARERR 26 |
867 | #define V_IBQTPPARERR(x) ((x) << S_IBQTPPARERR) |
868 | #define F_IBQTPPARERR V_IBQTPPARERR(1U) |
869 | |
870 | #define S_IBQULPPARERR 25 |
871 | #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR) |
872 | #define F_IBQULPPARERR V_IBQULPPARERR(1U) |
873 | |
874 | #define S_IBQSGEHIPARERR 24 |
875 | #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR) |
876 | #define F_IBQSGEHIPARERR V_IBQSGEHIPARERR(1U) |
877 | |
878 | #define S_IBQSGELOPARERR 23 |
879 | #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR) |
880 | #define F_IBQSGELOPARERR V_IBQSGELOPARERR(1U) |
881 | |
882 | #define S_OBQULPLOPARERR 22 |
883 | #define V_OBQULPLOPARERR(x) ((x) << S_OBQULPLOPARERR) |
884 | #define F_OBQULPLOPARERR V_OBQULPLOPARERR(1U) |
885 | |
886 | #define S_OBQULPHIPARERR 21 |
887 | #define V_OBQULPHIPARERR(x) ((x) << S_OBQULPHIPARERR) |
888 | #define F_OBQULPHIPARERR V_OBQULPHIPARERR(1U) |
889 | |
890 | #define S_OBQSGEPARERR 20 |
891 | #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR) |
892 | #define F_OBQSGEPARERR V_OBQSGEPARERR(1U) |
893 | |
894 | #define S_DCACHEPARERR 19 |
895 | #define V_DCACHEPARERR(x) ((x) << S_DCACHEPARERR) |
896 | #define F_DCACHEPARERR V_DCACHEPARERR(1U) |
897 | |
898 | #define S_ICACHEPARERR 18 |
899 | #define V_ICACHEPARERR(x) ((x) << S_ICACHEPARERR) |
900 | #define F_ICACHEPARERR V_ICACHEPARERR(1U) |
901 | |
902 | #define S_DRAMPARERR 17 |
903 | #define V_DRAMPARERR(x) ((x) << S_DRAMPARERR) |
904 | #define F_DRAMPARERR V_DRAMPARERR(1U) |
905 | |
906 | #define A_CIM_HOST_INT_CAUSE 0x29c |
907 | |
908 | #define S_BLKWRPLINT 12 |
909 | #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT) |
910 | #define F_BLKWRPLINT V_BLKWRPLINT(1U) |
911 | |
912 | #define S_BLKRDPLINT 11 |
913 | #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT) |
914 | #define F_BLKRDPLINT V_BLKRDPLINT(1U) |
915 | |
916 | #define S_BLKWRCTLINT 10 |
917 | #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT) |
918 | #define F_BLKWRCTLINT V_BLKWRCTLINT(1U) |
919 | |
920 | #define S_BLKRDCTLINT 9 |
921 | #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT) |
922 | #define F_BLKRDCTLINT V_BLKRDCTLINT(1U) |
923 | |
924 | #define S_BLKWRFLASHINT 8 |
925 | #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT) |
926 | #define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U) |
927 | |
928 | #define S_BLKRDFLASHINT 7 |
929 | #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT) |
930 | #define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U) |
931 | |
932 | #define S_SGLWRFLASHINT 6 |
933 | #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT) |
934 | #define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U) |
935 | |
936 | #define S_WRBLKFLASHINT 5 |
937 | #define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT) |
938 | #define F_WRBLKFLASHINT V_WRBLKFLASHINT(1U) |
939 | |
940 | #define S_BLKWRBOOTINT 4 |
941 | #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT) |
942 | #define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U) |
943 | |
944 | #define S_FLASHRANGEINT 2 |
945 | #define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT) |
946 | #define F_FLASHRANGEINT V_FLASHRANGEINT(1U) |
947 | |
948 | #define S_SDRAMRANGEINT 1 |
949 | #define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT) |
950 | #define F_SDRAMRANGEINT V_SDRAMRANGEINT(1U) |
951 | |
952 | #define S_RSVDSPACEINT 0 |
953 | #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT) |
954 | #define F_RSVDSPACEINT V_RSVDSPACEINT(1U) |
955 | |
956 | #define A_CIM_HOST_ACC_CTRL 0x2b0 |
957 | |
958 | #define S_HOSTBUSY 17 |
959 | #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY) |
960 | #define F_HOSTBUSY V_HOSTBUSY(1U) |
961 | |
962 | #define A_CIM_HOST_ACC_DATA 0x2b4 |
963 | |
964 | #define A_CIM_IBQ_DBG_CFG 0x2c0 |
965 | |
966 | #define S_IBQDBGADDR 16 |
967 | #define M_IBQDBGADDR 0x1ff |
968 | #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR) |
969 | #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR) |
970 | |
971 | #define S_IBQDBGQID 3 |
972 | #define M_IBQDBGQID 0x3 |
973 | #define V_IBQDBGQID(x) ((x) << S_IBQDBGQID) |
974 | #define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID) |
975 | |
976 | #define S_IBQDBGWR 2 |
977 | #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR) |
978 | #define F_IBQDBGWR V_IBQDBGWR(1U) |
979 | |
980 | #define S_IBQDBGBUSY 1 |
981 | #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY) |
982 | #define F_IBQDBGBUSY V_IBQDBGBUSY(1U) |
983 | |
984 | #define S_IBQDBGEN 0 |
985 | #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN) |
986 | #define F_IBQDBGEN V_IBQDBGEN(1U) |
987 | |
988 | #define A_CIM_IBQ_DBG_DATA 0x2c8 |
989 | |
990 | #define A_TP_IN_CONFIG 0x300 |
991 | |
992 | #define S_RXFBARBPRIO 25 |
993 | #define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO) |
994 | #define F_RXFBARBPRIO V_RXFBARBPRIO(1U) |
995 | |
996 | #define S_TXFBARBPRIO 24 |
997 | #define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO) |
998 | #define F_TXFBARBPRIO V_TXFBARBPRIO(1U) |
999 | |
1000 | #define S_NICMODE 14 |
1001 | #define V_NICMODE(x) ((x) << S_NICMODE) |
1002 | #define F_NICMODE V_NICMODE(1U) |
1003 | |
1004 | #define S_IPV6ENABLE 15 |
1005 | #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE) |
1006 | #define F_IPV6ENABLE V_IPV6ENABLE(1U) |
1007 | |
1008 | #define A_TP_OUT_CONFIG 0x304 |
1009 | |
1010 | #define 12 |
1011 | |
1012 | #define A_TP_GLOBAL_CONFIG 0x308 |
1013 | |
1014 | #define S_TXPACINGENABLE 24 |
1015 | #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE) |
1016 | #define F_TXPACINGENABLE V_TXPACINGENABLE(1U) |
1017 | |
1018 | #define S_PATHMTU 15 |
1019 | #define V_PATHMTU(x) ((x) << S_PATHMTU) |
1020 | #define F_PATHMTU V_PATHMTU(1U) |
1021 | |
1022 | #define S_IPCHECKSUMOFFLOAD 13 |
1023 | #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD) |
1024 | #define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U) |
1025 | |
1026 | #define S_UDPCHECKSUMOFFLOAD 12 |
1027 | #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD) |
1028 | #define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U) |
1029 | |
1030 | #define S_TCPCHECKSUMOFFLOAD 11 |
1031 | #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD) |
1032 | #define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U) |
1033 | |
1034 | #define S_IPTTL 0 |
1035 | #define M_IPTTL 0xff |
1036 | #define V_IPTTL(x) ((x) << S_IPTTL) |
1037 | |
1038 | #define A_TP_CMM_MM_BASE 0x314 |
1039 | |
1040 | #define A_TP_CMM_TIMER_BASE 0x318 |
1041 | |
1042 | #define S_CMTIMERMAXNUM 28 |
1043 | #define M_CMTIMERMAXNUM 0x3 |
1044 | #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM) |
1045 | |
1046 | #define A_TP_PMM_SIZE 0x31c |
1047 | |
1048 | #define A_TP_PMM_TX_BASE 0x320 |
1049 | |
1050 | #define A_TP_PMM_RX_BASE 0x328 |
1051 | |
1052 | #define A_TP_PMM_RX_PAGE_SIZE 0x32c |
1053 | |
1054 | #define A_TP_PMM_RX_MAX_PAGE 0x330 |
1055 | |
1056 | #define A_TP_PMM_TX_PAGE_SIZE 0x334 |
1057 | |
1058 | #define A_TP_PMM_TX_MAX_PAGE 0x338 |
1059 | |
1060 | #define A_TP_TCP_OPTIONS 0x340 |
1061 | |
1062 | #define S_MTUDEFAULT 16 |
1063 | #define M_MTUDEFAULT 0xffff |
1064 | #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT) |
1065 | |
1066 | #define S_MTUENABLE 10 |
1067 | #define V_MTUENABLE(x) ((x) << S_MTUENABLE) |
1068 | #define F_MTUENABLE V_MTUENABLE(1U) |
1069 | |
1070 | #define S_SACKRX 8 |
1071 | #define V_SACKRX(x) ((x) << S_SACKRX) |
1072 | #define F_SACKRX V_SACKRX(1U) |
1073 | |
1074 | #define S_SACKMODE 4 |
1075 | |
1076 | #define M_SACKMODE 0x3 |
1077 | |
1078 | #define V_SACKMODE(x) ((x) << S_SACKMODE) |
1079 | |
1080 | #define S_WINDOWSCALEMODE 2 |
1081 | #define M_WINDOWSCALEMODE 0x3 |
1082 | #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE) |
1083 | |
1084 | #define S_TIMESTAMPSMODE 0 |
1085 | |
1086 | #define M_TIMESTAMPSMODE 0x3 |
1087 | |
1088 | #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE) |
1089 | |
1090 | #define A_TP_DACK_CONFIG 0x344 |
1091 | |
1092 | #define S_AUTOSTATE3 30 |
1093 | #define M_AUTOSTATE3 0x3 |
1094 | #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3) |
1095 | |
1096 | #define S_AUTOSTATE2 28 |
1097 | #define M_AUTOSTATE2 0x3 |
1098 | #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2) |
1099 | |
1100 | #define S_AUTOSTATE1 26 |
1101 | #define M_AUTOSTATE1 0x3 |
1102 | #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1) |
1103 | |
1104 | #define S_BYTETHRESHOLD 5 |
1105 | #define M_BYTETHRESHOLD 0xfffff |
1106 | #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD) |
1107 | |
1108 | #define S_MSSTHRESHOLD 3 |
1109 | #define M_MSSTHRESHOLD 0x3 |
1110 | #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD) |
1111 | |
1112 | #define S_AUTOCAREFUL 2 |
1113 | #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL) |
1114 | #define F_AUTOCAREFUL V_AUTOCAREFUL(1U) |
1115 | |
1116 | #define S_AUTOENABLE 1 |
1117 | #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE) |
1118 | #define F_AUTOENABLE V_AUTOENABLE(1U) |
1119 | |
1120 | #define S_DACK_MODE 0 |
1121 | #define V_DACK_MODE(x) ((x) << S_DACK_MODE) |
1122 | #define F_DACK_MODE V_DACK_MODE(1U) |
1123 | |
1124 | #define A_TP_PC_CONFIG 0x348 |
1125 | |
1126 | #define S_TXTOSQUEUEMAPMODE 26 |
1127 | #define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE) |
1128 | #define F_TXTOSQUEUEMAPMODE V_TXTOSQUEUEMAPMODE(1U) |
1129 | |
1130 | #define S_ENABLEEPCMDAFULL 23 |
1131 | #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL) |
1132 | #define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U) |
1133 | |
1134 | #define S_MODULATEUNIONMODE 22 |
1135 | #define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE) |
1136 | #define F_MODULATEUNIONMODE V_MODULATEUNIONMODE(1U) |
1137 | |
1138 | #define S_TXDEFERENABLE 20 |
1139 | #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE) |
1140 | #define F_TXDEFERENABLE V_TXDEFERENABLE(1U) |
1141 | |
1142 | #define S_RXCONGESTIONMODE 19 |
1143 | #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE) |
1144 | #define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U) |
1145 | |
1146 | #define S_HEARBEATDACK 16 |
1147 | #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK) |
1148 | #define F_HEARBEATDACK V_HEARBEATDACK(1U) |
1149 | |
1150 | #define S_TXCONGESTIONMODE 15 |
1151 | #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE) |
1152 | #define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U) |
1153 | |
1154 | #define S_ENABLEOCSPIFULL 30 |
1155 | #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL) |
1156 | #define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U) |
1157 | |
1158 | #define S_LOCKTID 28 |
1159 | #define V_LOCKTID(x) ((x) << S_LOCKTID) |
1160 | #define F_LOCKTID V_LOCKTID(1U) |
1161 | |
1162 | #define S_TABLELATENCYDELTA 0 |
1163 | #define M_TABLELATENCYDELTA 0xf |
1164 | #define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA) |
1165 | #define G_TABLELATENCYDELTA(x) \ |
1166 | (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA) |
1167 | |
1168 | #define A_TP_PC_CONFIG2 0x34c |
1169 | |
1170 | #define S_DISBLEDAPARBIT0 15 |
1171 | #define V_DISBLEDAPARBIT0(x) ((x) << S_DISBLEDAPARBIT0) |
1172 | #define F_DISBLEDAPARBIT0 V_DISBLEDAPARBIT0(1U) |
1173 | |
1174 | #define S_ENABLEARPMISS 13 |
1175 | #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS) |
1176 | #define F_ENABLEARPMISS V_ENABLEARPMISS(1U) |
1177 | |
1178 | #define S_ENABLENONOFDTNLSYN 12 |
1179 | #define V_ENABLENONOFDTNLSYN(x) ((x) << S_ENABLENONOFDTNLSYN) |
1180 | #define F_ENABLENONOFDTNLSYN V_ENABLENONOFDTNLSYN(1U) |
1181 | |
1182 | #define 11 |
1183 | #define (x) ((x) << S_ENABLEIPV6RSS) |
1184 | #define V_ENABLEIPV6RSS(1U) |
1185 | |
1186 | #define S_CHDRAFULL 4 |
1187 | #define V_CHDRAFULL(x) ((x) << S_CHDRAFULL) |
1188 | #define F_CHDRAFULL V_CHDRAFULL(1U) |
1189 | |
1190 | #define A_TP_TCP_BACKOFF_REG0 0x350 |
1191 | |
1192 | #define A_TP_TCP_BACKOFF_REG1 0x354 |
1193 | |
1194 | #define A_TP_TCP_BACKOFF_REG2 0x358 |
1195 | |
1196 | #define A_TP_TCP_BACKOFF_REG3 0x35c |
1197 | |
1198 | #define A_TP_PARA_REG2 0x368 |
1199 | |
1200 | #define S_MAXRXDATA 16 |
1201 | #define M_MAXRXDATA 0xffff |
1202 | #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA) |
1203 | |
1204 | #define S_RXCOALESCESIZE 0 |
1205 | #define M_RXCOALESCESIZE 0xffff |
1206 | #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE) |
1207 | |
1208 | #define A_TP_PARA_REG3 0x36c |
1209 | |
1210 | #define S_TXDATAACKIDX 16 |
1211 | #define M_TXDATAACKIDX 0xf |
1212 | |
1213 | #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX) |
1214 | |
1215 | #define S_TXPACEAUTOSTRICT 10 |
1216 | #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT) |
1217 | #define F_TXPACEAUTOSTRICT V_TXPACEAUTOSTRICT(1U) |
1218 | |
1219 | #define S_TXPACEFIXED 9 |
1220 | #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED) |
1221 | #define F_TXPACEFIXED V_TXPACEFIXED(1U) |
1222 | |
1223 | #define S_TXPACEAUTO 8 |
1224 | #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO) |
1225 | #define F_TXPACEAUTO V_TXPACEAUTO(1U) |
1226 | |
1227 | #define S_RXCOALESCEENABLE 1 |
1228 | #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE) |
1229 | #define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U) |
1230 | |
1231 | #define S_RXCOALESCEPSHEN 0 |
1232 | #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN) |
1233 | #define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U) |
1234 | |
1235 | #define A_TP_PARA_REG4 0x370 |
1236 | |
1237 | #define A_TP_PARA_REG5 0x374 |
1238 | |
1239 | #define S_RXDDPOFFINIT 3 |
1240 | #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT) |
1241 | #define F_RXDDPOFFINIT V_RXDDPOFFINIT(1U) |
1242 | |
1243 | #define A_TP_PARA_REG6 0x378 |
1244 | |
1245 | #define S_T3A_ENABLEESND 13 |
1246 | #define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND) |
1247 | #define F_T3A_ENABLEESND V_T3A_ENABLEESND(1U) |
1248 | |
1249 | #define S_ENABLEESND 11 |
1250 | #define V_ENABLEESND(x) ((x) << S_ENABLEESND) |
1251 | #define F_ENABLEESND V_ENABLEESND(1U) |
1252 | |
1253 | #define A_TP_PARA_REG7 0x37c |
1254 | |
1255 | #define S_PMMAXXFERLEN1 16 |
1256 | #define M_PMMAXXFERLEN1 0xffff |
1257 | #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1) |
1258 | |
1259 | #define S_PMMAXXFERLEN0 0 |
1260 | #define M_PMMAXXFERLEN0 0xffff |
1261 | #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0) |
1262 | |
1263 | #define A_TP_TIMER_RESOLUTION 0x390 |
1264 | |
1265 | #define S_TIMERRESOLUTION 16 |
1266 | #define M_TIMERRESOLUTION 0xff |
1267 | #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION) |
1268 | |
1269 | #define S_TIMESTAMPRESOLUTION 8 |
1270 | #define M_TIMESTAMPRESOLUTION 0xff |
1271 | #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION) |
1272 | |
1273 | #define S_DELAYEDACKRESOLUTION 0 |
1274 | #define M_DELAYEDACKRESOLUTION 0xff |
1275 | #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION) |
1276 | |
1277 | #define A_TP_MSL 0x394 |
1278 | |
1279 | #define A_TP_RXT_MIN 0x398 |
1280 | |
1281 | #define A_TP_RXT_MAX 0x39c |
1282 | |
1283 | #define A_TP_PERS_MIN 0x3a0 |
1284 | |
1285 | #define A_TP_PERS_MAX 0x3a4 |
1286 | |
1287 | #define A_TP_KEEP_IDLE 0x3a8 |
1288 | |
1289 | #define A_TP_KEEP_INTVL 0x3ac |
1290 | |
1291 | #define A_TP_INIT_SRTT 0x3b0 |
1292 | |
1293 | #define A_TP_DACK_TIMER 0x3b4 |
1294 | |
1295 | #define A_TP_FINWAIT2_TIMER 0x3b8 |
1296 | |
1297 | #define A_TP_SHIFT_CNT 0x3c0 |
1298 | |
1299 | #define S_SYNSHIFTMAX 24 |
1300 | |
1301 | #define M_SYNSHIFTMAX 0xff |
1302 | |
1303 | #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX) |
1304 | |
1305 | #define S_RXTSHIFTMAXR1 20 |
1306 | |
1307 | #define M_RXTSHIFTMAXR1 0xf |
1308 | |
1309 | #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1) |
1310 | |
1311 | #define S_RXTSHIFTMAXR2 16 |
1312 | |
1313 | #define M_RXTSHIFTMAXR2 0xf |
1314 | |
1315 | #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2) |
1316 | |
1317 | #define S_PERSHIFTBACKOFFMAX 12 |
1318 | #define M_PERSHIFTBACKOFFMAX 0xf |
1319 | #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX) |
1320 | |
1321 | #define S_PERSHIFTMAX 8 |
1322 | #define M_PERSHIFTMAX 0xf |
1323 | #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX) |
1324 | |
1325 | #define S_KEEPALIVEMAX 0 |
1326 | |
1327 | #define M_KEEPALIVEMAX 0xff |
1328 | |
1329 | #define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX) |
1330 | |
1331 | #define A_TP_MTU_PORT_TABLE 0x3d0 |
1332 | |
1333 | #define A_TP_CCTRL_TABLE 0x3dc |
1334 | |
1335 | #define A_TP_MTU_TABLE 0x3e4 |
1336 | |
1337 | #define 0x3e8 |
1338 | |
1339 | #define 0x3ec |
1340 | |
1341 | #define 0x3f0 |
1342 | |
1343 | #define S_TNL4TUPEN 29 |
1344 | #define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN) |
1345 | #define F_TNL4TUPEN V_TNL4TUPEN(1U) |
1346 | |
1347 | #define S_TNL2TUPEN 28 |
1348 | #define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN) |
1349 | #define F_TNL2TUPEN V_TNL2TUPEN(1U) |
1350 | |
1351 | #define S_TNLPRTEN 26 |
1352 | #define V_TNLPRTEN(x) ((x) << S_TNLPRTEN) |
1353 | #define F_TNLPRTEN V_TNLPRTEN(1U) |
1354 | |
1355 | #define S_TNLMAPEN 25 |
1356 | #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN) |
1357 | #define F_TNLMAPEN V_TNLMAPEN(1U) |
1358 | |
1359 | #define S_TNLLKPEN 24 |
1360 | #define V_TNLLKPEN(x) ((x) << S_TNLLKPEN) |
1361 | #define F_TNLLKPEN V_TNLLKPEN(1U) |
1362 | |
1363 | #define S_RRCPLMAPEN 7 |
1364 | #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN) |
1365 | #define F_RRCPLMAPEN V_RRCPLMAPEN(1U) |
1366 | |
1367 | #define S_RRCPLCPUSIZE 4 |
1368 | #define M_RRCPLCPUSIZE 0x7 |
1369 | #define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE) |
1370 | |
1371 | #define S_RQFEEDBACKENABLE 3 |
1372 | #define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE) |
1373 | #define F_RQFEEDBACKENABLE V_RQFEEDBACKENABLE(1U) |
1374 | |
1375 | #define S_HASHTOEPLITZ 2 |
1376 | #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ) |
1377 | #define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U) |
1378 | |
1379 | #define S_DISABLE 0 |
1380 | |
1381 | #define A_TP_TM_PIO_ADDR 0x418 |
1382 | |
1383 | #define A_TP_TM_PIO_DATA 0x41c |
1384 | |
1385 | #define A_TP_TX_MOD_QUE_TABLE 0x420 |
1386 | |
1387 | #define A_TP_TX_RESOURCE_LIMIT 0x424 |
1388 | |
1389 | #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428 |
1390 | |
1391 | #define S_TX_MOD_QUEUE_REQ_MAP 0 |
1392 | #define M_TX_MOD_QUEUE_REQ_MAP 0xff |
1393 | #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) |
1394 | |
1395 | #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c |
1396 | |
1397 | #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430 |
1398 | |
1399 | #define A_TP_MOD_CHANNEL_WEIGHT 0x434 |
1400 | |
1401 | #define A_TP_MOD_RATE_LIMIT 0x438 |
1402 | |
1403 | #define A_TP_PIO_ADDR 0x440 |
1404 | |
1405 | #define A_TP_PIO_DATA 0x444 |
1406 | |
1407 | #define A_TP_RESET 0x44c |
1408 | |
1409 | #define S_FLSTINITENABLE 1 |
1410 | #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE) |
1411 | #define F_FLSTINITENABLE V_FLSTINITENABLE(1U) |
1412 | |
1413 | #define S_TPRESET 0 |
1414 | #define V_TPRESET(x) ((x) << S_TPRESET) |
1415 | #define F_TPRESET V_TPRESET(1U) |
1416 | |
1417 | #define A_TP_CMM_MM_RX_FLST_BASE 0x460 |
1418 | |
1419 | #define A_TP_CMM_MM_TX_FLST_BASE 0x464 |
1420 | |
1421 | #define A_TP_CMM_MM_PS_FLST_BASE 0x468 |
1422 | |
1423 | #define A_TP_MIB_INDEX 0x450 |
1424 | |
1425 | #define A_TP_MIB_RDATA 0x454 |
1426 | |
1427 | #define A_TP_CMM_MM_MAX_PSTRUCT 0x46c |
1428 | |
1429 | #define A_TP_INT_ENABLE 0x470 |
1430 | |
1431 | #define S_FLMTXFLSTEMPTY 30 |
1432 | #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY) |
1433 | #define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U) |
1434 | |
1435 | #define S_FLMRXFLSTEMPTY 29 |
1436 | #define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY) |
1437 | #define F_FLMRXFLSTEMPTY V_FLMRXFLSTEMPTY(1U) |
1438 | |
1439 | #define S_ARPLUTPERR 26 |
1440 | #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR) |
1441 | #define F_ARPLUTPERR V_ARPLUTPERR(1U) |
1442 | |
1443 | #define S_CMCACHEPERR 24 |
1444 | #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR) |
1445 | #define F_CMCACHEPERR V_CMCACHEPERR(1U) |
1446 | |
1447 | #define A_TP_INT_CAUSE 0x474 |
1448 | |
1449 | #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8 |
1450 | |
1451 | #define A_TP_TX_DROP_CFG_CH0 0x12b |
1452 | |
1453 | #define A_TP_TX_DROP_MODE 0x12f |
1454 | |
1455 | #define A_TP_EGRESS_CONFIG 0x145 |
1456 | |
1457 | #define S_REWRITEFORCETOSIZE 0 |
1458 | #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE) |
1459 | #define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U) |
1460 | |
1461 | #define A_TP_TX_TRC_KEY0 0x20 |
1462 | |
1463 | #define A_TP_RX_TRC_KEY0 0x120 |
1464 | |
1465 | #define A_TP_TX_DROP_CNT_CH0 0x12d |
1466 | |
1467 | #define S_TXDROPCNTCH0RCVD 0 |
1468 | #define M_TXDROPCNTCH0RCVD 0xffff |
1469 | #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD) |
1470 | #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \ |
1471 | M_TXDROPCNTCH0RCVD) |
1472 | |
1473 | #define A_TP_PROXY_FLOW_CNTL 0x4b0 |
1474 | |
1475 | #define A_TP_EMBED_OP_FIELD0 0x4e8 |
1476 | #define A_TP_EMBED_OP_FIELD1 0x4ec |
1477 | #define A_TP_EMBED_OP_FIELD2 0x4f0 |
1478 | #define A_TP_EMBED_OP_FIELD3 0x4f4 |
1479 | #define A_TP_EMBED_OP_FIELD4 0x4f8 |
1480 | #define A_TP_EMBED_OP_FIELD5 0x4fc |
1481 | |
1482 | #define A_ULPRX_CTL 0x500 |
1483 | |
1484 | #define S_ROUND_ROBIN 4 |
1485 | #define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN) |
1486 | #define F_ROUND_ROBIN V_ROUND_ROBIN(1U) |
1487 | |
1488 | #define A_ULPRX_INT_ENABLE 0x504 |
1489 | |
1490 | #define S_DATASELFRAMEERR0 7 |
1491 | #define V_DATASELFRAMEERR0(x) ((x) << S_DATASELFRAMEERR0) |
1492 | #define F_DATASELFRAMEERR0 V_DATASELFRAMEERR0(1U) |
1493 | |
1494 | #define S_DATASELFRAMEERR1 6 |
1495 | #define V_DATASELFRAMEERR1(x) ((x) << S_DATASELFRAMEERR1) |
1496 | #define F_DATASELFRAMEERR1 V_DATASELFRAMEERR1(1U) |
1497 | |
1498 | #define S_PCMDMUXPERR 5 |
1499 | #define V_PCMDMUXPERR(x) ((x) << S_PCMDMUXPERR) |
1500 | #define F_PCMDMUXPERR V_PCMDMUXPERR(1U) |
1501 | |
1502 | #define S_ARBFPERR 4 |
1503 | #define V_ARBFPERR(x) ((x) << S_ARBFPERR) |
1504 | #define F_ARBFPERR V_ARBFPERR(1U) |
1505 | |
1506 | #define S_ARBPF0PERR 3 |
1507 | #define V_ARBPF0PERR(x) ((x) << S_ARBPF0PERR) |
1508 | #define F_ARBPF0PERR V_ARBPF0PERR(1U) |
1509 | |
1510 | #define S_ARBPF1PERR 2 |
1511 | #define V_ARBPF1PERR(x) ((x) << S_ARBPF1PERR) |
1512 | #define F_ARBPF1PERR V_ARBPF1PERR(1U) |
1513 | |
1514 | #define S_PARERRPCMD 1 |
1515 | #define V_PARERRPCMD(x) ((x) << S_PARERRPCMD) |
1516 | #define F_PARERRPCMD V_PARERRPCMD(1U) |
1517 | |
1518 | #define S_PARERRDATA 0 |
1519 | #define V_PARERRDATA(x) ((x) << S_PARERRDATA) |
1520 | #define F_PARERRDATA V_PARERRDATA(1U) |
1521 | |
1522 | #define A_ULPRX_INT_CAUSE 0x508 |
1523 | |
1524 | #define A_ULPRX_ISCSI_LLIMIT 0x50c |
1525 | |
1526 | #define A_ULPRX_ISCSI_ULIMIT 0x510 |
1527 | |
1528 | #define A_ULPRX_ISCSI_TAGMASK 0x514 |
1529 | |
1530 | #define A_ULPRX_ISCSI_PSZ 0x518 |
1531 | |
1532 | #define A_ULPRX_TDDP_LLIMIT 0x51c |
1533 | |
1534 | #define A_ULPRX_TDDP_ULIMIT 0x520 |
1535 | #define A_ULPRX_TDDP_PSZ 0x528 |
1536 | |
1537 | #define S_HPZ0 0 |
1538 | #define M_HPZ0 0xf |
1539 | #define V_HPZ0(x) ((x) << S_HPZ0) |
1540 | #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0) |
1541 | |
1542 | #define A_ULPRX_STAG_LLIMIT 0x52c |
1543 | |
1544 | #define A_ULPRX_STAG_ULIMIT 0x530 |
1545 | |
1546 | #define A_ULPRX_RQ_LLIMIT 0x534 |
1547 | |
1548 | #define A_ULPRX_RQ_ULIMIT 0x538 |
1549 | |
1550 | #define A_ULPRX_PBL_LLIMIT 0x53c |
1551 | |
1552 | #define A_ULPRX_PBL_ULIMIT 0x540 |
1553 | |
1554 | #define A_ULPRX_TDDP_TAGMASK 0x524 |
1555 | |
1556 | #define A_ULPTX_CONFIG 0x580 |
1557 | |
1558 | #define S_CFG_CQE_SOP_MASK 1 |
1559 | #define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK) |
1560 | #define F_CFG_CQE_SOP_MASK V_CFG_CQE_SOP_MASK(1U) |
1561 | |
1562 | #define S_CFG_RR_ARB 0 |
1563 | #define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB) |
1564 | #define F_CFG_RR_ARB V_CFG_RR_ARB(1U) |
1565 | |
1566 | #define A_ULPTX_INT_ENABLE 0x584 |
1567 | |
1568 | #define S_PBL_BOUND_ERR_CH1 1 |
1569 | #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1) |
1570 | #define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U) |
1571 | |
1572 | #define S_PBL_BOUND_ERR_CH0 0 |
1573 | #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0) |
1574 | #define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U) |
1575 | |
1576 | #define A_ULPTX_INT_CAUSE 0x588 |
1577 | |
1578 | #define A_ULPTX_TPT_LLIMIT 0x58c |
1579 | |
1580 | #define A_ULPTX_TPT_ULIMIT 0x590 |
1581 | |
1582 | #define A_ULPTX_PBL_LLIMIT 0x594 |
1583 | |
1584 | #define A_ULPTX_PBL_ULIMIT 0x598 |
1585 | |
1586 | #define A_ULPTX_DMA_WEIGHT 0x5ac |
1587 | |
1588 | #define S_D1_WEIGHT 16 |
1589 | #define M_D1_WEIGHT 0xffff |
1590 | #define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT) |
1591 | |
1592 | #define S_D0_WEIGHT 0 |
1593 | #define M_D0_WEIGHT 0xffff |
1594 | #define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT) |
1595 | |
1596 | #define A_PM1_RX_CFG 0x5c0 |
1597 | #define A_PM1_RX_MODE 0x5c4 |
1598 | |
1599 | #define A_PM1_RX_INT_ENABLE 0x5d8 |
1600 | |
1601 | #define S_ZERO_E_CMD_ERROR 18 |
1602 | #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR) |
1603 | #define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U) |
1604 | |
1605 | #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 17 |
1606 | #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR) |
1607 | #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U) |
1608 | |
1609 | #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 16 |
1610 | #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR) |
1611 | #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U) |
1612 | |
1613 | #define S_IESPI0_RX_FRAMING_ERROR 15 |
1614 | #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR) |
1615 | #define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U) |
1616 | |
1617 | #define S_IESPI1_RX_FRAMING_ERROR 14 |
1618 | #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR) |
1619 | #define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U) |
1620 | |
1621 | #define S_IESPI0_TX_FRAMING_ERROR 13 |
1622 | #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR) |
1623 | #define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U) |
1624 | |
1625 | #define S_IESPI1_TX_FRAMING_ERROR 12 |
1626 | #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR) |
1627 | #define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U) |
1628 | |
1629 | #define S_OCSPI0_RX_FRAMING_ERROR 11 |
1630 | #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR) |
1631 | #define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U) |
1632 | |
1633 | #define S_OCSPI1_RX_FRAMING_ERROR 10 |
1634 | #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR) |
1635 | #define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U) |
1636 | |
1637 | #define S_OCSPI0_TX_FRAMING_ERROR 9 |
1638 | #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR) |
1639 | #define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U) |
1640 | |
1641 | #define S_OCSPI1_TX_FRAMING_ERROR 8 |
1642 | #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR) |
1643 | #define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U) |
1644 | |
1645 | #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 7 |
1646 | #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR) |
1647 | #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U) |
1648 | |
1649 | #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 6 |
1650 | #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR) |
1651 | #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U) |
1652 | |
1653 | #define S_IESPI_PAR_ERROR 3 |
1654 | #define M_IESPI_PAR_ERROR 0x7 |
1655 | |
1656 | #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR) |
1657 | |
1658 | #define S_OCSPI_PAR_ERROR 0 |
1659 | #define M_OCSPI_PAR_ERROR 0x7 |
1660 | |
1661 | #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR) |
1662 | |
1663 | #define A_PM1_RX_INT_CAUSE 0x5dc |
1664 | |
1665 | #define A_PM1_TX_CFG 0x5e0 |
1666 | #define A_PM1_TX_MODE 0x5e4 |
1667 | |
1668 | #define A_PM1_TX_INT_ENABLE 0x5f8 |
1669 | |
1670 | #define S_ZERO_C_CMD_ERROR 18 |
1671 | #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR) |
1672 | #define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U) |
1673 | |
1674 | #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 17 |
1675 | #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR) |
1676 | #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U) |
1677 | |
1678 | #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 16 |
1679 | #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR) |
1680 | #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U) |
1681 | |
1682 | #define S_ICSPI0_RX_FRAMING_ERROR 15 |
1683 | #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR) |
1684 | #define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U) |
1685 | |
1686 | #define S_ICSPI1_RX_FRAMING_ERROR 14 |
1687 | #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR) |
1688 | #define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U) |
1689 | |
1690 | #define S_ICSPI0_TX_FRAMING_ERROR 13 |
1691 | #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR) |
1692 | #define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U) |
1693 | |
1694 | #define S_ICSPI1_TX_FRAMING_ERROR 12 |
1695 | #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR) |
1696 | #define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U) |
1697 | |
1698 | #define S_OESPI0_RX_FRAMING_ERROR 11 |
1699 | #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR) |
1700 | #define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U) |
1701 | |
1702 | #define S_OESPI1_RX_FRAMING_ERROR 10 |
1703 | #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR) |
1704 | #define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U) |
1705 | |
1706 | #define S_OESPI0_TX_FRAMING_ERROR 9 |
1707 | #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR) |
1708 | #define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U) |
1709 | |
1710 | #define S_OESPI1_TX_FRAMING_ERROR 8 |
1711 | #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR) |
1712 | #define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U) |
1713 | |
1714 | #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7 |
1715 | #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR) |
1716 | #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U) |
1717 | |
1718 | #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6 |
1719 | #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR) |
1720 | #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U) |
1721 | |
1722 | #define S_ICSPI_PAR_ERROR 3 |
1723 | #define M_ICSPI_PAR_ERROR 0x7 |
1724 | |
1725 | #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR) |
1726 | |
1727 | #define S_OESPI_PAR_ERROR 0 |
1728 | #define M_OESPI_PAR_ERROR 0x7 |
1729 | |
1730 | #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR) |
1731 | |
1732 | #define A_PM1_TX_INT_CAUSE 0x5fc |
1733 | |
1734 | #define A_MPS_CFG 0x600 |
1735 | |
1736 | #define S_TPRXPORTEN 4 |
1737 | #define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN) |
1738 | #define F_TPRXPORTEN V_TPRXPORTEN(1U) |
1739 | |
1740 | #define S_TPTXPORT1EN 3 |
1741 | #define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN) |
1742 | #define F_TPTXPORT1EN V_TPTXPORT1EN(1U) |
1743 | |
1744 | #define S_TPTXPORT0EN 2 |
1745 | #define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN) |
1746 | #define F_TPTXPORT0EN V_TPTXPORT0EN(1U) |
1747 | |
1748 | #define S_PORT1ACTIVE 1 |
1749 | #define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE) |
1750 | #define F_PORT1ACTIVE V_PORT1ACTIVE(1U) |
1751 | |
1752 | #define S_PORT0ACTIVE 0 |
1753 | #define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE) |
1754 | #define F_PORT0ACTIVE V_PORT0ACTIVE(1U) |
1755 | |
1756 | #define S_ENFORCEPKT 11 |
1757 | #define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT) |
1758 | #define F_ENFORCEPKT V_ENFORCEPKT(1U) |
1759 | |
1760 | #define A_MPS_INT_ENABLE 0x61c |
1761 | |
1762 | #define S_MCAPARERRENB 6 |
1763 | #define M_MCAPARERRENB 0x7 |
1764 | |
1765 | #define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB) |
1766 | |
1767 | #define S_RXTPPARERRENB 4 |
1768 | #define M_RXTPPARERRENB 0x3 |
1769 | |
1770 | #define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB) |
1771 | |
1772 | #define S_TX1TPPARERRENB 2 |
1773 | #define M_TX1TPPARERRENB 0x3 |
1774 | |
1775 | #define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB) |
1776 | |
1777 | #define S_TX0TPPARERRENB 0 |
1778 | #define M_TX0TPPARERRENB 0x3 |
1779 | |
1780 | #define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB) |
1781 | |
1782 | #define A_MPS_INT_CAUSE 0x620 |
1783 | |
1784 | #define S_MCAPARERR 6 |
1785 | #define M_MCAPARERR 0x7 |
1786 | |
1787 | #define V_MCAPARERR(x) ((x) << S_MCAPARERR) |
1788 | |
1789 | #define S_RXTPPARERR 4 |
1790 | #define M_RXTPPARERR 0x3 |
1791 | |
1792 | #define V_RXTPPARERR(x) ((x) << S_RXTPPARERR) |
1793 | |
1794 | #define S_TX1TPPARERR 2 |
1795 | #define M_TX1TPPARERR 0x3 |
1796 | |
1797 | #define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR) |
1798 | |
1799 | #define S_TX0TPPARERR 0 |
1800 | #define M_TX0TPPARERR 0x3 |
1801 | |
1802 | #define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR) |
1803 | |
1804 | #define A_CPL_SWITCH_CNTRL 0x640 |
1805 | |
1806 | #define A_CPL_INTR_ENABLE 0x650 |
1807 | |
1808 | #define S_CIM_OP_MAP_PERR 5 |
1809 | #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR) |
1810 | #define F_CIM_OP_MAP_PERR V_CIM_OP_MAP_PERR(1U) |
1811 | |
1812 | #define S_CIM_OVFL_ERROR 4 |
1813 | #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR) |
1814 | #define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U) |
1815 | |
1816 | #define S_TP_FRAMING_ERROR 3 |
1817 | #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR) |
1818 | #define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U) |
1819 | |
1820 | #define S_SGE_FRAMING_ERROR 2 |
1821 | #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR) |
1822 | #define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U) |
1823 | |
1824 | #define S_CIM_FRAMING_ERROR 1 |
1825 | #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR) |
1826 | #define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U) |
1827 | |
1828 | #define S_ZERO_SWITCH_ERROR 0 |
1829 | #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR) |
1830 | #define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U) |
1831 | |
1832 | #define A_CPL_INTR_CAUSE 0x654 |
1833 | |
1834 | #define A_CPL_MAP_TBL_DATA 0x65c |
1835 | |
1836 | #define A_SMB_GLOBAL_TIME_CFG 0x660 |
1837 | |
1838 | #define A_I2C_CFG 0x6a0 |
1839 | |
1840 | #define S_I2C_CLKDIV 0 |
1841 | #define M_I2C_CLKDIV 0xfff |
1842 | #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV) |
1843 | |
1844 | #define A_MI1_CFG 0x6b0 |
1845 | |
1846 | #define S_CLKDIV 5 |
1847 | #define M_CLKDIV 0xff |
1848 | #define V_CLKDIV(x) ((x) << S_CLKDIV) |
1849 | |
1850 | #define S_ST 3 |
1851 | |
1852 | #define M_ST 0x3 |
1853 | |
1854 | #define V_ST(x) ((x) << S_ST) |
1855 | |
1856 | #define G_ST(x) (((x) >> S_ST) & M_ST) |
1857 | |
1858 | #define S_PREEN 2 |
1859 | #define V_PREEN(x) ((x) << S_PREEN) |
1860 | #define F_PREEN V_PREEN(1U) |
1861 | |
1862 | #define S_MDIINV 1 |
1863 | #define V_MDIINV(x) ((x) << S_MDIINV) |
1864 | #define F_MDIINV V_MDIINV(1U) |
1865 | |
1866 | #define S_MDIEN 0 |
1867 | #define V_MDIEN(x) ((x) << S_MDIEN) |
1868 | #define F_MDIEN V_MDIEN(1U) |
1869 | |
1870 | #define A_MI1_ADDR 0x6b4 |
1871 | |
1872 | #define S_PHYADDR 5 |
1873 | #define M_PHYADDR 0x1f |
1874 | #define V_PHYADDR(x) ((x) << S_PHYADDR) |
1875 | |
1876 | #define S_REGADDR 0 |
1877 | #define M_REGADDR 0x1f |
1878 | #define V_REGADDR(x) ((x) << S_REGADDR) |
1879 | |
1880 | #define A_MI1_DATA 0x6b8 |
1881 | |
1882 | #define A_MI1_OP 0x6bc |
1883 | |
1884 | #define S_MDI_OP 0 |
1885 | #define M_MDI_OP 0x3 |
1886 | #define V_MDI_OP(x) ((x) << S_MDI_OP) |
1887 | |
1888 | #define A_SF_DATA 0x6d8 |
1889 | |
1890 | #define A_SF_OP 0x6dc |
1891 | |
1892 | #define S_BYTECNT 1 |
1893 | #define M_BYTECNT 0x3 |
1894 | #define V_BYTECNT(x) ((x) << S_BYTECNT) |
1895 | |
1896 | #define A_PL_INT_ENABLE0 0x6e0 |
1897 | |
1898 | #define S_T3DBG 23 |
1899 | #define V_T3DBG(x) ((x) << S_T3DBG) |
1900 | #define F_T3DBG V_T3DBG(1U) |
1901 | |
1902 | #define S_XGMAC0_1 20 |
1903 | #define V_XGMAC0_1(x) ((x) << S_XGMAC0_1) |
1904 | #define F_XGMAC0_1 V_XGMAC0_1(1U) |
1905 | |
1906 | #define S_XGMAC0_0 19 |
1907 | #define V_XGMAC0_0(x) ((x) << S_XGMAC0_0) |
1908 | #define F_XGMAC0_0 V_XGMAC0_0(1U) |
1909 | |
1910 | #define S_MC5A 18 |
1911 | #define V_MC5A(x) ((x) << S_MC5A) |
1912 | #define F_MC5A V_MC5A(1U) |
1913 | |
1914 | #define S_CPL_SWITCH 12 |
1915 | #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH) |
1916 | #define F_CPL_SWITCH V_CPL_SWITCH(1U) |
1917 | |
1918 | #define S_MPS0 11 |
1919 | #define V_MPS0(x) ((x) << S_MPS0) |
1920 | #define F_MPS0 V_MPS0(1U) |
1921 | |
1922 | #define S_PM1_TX 10 |
1923 | #define V_PM1_TX(x) ((x) << S_PM1_TX) |
1924 | #define F_PM1_TX V_PM1_TX(1U) |
1925 | |
1926 | #define S_PM1_RX 9 |
1927 | #define V_PM1_RX(x) ((x) << S_PM1_RX) |
1928 | #define F_PM1_RX V_PM1_RX(1U) |
1929 | |
1930 | #define S_ULP2_TX 8 |
1931 | #define V_ULP2_TX(x) ((x) << S_ULP2_TX) |
1932 | #define F_ULP2_TX V_ULP2_TX(1U) |
1933 | |
1934 | #define S_ULP2_RX 7 |
1935 | #define V_ULP2_RX(x) ((x) << S_ULP2_RX) |
1936 | #define F_ULP2_RX V_ULP2_RX(1U) |
1937 | |
1938 | #define S_TP1 6 |
1939 | #define V_TP1(x) ((x) << S_TP1) |
1940 | #define F_TP1 V_TP1(1U) |
1941 | |
1942 | #define S_CIM 5 |
1943 | #define V_CIM(x) ((x) << S_CIM) |
1944 | #define F_CIM V_CIM(1U) |
1945 | |
1946 | #define S_MC7_CM 4 |
1947 | #define V_MC7_CM(x) ((x) << S_MC7_CM) |
1948 | #define F_MC7_CM V_MC7_CM(1U) |
1949 | |
1950 | #define S_MC7_PMTX 3 |
1951 | #define V_MC7_PMTX(x) ((x) << S_MC7_PMTX) |
1952 | #define F_MC7_PMTX V_MC7_PMTX(1U) |
1953 | |
1954 | #define S_MC7_PMRX 2 |
1955 | #define V_MC7_PMRX(x) ((x) << S_MC7_PMRX) |
1956 | #define F_MC7_PMRX V_MC7_PMRX(1U) |
1957 | |
1958 | #define S_PCIM0 1 |
1959 | #define V_PCIM0(x) ((x) << S_PCIM0) |
1960 | #define F_PCIM0 V_PCIM0(1U) |
1961 | |
1962 | #define S_SGE3 0 |
1963 | #define V_SGE3(x) ((x) << S_SGE3) |
1964 | #define F_SGE3 V_SGE3(1U) |
1965 | |
1966 | #define A_PL_INT_CAUSE0 0x6e4 |
1967 | |
1968 | #define A_PL_RST 0x6f0 |
1969 | |
1970 | #define S_FATALPERREN 4 |
1971 | #define V_FATALPERREN(x) ((x) << S_FATALPERREN) |
1972 | #define F_FATALPERREN V_FATALPERREN(1U) |
1973 | |
1974 | #define S_CRSTWRM 1 |
1975 | #define V_CRSTWRM(x) ((x) << S_CRSTWRM) |
1976 | #define F_CRSTWRM V_CRSTWRM(1U) |
1977 | |
1978 | #define A_PL_REV 0x6f4 |
1979 | |
1980 | #define A_PL_CLI 0x6f8 |
1981 | |
1982 | #define A_MC5_DB_CONFIG 0x704 |
1983 | |
1984 | #define S_TMTYPEHI 30 |
1985 | #define V_TMTYPEHI(x) ((x) << S_TMTYPEHI) |
1986 | #define F_TMTYPEHI V_TMTYPEHI(1U) |
1987 | |
1988 | #define S_TMPARTSIZE 28 |
1989 | #define M_TMPARTSIZE 0x3 |
1990 | #define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE) |
1991 | #define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE) |
1992 | |
1993 | #define S_TMTYPE 26 |
1994 | #define M_TMTYPE 0x3 |
1995 | #define V_TMTYPE(x) ((x) << S_TMTYPE) |
1996 | #define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE) |
1997 | |
1998 | #define S_COMPEN 17 |
1999 | #define V_COMPEN(x) ((x) << S_COMPEN) |
2000 | #define F_COMPEN V_COMPEN(1U) |
2001 | |
2002 | #define S_PRTYEN 6 |
2003 | #define V_PRTYEN(x) ((x) << S_PRTYEN) |
2004 | #define F_PRTYEN V_PRTYEN(1U) |
2005 | |
2006 | #define S_MBUSEN 5 |
2007 | #define V_MBUSEN(x) ((x) << S_MBUSEN) |
2008 | #define F_MBUSEN V_MBUSEN(1U) |
2009 | |
2010 | #define S_DBGIEN 4 |
2011 | #define V_DBGIEN(x) ((x) << S_DBGIEN) |
2012 | #define F_DBGIEN V_DBGIEN(1U) |
2013 | |
2014 | #define S_TMRDY 2 |
2015 | #define V_TMRDY(x) ((x) << S_TMRDY) |
2016 | #define F_TMRDY V_TMRDY(1U) |
2017 | |
2018 | #define S_TMRST 1 |
2019 | #define V_TMRST(x) ((x) << S_TMRST) |
2020 | #define F_TMRST V_TMRST(1U) |
2021 | |
2022 | #define S_TMMODE 0 |
2023 | #define V_TMMODE(x) ((x) << S_TMMODE) |
2024 | #define F_TMMODE V_TMMODE(1U) |
2025 | |
2026 | #define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c |
2027 | |
2028 | #define A_MC5_DB_FILTER_TABLE 0x710 |
2029 | |
2030 | #define A_MC5_DB_SERVER_INDEX 0x714 |
2031 | |
2032 | #define A_MC5_DB_RSP_LATENCY 0x720 |
2033 | |
2034 | #define S_RDLAT 16 |
2035 | #define M_RDLAT 0x1f |
2036 | #define V_RDLAT(x) ((x) << S_RDLAT) |
2037 | |
2038 | #define S_LRNLAT 8 |
2039 | #define M_LRNLAT 0x1f |
2040 | #define V_LRNLAT(x) ((x) << S_LRNLAT) |
2041 | |
2042 | #define S_SRCHLAT 0 |
2043 | #define M_SRCHLAT 0x1f |
2044 | #define V_SRCHLAT(x) ((x) << S_SRCHLAT) |
2045 | |
2046 | #define A_MC5_DB_PART_ID_INDEX 0x72c |
2047 | |
2048 | #define A_MC5_DB_INT_ENABLE 0x740 |
2049 | |
2050 | #define S_DELACTEMPTY 18 |
2051 | #define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY) |
2052 | #define F_DELACTEMPTY V_DELACTEMPTY(1U) |
2053 | |
2054 | #define S_DISPQPARERR 17 |
2055 | #define V_DISPQPARERR(x) ((x) << S_DISPQPARERR) |
2056 | #define F_DISPQPARERR V_DISPQPARERR(1U) |
2057 | |
2058 | #define S_REQQPARERR 16 |
2059 | #define V_REQQPARERR(x) ((x) << S_REQQPARERR) |
2060 | #define F_REQQPARERR V_REQQPARERR(1U) |
2061 | |
2062 | #define S_UNKNOWNCMD 15 |
2063 | #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD) |
2064 | #define F_UNKNOWNCMD V_UNKNOWNCMD(1U) |
2065 | |
2066 | #define S_NFASRCHFAIL 8 |
2067 | #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL) |
2068 | #define F_NFASRCHFAIL V_NFASRCHFAIL(1U) |
2069 | |
2070 | #define S_ACTRGNFULL 7 |
2071 | #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL) |
2072 | #define F_ACTRGNFULL V_ACTRGNFULL(1U) |
2073 | |
2074 | #define S_PARITYERR 6 |
2075 | #define V_PARITYERR(x) ((x) << S_PARITYERR) |
2076 | #define F_PARITYERR V_PARITYERR(1U) |
2077 | |
2078 | #define A_MC5_DB_INT_CAUSE 0x744 |
2079 | |
2080 | #define A_MC5_DB_DBGI_CONFIG 0x774 |
2081 | |
2082 | #define A_MC5_DB_DBGI_REQ_CMD 0x778 |
2083 | |
2084 | #define A_MC5_DB_DBGI_REQ_ADDR0 0x77c |
2085 | |
2086 | #define A_MC5_DB_DBGI_REQ_ADDR1 0x780 |
2087 | |
2088 | #define A_MC5_DB_DBGI_REQ_ADDR2 0x784 |
2089 | |
2090 | #define A_MC5_DB_DBGI_REQ_DATA0 0x788 |
2091 | |
2092 | #define A_MC5_DB_DBGI_REQ_DATA1 0x78c |
2093 | |
2094 | #define A_MC5_DB_DBGI_REQ_DATA2 0x790 |
2095 | |
2096 | #define A_MC5_DB_DBGI_RSP_STATUS 0x7b0 |
2097 | |
2098 | #define S_DBGIRSPVALID 0 |
2099 | #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID) |
2100 | #define F_DBGIRSPVALID V_DBGIRSPVALID(1U) |
2101 | |
2102 | #define A_MC5_DB_DBGI_RSP_DATA0 0x7b4 |
2103 | |
2104 | #define A_MC5_DB_DBGI_RSP_DATA1 0x7b8 |
2105 | |
2106 | #define A_MC5_DB_DBGI_RSP_DATA2 0x7bc |
2107 | |
2108 | #define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc |
2109 | |
2110 | #define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0 |
2111 | |
2112 | #define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4 |
2113 | |
2114 | #define A_MC5_DB_AOPEN_LRN_CMD 0x7d8 |
2115 | |
2116 | #define A_MC5_DB_SYN_SRCH_CMD 0x7dc |
2117 | |
2118 | #define A_MC5_DB_SYN_LRN_CMD 0x7e0 |
2119 | |
2120 | #define A_MC5_DB_ACK_SRCH_CMD 0x7e4 |
2121 | |
2122 | #define A_MC5_DB_ACK_LRN_CMD 0x7e8 |
2123 | |
2124 | #define A_MC5_DB_ILOOKUP_CMD 0x7ec |
2125 | |
2126 | #define A_MC5_DB_ELOOKUP_CMD 0x7f0 |
2127 | |
2128 | #define A_MC5_DB_DATA_WRITE_CMD 0x7f4 |
2129 | |
2130 | #define A_MC5_DB_DATA_READ_CMD 0x7f8 |
2131 | |
2132 | #define XGMAC0_0_BASE_ADDR 0x800 |
2133 | |
2134 | #define A_XGM_TX_CTRL 0x800 |
2135 | |
2136 | #define S_TXEN 0 |
2137 | #define V_TXEN(x) ((x) << S_TXEN) |
2138 | #define F_TXEN V_TXEN(1U) |
2139 | |
2140 | #define A_XGM_TX_CFG 0x804 |
2141 | |
2142 | #define S_TXPAUSEEN 0 |
2143 | #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN) |
2144 | #define F_TXPAUSEEN V_TXPAUSEEN(1U) |
2145 | |
2146 | #define A_XGM_TX_PAUSE_QUANTA 0x808 |
2147 | |
2148 | #define A_XGM_RX_CTRL 0x80c |
2149 | |
2150 | #define S_RXEN 0 |
2151 | #define V_RXEN(x) ((x) << S_RXEN) |
2152 | #define F_RXEN V_RXEN(1U) |
2153 | |
2154 | #define A_XGM_RX_CFG 0x810 |
2155 | |
2156 | #define S_DISPAUSEFRAMES 9 |
2157 | #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES) |
2158 | #define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U) |
2159 | |
2160 | #define S_EN1536BFRAMES 8 |
2161 | #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES) |
2162 | #define F_EN1536BFRAMES V_EN1536BFRAMES(1U) |
2163 | |
2164 | #define S_ENJUMBO 7 |
2165 | #define V_ENJUMBO(x) ((x) << S_ENJUMBO) |
2166 | #define F_ENJUMBO V_ENJUMBO(1U) |
2167 | |
2168 | #define S_RMFCS 6 |
2169 | #define V_RMFCS(x) ((x) << S_RMFCS) |
2170 | #define F_RMFCS V_RMFCS(1U) |
2171 | |
2172 | #define S_ENHASHMCAST 2 |
2173 | #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST) |
2174 | #define F_ENHASHMCAST V_ENHASHMCAST(1U) |
2175 | |
2176 | #define S_COPYALLFRAMES 0 |
2177 | #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES) |
2178 | #define F_COPYALLFRAMES V_COPYALLFRAMES(1U) |
2179 | |
2180 | #define S_DISBCAST 1 |
2181 | #define V_DISBCAST(x) ((x) << S_DISBCAST) |
2182 | #define F_DISBCAST V_DISBCAST(1U) |
2183 | |
2184 | #define A_XGM_RX_HASH_LOW 0x814 |
2185 | |
2186 | #define A_XGM_RX_HASH_HIGH 0x818 |
2187 | |
2188 | #define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c |
2189 | |
2190 | #define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820 |
2191 | |
2192 | #define A_XGM_RX_EXACT_MATCH_LOW_2 0x824 |
2193 | |
2194 | #define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c |
2195 | |
2196 | #define A_XGM_RX_EXACT_MATCH_LOW_4 0x834 |
2197 | |
2198 | #define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c |
2199 | |
2200 | #define A_XGM_RX_EXACT_MATCH_LOW_6 0x844 |
2201 | |
2202 | #define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c |
2203 | |
2204 | #define A_XGM_RX_EXACT_MATCH_LOW_8 0x854 |
2205 | |
2206 | #define A_XGM_INT_STATUS 0x86c |
2207 | |
2208 | #define S_LINKFAULTCHANGE 9 |
2209 | #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE) |
2210 | #define F_LINKFAULTCHANGE V_LINKFAULTCHANGE(1U) |
2211 | |
2212 | #define A_XGM_XGM_INT_ENABLE 0x874 |
2213 | #define A_XGM_XGM_INT_DISABLE 0x878 |
2214 | |
2215 | #define A_XGM_STAT_CTRL 0x880 |
2216 | |
2217 | #define S_CLRSTATS 2 |
2218 | #define V_CLRSTATS(x) ((x) << S_CLRSTATS) |
2219 | #define F_CLRSTATS V_CLRSTATS(1U) |
2220 | |
2221 | #define A_XGM_RXFIFO_CFG 0x884 |
2222 | |
2223 | #define S_RXFIFO_EMPTY 31 |
2224 | #define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY) |
2225 | #define F_RXFIFO_EMPTY V_RXFIFO_EMPTY(1U) |
2226 | |
2227 | #define S_RXFIFOPAUSEHWM 17 |
2228 | #define M_RXFIFOPAUSEHWM 0xfff |
2229 | |
2230 | #define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM) |
2231 | |
2232 | #define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM) |
2233 | |
2234 | #define S_RXFIFOPAUSELWM 5 |
2235 | #define M_RXFIFOPAUSELWM 0xfff |
2236 | |
2237 | #define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM) |
2238 | |
2239 | #define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM) |
2240 | |
2241 | #define S_RXSTRFRWRD 1 |
2242 | #define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD) |
2243 | #define F_RXSTRFRWRD V_RXSTRFRWRD(1U) |
2244 | |
2245 | #define S_DISERRFRAMES 0 |
2246 | #define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES) |
2247 | #define F_DISERRFRAMES V_DISERRFRAMES(1U) |
2248 | |
2249 | #define A_XGM_TXFIFO_CFG 0x888 |
2250 | |
2251 | #define S_UNDERUNFIX 22 |
2252 | #define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX) |
2253 | #define F_UNDERUNFIX V_UNDERUNFIX(1U) |
2254 | |
2255 | #define S_TXIPG 13 |
2256 | #define M_TXIPG 0xff |
2257 | #define V_TXIPG(x) ((x) << S_TXIPG) |
2258 | #define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG) |
2259 | |
2260 | #define S_TXFIFOTHRESH 4 |
2261 | #define M_TXFIFOTHRESH 0x1ff |
2262 | |
2263 | #define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH) |
2264 | |
2265 | #define S_ENDROPPKT 21 |
2266 | #define V_ENDROPPKT(x) ((x) << S_ENDROPPKT) |
2267 | #define F_ENDROPPKT V_ENDROPPKT(1U) |
2268 | |
2269 | #define A_XGM_SERDES_CTRL 0x890 |
2270 | #define A_XGM_SERDES_CTRL0 0x8e0 |
2271 | |
2272 | #define S_SERDESRESET_ 24 |
2273 | #define V_SERDESRESET_(x) ((x) << S_SERDESRESET_) |
2274 | #define F_SERDESRESET_ V_SERDESRESET_(1U) |
2275 | |
2276 | #define S_RXENABLE 4 |
2277 | #define V_RXENABLE(x) ((x) << S_RXENABLE) |
2278 | #define F_RXENABLE V_RXENABLE(1U) |
2279 | |
2280 | #define S_TXENABLE 3 |
2281 | #define V_TXENABLE(x) ((x) << S_TXENABLE) |
2282 | #define F_TXENABLE V_TXENABLE(1U) |
2283 | |
2284 | #define A_XGM_PAUSE_TIMER 0x890 |
2285 | |
2286 | #define A_XGM_RGMII_IMP 0x89c |
2287 | |
2288 | #define S_XGM_IMPSETUPDATE 6 |
2289 | #define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE) |
2290 | #define F_XGM_IMPSETUPDATE V_XGM_IMPSETUPDATE(1U) |
2291 | |
2292 | #define S_RGMIIIMPPD 3 |
2293 | #define M_RGMIIIMPPD 0x7 |
2294 | #define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD) |
2295 | |
2296 | #define S_RGMIIIMPPU 0 |
2297 | #define M_RGMIIIMPPU 0x7 |
2298 | #define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU) |
2299 | |
2300 | #define S_CALRESET 8 |
2301 | #define V_CALRESET(x) ((x) << S_CALRESET) |
2302 | #define F_CALRESET V_CALRESET(1U) |
2303 | |
2304 | #define S_CALUPDATE 7 |
2305 | #define V_CALUPDATE(x) ((x) << S_CALUPDATE) |
2306 | #define F_CALUPDATE V_CALUPDATE(1U) |
2307 | |
2308 | #define A_XGM_XAUI_IMP 0x8a0 |
2309 | |
2310 | #define S_CALBUSY 31 |
2311 | #define V_CALBUSY(x) ((x) << S_CALBUSY) |
2312 | #define F_CALBUSY V_CALBUSY(1U) |
2313 | |
2314 | #define S_XGM_CALFAULT 29 |
2315 | #define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT) |
2316 | #define F_XGM_CALFAULT V_XGM_CALFAULT(1U) |
2317 | |
2318 | #define S_CALIMP 24 |
2319 | #define M_CALIMP 0x1f |
2320 | #define V_CALIMP(x) ((x) << S_CALIMP) |
2321 | #define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP) |
2322 | |
2323 | #define S_XAUIIMP 0 |
2324 | #define M_XAUIIMP 0x7 |
2325 | #define V_XAUIIMP(x) ((x) << S_XAUIIMP) |
2326 | |
2327 | #define A_XGM_RX_MAX_PKT_SIZE 0x8a8 |
2328 | |
2329 | #define S_RXMAXFRAMERSIZE 17 |
2330 | #define M_RXMAXFRAMERSIZE 0x3fff |
2331 | #define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE) |
2332 | #define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE) |
2333 | |
2334 | #define S_RXENFRAMER 14 |
2335 | #define V_RXENFRAMER(x) ((x) << S_RXENFRAMER) |
2336 | #define F_RXENFRAMER V_RXENFRAMER(1U) |
2337 | |
2338 | #define S_RXMAXPKTSIZE 0 |
2339 | #define M_RXMAXPKTSIZE 0x3fff |
2340 | #define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE) |
2341 | #define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE) |
2342 | |
2343 | #define A_XGM_RESET_CTRL 0x8ac |
2344 | |
2345 | #define S_XGMAC_STOP_EN 4 |
2346 | #define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN) |
2347 | #define F_XGMAC_STOP_EN V_XGMAC_STOP_EN(1U) |
2348 | |
2349 | #define S_XG2G_RESET_ 3 |
2350 | #define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_) |
2351 | #define F_XG2G_RESET_ V_XG2G_RESET_(1U) |
2352 | |
2353 | #define S_RGMII_RESET_ 2 |
2354 | #define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_) |
2355 | #define F_RGMII_RESET_ V_RGMII_RESET_(1U) |
2356 | |
2357 | #define S_PCS_RESET_ 1 |
2358 | #define V_PCS_RESET_(x) ((x) << S_PCS_RESET_) |
2359 | #define F_PCS_RESET_ V_PCS_RESET_(1U) |
2360 | |
2361 | #define S_MAC_RESET_ 0 |
2362 | #define V_MAC_RESET_(x) ((x) << S_MAC_RESET_) |
2363 | #define F_MAC_RESET_ V_MAC_RESET_(1U) |
2364 | |
2365 | #define A_XGM_PORT_CFG 0x8b8 |
2366 | |
2367 | #define S_CLKDIVRESET_ 3 |
2368 | #define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_) |
2369 | #define F_CLKDIVRESET_ V_CLKDIVRESET_(1U) |
2370 | |
2371 | #define S_PORTSPEED 1 |
2372 | #define M_PORTSPEED 0x3 |
2373 | |
2374 | #define V_PORTSPEED(x) ((x) << S_PORTSPEED) |
2375 | |
2376 | #define S_ENRGMII 0 |
2377 | #define V_ENRGMII(x) ((x) << S_ENRGMII) |
2378 | #define F_ENRGMII V_ENRGMII(1U) |
2379 | |
2380 | #define A_XGM_INT_ENABLE 0x8d4 |
2381 | |
2382 | #define S_TXFIFO_PRTY_ERR 17 |
2383 | #define M_TXFIFO_PRTY_ERR 0x7 |
2384 | |
2385 | #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR) |
2386 | |
2387 | #define S_RXFIFO_PRTY_ERR 14 |
2388 | #define M_RXFIFO_PRTY_ERR 0x7 |
2389 | |
2390 | #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR) |
2391 | |
2392 | #define S_TXFIFO_UNDERRUN 13 |
2393 | #define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN) |
2394 | #define F_TXFIFO_UNDERRUN V_TXFIFO_UNDERRUN(1U) |
2395 | |
2396 | #define S_RXFIFO_OVERFLOW 12 |
2397 | #define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW) |
2398 | #define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U) |
2399 | |
2400 | #define S_SERDES_LOS 4 |
2401 | #define M_SERDES_LOS 0xf |
2402 | |
2403 | #define V_SERDES_LOS(x) ((x) << S_SERDES_LOS) |
2404 | |
2405 | #define S_XAUIPCSCTCERR 3 |
2406 | #define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR) |
2407 | #define F_XAUIPCSCTCERR V_XAUIPCSCTCERR(1U) |
2408 | |
2409 | #define S_XAUIPCSALIGNCHANGE 2 |
2410 | #define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE) |
2411 | #define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U) |
2412 | |
2413 | #define S_XGM_INT 0 |
2414 | #define V_XGM_INT(x) ((x) << S_XGM_INT) |
2415 | #define F_XGM_INT V_XGM_INT(1U) |
2416 | |
2417 | #define A_XGM_INT_CAUSE 0x8d8 |
2418 | |
2419 | #define A_XGM_XAUI_ACT_CTRL 0x8dc |
2420 | |
2421 | #define S_TXACTENABLE 1 |
2422 | #define V_TXACTENABLE(x) ((x) << S_TXACTENABLE) |
2423 | #define F_TXACTENABLE V_TXACTENABLE(1U) |
2424 | |
2425 | #define S_RESET3 23 |
2426 | #define V_RESET3(x) ((x) << S_RESET3) |
2427 | #define F_RESET3 V_RESET3(1U) |
2428 | |
2429 | #define S_RESET2 22 |
2430 | #define V_RESET2(x) ((x) << S_RESET2) |
2431 | #define F_RESET2 V_RESET2(1U) |
2432 | |
2433 | #define S_RESET1 21 |
2434 | #define V_RESET1(x) ((x) << S_RESET1) |
2435 | #define F_RESET1 V_RESET1(1U) |
2436 | |
2437 | #define S_RESET0 20 |
2438 | #define V_RESET0(x) ((x) << S_RESET0) |
2439 | #define F_RESET0 V_RESET0(1U) |
2440 | |
2441 | #define S_PWRDN3 19 |
2442 | #define V_PWRDN3(x) ((x) << S_PWRDN3) |
2443 | #define F_PWRDN3 V_PWRDN3(1U) |
2444 | |
2445 | #define S_PWRDN2 18 |
2446 | #define V_PWRDN2(x) ((x) << S_PWRDN2) |
2447 | #define F_PWRDN2 V_PWRDN2(1U) |
2448 | |
2449 | #define S_PWRDN1 17 |
2450 | #define V_PWRDN1(x) ((x) << S_PWRDN1) |
2451 | #define F_PWRDN1 V_PWRDN1(1U) |
2452 | |
2453 | #define S_PWRDN0 16 |
2454 | #define V_PWRDN0(x) ((x) << S_PWRDN0) |
2455 | #define F_PWRDN0 V_PWRDN0(1U) |
2456 | |
2457 | #define S_RESETPLL23 15 |
2458 | #define V_RESETPLL23(x) ((x) << S_RESETPLL23) |
2459 | #define F_RESETPLL23 V_RESETPLL23(1U) |
2460 | |
2461 | #define S_RESETPLL01 14 |
2462 | #define V_RESETPLL01(x) ((x) << S_RESETPLL01) |
2463 | #define F_RESETPLL01 V_RESETPLL01(1U) |
2464 | |
2465 | #define A_XGM_SERDES_STAT0 0x8f0 |
2466 | #define A_XGM_SERDES_STAT1 0x8f4 |
2467 | #define A_XGM_SERDES_STAT2 0x8f8 |
2468 | |
2469 | #define S_LOWSIG0 0 |
2470 | #define V_LOWSIG0(x) ((x) << S_LOWSIG0) |
2471 | #define F_LOWSIG0 V_LOWSIG0(1U) |
2472 | |
2473 | #define A_XGM_SERDES_STAT3 0x8fc |
2474 | |
2475 | #define A_XGM_STAT_TX_BYTE_LOW 0x900 |
2476 | |
2477 | #define A_XGM_STAT_TX_BYTE_HIGH 0x904 |
2478 | |
2479 | #define A_XGM_STAT_TX_FRAME_LOW 0x908 |
2480 | |
2481 | #define A_XGM_STAT_TX_FRAME_HIGH 0x90c |
2482 | |
2483 | #define A_XGM_STAT_TX_BCAST 0x910 |
2484 | |
2485 | #define A_XGM_STAT_TX_MCAST 0x914 |
2486 | |
2487 | #define A_XGM_STAT_TX_PAUSE 0x918 |
2488 | |
2489 | #define A_XGM_STAT_TX_64B_FRAMES 0x91c |
2490 | |
2491 | #define A_XGM_STAT_TX_65_127B_FRAMES 0x920 |
2492 | |
2493 | #define A_XGM_STAT_TX_128_255B_FRAMES 0x924 |
2494 | |
2495 | #define A_XGM_STAT_TX_256_511B_FRAMES 0x928 |
2496 | |
2497 | #define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c |
2498 | |
2499 | #define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930 |
2500 | |
2501 | #define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934 |
2502 | |
2503 | #define A_XGM_STAT_TX_ERR_FRAMES 0x938 |
2504 | |
2505 | #define A_XGM_STAT_RX_BYTES_LOW 0x93c |
2506 | |
2507 | #define A_XGM_STAT_RX_BYTES_HIGH 0x940 |
2508 | |
2509 | #define A_XGM_STAT_RX_FRAMES_LOW 0x944 |
2510 | |
2511 | #define A_XGM_STAT_RX_FRAMES_HIGH 0x948 |
2512 | |
2513 | #define A_XGM_STAT_RX_BCAST_FRAMES 0x94c |
2514 | |
2515 | #define A_XGM_STAT_RX_MCAST_FRAMES 0x950 |
2516 | |
2517 | #define A_XGM_STAT_RX_PAUSE_FRAMES 0x954 |
2518 | |
2519 | #define A_XGM_STAT_RX_64B_FRAMES 0x958 |
2520 | |
2521 | #define A_XGM_STAT_RX_65_127B_FRAMES 0x95c |
2522 | |
2523 | #define A_XGM_STAT_RX_128_255B_FRAMES 0x960 |
2524 | |
2525 | #define A_XGM_STAT_RX_256_511B_FRAMES 0x964 |
2526 | |
2527 | #define A_XGM_STAT_RX_512_1023B_FRAMES 0x968 |
2528 | |
2529 | #define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c |
2530 | |
2531 | #define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970 |
2532 | |
2533 | #define A_XGM_STAT_RX_SHORT_FRAMES 0x974 |
2534 | |
2535 | #define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978 |
2536 | |
2537 | #define A_XGM_STAT_RX_JABBER_FRAMES 0x97c |
2538 | |
2539 | #define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980 |
2540 | |
2541 | #define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984 |
2542 | |
2543 | #define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988 |
2544 | |
2545 | #define A_XGM_SERDES_STATUS0 0x98c |
2546 | |
2547 | #define A_XGM_SERDES_STATUS1 0x990 |
2548 | |
2549 | #define S_CMULOCK 31 |
2550 | #define V_CMULOCK(x) ((x) << S_CMULOCK) |
2551 | #define F_CMULOCK V_CMULOCK(1U) |
2552 | |
2553 | #define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4 |
2554 | |
2555 | #define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8 |
2556 | |
2557 | #define S_TXSPI4SOPCNT 16 |
2558 | #define M_TXSPI4SOPCNT 0xffff |
2559 | #define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT) |
2560 | #define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT) |
2561 | |
2562 | #define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac |
2563 | |
2564 | #define XGMAC0_1_BASE_ADDR 0xa00 |
2565 | |