1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2017 Chelsio Communications. All rights reserved. |
4 | */ |
5 | |
6 | #ifndef __CUDBG_ENTITY_H__ |
7 | #define __CUDBG_ENTITY_H__ |
8 | |
9 | #define EDC0_FLAG 0 |
10 | #define EDC1_FLAG 1 |
11 | #define MC_FLAG 2 |
12 | #define MC0_FLAG 3 |
13 | #define MC1_FLAG 4 |
14 | #define HMA_FLAG 5 |
15 | |
16 | #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001 |
17 | |
18 | struct cudbg_mbox_log { |
19 | struct mbox_cmd entry; |
20 | u32 hi[MBOX_LEN / 8]; |
21 | u32 lo[MBOX_LEN / 8]; |
22 | }; |
23 | |
24 | struct cudbg_cim_qcfg { |
25 | u8 chip; |
26 | u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; |
27 | u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; |
28 | u16 thres[CIM_NUM_IBQ]; |
29 | u32 obq_wr[2 * CIM_NUM_OBQ_T5]; |
30 | u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)]; |
31 | }; |
32 | |
33 | struct { |
34 | u32 ; |
35 | u32 ; |
36 | }; |
37 | |
38 | struct cudbg_pm_stats { |
39 | u32 tx_cnt[T6_PM_NSTATS]; |
40 | u32 rx_cnt[T6_PM_NSTATS]; |
41 | u64 tx_cyc[T6_PM_NSTATS]; |
42 | u64 rx_cyc[T6_PM_NSTATS]; |
43 | }; |
44 | |
45 | struct cudbg_hw_sched { |
46 | u32 kbps[NTX_SCHED]; |
47 | u32 ipg[NTX_SCHED]; |
48 | u32 pace_tab[NTX_SCHED]; |
49 | u32 mode; |
50 | u32 map; |
51 | }; |
52 | |
53 | #define SGE_QBASE_DATA_REG_NUM 4 |
54 | |
55 | struct sge_qbase_reg_field { |
56 | u32 reg_addr; |
57 | u32 reg_data[SGE_QBASE_DATA_REG_NUM]; |
58 | /* Max supported PFs */ |
59 | u32 pf_data_value[PCIE_FW_MASTER_M + 1][SGE_QBASE_DATA_REG_NUM]; |
60 | /* Max supported VFs */ |
61 | u32 vf_data_value[T6_VF_M + 1][SGE_QBASE_DATA_REG_NUM]; |
62 | u32 vfcount; /* Actual number of max vfs in current configuration */ |
63 | }; |
64 | |
65 | struct ireg_field { |
66 | u32 ireg_addr; |
67 | u32 ireg_data; |
68 | u32 ireg_local_offset; |
69 | u32 ireg_offset_range; |
70 | }; |
71 | |
72 | struct ireg_buf { |
73 | struct ireg_field tp_pio; |
74 | u32 outbuf[32]; |
75 | }; |
76 | |
77 | struct cudbg_ulprx_la { |
78 | u32 data[ULPRX_LA_SIZE * 8]; |
79 | u32 size; |
80 | }; |
81 | |
82 | struct cudbg_tp_la { |
83 | u32 size; |
84 | u32 mode; |
85 | u8 data[]; |
86 | }; |
87 | |
88 | static const char * const cudbg_region[] = { |
89 | "DBQ contexts:" , "IMSG contexts:" , "FLM cache:" , "TCBs:" , |
90 | "Pstructs:" , "Timers:" , "Rx FL:" , "Tx FL:" , "Pstruct FL:" , |
91 | "Tx payload:" , "Rx payload:" , "LE hash:" , "iSCSI region:" , |
92 | "TDDP region:" , "TPT region:" , "STAG region:" , "RQ region:" , |
93 | "RQUDP region:" , "PBL region:" , "TXPBL region:" , |
94 | "DBVFIFO region:" , "ULPRX state:" , "ULPTX state:" , |
95 | "On-chip queues:" |
96 | }; |
97 | |
98 | /* Memory region info relative to current memory (i.e. wrt 0). */ |
99 | struct cudbg_region_info { |
100 | bool exist; /* Does region exists in current memory? */ |
101 | u32 start; /* Start wrt 0 */ |
102 | u32 end; /* End wrt 0 */ |
103 | }; |
104 | |
105 | struct cudbg_mem_desc { |
106 | u32 base; |
107 | u32 limit; |
108 | u32 idx; |
109 | }; |
110 | |
111 | #define CUDBG_MEMINFO_REV 1 |
112 | |
113 | struct cudbg_meminfo { |
114 | struct cudbg_mem_desc avail[4]; |
115 | struct cudbg_mem_desc mem[ARRAY_SIZE(cudbg_region) + 3]; |
116 | u32 avail_c; |
117 | u32 mem_c; |
118 | u32 up_ram_lo; |
119 | u32 up_ram_hi; |
120 | u32 up_extmem2_lo; |
121 | u32 up_extmem2_hi; |
122 | u32 rx_pages_data[3]; |
123 | u32 tx_pages_data[4]; |
124 | u32 p_structs; |
125 | u32 reserved[12]; |
126 | u32 port_used[4]; |
127 | u32 port_alloc[4]; |
128 | u32 loopback_used[NCHAN]; |
129 | u32 loopback_alloc[NCHAN]; |
130 | u32 p_structs_free_cnt; |
131 | u32 free_rx_cnt; |
132 | u32 free_tx_cnt; |
133 | }; |
134 | |
135 | struct cudbg_cim_pif_la { |
136 | int size; |
137 | u8 data[]; |
138 | }; |
139 | |
140 | struct cudbg_clk_info { |
141 | u64 retransmit_min; |
142 | u64 retransmit_max; |
143 | u64 persist_timer_min; |
144 | u64 persist_timer_max; |
145 | u64 keepalive_idle_timer; |
146 | u64 keepalive_interval; |
147 | u64 initial_srtt; |
148 | u64 finwait2_timer; |
149 | u32 dack_timer; |
150 | u32 res; |
151 | u32 cclk_ps; |
152 | u32 tre; |
153 | u32 dack_re; |
154 | }; |
155 | |
156 | struct cudbg_tid_info_region { |
157 | u32 ntids; |
158 | u32 nstids; |
159 | u32 stid_base; |
160 | u32 hash_base; |
161 | |
162 | u32 natids; |
163 | u32 nftids; |
164 | u32 ftid_base; |
165 | u32 aftid_base; |
166 | u32 aftid_end; |
167 | |
168 | u32 sftid_base; |
169 | u32 nsftids; |
170 | |
171 | u32 uotid_base; |
172 | u32 nuotids; |
173 | |
174 | u32 sb; |
175 | u32 flags; |
176 | u32 le_db_conf; |
177 | u32 ip_users; |
178 | u32 ipv6_users; |
179 | |
180 | u32 hpftid_base; |
181 | u32 nhpftids; |
182 | }; |
183 | |
184 | #define CUDBG_TID_INFO_REV 1 |
185 | |
186 | struct cudbg_tid_info_region_rev1 { |
187 | struct cudbg_ver_hdr ver_hdr; |
188 | struct cudbg_tid_info_region tid; |
189 | u32 tid_start; |
190 | u32 reserved[16]; |
191 | }; |
192 | |
193 | #define CUDBG_LOWMEM_MAX_CTXT_QIDS 256 |
194 | #define CUDBG_MAX_FL_QIDS 1024 |
195 | |
196 | struct cudbg_ch_cntxt { |
197 | u32 cntxt_type; |
198 | u32 cntxt_id; |
199 | u32 data[SGE_CTXT_SIZE / 4]; |
200 | }; |
201 | |
202 | #define CUDBG_MAX_RPLC_SIZE 128 |
203 | |
204 | struct cudbg_mps_tcam { |
205 | u64 mask; |
206 | u32 rplc[8]; |
207 | u32 idx; |
208 | u32 cls_lo; |
209 | u32 cls_hi; |
210 | u32 rplc_size; |
211 | u32 vniy; |
212 | u32 vnix; |
213 | u32 dip_hit; |
214 | u32 vlan_vld; |
215 | u32 repli; |
216 | u16 ivlan; |
217 | u8 addr[ETH_ALEN]; |
218 | u8 lookup_type; |
219 | u8 port_num; |
220 | u8 reserved[2]; |
221 | }; |
222 | |
223 | #define CUDBG_VPD_VER_ADDR 0x18c7 |
224 | #define CUDBG_VPD_VER_LEN 2 |
225 | |
226 | struct cudbg_vpd_data { |
227 | u8 sn[SERNUM_LEN + 1]; |
228 | u8 bn[PN_LEN + 1]; |
229 | u8 na[MACADDR_LEN + 1]; |
230 | u8 mn[ID_LEN + 1]; |
231 | u16 fw_major; |
232 | u16 fw_minor; |
233 | u16 fw_micro; |
234 | u16 fw_build; |
235 | u32 scfg_vers; |
236 | u32 vpd_vers; |
237 | }; |
238 | |
239 | #define CUDBG_MAX_TCAM_TID 0x800 |
240 | #define CUDBG_T6_CLIP 1536 |
241 | #define CUDBG_MAX_TID_COMP_EN 6144 |
242 | #define CUDBG_MAX_TID_COMP_DIS 3072 |
243 | |
244 | enum cudbg_le_entry_types { |
245 | LE_ET_UNKNOWN = 0, |
246 | LE_ET_TCAM_CON = 1, |
247 | LE_ET_TCAM_SERVER = 2, |
248 | LE_ET_TCAM_FILTER = 3, |
249 | LE_ET_TCAM_CLIP = 4, |
250 | LE_ET_TCAM_ROUTING = 5, |
251 | LE_ET_HASH_CON = 6, |
252 | LE_ET_INVALID_TID = 8, |
253 | }; |
254 | |
255 | struct cudbg_tcam { |
256 | u32 filter_start; |
257 | u32 server_start; |
258 | u32 clip_start; |
259 | u32 routing_start; |
260 | u32 tid_hash_base; |
261 | u32 max_tid; |
262 | }; |
263 | |
264 | struct cudbg_tid_data { |
265 | u32 tid; |
266 | u32 dbig_cmd; |
267 | u32 dbig_conf; |
268 | u32 dbig_rsp_stat; |
269 | u32 data[NUM_LE_DB_DBGI_RSP_DATA_INSTANCES]; |
270 | }; |
271 | |
272 | #define CUDBG_NUM_ULPTX 11 |
273 | #define CUDBG_NUM_ULPTX_READ 512 |
274 | #define CUDBG_NUM_ULPTX_ASIC 6 |
275 | #define CUDBG_NUM_ULPTX_ASIC_READ 128 |
276 | |
277 | #define CUDBG_ULPTX_LA_REV 1 |
278 | |
279 | struct cudbg_ulptx_la { |
280 | u32 rdptr[CUDBG_NUM_ULPTX]; |
281 | u32 wrptr[CUDBG_NUM_ULPTX]; |
282 | u32 rddata[CUDBG_NUM_ULPTX]; |
283 | u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ]; |
284 | u32 rdptr_asic[CUDBG_NUM_ULPTX_ASIC_READ]; |
285 | u32 rddata_asic[CUDBG_NUM_ULPTX_ASIC_READ][CUDBG_NUM_ULPTX_ASIC]; |
286 | }; |
287 | |
288 | #define CUDBG_CHAC_PBT_ADDR 0x2800 |
289 | #define CUDBG_CHAC_PBT_LRF 0x3000 |
290 | #define CUDBG_CHAC_PBT_DATA 0x3800 |
291 | #define CUDBG_PBT_DYNAMIC_ENTRIES 8 |
292 | #define CUDBG_PBT_STATIC_ENTRIES 16 |
293 | #define CUDBG_LRF_ENTRIES 8 |
294 | #define CUDBG_PBT_DATA_ENTRIES 512 |
295 | |
296 | struct cudbg_pbt_tables { |
297 | u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES]; |
298 | u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES]; |
299 | u32 lrf_table[CUDBG_LRF_ENTRIES]; |
300 | u32 pbt_data[CUDBG_PBT_DATA_ENTRIES]; |
301 | }; |
302 | |
303 | enum cudbg_qdesc_qtype { |
304 | CUDBG_QTYPE_UNKNOWN = 0, |
305 | CUDBG_QTYPE_NIC_TXQ, |
306 | CUDBG_QTYPE_NIC_RXQ, |
307 | CUDBG_QTYPE_NIC_FLQ, |
308 | CUDBG_QTYPE_CTRLQ, |
309 | CUDBG_QTYPE_FWEVTQ, |
310 | CUDBG_QTYPE_INTRQ, |
311 | CUDBG_QTYPE_PTP_TXQ, |
312 | CUDBG_QTYPE_OFLD_TXQ, |
313 | CUDBG_QTYPE_RDMA_RXQ, |
314 | CUDBG_QTYPE_RDMA_FLQ, |
315 | CUDBG_QTYPE_RDMA_CIQ, |
316 | CUDBG_QTYPE_ISCSI_RXQ, |
317 | CUDBG_QTYPE_ISCSI_FLQ, |
318 | CUDBG_QTYPE_ISCSIT_RXQ, |
319 | CUDBG_QTYPE_ISCSIT_FLQ, |
320 | CUDBG_QTYPE_CRYPTO_TXQ, |
321 | CUDBG_QTYPE_CRYPTO_RXQ, |
322 | CUDBG_QTYPE_CRYPTO_FLQ, |
323 | CUDBG_QTYPE_TLS_RXQ, |
324 | CUDBG_QTYPE_TLS_FLQ, |
325 | CUDBG_QTYPE_ETHOFLD_TXQ, |
326 | CUDBG_QTYPE_ETHOFLD_RXQ, |
327 | CUDBG_QTYPE_ETHOFLD_FLQ, |
328 | CUDBG_QTYPE_MAX, |
329 | }; |
330 | |
331 | #define CUDBG_QDESC_REV 1 |
332 | |
333 | struct cudbg_qdesc_entry { |
334 | u32 data_size; |
335 | u32 qtype; |
336 | u32 qid; |
337 | u32 desc_size; |
338 | u32 num_desc; |
339 | u8 data[]; /* Must be last */ |
340 | }; |
341 | |
342 | struct cudbg_qdesc_info { |
343 | u32 qdesc_entry_size; |
344 | u32 num_queues; |
345 | u8 data[]; /* Must be last */ |
346 | }; |
347 | |
348 | #define IREG_NUM_ELEM 4 |
349 | |
350 | #define CUDBG_NUM_PCIE_CONFIG_REGS 0x61 |
351 | |
352 | #endif /* __CUDBG_ENTITY_H__ */ |
353 | |