1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2006 Intel Corporation. */
3
4/*
5 * e100.c: Intel(R) PRO/100 ethernet driver
6 *
7 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
8 * original e100 driver, but better described as a munging of
9 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
10 *
11 * References:
12 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
13 * Open Source Software Developers Manual,
14 * http://sourceforge.net/projects/e1000
15 *
16 *
17 * Theory of Operation
18 *
19 * I. General
20 *
21 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
22 * controller family, which includes the 82557, 82558, 82559, 82550,
23 * 82551, and 82562 devices. 82558 and greater controllers
24 * integrate the Intel 82555 PHY. The controllers are used in
25 * server and client network interface cards, as well as in
26 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
27 * configurations. 8255x supports a 32-bit linear addressing
28 * mode and operates at 33Mhz PCI clock rate.
29 *
30 * II. Driver Operation
31 *
32 * Memory-mapped mode is used exclusively to access the device's
33 * shared-memory structure, the Control/Status Registers (CSR). All
34 * setup, configuration, and control of the device, including queuing
35 * of Tx, Rx, and configuration commands is through the CSR.
36 * cmd_lock serializes accesses to the CSR command register. cb_lock
37 * protects the shared Command Block List (CBL).
38 *
39 * 8255x is highly MII-compliant and all access to the PHY go
40 * through the Management Data Interface (MDI). Consequently, the
41 * driver leverages the mii.c library shared with other MII-compliant
42 * devices.
43 *
44 * Big- and Little-Endian byte order as well as 32- and 64-bit
45 * archs are supported. Weak-ordered memory and non-cache-coherent
46 * archs are supported.
47 *
48 * III. Transmit
49 *
50 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
51 * together in a fixed-size ring (CBL) thus forming the flexible mode
52 * memory structure. A TCB marked with the suspend-bit indicates
53 * the end of the ring. The last TCB processed suspends the
54 * controller, and the controller can be restarted by issue a CU
55 * resume command to continue from the suspend point, or a CU start
56 * command to start at a given position in the ring.
57 *
58 * Non-Tx commands (config, multicast setup, etc) are linked
59 * into the CBL ring along with Tx commands. The common structure
60 * used for both Tx and non-Tx commands is the Command Block (CB).
61 *
62 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
63 * is the next CB to check for completion; cb_to_send is the first
64 * CB to start on in case of a previous failure to resume. CB clean
65 * up happens in interrupt context in response to a CU interrupt.
66 * cbs_avail keeps track of number of free CB resources available.
67 *
68 * Hardware padding of short packets to minimum packet size is
69 * enabled. 82557 pads with 7Eh, while the later controllers pad
70 * with 00h.
71 *
72 * IV. Receive
73 *
74 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
75 * Descriptors (RFD) + data buffer, thus forming the simplified mode
76 * memory structure. Rx skbs are allocated to contain both the RFD
77 * and the data buffer, but the RFD is pulled off before the skb is
78 * indicated. The data buffer is aligned such that encapsulated
79 * protocol headers are u32-aligned. Since the RFD is part of the
80 * mapped shared memory, and completion status is contained within
81 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
82 * view from software and hardware.
83 *
84 * In order to keep updates to the RFD link field from colliding with
85 * hardware writes to mark packets complete, we use the feature that
86 * hardware will not write to a size 0 descriptor and mark the previous
87 * packet as end-of-list (EL). After updating the link, we remove EL
88 * and only then restore the size such that hardware may use the
89 * previous-to-end RFD.
90 *
91 * Under typical operation, the receive unit (RU) is start once,
92 * and the controller happily fills RFDs as frames arrive. If
93 * replacement RFDs cannot be allocated, or the RU goes non-active,
94 * the RU must be restarted. Frame arrival generates an interrupt,
95 * and Rx indication and re-allocation happen in the same context,
96 * therefore no locking is required. A software-generated interrupt
97 * is generated from the watchdog to recover from a failed allocation
98 * scenario where all Rx resources have been indicated and none re-
99 * placed.
100 *
101 * V. Miscellaneous
102 *
103 * VLAN offloading of tagging, stripping and filtering is not
104 * supported, but driver will accommodate the extra 4-byte VLAN tag
105 * for processing by upper layers. Tx/Rx Checksum offloading is not
106 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
107 * not supported (hardware limitation).
108 *
109 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
110 *
111 * Thanks to JC (jchapman@katalix.com) for helping with
112 * testing/troubleshooting the development driver.
113 *
114 * TODO:
115 * o several entry points race with dev->close
116 * o check for tx-no-resources/stop Q races with tx clean/wake Q
117 *
118 * FIXES:
119 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
120 * - Stratus87247: protect MDI control register manipulations
121 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
122 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
123 */
124
125#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
126
127#include <linux/hardirq.h>
128#include <linux/interrupt.h>
129#include <linux/module.h>
130#include <linux/moduleparam.h>
131#include <linux/kernel.h>
132#include <linux/types.h>
133#include <linux/sched.h>
134#include <linux/slab.h>
135#include <linux/delay.h>
136#include <linux/init.h>
137#include <linux/pci.h>
138#include <linux/dma-mapping.h>
139#include <linux/dmapool.h>
140#include <linux/netdevice.h>
141#include <linux/etherdevice.h>
142#include <linux/mii.h>
143#include <linux/if_vlan.h>
144#include <linux/skbuff.h>
145#include <linux/ethtool.h>
146#include <linux/string.h>
147#include <linux/firmware.h>
148#include <linux/rtnetlink.h>
149#include <asm/unaligned.h>
150
151
152#define DRV_NAME "e100"
153#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
154#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
155
156#define E100_WATCHDOG_PERIOD (2 * HZ)
157#define E100_NAPI_WEIGHT 16
158
159#define FIRMWARE_D101M "e100/d101m_ucode.bin"
160#define FIRMWARE_D101S "e100/d101s_ucode.bin"
161#define FIRMWARE_D102E "e100/d102e_ucode.bin"
162
163MODULE_DESCRIPTION(DRV_DESCRIPTION);
164MODULE_AUTHOR(DRV_COPYRIGHT);
165MODULE_LICENSE("GPL v2");
166MODULE_FIRMWARE(FIRMWARE_D101M);
167MODULE_FIRMWARE(FIRMWARE_D101S);
168MODULE_FIRMWARE(FIRMWARE_D102E);
169
170static int debug = 3;
171static int eeprom_bad_csum_allow = 0;
172static int use_io = 0;
173module_param(debug, int, 0);
174module_param(eeprom_bad_csum_allow, int, 0);
175module_param(use_io, int, 0);
176MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
177MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
178MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
179
180#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
181 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
182 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
183static const struct pci_device_id e100_id_table[] = {
184 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
185 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
186 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
187 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
188 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
189 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
191 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
192 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
193 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
194 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
197 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
198 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
199 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
200 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
205 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
206 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
207 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
208 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
209 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
213 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
214 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
215 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
216 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
217 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
218 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
219 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
220 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
221 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
222 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
223 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
224 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
225 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
226 { 0, }
227};
228MODULE_DEVICE_TABLE(pci, e100_id_table);
229
230enum mac {
231 mac_82557_D100_A = 0,
232 mac_82557_D100_B = 1,
233 mac_82557_D100_C = 2,
234 mac_82558_D101_A4 = 4,
235 mac_82558_D101_B0 = 5,
236 mac_82559_D101M = 8,
237 mac_82559_D101S = 9,
238 mac_82550_D102 = 12,
239 mac_82550_D102_C = 13,
240 mac_82551_E = 14,
241 mac_82551_F = 15,
242 mac_82551_10 = 16,
243 mac_unknown = 0xFF,
244};
245
246enum phy {
247 phy_100a = 0x000003E0,
248 phy_100c = 0x035002A8,
249 phy_82555_tx = 0x015002A8,
250 phy_nsc_tx = 0x5C002000,
251 phy_82562_et = 0x033002A8,
252 phy_82562_em = 0x032002A8,
253 phy_82562_ek = 0x031002A8,
254 phy_82562_eh = 0x017002A8,
255 phy_82552_v = 0xd061004d,
256 phy_unknown = 0xFFFFFFFF,
257};
258
259/* CSR (Control/Status Registers) */
260struct csr {
261 struct {
262 u8 status;
263 u8 stat_ack;
264 u8 cmd_lo;
265 u8 cmd_hi;
266 u32 gen_ptr;
267 } scb;
268 u32 port;
269 u16 flash_ctrl;
270 u8 eeprom_ctrl_lo;
271 u8 eeprom_ctrl_hi;
272 u32 mdi_ctrl;
273 u32 rx_dma_count;
274};
275
276enum scb_status {
277 rus_no_res = 0x08,
278 rus_ready = 0x10,
279 rus_mask = 0x3C,
280};
281
282enum ru_state {
283 RU_SUSPENDED = 0,
284 RU_RUNNING = 1,
285 RU_UNINITIALIZED = -1,
286};
287
288enum scb_stat_ack {
289 stat_ack_not_ours = 0x00,
290 stat_ack_sw_gen = 0x04,
291 stat_ack_rnr = 0x10,
292 stat_ack_cu_idle = 0x20,
293 stat_ack_frame_rx = 0x40,
294 stat_ack_cu_cmd_done = 0x80,
295 stat_ack_not_present = 0xFF,
296 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
297 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
298};
299
300enum scb_cmd_hi {
301 irq_mask_none = 0x00,
302 irq_mask_all = 0x01,
303 irq_sw_gen = 0x02,
304};
305
306enum scb_cmd_lo {
307 cuc_nop = 0x00,
308 ruc_start = 0x01,
309 ruc_load_base = 0x06,
310 cuc_start = 0x10,
311 cuc_resume = 0x20,
312 cuc_dump_addr = 0x40,
313 cuc_dump_stats = 0x50,
314 cuc_load_base = 0x60,
315 cuc_dump_reset = 0x70,
316};
317
318enum cuc_dump {
319 cuc_dump_complete = 0x0000A005,
320 cuc_dump_reset_complete = 0x0000A007,
321};
322
323enum port {
324 software_reset = 0x0000,
325 selftest = 0x0001,
326 selective_reset = 0x0002,
327};
328
329enum eeprom_ctrl_lo {
330 eesk = 0x01,
331 eecs = 0x02,
332 eedi = 0x04,
333 eedo = 0x08,
334};
335
336enum mdi_ctrl {
337 mdi_write = 0x04000000,
338 mdi_read = 0x08000000,
339 mdi_ready = 0x10000000,
340};
341
342enum eeprom_op {
343 op_write = 0x05,
344 op_read = 0x06,
345 op_ewds = 0x10,
346 op_ewen = 0x13,
347};
348
349enum eeprom_offsets {
350 eeprom_cnfg_mdix = 0x03,
351 eeprom_phy_iface = 0x06,
352 eeprom_id = 0x0A,
353 eeprom_config_asf = 0x0D,
354 eeprom_smbus_addr = 0x90,
355};
356
357enum eeprom_cnfg_mdix {
358 eeprom_mdix_enabled = 0x0080,
359};
360
361enum eeprom_phy_iface {
362 NoSuchPhy = 0,
363 I82553AB,
364 I82553C,
365 I82503,
366 DP83840,
367 S80C240,
368 S80C24,
369 I82555,
370 DP83840A = 10,
371};
372
373enum eeprom_id {
374 eeprom_id_wol = 0x0020,
375};
376
377enum eeprom_config_asf {
378 eeprom_asf = 0x8000,
379 eeprom_gcl = 0x4000,
380};
381
382enum cb_status {
383 cb_complete = 0x8000,
384 cb_ok = 0x2000,
385};
386
387/*
388 * cb_command - Command Block flags
389 * @cb_tx_nc: 0: controller does CRC (normal), 1: CRC from skb memory
390 */
391enum cb_command {
392 cb_nop = 0x0000,
393 cb_iaaddr = 0x0001,
394 cb_config = 0x0002,
395 cb_multi = 0x0003,
396 cb_tx = 0x0004,
397 cb_ucode = 0x0005,
398 cb_dump = 0x0006,
399 cb_tx_sf = 0x0008,
400 cb_tx_nc = 0x0010,
401 cb_cid = 0x1f00,
402 cb_i = 0x2000,
403 cb_s = 0x4000,
404 cb_el = 0x8000,
405};
406
407struct rfd {
408 __le16 status;
409 __le16 command;
410 __le32 link;
411 __le32 rbd;
412 __le16 actual_size;
413 __le16 size;
414};
415
416struct rx {
417 struct rx *next, *prev;
418 struct sk_buff *skb;
419 dma_addr_t dma_addr;
420};
421
422#if defined(__BIG_ENDIAN_BITFIELD)
423#define X(a,b) b,a
424#else
425#define X(a,b) a,b
426#endif
427struct config {
428/*0*/ u8 X(byte_count:6, pad0:2);
429/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
430/*2*/ u8 adaptive_ifs;
431/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
432 term_write_cache_line:1), pad3:4);
433/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
434/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
435/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
436 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
437 rx_save_overruns : 1), rx_save_bad_frames : 1);
438/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
439 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
440 tx_dynamic_tbd:1);
441/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
442/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
443 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
444/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
445 loopback:2);
446/*11*/ u8 X(linear_priority:3, pad11:5);
447/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
448/*13*/ u8 ip_addr_lo;
449/*14*/ u8 ip_addr_hi;
450/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
451 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
452 pad15_2:1), crs_or_cdt:1);
453/*16*/ u8 fc_delay_lo;
454/*17*/ u8 fc_delay_hi;
455/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
456 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
457/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
458 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
459 full_duplex_force:1), full_duplex_pin:1);
460/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
461/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
462/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
463 u8 pad_d102[9];
464};
465
466#define E100_MAX_MULTICAST_ADDRS 64
467struct multi {
468 __le16 count;
469 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
470};
471
472/* Important: keep total struct u32-aligned */
473#define UCODE_SIZE 134
474struct cb {
475 __le16 status;
476 __le16 command;
477 __le32 link;
478 union {
479 u8 iaaddr[ETH_ALEN];
480 __le32 ucode[UCODE_SIZE];
481 struct config config;
482 struct multi multi;
483 struct {
484 u32 tbd_array;
485 u16 tcb_byte_count;
486 u8 threshold;
487 u8 tbd_count;
488 struct {
489 __le32 buf_addr;
490 __le16 size;
491 u16 eol;
492 } tbd;
493 } tcb;
494 __le32 dump_buffer_addr;
495 } u;
496 struct cb *next, *prev;
497 dma_addr_t dma_addr;
498 struct sk_buff *skb;
499};
500
501enum loopback {
502 lb_none = 0, lb_mac = 1, lb_phy = 3,
503};
504
505struct stats {
506 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
507 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
508 tx_multiple_collisions, tx_total_collisions;
509 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
510 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
511 rx_short_frame_errors;
512 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
513 __le16 xmt_tco_frames, rcv_tco_frames;
514 __le32 complete;
515};
516
517struct mem {
518 struct {
519 u32 signature;
520 u32 result;
521 } selftest;
522 struct stats stats;
523 u8 dump_buf[596];
524};
525
526struct param_range {
527 u32 min;
528 u32 max;
529 u32 count;
530};
531
532struct params {
533 struct param_range rfds;
534 struct param_range cbs;
535};
536
537struct nic {
538 /* Begin: frequently used values: keep adjacent for cache effect */
539 u32 msg_enable ____cacheline_aligned;
540 struct net_device *netdev;
541 struct pci_dev *pdev;
542 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
543
544 struct rx *rxs ____cacheline_aligned;
545 struct rx *rx_to_use;
546 struct rx *rx_to_clean;
547 struct rfd blank_rfd;
548 enum ru_state ru_running;
549
550 spinlock_t cb_lock ____cacheline_aligned;
551 spinlock_t cmd_lock;
552 struct csr __iomem *csr;
553 enum scb_cmd_lo cuc_cmd;
554 unsigned int cbs_avail;
555 struct napi_struct napi;
556 struct cb *cbs;
557 struct cb *cb_to_use;
558 struct cb *cb_to_send;
559 struct cb *cb_to_clean;
560 __le16 tx_command;
561 /* End: frequently used values: keep adjacent for cache effect */
562
563 enum {
564 ich = (1 << 0),
565 promiscuous = (1 << 1),
566 multicast_all = (1 << 2),
567 wol_magic = (1 << 3),
568 ich_10h_workaround = (1 << 4),
569 } flags ____cacheline_aligned;
570
571 enum mac mac;
572 enum phy phy;
573 struct params params;
574 struct timer_list watchdog;
575 struct mii_if_info mii;
576 struct work_struct tx_timeout_task;
577 enum loopback loopback;
578
579 struct mem *mem;
580 dma_addr_t dma_addr;
581
582 struct dma_pool *cbs_pool;
583 dma_addr_t cbs_dma_addr;
584 u8 adaptive_ifs;
585 u8 tx_threshold;
586 u32 tx_frames;
587 u32 tx_collisions;
588 u32 tx_deferred;
589 u32 tx_single_collisions;
590 u32 tx_multiple_collisions;
591 u32 tx_fc_pause;
592 u32 tx_tco_frames;
593
594 u32 rx_fc_pause;
595 u32 rx_fc_unsupported;
596 u32 rx_tco_frames;
597 u32 rx_short_frame_errors;
598 u32 rx_over_length_errors;
599
600 u16 eeprom_wc;
601 __le16 eeprom[256];
602 spinlock_t mdio_lock;
603 const struct firmware *fw;
604};
605
606static inline void e100_write_flush(struct nic *nic)
607{
608 /* Flush previous PCI writes through intermediate bridges
609 * by doing a benign read */
610 (void)ioread8(&nic->csr->scb.status);
611}
612
613static void e100_enable_irq(struct nic *nic)
614{
615 unsigned long flags;
616
617 spin_lock_irqsave(&nic->cmd_lock, flags);
618 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
619 e100_write_flush(nic);
620 spin_unlock_irqrestore(&nic->cmd_lock, flags);
621}
622
623static void e100_disable_irq(struct nic *nic)
624{
625 unsigned long flags;
626
627 spin_lock_irqsave(&nic->cmd_lock, flags);
628 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
629 e100_write_flush(nic);
630 spin_unlock_irqrestore(&nic->cmd_lock, flags);
631}
632
633static void e100_hw_reset(struct nic *nic)
634{
635 /* Put CU and RU into idle with a selective reset to get
636 * device off of PCI bus */
637 iowrite32(selective_reset, &nic->csr->port);
638 e100_write_flush(nic); udelay(20);
639
640 /* Now fully reset device */
641 iowrite32(software_reset, &nic->csr->port);
642 e100_write_flush(nic); udelay(20);
643
644 /* Mask off our interrupt line - it's unmasked after reset */
645 e100_disable_irq(nic);
646}
647
648static int e100_self_test(struct nic *nic)
649{
650 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
651
652 /* Passing the self-test is a pretty good indication
653 * that the device can DMA to/from host memory */
654
655 nic->mem->selftest.signature = 0;
656 nic->mem->selftest.result = 0xFFFFFFFF;
657
658 iowrite32(selftest | dma_addr, &nic->csr->port);
659 e100_write_flush(nic);
660 /* Wait 10 msec for self-test to complete */
661 msleep(10);
662
663 /* Interrupts are enabled after self-test */
664 e100_disable_irq(nic);
665
666 /* Check results of self-test */
667 if (nic->mem->selftest.result != 0) {
668 netif_err(nic, hw, nic->netdev,
669 "Self-test failed: result=0x%08X\n",
670 nic->mem->selftest.result);
671 return -ETIMEDOUT;
672 }
673 if (nic->mem->selftest.signature == 0) {
674 netif_err(nic, hw, nic->netdev, "Self-test failed: timed out\n");
675 return -ETIMEDOUT;
676 }
677
678 return 0;
679}
680
681static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
682{
683 u32 cmd_addr_data[3];
684 u8 ctrl;
685 int i, j;
686
687 /* Three cmds: write/erase enable, write data, write/erase disable */
688 cmd_addr_data[0] = op_ewen << (addr_len - 2);
689 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
690 le16_to_cpu(data);
691 cmd_addr_data[2] = op_ewds << (addr_len - 2);
692
693 /* Bit-bang cmds to write word to eeprom */
694 for (j = 0; j < 3; j++) {
695
696 /* Chip select */
697 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
698 e100_write_flush(nic); udelay(4);
699
700 for (i = 31; i >= 0; i--) {
701 ctrl = (cmd_addr_data[j] & (1 << i)) ?
702 eecs | eedi : eecs;
703 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
704 e100_write_flush(nic); udelay(4);
705
706 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
707 e100_write_flush(nic); udelay(4);
708 }
709 /* Wait 10 msec for cmd to complete */
710 msleep(10);
711
712 /* Chip deselect */
713 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
714 e100_write_flush(nic); udelay(4);
715 }
716};
717
718/* General technique stolen from the eepro100 driver - very clever */
719static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
720{
721 u32 cmd_addr_data;
722 u16 data = 0;
723 u8 ctrl;
724 int i;
725
726 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
727
728 /* Chip select */
729 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
730 e100_write_flush(nic); udelay(4);
731
732 /* Bit-bang to read word from eeprom */
733 for (i = 31; i >= 0; i--) {
734 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
735 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
736 e100_write_flush(nic); udelay(4);
737
738 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
739 e100_write_flush(nic); udelay(4);
740
741 /* Eeprom drives a dummy zero to EEDO after receiving
742 * complete address. Use this to adjust addr_len. */
743 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
744 if (!(ctrl & eedo) && i > 16) {
745 *addr_len -= (i - 16);
746 i = 17;
747 }
748
749 data = (data << 1) | (ctrl & eedo ? 1 : 0);
750 }
751
752 /* Chip deselect */
753 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
754 e100_write_flush(nic); udelay(4);
755
756 return cpu_to_le16(data);
757};
758
759/* Load entire EEPROM image into driver cache and validate checksum */
760static int e100_eeprom_load(struct nic *nic)
761{
762 u16 addr, addr_len = 8, checksum = 0;
763
764 /* Try reading with an 8-bit addr len to discover actual addr len */
765 e100_eeprom_read(nic, &addr_len, 0);
766 nic->eeprom_wc = 1 << addr_len;
767
768 for (addr = 0; addr < nic->eeprom_wc; addr++) {
769 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
770 if (addr < nic->eeprom_wc - 1)
771 checksum += le16_to_cpu(nic->eeprom[addr]);
772 }
773
774 /* The checksum, stored in the last word, is calculated such that
775 * the sum of words should be 0xBABA */
776 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
777 netif_err(nic, probe, nic->netdev, "EEPROM corrupted\n");
778 if (!eeprom_bad_csum_allow)
779 return -EAGAIN;
780 }
781
782 return 0;
783}
784
785/* Save (portion of) driver EEPROM cache to device and update checksum */
786static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
787{
788 u16 addr, addr_len = 8, checksum = 0;
789
790 /* Try reading with an 8-bit addr len to discover actual addr len */
791 e100_eeprom_read(nic, &addr_len, 0);
792 nic->eeprom_wc = 1 << addr_len;
793
794 if (start + count >= nic->eeprom_wc)
795 return -EINVAL;
796
797 for (addr = start; addr < start + count; addr++)
798 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
799
800 /* The checksum, stored in the last word, is calculated such that
801 * the sum of words should be 0xBABA */
802 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
803 checksum += le16_to_cpu(nic->eeprom[addr]);
804 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
805 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
806 nic->eeprom[nic->eeprom_wc - 1]);
807
808 return 0;
809}
810
811#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
812#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
813static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
814{
815 unsigned long flags;
816 unsigned int i;
817 int err = 0;
818
819 spin_lock_irqsave(&nic->cmd_lock, flags);
820
821 /* Previous command is accepted when SCB clears */
822 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
823 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
824 break;
825 cpu_relax();
826 if (unlikely(i > E100_WAIT_SCB_FAST))
827 udelay(5);
828 }
829 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
830 err = -EAGAIN;
831 goto err_unlock;
832 }
833
834 if (unlikely(cmd != cuc_resume))
835 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
836 iowrite8(cmd, &nic->csr->scb.cmd_lo);
837
838err_unlock:
839 spin_unlock_irqrestore(&nic->cmd_lock, flags);
840
841 return err;
842}
843
844static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
845 int (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
846{
847 struct cb *cb;
848 unsigned long flags;
849 int err;
850
851 spin_lock_irqsave(&nic->cb_lock, flags);
852
853 if (unlikely(!nic->cbs_avail)) {
854 err = -ENOMEM;
855 goto err_unlock;
856 }
857
858 cb = nic->cb_to_use;
859 nic->cb_to_use = cb->next;
860 nic->cbs_avail--;
861 cb->skb = skb;
862
863 err = cb_prepare(nic, cb, skb);
864 if (err)
865 goto err_unlock;
866
867 if (unlikely(!nic->cbs_avail))
868 err = -ENOSPC;
869
870
871 /* Order is important otherwise we'll be in a race with h/w:
872 * set S-bit in current first, then clear S-bit in previous. */
873 cb->command |= cpu_to_le16(cb_s);
874 dma_wmb();
875 cb->prev->command &= cpu_to_le16(~cb_s);
876
877 while (nic->cb_to_send != nic->cb_to_use) {
878 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
879 nic->cb_to_send->dma_addr))) {
880 /* Ok, here's where things get sticky. It's
881 * possible that we can't schedule the command
882 * because the controller is too busy, so
883 * let's just queue the command and try again
884 * when another command is scheduled. */
885 if (err == -ENOSPC) {
886 //request a reset
887 schedule_work(&nic->tx_timeout_task);
888 }
889 break;
890 } else {
891 nic->cuc_cmd = cuc_resume;
892 nic->cb_to_send = nic->cb_to_send->next;
893 }
894 }
895
896err_unlock:
897 spin_unlock_irqrestore(&nic->cb_lock, flags);
898
899 return err;
900}
901
902static int mdio_read(struct net_device *netdev, int addr, int reg)
903{
904 struct nic *nic = netdev_priv(netdev);
905 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
906}
907
908static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
909{
910 struct nic *nic = netdev_priv(netdev);
911
912 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
913}
914
915/* the standard mdio_ctrl() function for usual MII-compliant hardware */
916static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
917{
918 u32 data_out = 0;
919 unsigned int i;
920 unsigned long flags;
921
922
923 /*
924 * Stratus87247: we shouldn't be writing the MDI control
925 * register until the Ready bit shows True. Also, since
926 * manipulation of the MDI control registers is a multi-step
927 * procedure it should be done under lock.
928 */
929 spin_lock_irqsave(&nic->mdio_lock, flags);
930 for (i = 100; i; --i) {
931 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
932 break;
933 udelay(20);
934 }
935 if (unlikely(!i)) {
936 netdev_err(nic->netdev, "e100.mdio_ctrl won't go Ready\n");
937 spin_unlock_irqrestore(&nic->mdio_lock, flags);
938 return 0; /* No way to indicate timeout error */
939 }
940 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
941
942 for (i = 0; i < 100; i++) {
943 udelay(20);
944 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
945 break;
946 }
947 spin_unlock_irqrestore(&nic->mdio_lock, flags);
948 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
949 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
950 dir == mdi_read ? "READ" : "WRITE",
951 addr, reg, data, data_out);
952 return (u16)data_out;
953}
954
955/* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
956static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
957 u32 addr,
958 u32 dir,
959 u32 reg,
960 u16 data)
961{
962 if ((reg == MII_BMCR) && (dir == mdi_write)) {
963 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
964 u16 = mdio_read(nic->netdev, nic->mii.phy_id,
965 MII_ADVERTISE);
966
967 /*
968 * Workaround Si issue where sometimes the part will not
969 * autoneg to 100Mbps even when advertised.
970 */
971 if (advert & ADVERTISE_100FULL)
972 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
973 else if (advert & ADVERTISE_100HALF)
974 data |= BMCR_SPEED100;
975 }
976 }
977 return mdio_ctrl_hw(nic, addr, dir, reg, data);
978}
979
980/* Fully software-emulated mdio_ctrl() function for cards without
981 * MII-compliant PHYs.
982 * For now, this is mainly geared towards 80c24 support; in case of further
983 * requirements for other types (i82503, ...?) either extend this mechanism
984 * or split it, whichever is cleaner.
985 */
986static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
987 u32 addr,
988 u32 dir,
989 u32 reg,
990 u16 data)
991{
992 /* might need to allocate a netdev_priv'ed register array eventually
993 * to be able to record state changes, but for now
994 * some fully hardcoded register handling ought to be ok I guess. */
995
996 if (dir == mdi_read) {
997 switch (reg) {
998 case MII_BMCR:
999 /* Auto-negotiation, right? */
1000 return BMCR_ANENABLE |
1001 BMCR_FULLDPLX;
1002 case MII_BMSR:
1003 return BMSR_LSTATUS /* for mii_link_ok() */ |
1004 BMSR_ANEGCAPABLE |
1005 BMSR_10FULL;
1006 case MII_ADVERTISE:
1007 /* 80c24 is a "combo card" PHY, right? */
1008 return ADVERTISE_10HALF |
1009 ADVERTISE_10FULL;
1010 default:
1011 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1012 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1013 dir == mdi_read ? "READ" : "WRITE",
1014 addr, reg, data);
1015 return 0xFFFF;
1016 }
1017 } else {
1018 switch (reg) {
1019 default:
1020 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1021 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1022 dir == mdi_read ? "READ" : "WRITE",
1023 addr, reg, data);
1024 return 0xFFFF;
1025 }
1026 }
1027}
1028static inline int e100_phy_supports_mii(struct nic *nic)
1029{
1030 /* for now, just check it by comparing whether we
1031 are using MII software emulation.
1032 */
1033 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1034}
1035
1036static void e100_get_defaults(struct nic *nic)
1037{
1038 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1039 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1040
1041 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
1042 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1043 if (nic->mac == mac_unknown)
1044 nic->mac = mac_82557_D100_A;
1045
1046 nic->params.rfds = rfds;
1047 nic->params.cbs = cbs;
1048
1049 /* Quadwords to DMA into FIFO before starting frame transmit */
1050 nic->tx_threshold = 0xE0;
1051
1052 /* no interrupt for every tx completion, delay = 256us if not 557 */
1053 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1054 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1055
1056 /* Template for a freshly allocated RFD */
1057 nic->blank_rfd.command = 0;
1058 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1059 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN);
1060
1061 /* MII setup */
1062 nic->mii.phy_id_mask = 0x1F;
1063 nic->mii.reg_num_mask = 0x1F;
1064 nic->mii.dev = nic->netdev;
1065 nic->mii.mdio_read = mdio_read;
1066 nic->mii.mdio_write = mdio_write;
1067}
1068
1069static int e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1070{
1071 struct config *config = &cb->u.config;
1072 u8 *c = (u8 *)config;
1073 struct net_device *netdev = nic->netdev;
1074
1075 cb->command = cpu_to_le16(cb_config);
1076
1077 memset(config, 0, sizeof(struct config));
1078
1079 config->byte_count = 0x16; /* bytes in this struct */
1080 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1081 config->direct_rx_dma = 0x1; /* reserved */
1082 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1083 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1084 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1085 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1086 if (e100_phy_supports_mii(nic))
1087 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1088 config->pad10 = 0x6;
1089 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1090 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1091 config->ifs = 0x6; /* x16 = inter frame spacing */
1092 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1093 config->pad15_1 = 0x1;
1094 config->pad15_2 = 0x1;
1095 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1096 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1097 config->tx_padding = 0x1; /* 1=pad short frames */
1098 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1099 config->pad18 = 0x1;
1100 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1101 config->pad20_1 = 0x1F;
1102 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1103 config->pad21_1 = 0x5;
1104
1105 config->adaptive_ifs = nic->adaptive_ifs;
1106 config->loopback = nic->loopback;
1107
1108 if (nic->mii.force_media && nic->mii.full_duplex)
1109 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1110
1111 if (nic->flags & promiscuous || nic->loopback) {
1112 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1113 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1114 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1115 }
1116
1117 if (unlikely(netdev->features & NETIF_F_RXFCS))
1118 config->rx_crc_transfer = 0x1; /* 1=save, 0=discard */
1119
1120 if (nic->flags & multicast_all)
1121 config->multicast_all = 0x1; /* 1=accept, 0=no */
1122
1123 /* disable WoL when up */
1124 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1125 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1126
1127 if (nic->mac >= mac_82558_D101_A4) {
1128 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1129 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1130 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1131 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1132 if (nic->mac >= mac_82559_D101M) {
1133 config->tno_intr = 0x1; /* TCO stats enable */
1134 /* Enable TCO in extended config */
1135 if (nic->mac >= mac_82551_10) {
1136 config->byte_count = 0x20; /* extended bytes */
1137 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1138 }
1139 } else {
1140 config->standard_stat_counter = 0x0;
1141 }
1142 }
1143
1144 if (netdev->features & NETIF_F_RXALL) {
1145 config->rx_save_overruns = 0x1; /* 1=save, 0=discard */
1146 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1147 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1148 }
1149
1150 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[00-07]=%8ph\n",
1151 c + 0);
1152 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[08-15]=%8ph\n",
1153 c + 8);
1154 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[16-23]=%8ph\n",
1155 c + 16);
1156 return 0;
1157}
1158
1159/*************************************************************************
1160* CPUSaver parameters
1161*
1162* All CPUSaver parameters are 16-bit literals that are part of a
1163* "move immediate value" instruction. By changing the value of
1164* the literal in the instruction before the code is loaded, the
1165* driver can change the algorithm.
1166*
1167* INTDELAY - This loads the dead-man timer with its initial value.
1168* When this timer expires the interrupt is asserted, and the
1169* timer is reset each time a new packet is received. (see
1170* BUNDLEMAX below to set the limit on number of chained packets)
1171* The current default is 0x600 or 1536. Experiments show that
1172* the value should probably stay within the 0x200 - 0x1000.
1173*
1174* BUNDLEMAX -
1175* This sets the maximum number of frames that will be bundled. In
1176* some situations, such as the TCP windowing algorithm, it may be
1177* better to limit the growth of the bundle size than let it go as
1178* high as it can, because that could cause too much added latency.
1179* The default is six, because this is the number of packets in the
1180* default TCP window size. A value of 1 would make CPUSaver indicate
1181* an interrupt for every frame received. If you do not want to put
1182* a limit on the bundle size, set this value to xFFFF.
1183*
1184* BUNDLESMALL -
1185* This contains a bit-mask describing the minimum size frame that
1186* will be bundled. The default masks the lower 7 bits, which means
1187* that any frame less than 128 bytes in length will not be bundled,
1188* but will instead immediately generate an interrupt. This does
1189* not affect the current bundle in any way. Any frame that is 128
1190* bytes or large will be bundled normally. This feature is meant
1191* to provide immediate indication of ACK frames in a TCP environment.
1192* Customers were seeing poor performance when a machine with CPUSaver
1193* enabled was sending but not receiving. The delay introduced when
1194* the ACKs were received was enough to reduce total throughput, because
1195* the sender would sit idle until the ACK was finally seen.
1196*
1197* The current default is 0xFF80, which masks out the lower 7 bits.
1198* This means that any frame which is x7F (127) bytes or smaller
1199* will cause an immediate interrupt. Because this value must be a
1200* bit mask, there are only a few valid values that can be used. To
1201* turn this feature off, the driver can write the value xFFFF to the
1202* lower word of this instruction (in the same way that the other
1203* parameters are used). Likewise, a value of 0xF800 (2047) would
1204* cause an interrupt to be generated for every frame, because all
1205* standard Ethernet frames are <= 2047 bytes in length.
1206*************************************************************************/
1207
1208/* if you wish to disable the ucode functionality, while maintaining the
1209 * workarounds it provides, set the following defines to:
1210 * BUNDLESMALL 0
1211 * BUNDLEMAX 1
1212 * INTDELAY 1
1213 */
1214#define BUNDLESMALL 1
1215#define BUNDLEMAX (u16)6
1216#define INTDELAY (u16)1536 /* 0x600 */
1217
1218/* Initialize firmware */
1219static const struct firmware *e100_request_firmware(struct nic *nic)
1220{
1221 const char *fw_name;
1222 const struct firmware *fw = nic->fw;
1223 u8 timer, bundle, min_size;
1224 int err = 0;
1225 bool required = false;
1226
1227 /* do not load u-code for ICH devices */
1228 if (nic->flags & ich)
1229 return NULL;
1230
1231 /* Search for ucode match against h/w revision
1232 *
1233 * Based on comments in the source code for the FreeBSD fxp
1234 * driver, the FIRMWARE_D102E ucode includes both CPUSaver and
1235 *
1236 * "fixes for bugs in the B-step hardware (specifically, bugs
1237 * with Inline Receive)."
1238 *
1239 * So we must fail if it cannot be loaded.
1240 *
1241 * The other microcode files are only required for the optional
1242 * CPUSaver feature. Nice to have, but no reason to fail.
1243 */
1244 if (nic->mac == mac_82559_D101M) {
1245 fw_name = FIRMWARE_D101M;
1246 } else if (nic->mac == mac_82559_D101S) {
1247 fw_name = FIRMWARE_D101S;
1248 } else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10) {
1249 fw_name = FIRMWARE_D102E;
1250 required = true;
1251 } else { /* No ucode on other devices */
1252 return NULL;
1253 }
1254
1255 /* If the firmware has not previously been loaded, request a pointer
1256 * to it. If it was previously loaded, we are reinitializing the
1257 * adapter, possibly in a resume from hibernate, in which case
1258 * request_firmware() cannot be used.
1259 */
1260 if (!fw)
1261 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1262
1263 if (err) {
1264 if (required) {
1265 netif_err(nic, probe, nic->netdev,
1266 "Failed to load firmware \"%s\": %d\n",
1267 fw_name, err);
1268 return ERR_PTR(err);
1269 } else {
1270 netif_info(nic, probe, nic->netdev,
1271 "CPUSaver disabled. Needs \"%s\": %d\n",
1272 fw_name, err);
1273 return NULL;
1274 }
1275 }
1276
1277 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1278 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1279 if (fw->size != UCODE_SIZE * 4 + 3) {
1280 netif_err(nic, probe, nic->netdev,
1281 "Firmware \"%s\" has wrong size %zu\n",
1282 fw_name, fw->size);
1283 release_firmware(fw);
1284 return ERR_PTR(-EINVAL);
1285 }
1286
1287 /* Read timer, bundle and min_size from end of firmware blob */
1288 timer = fw->data[UCODE_SIZE * 4];
1289 bundle = fw->data[UCODE_SIZE * 4 + 1];
1290 min_size = fw->data[UCODE_SIZE * 4 + 2];
1291
1292 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1293 min_size >= UCODE_SIZE) {
1294 netif_err(nic, probe, nic->netdev,
1295 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1296 fw_name, timer, bundle, min_size);
1297 release_firmware(fw);
1298 return ERR_PTR(-EINVAL);
1299 }
1300
1301 /* OK, firmware is validated and ready to use. Save a pointer
1302 * to it in the nic */
1303 nic->fw = fw;
1304 return fw;
1305}
1306
1307static int e100_setup_ucode(struct nic *nic, struct cb *cb,
1308 struct sk_buff *skb)
1309{
1310 const struct firmware *fw = (void *)skb;
1311 u8 timer, bundle, min_size;
1312
1313 /* It's not a real skb; we just abused the fact that e100_exec_cb
1314 will pass it through to here... */
1315 cb->skb = NULL;
1316
1317 /* firmware is stored as little endian already */
1318 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1319
1320 /* Read timer, bundle and min_size from end of firmware blob */
1321 timer = fw->data[UCODE_SIZE * 4];
1322 bundle = fw->data[UCODE_SIZE * 4 + 1];
1323 min_size = fw->data[UCODE_SIZE * 4 + 2];
1324
1325 /* Insert user-tunable settings in cb->u.ucode */
1326 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1327 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1328 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1329 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1330 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1331 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1332
1333 cb->command = cpu_to_le16(cb_ucode | cb_el);
1334 return 0;
1335}
1336
1337static inline int e100_load_ucode_wait(struct nic *nic)
1338{
1339 const struct firmware *fw;
1340 int err = 0, counter = 50;
1341 struct cb *cb = nic->cb_to_clean;
1342
1343 fw = e100_request_firmware(nic);
1344 /* If it's NULL, then no ucode is required */
1345 if (IS_ERR_OR_NULL(fw))
1346 return PTR_ERR_OR_ZERO(fw);
1347
1348 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1349 netif_err(nic, probe, nic->netdev,
1350 "ucode cmd failed with error %d\n", err);
1351
1352 /* must restart cuc */
1353 nic->cuc_cmd = cuc_start;
1354
1355 /* wait for completion */
1356 e100_write_flush(nic);
1357 udelay(10);
1358
1359 /* wait for possibly (ouch) 500ms */
1360 while (!(cb->status & cpu_to_le16(cb_complete))) {
1361 msleep(10);
1362 if (!--counter) break;
1363 }
1364
1365 /* ack any interrupts, something could have been set */
1366 iowrite8(~0, &nic->csr->scb.stat_ack);
1367
1368 /* if the command failed, or is not OK, notify and return */
1369 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1370 netif_err(nic, probe, nic->netdev, "ucode load failed\n");
1371 err = -EPERM;
1372 }
1373
1374 return err;
1375}
1376
1377static int e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1378 struct sk_buff *skb)
1379{
1380 cb->command = cpu_to_le16(cb_iaaddr);
1381 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1382 return 0;
1383}
1384
1385static int e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1386{
1387 cb->command = cpu_to_le16(cb_dump);
1388 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1389 offsetof(struct mem, dump_buf));
1390 return 0;
1391}
1392
1393static int e100_phy_check_without_mii(struct nic *nic)
1394{
1395 u8 phy_type;
1396 int without_mii;
1397
1398 phy_type = (le16_to_cpu(nic->eeprom[eeprom_phy_iface]) >> 8) & 0x0f;
1399
1400 switch (phy_type) {
1401 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1402 case I82503: /* Non-MII PHY; UNTESTED! */
1403 case S80C24: /* Non-MII PHY; tested and working */
1404 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1405 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1406 * doesn't have a programming interface of any sort. The
1407 * media is sensed automatically based on how the link partner
1408 * is configured. This is, in essence, manual configuration.
1409 */
1410 netif_info(nic, probe, nic->netdev,
1411 "found MII-less i82503 or 80c24 or other PHY\n");
1412
1413 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1414 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1415
1416 /* these might be needed for certain MII-less cards...
1417 * nic->flags |= ich;
1418 * nic->flags |= ich_10h_workaround; */
1419
1420 without_mii = 1;
1421 break;
1422 default:
1423 without_mii = 0;
1424 break;
1425 }
1426 return without_mii;
1427}
1428
1429#define NCONFIG_AUTO_SWITCH 0x0080
1430#define MII_NSC_CONG MII_RESV1
1431#define NSC_CONG_ENABLE 0x0100
1432#define NSC_CONG_TXREADY 0x0400
1433static int e100_phy_init(struct nic *nic)
1434{
1435 struct net_device *netdev = nic->netdev;
1436 u32 addr;
1437 u16 bmcr, stat, id_lo, id_hi, cong;
1438
1439 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1440 for (addr = 0; addr < 32; addr++) {
1441 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1442 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1443 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1444 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1445 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1446 break;
1447 }
1448 if (addr == 32) {
1449 /* uhoh, no PHY detected: check whether we seem to be some
1450 * weird, rare variant which is *known* to not have any MII.
1451 * But do this AFTER MII checking only, since this does
1452 * lookup of EEPROM values which may easily be unreliable. */
1453 if (e100_phy_check_without_mii(nic))
1454 return 0; /* simply return and hope for the best */
1455 else {
1456 /* for unknown cases log a fatal error */
1457 netif_err(nic, hw, nic->netdev,
1458 "Failed to locate any known PHY, aborting\n");
1459 return -EAGAIN;
1460 }
1461 } else
1462 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1463 "phy_addr = %d\n", nic->mii.phy_id);
1464
1465 /* Get phy ID */
1466 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1467 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1468 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1469 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1470 "phy ID = 0x%08X\n", nic->phy);
1471
1472 /* Select the phy and isolate the rest */
1473 for (addr = 0; addr < 32; addr++) {
1474 if (addr != nic->mii.phy_id) {
1475 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1476 } else if (nic->phy != phy_82552_v) {
1477 bmcr = mdio_read(netdev, addr, MII_BMCR);
1478 mdio_write(netdev, addr, MII_BMCR,
1479 bmcr & ~BMCR_ISOLATE);
1480 }
1481 }
1482 /*
1483 * Workaround for 82552:
1484 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1485 * other phy_id's) using bmcr value from addr discovery loop above.
1486 */
1487 if (nic->phy == phy_82552_v)
1488 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1489 bmcr & ~BMCR_ISOLATE);
1490
1491 /* Handle National tx phys */
1492#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1493 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1494 /* Disable congestion control */
1495 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1496 cong |= NSC_CONG_TXREADY;
1497 cong &= ~NSC_CONG_ENABLE;
1498 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1499 }
1500
1501 if (nic->phy == phy_82552_v) {
1502 u16 = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1503
1504 /* assign special tweaked mdio_ctrl() function */
1505 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1506
1507 /* Workaround Si not advertising flow-control during autoneg */
1508 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1509 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1510
1511 /* Reset for the above changes to take effect */
1512 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1513 bmcr |= BMCR_RESET;
1514 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1515 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1516 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1517 (le16_to_cpu(nic->eeprom[eeprom_cnfg_mdix]) & eeprom_mdix_enabled))) {
1518 /* enable/disable MDI/MDI-X auto-switching. */
1519 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1520 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1521 }
1522
1523 return 0;
1524}
1525
1526static int e100_hw_init(struct nic *nic)
1527{
1528 int err = 0;
1529
1530 e100_hw_reset(nic);
1531
1532 netif_err(nic, hw, nic->netdev, "e100_hw_init\n");
1533 if ((err = e100_self_test(nic)))
1534 return err;
1535
1536 if ((err = e100_phy_init(nic)))
1537 return err;
1538 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1539 return err;
1540 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1541 return err;
1542 if ((err = e100_load_ucode_wait(nic)))
1543 return err;
1544 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1545 return err;
1546 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1547 return err;
1548 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1549 nic->dma_addr + offsetof(struct mem, stats))))
1550 return err;
1551 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1552 return err;
1553
1554 e100_disable_irq(nic);
1555
1556 return 0;
1557}
1558
1559static int e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1560{
1561 struct net_device *netdev = nic->netdev;
1562 struct netdev_hw_addr *ha;
1563 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS);
1564
1565 cb->command = cpu_to_le16(cb_multi);
1566 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1567 i = 0;
1568 netdev_for_each_mc_addr(ha, netdev) {
1569 if (i == count)
1570 break;
1571 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &ha->addr,
1572 ETH_ALEN);
1573 }
1574 return 0;
1575}
1576
1577static void e100_set_multicast_list(struct net_device *netdev)
1578{
1579 struct nic *nic = netdev_priv(netdev);
1580
1581 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1582 "mc_count=%d, flags=0x%04X\n",
1583 netdev_mc_count(netdev), netdev->flags);
1584
1585 if (netdev->flags & IFF_PROMISC)
1586 nic->flags |= promiscuous;
1587 else
1588 nic->flags &= ~promiscuous;
1589
1590 if (netdev->flags & IFF_ALLMULTI ||
1591 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS)
1592 nic->flags |= multicast_all;
1593 else
1594 nic->flags &= ~multicast_all;
1595
1596 e100_exec_cb(nic, NULL, e100_configure);
1597 e100_exec_cb(nic, NULL, e100_multi);
1598}
1599
1600static void e100_update_stats(struct nic *nic)
1601{
1602 struct net_device *dev = nic->netdev;
1603 struct net_device_stats *ns = &dev->stats;
1604 struct stats *s = &nic->mem->stats;
1605 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1606 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1607 &s->complete;
1608
1609 /* Device's stats reporting may take several microseconds to
1610 * complete, so we're always waiting for results of the
1611 * previous command. */
1612
1613 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1614 *complete = 0;
1615 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1616 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1617 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1618 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1619 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1620 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1621 ns->collisions += nic->tx_collisions;
1622 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1623 le32_to_cpu(s->tx_lost_crs);
1624 nic->rx_short_frame_errors +=
1625 le32_to_cpu(s->rx_short_frame_errors);
1626 ns->rx_length_errors = nic->rx_short_frame_errors +
1627 nic->rx_over_length_errors;
1628 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1629 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1630 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1631 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1632 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1633 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1634 le32_to_cpu(s->rx_alignment_errors) +
1635 le32_to_cpu(s->rx_short_frame_errors) +
1636 le32_to_cpu(s->rx_cdt_errors);
1637 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1638 nic->tx_single_collisions +=
1639 le32_to_cpu(s->tx_single_collisions);
1640 nic->tx_multiple_collisions +=
1641 le32_to_cpu(s->tx_multiple_collisions);
1642 if (nic->mac >= mac_82558_D101_A4) {
1643 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1644 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1645 nic->rx_fc_unsupported +=
1646 le32_to_cpu(s->fc_rcv_unsupported);
1647 if (nic->mac >= mac_82559_D101M) {
1648 nic->tx_tco_frames +=
1649 le16_to_cpu(s->xmt_tco_frames);
1650 nic->rx_tco_frames +=
1651 le16_to_cpu(s->rcv_tco_frames);
1652 }
1653 }
1654 }
1655
1656
1657 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1658 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1659 "exec cuc_dump_reset failed\n");
1660}
1661
1662static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1663{
1664 /* Adjust inter-frame-spacing (IFS) between two transmits if
1665 * we're getting collisions on a half-duplex connection. */
1666
1667 if (duplex == DUPLEX_HALF) {
1668 u32 prev = nic->adaptive_ifs;
1669 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1670
1671 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1672 (nic->tx_frames > min_frames)) {
1673 if (nic->adaptive_ifs < 60)
1674 nic->adaptive_ifs += 5;
1675 } else if (nic->tx_frames < min_frames) {
1676 if (nic->adaptive_ifs >= 5)
1677 nic->adaptive_ifs -= 5;
1678 }
1679 if (nic->adaptive_ifs != prev)
1680 e100_exec_cb(nic, NULL, e100_configure);
1681 }
1682}
1683
1684static void e100_watchdog(struct timer_list *t)
1685{
1686 struct nic *nic = from_timer(nic, t, watchdog);
1687 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1688 u32 speed;
1689
1690 netif_printk(nic, timer, KERN_DEBUG, nic->netdev,
1691 "right now = %ld\n", jiffies);
1692
1693 /* mii library handles link maintenance tasks */
1694
1695 mii_ethtool_gset(&nic->mii, &cmd);
1696 speed = ethtool_cmd_speed(&cmd);
1697
1698 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1699 netdev_info(nic->netdev, "NIC Link is Up %u Mbps %s Duplex\n",
1700 speed == SPEED_100 ? 100 : 10,
1701 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1702 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1703 netdev_info(nic->netdev, "NIC Link is Down\n");
1704 }
1705
1706 mii_check_link(&nic->mii);
1707
1708 /* Software generated interrupt to recover from (rare) Rx
1709 * allocation failure.
1710 * Unfortunately have to use a spinlock to not re-enable interrupts
1711 * accidentally, due to hardware that shares a register between the
1712 * interrupt mask bit and the SW Interrupt generation bit */
1713 spin_lock_irq(&nic->cmd_lock);
1714 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1715 e100_write_flush(nic);
1716 spin_unlock_irq(&nic->cmd_lock);
1717
1718 e100_update_stats(nic);
1719 e100_adjust_adaptive_ifs(nic, speed, cmd.duplex);
1720
1721 if (nic->mac <= mac_82557_D100_C)
1722 /* Issue a multicast command to workaround a 557 lock up */
1723 e100_set_multicast_list(nic->netdev);
1724
1725 if (nic->flags & ich && speed == SPEED_10 && cmd.duplex == DUPLEX_HALF)
1726 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1727 nic->flags |= ich_10h_workaround;
1728 else
1729 nic->flags &= ~ich_10h_workaround;
1730
1731 mod_timer(&nic->watchdog,
1732 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1733}
1734
1735static int e100_xmit_prepare(struct nic *nic, struct cb *cb,
1736 struct sk_buff *skb)
1737{
1738 dma_addr_t dma_addr;
1739 cb->command = nic->tx_command;
1740
1741 dma_addr = dma_map_single(&nic->pdev->dev, skb->data, skb->len,
1742 DMA_TO_DEVICE);
1743 /* If we can't map the skb, have the upper layer try later */
1744 if (dma_mapping_error(&nic->pdev->dev, dma_addr)) {
1745 dev_kfree_skb_any(skb);
1746 skb = NULL;
1747 return -ENOMEM;
1748 }
1749
1750 /*
1751 * Use the last 4 bytes of the SKB payload packet as the CRC, used for
1752 * testing, ie sending frames with bad CRC.
1753 */
1754 if (unlikely(skb->no_fcs))
1755 cb->command |= cpu_to_le16(cb_tx_nc);
1756 else
1757 cb->command &= ~cpu_to_le16(cb_tx_nc);
1758
1759 /* interrupt every 16 packets regardless of delay */
1760 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1761 cb->command |= cpu_to_le16(cb_i);
1762 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1763 cb->u.tcb.tcb_byte_count = 0;
1764 cb->u.tcb.threshold = nic->tx_threshold;
1765 cb->u.tcb.tbd_count = 1;
1766 cb->u.tcb.tbd.buf_addr = cpu_to_le32(dma_addr);
1767 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1768 skb_tx_timestamp(skb);
1769 return 0;
1770}
1771
1772static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1773 struct net_device *netdev)
1774{
1775 struct nic *nic = netdev_priv(netdev);
1776 int err;
1777
1778 if (nic->flags & ich_10h_workaround) {
1779 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1780 Issue a NOP command followed by a 1us delay before
1781 issuing the Tx command. */
1782 if (e100_exec_cmd(nic, cuc_nop, 0))
1783 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1784 "exec cuc_nop failed\n");
1785 udelay(1);
1786 }
1787
1788 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1789
1790 switch (err) {
1791 case -ENOSPC:
1792 /* We queued the skb, but now we're out of space. */
1793 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1794 "No space for CB\n");
1795 netif_stop_queue(netdev);
1796 break;
1797 case -ENOMEM:
1798 /* This is a hard error - log it. */
1799 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1800 "Out of Tx resources, returning skb\n");
1801 netif_stop_queue(netdev);
1802 return NETDEV_TX_BUSY;
1803 }
1804
1805 return NETDEV_TX_OK;
1806}
1807
1808static int e100_tx_clean(struct nic *nic)
1809{
1810 struct net_device *dev = nic->netdev;
1811 struct cb *cb;
1812 int tx_cleaned = 0;
1813
1814 spin_lock(&nic->cb_lock);
1815
1816 /* Clean CBs marked complete */
1817 for (cb = nic->cb_to_clean;
1818 cb->status & cpu_to_le16(cb_complete);
1819 cb = nic->cb_to_clean = cb->next) {
1820 dma_rmb(); /* read skb after status */
1821 netif_printk(nic, tx_done, KERN_DEBUG, nic->netdev,
1822 "cb[%d]->status = 0x%04X\n",
1823 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1824 cb->status);
1825
1826 if (likely(cb->skb != NULL)) {
1827 dev->stats.tx_packets++;
1828 dev->stats.tx_bytes += cb->skb->len;
1829
1830 dma_unmap_single(&nic->pdev->dev,
1831 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1832 le16_to_cpu(cb->u.tcb.tbd.size),
1833 DMA_TO_DEVICE);
1834 dev_kfree_skb_any(cb->skb);
1835 cb->skb = NULL;
1836 tx_cleaned = 1;
1837 }
1838 cb->status = 0;
1839 nic->cbs_avail++;
1840 }
1841
1842 spin_unlock(&nic->cb_lock);
1843
1844 /* Recover from running out of Tx resources in xmit_frame */
1845 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1846 netif_wake_queue(nic->netdev);
1847
1848 return tx_cleaned;
1849}
1850
1851static void e100_clean_cbs(struct nic *nic)
1852{
1853 if (nic->cbs) {
1854 while (nic->cbs_avail != nic->params.cbs.count) {
1855 struct cb *cb = nic->cb_to_clean;
1856 if (cb->skb) {
1857 dma_unmap_single(&nic->pdev->dev,
1858 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1859 le16_to_cpu(cb->u.tcb.tbd.size),
1860 DMA_TO_DEVICE);
1861 dev_kfree_skb(cb->skb);
1862 }
1863 nic->cb_to_clean = nic->cb_to_clean->next;
1864 nic->cbs_avail++;
1865 }
1866 dma_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1867 nic->cbs = NULL;
1868 nic->cbs_avail = 0;
1869 }
1870 nic->cuc_cmd = cuc_start;
1871 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1872 nic->cbs;
1873}
1874
1875static int e100_alloc_cbs(struct nic *nic)
1876{
1877 struct cb *cb;
1878 unsigned int i, count = nic->params.cbs.count;
1879
1880 nic->cuc_cmd = cuc_start;
1881 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1882 nic->cbs_avail = 0;
1883
1884 nic->cbs = dma_pool_zalloc(nic->cbs_pool, GFP_KERNEL,
1885 &nic->cbs_dma_addr);
1886 if (!nic->cbs)
1887 return -ENOMEM;
1888
1889 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1890 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1891 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1892
1893 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1894 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1895 ((i+1) % count) * sizeof(struct cb));
1896 }
1897
1898 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1899 nic->cbs_avail = count;
1900
1901 return 0;
1902}
1903
1904static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1905{
1906 if (!nic->rxs) return;
1907 if (RU_SUSPENDED != nic->ru_running) return;
1908
1909 /* handle init time starts */
1910 if (!rx) rx = nic->rxs;
1911
1912 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1913 if (rx->skb) {
1914 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1915 nic->ru_running = RU_RUNNING;
1916 }
1917}
1918
1919#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
1920static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1921{
1922 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN)))
1923 return -ENOMEM;
1924
1925 /* Init, and map the RFD. */
1926 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1927 rx->dma_addr = dma_map_single(&nic->pdev->dev, rx->skb->data,
1928 RFD_BUF_LEN, DMA_BIDIRECTIONAL);
1929
1930 if (dma_mapping_error(&nic->pdev->dev, rx->dma_addr)) {
1931 dev_kfree_skb_any(rx->skb);
1932 rx->skb = NULL;
1933 rx->dma_addr = 0;
1934 return -ENOMEM;
1935 }
1936
1937 /* Link the RFD to end of RFA by linking previous RFD to
1938 * this one. We are safe to touch the previous RFD because
1939 * it is protected by the before last buffer's el bit being set */
1940 if (rx->prev->skb) {
1941 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1942 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1943 dma_sync_single_for_device(&nic->pdev->dev,
1944 rx->prev->dma_addr,
1945 sizeof(struct rfd),
1946 DMA_BIDIRECTIONAL);
1947 }
1948
1949 return 0;
1950}
1951
1952static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1953 unsigned int *work_done, unsigned int work_to_do)
1954{
1955 struct net_device *dev = nic->netdev;
1956 struct sk_buff *skb = rx->skb;
1957 struct rfd *rfd = (struct rfd *)skb->data;
1958 u16 rfd_status, actual_size;
1959 u16 fcs_pad = 0;
1960
1961 if (unlikely(work_done && *work_done >= work_to_do))
1962 return -EAGAIN;
1963
1964 /* Need to sync before taking a peek at cb_complete bit */
1965 dma_sync_single_for_cpu(&nic->pdev->dev, rx->dma_addr,
1966 sizeof(struct rfd), DMA_BIDIRECTIONAL);
1967 rfd_status = le16_to_cpu(rfd->status);
1968
1969 netif_printk(nic, rx_status, KERN_DEBUG, nic->netdev,
1970 "status=0x%04X\n", rfd_status);
1971 dma_rmb(); /* read size after status bit */
1972
1973 /* If data isn't ready, nothing to indicate */
1974 if (unlikely(!(rfd_status & cb_complete))) {
1975 /* If the next buffer has the el bit, but we think the receiver
1976 * is still running, check to see if it really stopped while
1977 * we had interrupts off.
1978 * This allows for a fast restart without re-enabling
1979 * interrupts */
1980 if ((le16_to_cpu(rfd->command) & cb_el) &&
1981 (RU_RUNNING == nic->ru_running))
1982
1983 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1984 nic->ru_running = RU_SUSPENDED;
1985 dma_sync_single_for_device(&nic->pdev->dev, rx->dma_addr,
1986 sizeof(struct rfd),
1987 DMA_FROM_DEVICE);
1988 return -ENODATA;
1989 }
1990
1991 /* Get actual data size */
1992 if (unlikely(dev->features & NETIF_F_RXFCS))
1993 fcs_pad = 4;
1994 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1995 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1996 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1997
1998 /* Get data */
1999 dma_unmap_single(&nic->pdev->dev, rx->dma_addr, RFD_BUF_LEN,
2000 DMA_BIDIRECTIONAL);
2001
2002 /* If this buffer has the el bit, but we think the receiver
2003 * is still running, check to see if it really stopped while
2004 * we had interrupts off.
2005 * This allows for a fast restart without re-enabling interrupts.
2006 * This can happen when the RU sees the size change but also sees
2007 * the el bit set. */
2008 if ((le16_to_cpu(rfd->command) & cb_el) &&
2009 (RU_RUNNING == nic->ru_running)) {
2010
2011 if (ioread8(&nic->csr->scb.status) & rus_no_res)
2012 nic->ru_running = RU_SUSPENDED;
2013 }
2014
2015 /* Pull off the RFD and put the actual data (minus eth hdr) */
2016 skb_reserve(skb, sizeof(struct rfd));
2017 skb_put(skb, actual_size);
2018 skb->protocol = eth_type_trans(skb, nic->netdev);
2019
2020 /* If we are receiving all frames, then don't bother
2021 * checking for errors.
2022 */
2023 if (unlikely(dev->features & NETIF_F_RXALL)) {
2024 if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad)
2025 /* Received oversized frame, but keep it. */
2026 nic->rx_over_length_errors++;
2027 goto process_skb;
2028 }
2029
2030 if (unlikely(!(rfd_status & cb_ok))) {
2031 /* Don't indicate if hardware indicates errors */
2032 dev_kfree_skb_any(skb);
2033 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad) {
2034 /* Don't indicate oversized frames */
2035 nic->rx_over_length_errors++;
2036 dev_kfree_skb_any(skb);
2037 } else {
2038process_skb:
2039 dev->stats.rx_packets++;
2040 dev->stats.rx_bytes += (actual_size - fcs_pad);
2041 netif_receive_skb(skb);
2042 if (work_done)
2043 (*work_done)++;
2044 }
2045
2046 rx->skb = NULL;
2047
2048 return 0;
2049}
2050
2051static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
2052 unsigned int work_to_do)
2053{
2054 struct rx *rx;
2055 int restart_required = 0, err = 0;
2056 struct rx *old_before_last_rx, *new_before_last_rx;
2057 struct rfd *old_before_last_rfd, *new_before_last_rfd;
2058
2059 /* Indicate newly arrived packets */
2060 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
2061 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
2062 /* Hit quota or no more to clean */
2063 if (-EAGAIN == err || -ENODATA == err)
2064 break;
2065 }
2066
2067
2068 /* On EAGAIN, hit quota so have more work to do, restart once
2069 * cleanup is complete.
2070 * Else, are we already rnr? then pay attention!!! this ensures that
2071 * the state machine progression never allows a start with a
2072 * partially cleaned list, avoiding a race between hardware
2073 * and rx_to_clean when in NAPI mode */
2074 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
2075 restart_required = 1;
2076
2077 old_before_last_rx = nic->rx_to_use->prev->prev;
2078 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
2079
2080 /* Alloc new skbs to refill list */
2081 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
2082 if (unlikely(e100_rx_alloc_skb(nic, rx)))
2083 break; /* Better luck next time (see watchdog) */
2084 }
2085
2086 new_before_last_rx = nic->rx_to_use->prev->prev;
2087 if (new_before_last_rx != old_before_last_rx) {
2088 /* Set the el-bit on the buffer that is before the last buffer.
2089 * This lets us update the next pointer on the last buffer
2090 * without worrying about hardware touching it.
2091 * We set the size to 0 to prevent hardware from touching this
2092 * buffer.
2093 * When the hardware hits the before last buffer with el-bit
2094 * and size of 0, it will RNR interrupt, the RUS will go into
2095 * the No Resources state. It will not complete nor write to
2096 * this buffer. */
2097 new_before_last_rfd =
2098 (struct rfd *)new_before_last_rx->skb->data;
2099 new_before_last_rfd->size = 0;
2100 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2101 dma_sync_single_for_device(&nic->pdev->dev,
2102 new_before_last_rx->dma_addr,
2103 sizeof(struct rfd),
2104 DMA_BIDIRECTIONAL);
2105
2106 /* Now that we have a new stopping point, we can clear the old
2107 * stopping point. We must sync twice to get the proper
2108 * ordering on the hardware side of things. */
2109 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2110 dma_sync_single_for_device(&nic->pdev->dev,
2111 old_before_last_rx->dma_addr,
2112 sizeof(struct rfd),
2113 DMA_BIDIRECTIONAL);
2114 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN
2115 + ETH_FCS_LEN);
2116 dma_sync_single_for_device(&nic->pdev->dev,
2117 old_before_last_rx->dma_addr,
2118 sizeof(struct rfd),
2119 DMA_BIDIRECTIONAL);
2120 }
2121
2122 if (restart_required) {
2123 // ack the rnr?
2124 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2125 e100_start_receiver(nic, nic->rx_to_clean);
2126 if (work_done)
2127 (*work_done)++;
2128 }
2129}
2130
2131static void e100_rx_clean_list(struct nic *nic)
2132{
2133 struct rx *rx;
2134 unsigned int i, count = nic->params.rfds.count;
2135
2136 nic->ru_running = RU_UNINITIALIZED;
2137
2138 if (nic->rxs) {
2139 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2140 if (rx->skb) {
2141 dma_unmap_single(&nic->pdev->dev,
2142 rx->dma_addr, RFD_BUF_LEN,
2143 DMA_BIDIRECTIONAL);
2144 dev_kfree_skb(rx->skb);
2145 }
2146 }
2147 kfree(nic->rxs);
2148 nic->rxs = NULL;
2149 }
2150
2151 nic->rx_to_use = nic->rx_to_clean = NULL;
2152}
2153
2154static int e100_rx_alloc_list(struct nic *nic)
2155{
2156 struct rx *rx;
2157 unsigned int i, count = nic->params.rfds.count;
2158 struct rfd *before_last;
2159
2160 nic->rx_to_use = nic->rx_to_clean = NULL;
2161 nic->ru_running = RU_UNINITIALIZED;
2162
2163 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_KERNEL)))
2164 return -ENOMEM;
2165
2166 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2167 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2168 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2169 if (e100_rx_alloc_skb(nic, rx)) {
2170 e100_rx_clean_list(nic);
2171 return -ENOMEM;
2172 }
2173 }
2174 /* Set the el-bit on the buffer that is before the last buffer.
2175 * This lets us update the next pointer on the last buffer without
2176 * worrying about hardware touching it.
2177 * We set the size to 0 to prevent hardware from touching this buffer.
2178 * When the hardware hits the before last buffer with el-bit and size
2179 * of 0, it will RNR interrupt, the RU will go into the No Resources
2180 * state. It will not complete nor write to this buffer. */
2181 rx = nic->rxs->prev->prev;
2182 before_last = (struct rfd *)rx->skb->data;
2183 before_last->command |= cpu_to_le16(cb_el);
2184 before_last->size = 0;
2185 dma_sync_single_for_device(&nic->pdev->dev, rx->dma_addr,
2186 sizeof(struct rfd), DMA_BIDIRECTIONAL);
2187
2188 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2189 nic->ru_running = RU_SUSPENDED;
2190
2191 return 0;
2192}
2193
2194static irqreturn_t e100_intr(int irq, void *dev_id)
2195{
2196 struct net_device *netdev = dev_id;
2197 struct nic *nic = netdev_priv(netdev);
2198 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2199
2200 netif_printk(nic, intr, KERN_DEBUG, nic->netdev,
2201 "stat_ack = 0x%02X\n", stat_ack);
2202
2203 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
2204 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2205 return IRQ_NONE;
2206
2207 /* Ack interrupt(s) */
2208 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2209
2210 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2211 if (stat_ack & stat_ack_rnr)
2212 nic->ru_running = RU_SUSPENDED;
2213
2214 if (likely(napi_schedule_prep(&nic->napi))) {
2215 e100_disable_irq(nic);
2216 __napi_schedule(&nic->napi);
2217 }
2218
2219 return IRQ_HANDLED;
2220}
2221
2222static int e100_poll(struct napi_struct *napi, int budget)
2223{
2224 struct nic *nic = container_of(napi, struct nic, napi);
2225 unsigned int work_done = 0;
2226
2227 e100_rx_clean(nic, &work_done, budget);
2228 e100_tx_clean(nic);
2229
2230 /* If budget fully consumed, continue polling */
2231 if (work_done == budget)
2232 return budget;
2233
2234 /* only re-enable interrupt if stack agrees polling is really done */
2235 if (likely(napi_complete_done(napi, work_done)))
2236 e100_enable_irq(nic);
2237
2238 return work_done;
2239}
2240
2241#ifdef CONFIG_NET_POLL_CONTROLLER
2242static void e100_netpoll(struct net_device *netdev)
2243{
2244 struct nic *nic = netdev_priv(netdev);
2245
2246 e100_disable_irq(nic);
2247 e100_intr(nic->pdev->irq, netdev);
2248 e100_tx_clean(nic);
2249 e100_enable_irq(nic);
2250}
2251#endif
2252
2253static int e100_set_mac_address(struct net_device *netdev, void *p)
2254{
2255 struct nic *nic = netdev_priv(netdev);
2256 struct sockaddr *addr = p;
2257
2258 if (!is_valid_ether_addr(addr->sa_data))
2259 return -EADDRNOTAVAIL;
2260
2261 eth_hw_addr_set(netdev, addr->sa_data);
2262 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2263
2264 return 0;
2265}
2266
2267static int e100_asf(struct nic *nic)
2268{
2269 /* ASF can be enabled from eeprom */
2270 return (nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2271 (le16_to_cpu(nic->eeprom[eeprom_config_asf]) & eeprom_asf) &&
2272 !(le16_to_cpu(nic->eeprom[eeprom_config_asf]) & eeprom_gcl) &&
2273 ((le16_to_cpu(nic->eeprom[eeprom_smbus_addr]) & 0xFF) != 0xFE);
2274}
2275
2276static int e100_up(struct nic *nic)
2277{
2278 int err;
2279
2280 if ((err = e100_rx_alloc_list(nic)))
2281 return err;
2282 if ((err = e100_alloc_cbs(nic)))
2283 goto err_rx_clean_list;
2284 if ((err = e100_hw_init(nic)))
2285 goto err_clean_cbs;
2286 e100_set_multicast_list(nic->netdev);
2287 e100_start_receiver(nic, NULL);
2288 mod_timer(&nic->watchdog, jiffies);
2289 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2290 nic->netdev->name, nic->netdev)))
2291 goto err_no_irq;
2292 netif_wake_queue(nic->netdev);
2293 napi_enable(&nic->napi);
2294 /* enable ints _after_ enabling poll, preventing a race between
2295 * disable ints+schedule */
2296 e100_enable_irq(nic);
2297 return 0;
2298
2299err_no_irq:
2300 del_timer_sync(&nic->watchdog);
2301err_clean_cbs:
2302 e100_clean_cbs(nic);
2303err_rx_clean_list:
2304 e100_rx_clean_list(nic);
2305 return err;
2306}
2307
2308static void e100_down(struct nic *nic)
2309{
2310 /* wait here for poll to complete */
2311 napi_disable(&nic->napi);
2312 netif_stop_queue(nic->netdev);
2313 e100_hw_reset(nic);
2314 free_irq(nic->pdev->irq, nic->netdev);
2315 del_timer_sync(&nic->watchdog);
2316 netif_carrier_off(nic->netdev);
2317 e100_clean_cbs(nic);
2318 e100_rx_clean_list(nic);
2319}
2320
2321static void e100_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2322{
2323 struct nic *nic = netdev_priv(netdev);
2324
2325 /* Reset outside of interrupt context, to avoid request_irq
2326 * in interrupt context */
2327 schedule_work(&nic->tx_timeout_task);
2328}
2329
2330static void e100_tx_timeout_task(struct work_struct *work)
2331{
2332 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2333 struct net_device *netdev = nic->netdev;
2334
2335 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
2336 "scb.status=0x%02X\n", ioread8(&nic->csr->scb.status));
2337
2338 rtnl_lock();
2339 if (netif_running(netdev)) {
2340 e100_down(netdev_priv(netdev));
2341 e100_up(netdev_priv(netdev));
2342 }
2343 rtnl_unlock();
2344}
2345
2346static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2347{
2348 int err;
2349 struct sk_buff *skb;
2350
2351 /* Use driver resources to perform internal MAC or PHY
2352 * loopback test. A single packet is prepared and transmitted
2353 * in loopback mode, and the test passes if the received
2354 * packet compares byte-for-byte to the transmitted packet. */
2355
2356 if ((err = e100_rx_alloc_list(nic)))
2357 return err;
2358 if ((err = e100_alloc_cbs(nic)))
2359 goto err_clean_rx;
2360
2361 /* ICH PHY loopback is broken so do MAC loopback instead */
2362 if (nic->flags & ich && loopback_mode == lb_phy)
2363 loopback_mode = lb_mac;
2364
2365 nic->loopback = loopback_mode;
2366 if ((err = e100_hw_init(nic)))
2367 goto err_loopback_none;
2368
2369 if (loopback_mode == lb_phy)
2370 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2371 BMCR_LOOPBACK);
2372
2373 e100_start_receiver(nic, NULL);
2374
2375 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2376 err = -ENOMEM;
2377 goto err_loopback_none;
2378 }
2379 skb_put(skb, ETH_DATA_LEN);
2380 memset(skb->data, 0xFF, ETH_DATA_LEN);
2381 e100_xmit_frame(skb, nic->netdev);
2382
2383 msleep(10);
2384
2385 dma_sync_single_for_cpu(&nic->pdev->dev, nic->rx_to_clean->dma_addr,
2386 RFD_BUF_LEN, DMA_BIDIRECTIONAL);
2387
2388 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2389 skb->data, ETH_DATA_LEN))
2390 err = -EAGAIN;
2391
2392err_loopback_none:
2393 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2394 nic->loopback = lb_none;
2395 e100_clean_cbs(nic);
2396 e100_hw_reset(nic);
2397err_clean_rx:
2398 e100_rx_clean_list(nic);
2399 return err;
2400}
2401
2402#define MII_LED_CONTROL 0x1B
2403#define E100_82552_LED_OVERRIDE 0x19
2404#define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2405#define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2406
2407static int e100_get_link_ksettings(struct net_device *netdev,
2408 struct ethtool_link_ksettings *cmd)
2409{
2410 struct nic *nic = netdev_priv(netdev);
2411
2412 mii_ethtool_get_link_ksettings(&nic->mii, cmd);
2413
2414 return 0;
2415}
2416
2417static int e100_set_link_ksettings(struct net_device *netdev,
2418 const struct ethtool_link_ksettings *cmd)
2419{
2420 struct nic *nic = netdev_priv(netdev);
2421 int err;
2422
2423 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2424 err = mii_ethtool_set_link_ksettings(&nic->mii, cmd);
2425 e100_exec_cb(nic, NULL, e100_configure);
2426
2427 return err;
2428}
2429
2430static void e100_get_drvinfo(struct net_device *netdev,
2431 struct ethtool_drvinfo *info)
2432{
2433 struct nic *nic = netdev_priv(netdev);
2434 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2435 strlcpy(info->bus_info, pci_name(nic->pdev),
2436 sizeof(info->bus_info));
2437}
2438
2439#define E100_PHY_REGS 0x1D
2440static int e100_get_regs_len(struct net_device *netdev)
2441{
2442 struct nic *nic = netdev_priv(netdev);
2443
2444 /* We know the number of registers, and the size of the dump buffer.
2445 * Calculate the total size in bytes.
2446 */
2447 return (1 + E100_PHY_REGS) * sizeof(u32) + sizeof(nic->mem->dump_buf);
2448}
2449
2450static void e100_get_regs(struct net_device *netdev,
2451 struct ethtool_regs *regs, void *p)
2452{
2453 struct nic *nic = netdev_priv(netdev);
2454 u32 *buff = p;
2455 int i;
2456
2457 regs->version = (1 << 24) | nic->pdev->revision;
2458 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2459 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2460 ioread16(&nic->csr->scb.status);
2461 for (i = 0; i < E100_PHY_REGS; i++)
2462 /* Note that we read the registers in reverse order. This
2463 * ordering is the ABI apparently used by ethtool and other
2464 * applications.
2465 */
2466 buff[1 + i] = mdio_read(netdev, nic->mii.phy_id,
2467 E100_PHY_REGS - 1 - i);
2468 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2469 e100_exec_cb(nic, NULL, e100_dump);
2470 msleep(10);
2471 memcpy(&buff[1 + E100_PHY_REGS], nic->mem->dump_buf,
2472 sizeof(nic->mem->dump_buf));
2473}
2474
2475static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2476{
2477 struct nic *nic = netdev_priv(netdev);
2478 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2479 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2480}
2481
2482static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2483{
2484 struct nic *nic = netdev_priv(netdev);
2485
2486 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2487 !device_can_wakeup(&nic->pdev->dev))
2488 return -EOPNOTSUPP;
2489
2490 if (wol->wolopts)
2491 nic->flags |= wol_magic;
2492 else
2493 nic->flags &= ~wol_magic;
2494
2495 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2496
2497 e100_exec_cb(nic, NULL, e100_configure);
2498
2499 return 0;
2500}
2501
2502static u32 e100_get_msglevel(struct net_device *netdev)
2503{
2504 struct nic *nic = netdev_priv(netdev);
2505 return nic->msg_enable;
2506}
2507
2508static void e100_set_msglevel(struct net_device *netdev, u32 value)
2509{
2510 struct nic *nic = netdev_priv(netdev);
2511 nic->msg_enable = value;
2512}
2513
2514static int e100_nway_reset(struct net_device *netdev)
2515{
2516 struct nic *nic = netdev_priv(netdev);
2517 return mii_nway_restart(&nic->mii);
2518}
2519
2520static u32 e100_get_link(struct net_device *netdev)
2521{
2522 struct nic *nic = netdev_priv(netdev);
2523 return mii_link_ok(&nic->mii);
2524}
2525
2526static int e100_get_eeprom_len(struct net_device *netdev)
2527{
2528 struct nic *nic = netdev_priv(netdev);
2529 return nic->eeprom_wc << 1;
2530}
2531
2532#define E100_EEPROM_MAGIC 0x1234
2533static int e100_get_eeprom(struct net_device *netdev,
2534 struct ethtool_eeprom *eeprom, u8 *bytes)
2535{
2536 struct nic *nic = netdev_priv(netdev);
2537
2538 eeprom->magic = E100_EEPROM_MAGIC;
2539 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2540
2541 return 0;
2542}
2543
2544static int e100_set_eeprom(struct net_device *netdev,
2545 struct ethtool_eeprom *eeprom, u8 *bytes)
2546{
2547 struct nic *nic = netdev_priv(netdev);
2548
2549 if (eeprom->magic != E100_EEPROM_MAGIC)
2550 return -EINVAL;
2551
2552 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2553
2554 return e100_eeprom_save(nic, eeprom->offset >> 1,
2555 (eeprom->len >> 1) + 1);
2556}
2557
2558static void e100_get_ringparam(struct net_device *netdev,
2559 struct ethtool_ringparam *ring,
2560 struct kernel_ethtool_ringparam *kernel_ring,
2561 struct netlink_ext_ack *extack)
2562{
2563 struct nic *nic = netdev_priv(netdev);
2564 struct param_range *rfds = &nic->params.rfds;
2565 struct param_range *cbs = &nic->params.cbs;
2566
2567 ring->rx_max_pending = rfds->max;
2568 ring->tx_max_pending = cbs->max;
2569 ring->rx_pending = rfds->count;
2570 ring->tx_pending = cbs->count;
2571}
2572
2573static int e100_set_ringparam(struct net_device *netdev,
2574 struct ethtool_ringparam *ring,
2575 struct kernel_ethtool_ringparam *kernel_ring,
2576 struct netlink_ext_ack *extack)
2577{
2578 struct nic *nic = netdev_priv(netdev);
2579 struct param_range *rfds = &nic->params.rfds;
2580 struct param_range *cbs = &nic->params.cbs;
2581
2582 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2583 return -EINVAL;
2584
2585 if (netif_running(netdev))
2586 e100_down(nic);
2587 rfds->count = max(ring->rx_pending, rfds->min);
2588 rfds->count = min(rfds->count, rfds->max);
2589 cbs->count = max(ring->tx_pending, cbs->min);
2590 cbs->count = min(cbs->count, cbs->max);
2591 netif_info(nic, drv, nic->netdev, "Ring Param settings: rx: %d, tx %d\n",
2592 rfds->count, cbs->count);
2593 if (netif_running(netdev))
2594 e100_up(nic);
2595
2596 return 0;
2597}
2598
2599static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2600 "Link test (on/offline)",
2601 "Eeprom test (on/offline)",
2602 "Self test (offline)",
2603 "Mac loopback (offline)",
2604 "Phy loopback (offline)",
2605};
2606#define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2607
2608static void e100_diag_test(struct net_device *netdev,
2609 struct ethtool_test *test, u64 *data)
2610{
2611 struct ethtool_cmd cmd;
2612 struct nic *nic = netdev_priv(netdev);
2613 int i;
2614
2615 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2616 data[0] = !mii_link_ok(&nic->mii);
2617 data[1] = e100_eeprom_load(nic);
2618 if (test->flags & ETH_TEST_FL_OFFLINE) {
2619
2620 /* save speed, duplex & autoneg settings */
2621 mii_ethtool_gset(&nic->mii, &cmd);
2622
2623 if (netif_running(netdev))
2624 e100_down(nic);
2625 data[2] = e100_self_test(nic);
2626 data[3] = e100_loopback_test(nic, lb_mac);
2627 data[4] = e100_loopback_test(nic, lb_phy);
2628
2629 /* restore speed, duplex & autoneg settings */
2630 mii_ethtool_sset(&nic->mii, &cmd);
2631
2632 if (netif_running(netdev))
2633 e100_up(nic);
2634 }
2635 for (i = 0; i < E100_TEST_LEN; i++)
2636 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2637
2638 msleep_interruptible(4 * 1000);
2639}
2640
2641static int e100_set_phys_id(struct net_device *netdev,
2642 enum ethtool_phys_id_state state)
2643{
2644 struct nic *nic = netdev_priv(netdev);
2645 enum led_state {
2646 led_on = 0x01,
2647 led_off = 0x04,
2648 led_on_559 = 0x05,
2649 led_on_557 = 0x07,
2650 };
2651 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2652 MII_LED_CONTROL;
2653 u16 leds = 0;
2654
2655 switch (state) {
2656 case ETHTOOL_ID_ACTIVE:
2657 return 2;
2658
2659 case ETHTOOL_ID_ON:
2660 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_ON :
2661 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2662 break;
2663
2664 case ETHTOOL_ID_OFF:
2665 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_OFF : led_off;
2666 break;
2667
2668 case ETHTOOL_ID_INACTIVE:
2669 break;
2670 }
2671
2672 mdio_write(netdev, nic->mii.phy_id, led_reg, leds);
2673 return 0;
2674}
2675
2676static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2677 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2678 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2679 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2680 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2681 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2682 "tx_heartbeat_errors", "tx_window_errors",
2683 /* device-specific stats */
2684 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2685 "tx_flow_control_pause", "rx_flow_control_pause",
2686 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2687 "rx_short_frame_errors", "rx_over_length_errors",
2688};
2689#define E100_NET_STATS_LEN 21
2690#define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2691
2692static int e100_get_sset_count(struct net_device *netdev, int sset)
2693{
2694 switch (sset) {
2695 case ETH_SS_TEST:
2696 return E100_TEST_LEN;
2697 case ETH_SS_STATS:
2698 return E100_STATS_LEN;
2699 default:
2700 return -EOPNOTSUPP;
2701 }
2702}
2703
2704static void e100_get_ethtool_stats(struct net_device *netdev,
2705 struct ethtool_stats *stats, u64 *data)
2706{
2707 struct nic *nic = netdev_priv(netdev);
2708 int i;
2709
2710 for (i = 0; i < E100_NET_STATS_LEN; i++)
2711 data[i] = ((unsigned long *)&netdev->stats)[i];
2712
2713 data[i++] = nic->tx_deferred;
2714 data[i++] = nic->tx_single_collisions;
2715 data[i++] = nic->tx_multiple_collisions;
2716 data[i++] = nic->tx_fc_pause;
2717 data[i++] = nic->rx_fc_pause;
2718 data[i++] = nic->rx_fc_unsupported;
2719 data[i++] = nic->tx_tco_frames;
2720 data[i++] = nic->rx_tco_frames;
2721 data[i++] = nic->rx_short_frame_errors;
2722 data[i++] = nic->rx_over_length_errors;
2723}
2724
2725static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2726{
2727 switch (stringset) {
2728 case ETH_SS_TEST:
2729 memcpy(data, e100_gstrings_test, sizeof(e100_gstrings_test));
2730 break;
2731 case ETH_SS_STATS:
2732 memcpy(data, e100_gstrings_stats, sizeof(e100_gstrings_stats));
2733 break;
2734 }
2735}
2736
2737static const struct ethtool_ops e100_ethtool_ops = {
2738 .get_drvinfo = e100_get_drvinfo,
2739 .get_regs_len = e100_get_regs_len,
2740 .get_regs = e100_get_regs,
2741 .get_wol = e100_get_wol,
2742 .set_wol = e100_set_wol,
2743 .get_msglevel = e100_get_msglevel,
2744 .set_msglevel = e100_set_msglevel,
2745 .nway_reset = e100_nway_reset,
2746 .get_link = e100_get_link,
2747 .get_eeprom_len = e100_get_eeprom_len,
2748 .get_eeprom = e100_get_eeprom,
2749 .set_eeprom = e100_set_eeprom,
2750 .get_ringparam = e100_get_ringparam,
2751 .set_ringparam = e100_set_ringparam,
2752 .self_test = e100_diag_test,
2753 .get_strings = e100_get_strings,
2754 .set_phys_id = e100_set_phys_id,
2755 .get_ethtool_stats = e100_get_ethtool_stats,
2756 .get_sset_count = e100_get_sset_count,
2757 .get_ts_info = ethtool_op_get_ts_info,
2758 .get_link_ksettings = e100_get_link_ksettings,
2759 .set_link_ksettings = e100_set_link_ksettings,
2760};
2761
2762static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2763{
2764 struct nic *nic = netdev_priv(netdev);
2765
2766 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2767}
2768
2769static int e100_alloc(struct nic *nic)
2770{
2771 nic->mem = dma_alloc_coherent(&nic->pdev->dev, sizeof(struct mem),
2772 &nic->dma_addr, GFP_KERNEL);
2773 return nic->mem ? 0 : -ENOMEM;
2774}
2775
2776static void e100_free(struct nic *nic)
2777{
2778 if (nic->mem) {
2779 dma_free_coherent(&nic->pdev->dev, sizeof(struct mem),
2780 nic->mem, nic->dma_addr);
2781 nic->mem = NULL;
2782 }
2783}
2784
2785static int e100_open(struct net_device *netdev)
2786{
2787 struct nic *nic = netdev_priv(netdev);
2788 int err = 0;
2789
2790 netif_carrier_off(netdev);
2791 if ((err = e100_up(nic)))
2792 netif_err(nic, ifup, nic->netdev, "Cannot open interface, aborting\n");
2793 return err;
2794}
2795
2796static int e100_close(struct net_device *netdev)
2797{
2798 e100_down(netdev_priv(netdev));
2799 return 0;
2800}
2801
2802static int e100_set_features(struct net_device *netdev,
2803 netdev_features_t features)
2804{
2805 struct nic *nic = netdev_priv(netdev);
2806 netdev_features_t changed = features ^ netdev->features;
2807
2808 if (!(changed & (NETIF_F_RXFCS | NETIF_F_RXALL)))
2809 return 0;
2810
2811 netdev->features = features;
2812 e100_exec_cb(nic, NULL, e100_configure);
2813 return 1;
2814}
2815
2816static const struct net_device_ops e100_netdev_ops = {
2817 .ndo_open = e100_open,
2818 .ndo_stop = e100_close,
2819 .ndo_start_xmit = e100_xmit_frame,
2820 .ndo_validate_addr = eth_validate_addr,
2821 .ndo_set_rx_mode = e100_set_multicast_list,
2822 .ndo_set_mac_address = e100_set_mac_address,
2823 .ndo_eth_ioctl = e100_do_ioctl,
2824 .ndo_tx_timeout = e100_tx_timeout,
2825#ifdef CONFIG_NET_POLL_CONTROLLER
2826 .ndo_poll_controller = e100_netpoll,
2827#endif
2828 .ndo_set_features = e100_set_features,
2829};
2830
2831static int e100_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2832{
2833 struct net_device *netdev;
2834 struct nic *nic;
2835 int err;
2836
2837 if (!(netdev = alloc_etherdev(sizeof(struct nic))))
2838 return -ENOMEM;
2839
2840 netdev->hw_features |= NETIF_F_RXFCS;
2841 netdev->priv_flags |= IFF_SUPP_NOFCS;
2842 netdev->hw_features |= NETIF_F_RXALL;
2843
2844 netdev->netdev_ops = &e100_netdev_ops;
2845 netdev->ethtool_ops = &e100_ethtool_ops;
2846 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2847 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2848
2849 nic = netdev_priv(netdev);
2850 netif_napi_add_weight(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2851 nic->netdev = netdev;
2852 nic->pdev = pdev;
2853 nic->msg_enable = (1 << debug) - 1;
2854 nic->mdio_ctrl = mdio_ctrl_hw;
2855 pci_set_drvdata(pdev, netdev);
2856
2857 if ((err = pci_enable_device(pdev))) {
2858 netif_err(nic, probe, nic->netdev, "Cannot enable PCI device, aborting\n");
2859 goto err_out_free_dev;
2860 }
2861
2862 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2863 netif_err(nic, probe, nic->netdev, "Cannot find proper PCI device base address, aborting\n");
2864 err = -ENODEV;
2865 goto err_out_disable_pdev;
2866 }
2867
2868 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2869 netif_err(nic, probe, nic->netdev, "Cannot obtain PCI resources, aborting\n");
2870 goto err_out_disable_pdev;
2871 }
2872
2873 if ((err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) {
2874 netif_err(nic, probe, nic->netdev, "No usable DMA configuration, aborting\n");
2875 goto err_out_free_res;
2876 }
2877
2878 SET_NETDEV_DEV(netdev, &pdev->dev);
2879
2880 if (use_io)
2881 netif_info(nic, probe, nic->netdev, "using i/o access mode\n");
2882
2883 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2884 if (!nic->csr) {
2885 netif_err(nic, probe, nic->netdev, "Cannot map device registers, aborting\n");
2886 err = -ENOMEM;
2887 goto err_out_free_res;
2888 }
2889
2890 if (ent->driver_data)
2891 nic->flags |= ich;
2892 else
2893 nic->flags &= ~ich;
2894
2895 e100_get_defaults(nic);
2896
2897 /* D100 MAC doesn't allow rx of vlan packets with normal MTU */
2898 if (nic->mac < mac_82558_D101_A4)
2899 netdev->features |= NETIF_F_VLAN_CHALLENGED;
2900
2901 /* locks must be initialized before calling hw_reset */
2902 spin_lock_init(&nic->cb_lock);
2903 spin_lock_init(&nic->cmd_lock);
2904 spin_lock_init(&nic->mdio_lock);
2905
2906 /* Reset the device before pci_set_master() in case device is in some
2907 * funky state and has an interrupt pending - hint: we don't have the
2908 * interrupt handler registered yet. */
2909 e100_hw_reset(nic);
2910
2911 pci_set_master(pdev);
2912
2913 timer_setup(&nic->watchdog, e100_watchdog, 0);
2914
2915 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2916
2917 if ((err = e100_alloc(nic))) {
2918 netif_err(nic, probe, nic->netdev, "Cannot alloc driver memory, aborting\n");
2919 goto err_out_iounmap;
2920 }
2921
2922 if ((err = e100_eeprom_load(nic)))
2923 goto err_out_free;
2924
2925 e100_phy_init(nic);
2926
2927 eth_hw_addr_set(netdev, (u8 *)nic->eeprom);
2928 if (!is_valid_ether_addr(netdev->dev_addr)) {
2929 if (!eeprom_bad_csum_allow) {
2930 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, aborting\n");
2931 err = -EAGAIN;
2932 goto err_out_free;
2933 } else {
2934 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, you MUST configure one.\n");
2935 }
2936 }
2937
2938 /* Wol magic packet can be enabled from eeprom */
2939 if ((nic->mac >= mac_82558_D101_A4) &&
2940 (le16_to_cpu(nic->eeprom[eeprom_id]) & eeprom_id_wol)) {
2941 nic->flags |= wol_magic;
2942 device_set_wakeup_enable(&pdev->dev, true);
2943 }
2944
2945 /* ack any pending wake events, disable PME */
2946 pci_pme_active(pdev, false);
2947
2948 strcpy(netdev->name, "eth%d");
2949 if ((err = register_netdev(netdev))) {
2950 netif_err(nic, probe, nic->netdev, "Cannot register net device, aborting\n");
2951 goto err_out_free;
2952 }
2953 nic->cbs_pool = dma_pool_create(netdev->name,
2954 &nic->pdev->dev,
2955 nic->params.cbs.max * sizeof(struct cb),
2956 sizeof(u32),
2957 0);
2958 if (!nic->cbs_pool) {
2959 netif_err(nic, probe, nic->netdev, "Cannot create DMA pool, aborting\n");
2960 err = -ENOMEM;
2961 goto err_out_pool;
2962 }
2963 netif_info(nic, probe, nic->netdev,
2964 "addr 0x%llx, irq %d, MAC addr %pM\n",
2965 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2966 pdev->irq, netdev->dev_addr);
2967
2968 return 0;
2969
2970err_out_pool:
2971 unregister_netdev(netdev);
2972err_out_free:
2973 e100_free(nic);
2974err_out_iounmap:
2975 pci_iounmap(pdev, nic->csr);
2976err_out_free_res:
2977 pci_release_regions(pdev);
2978err_out_disable_pdev:
2979 pci_disable_device(pdev);
2980err_out_free_dev:
2981 free_netdev(netdev);
2982 return err;
2983}
2984
2985static void e100_remove(struct pci_dev *pdev)
2986{
2987 struct net_device *netdev = pci_get_drvdata(pdev);
2988
2989 if (netdev) {
2990 struct nic *nic = netdev_priv(netdev);
2991 unregister_netdev(netdev);
2992 e100_free(nic);
2993 pci_iounmap(pdev, nic->csr);
2994 dma_pool_destroy(nic->cbs_pool);
2995 free_netdev(netdev);
2996 pci_release_regions(pdev);
2997 pci_disable_device(pdev);
2998 }
2999}
3000
3001#define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
3002#define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
3003#define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
3004static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
3005{
3006 struct net_device *netdev = pci_get_drvdata(pdev);
3007 struct nic *nic = netdev_priv(netdev);
3008
3009 netif_device_detach(netdev);
3010
3011 if (netif_running(netdev))
3012 e100_down(nic);
3013
3014 if ((nic->flags & wol_magic) | e100_asf(nic)) {
3015 /* enable reverse auto-negotiation */
3016 if (nic->phy == phy_82552_v) {
3017 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
3018 E100_82552_SMARTSPEED);
3019
3020 mdio_write(netdev, nic->mii.phy_id,
3021 E100_82552_SMARTSPEED, smartspeed |
3022 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
3023 }
3024 *enable_wake = true;
3025 } else {
3026 *enable_wake = false;
3027 }
3028
3029 pci_disable_device(pdev);
3030}
3031
3032static int __e100_power_off(struct pci_dev *pdev, bool wake)
3033{
3034 if (wake)
3035 return pci_prepare_to_sleep(pdev);
3036
3037 pci_wake_from_d3(pdev, false);
3038 pci_set_power_state(pdev, PCI_D3hot);
3039
3040 return 0;
3041}
3042
3043static int __maybe_unused e100_suspend(struct device *dev_d)
3044{
3045 bool wake;
3046
3047 __e100_shutdown(to_pci_dev(dev_d), &wake);
3048
3049 return 0;
3050}
3051
3052static int __maybe_unused e100_resume(struct device *dev_d)
3053{
3054 struct net_device *netdev = dev_get_drvdata(dev_d);
3055 struct nic *nic = netdev_priv(netdev);
3056 int err;
3057
3058 err = pci_enable_device(to_pci_dev(dev_d));
3059 if (err) {
3060 netdev_err(netdev, "Resume cannot enable PCI device, aborting\n");
3061 return err;
3062 }
3063 pci_set_master(to_pci_dev(dev_d));
3064
3065 /* disable reverse auto-negotiation */
3066 if (nic->phy == phy_82552_v) {
3067 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
3068 E100_82552_SMARTSPEED);
3069
3070 mdio_write(netdev, nic->mii.phy_id,
3071 E100_82552_SMARTSPEED,
3072 smartspeed & ~(E100_82552_REV_ANEG));
3073 }
3074
3075 if (netif_running(netdev))
3076 e100_up(nic);
3077
3078 netif_device_attach(netdev);
3079
3080 return 0;
3081}
3082
3083static void e100_shutdown(struct pci_dev *pdev)
3084{
3085 bool wake;
3086 __e100_shutdown(pdev, &wake);
3087 if (system_state == SYSTEM_POWER_OFF)
3088 __e100_power_off(pdev, wake);
3089}
3090
3091/* ------------------ PCI Error Recovery infrastructure -------------- */
3092/**
3093 * e100_io_error_detected - called when PCI error is detected.
3094 * @pdev: Pointer to PCI device
3095 * @state: The current pci connection state
3096 */
3097static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
3098{
3099 struct net_device *netdev = pci_get_drvdata(pdev);
3100 struct nic *nic = netdev_priv(netdev);
3101
3102 netif_device_detach(netdev);
3103
3104 if (state == pci_channel_io_perm_failure)
3105 return PCI_ERS_RESULT_DISCONNECT;
3106
3107 if (netif_running(netdev))
3108 e100_down(nic);
3109 pci_disable_device(pdev);
3110
3111 /* Request a slot reset. */
3112 return PCI_ERS_RESULT_NEED_RESET;
3113}
3114
3115/**
3116 * e100_io_slot_reset - called after the pci bus has been reset.
3117 * @pdev: Pointer to PCI device
3118 *
3119 * Restart the card from scratch.
3120 */
3121static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
3122{
3123 struct net_device *netdev = pci_get_drvdata(pdev);
3124 struct nic *nic = netdev_priv(netdev);
3125
3126 if (pci_enable_device(pdev)) {
3127 pr_err("Cannot re-enable PCI device after reset\n");
3128 return PCI_ERS_RESULT_DISCONNECT;
3129 }
3130 pci_set_master(pdev);
3131
3132 /* Only one device per card can do a reset */
3133 if (0 != PCI_FUNC(pdev->devfn))
3134 return PCI_ERS_RESULT_RECOVERED;
3135 e100_hw_reset(nic);
3136 e100_phy_init(nic);
3137
3138 return PCI_ERS_RESULT_RECOVERED;
3139}
3140
3141/**
3142 * e100_io_resume - resume normal operations
3143 * @pdev: Pointer to PCI device
3144 *
3145 * Resume normal operations after an error recovery
3146 * sequence has been completed.
3147 */
3148static void e100_io_resume(struct pci_dev *pdev)
3149{
3150 struct net_device *netdev = pci_get_drvdata(pdev);
3151 struct nic *nic = netdev_priv(netdev);
3152
3153 /* ack any pending wake events, disable PME */
3154 pci_enable_wake(pdev, PCI_D0, 0);
3155
3156 netif_device_attach(netdev);
3157 if (netif_running(netdev)) {
3158 e100_open(netdev);
3159 mod_timer(&nic->watchdog, jiffies);
3160 }
3161}
3162
3163static const struct pci_error_handlers e100_err_handler = {
3164 .error_detected = e100_io_error_detected,
3165 .slot_reset = e100_io_slot_reset,
3166 .resume = e100_io_resume,
3167};
3168
3169static SIMPLE_DEV_PM_OPS(e100_pm_ops, e100_suspend, e100_resume);
3170
3171static struct pci_driver e100_driver = {
3172 .name = DRV_NAME,
3173 .id_table = e100_id_table,
3174 .probe = e100_probe,
3175 .remove = e100_remove,
3176
3177 /* Power Management hooks */
3178 .driver.pm = &e100_pm_ops,
3179
3180 .shutdown = e100_shutdown,
3181 .err_handler = &e100_err_handler,
3182};
3183
3184static int __init e100_init_module(void)
3185{
3186 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3187 pr_info("%s\n", DRV_DESCRIPTION);
3188 pr_info("%s\n", DRV_COPYRIGHT);
3189 }
3190 return pci_register_driver(&e100_driver);
3191}
3192
3193static void __exit e100_cleanup_module(void)
3194{
3195 pci_unregister_driver(&e100_driver);
3196}
3197
3198module_init(e100_init_module);
3199module_exit(e100_cleanup_module);
3200

source code of linux/drivers/net/ethernet/intel/e100.c