| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Copyright(c) 1999 - 2018 Intel Corporation. */ |
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| 3 | |
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| 4 | #ifndef _E1000E_MANAGE_H_ |
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| 5 | #define _E1000E_MANAGE_H_ |
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| 6 | |
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| 7 | bool e1000e_check_mng_mode_generic(struct e1000_hw *hw); |
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| 8 | bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); |
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| 9 | s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); |
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| 10 | bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); |
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| 11 | |
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| 12 | enum e1000_mng_mode { |
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| 13 | e1000_mng_mode_none = 0, |
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| 14 | e1000_mng_mode_asf, |
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| 15 | e1000_mng_mode_pt, |
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| 16 | e1000_mng_mode_ipmi, |
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| 17 | e1000_mng_mode_host_if_only |
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| 18 | }; |
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| 19 | |
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| 20 | #define E1000_FACTPS_MNGCG 0x20000000 |
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| 21 | |
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| 22 | #define E1000_FWSM_MODE_MASK 0xE |
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| 23 | #define E1000_FWSM_MODE_SHIFT 1 |
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| 24 | |
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| 25 | #define E1000_MNG_IAMT_MODE 0x3 |
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| 26 | #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 |
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| 27 | #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 |
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| 28 | #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 |
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| 29 | #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 |
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| 30 | #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 |
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| 31 | #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 |
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| 32 | |
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| 33 | #define E1000_VFTA_ENTRY_SHIFT 5 |
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| 34 | #define E1000_VFTA_ENTRY_MASK 0x7F |
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| 35 | #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F |
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| 36 | |
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| 37 | #define E1000_HICR_EN 0x01 /* Enable bit - RO */ |
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| 38 | /* Driver sets this bit when done to put command in RAM */ |
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| 39 | #define E1000_HICR_C 0x02 |
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| 40 | #define E1000_HICR_SV 0x04 /* Status Validity */ |
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| 41 | #define E1000_HICR_FW_RESET_ENABLE 0x40 |
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| 42 | #define E1000_HICR_FW_RESET 0x80 |
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| 43 | |
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| 44 | /* Intel(R) Active Management Technology signature */ |
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| 45 | #define E1000_IAMT_SIGNATURE 0x544D4149 |
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| 46 | |
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| 47 | #endif |
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| 48 | |
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