1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/delay.h>
13#include <linux/netdevice.h>
14#include <linux/interrupt.h>
15#include <linux/tcp.h>
16#include <linux/ipv6.h>
17#include <linux/slab.h>
18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/cpu.h>
23#include <linux/smp.h>
24#include <linux/pm_qos.h>
25#include <linux/pm_runtime.h>
26#include <linux/prefetch.h>
27#include <linux/suspend.h>
28
29#include "e1000.h"
30#define CREATE_TRACE_POINTS
31#include "e1000e_trace.h"
32
33char e1000e_driver_name[] = "e1000e";
34
35#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
36static int debug = -1;
37module_param(debug, int, 0);
38MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
39
40static const struct e1000_info *e1000_info_tbl[] = {
41 [board_82571] = &e1000_82571_info,
42 [board_82572] = &e1000_82572_info,
43 [board_82573] = &e1000_82573_info,
44 [board_82574] = &e1000_82574_info,
45 [board_82583] = &e1000_82583_info,
46 [board_80003es2lan] = &e1000_es2_info,
47 [board_ich8lan] = &e1000_ich8_info,
48 [board_ich9lan] = &e1000_ich9_info,
49 [board_ich10lan] = &e1000_ich10_info,
50 [board_pchlan] = &e1000_pch_info,
51 [board_pch2lan] = &e1000_pch2_info,
52 [board_pch_lpt] = &e1000_pch_lpt_info,
53 [board_pch_spt] = &e1000_pch_spt_info,
54 [board_pch_cnp] = &e1000_pch_cnp_info,
55 [board_pch_tgp] = &e1000_pch_tgp_info,
56 [board_pch_adp] = &e1000_pch_adp_info,
57 [board_pch_mtp] = &e1000_pch_mtp_info,
58};
59
60struct e1000_reg_info {
61 u32 ofs;
62 char *name;
63};
64
65static const struct e1000_reg_info e1000_reg_info_tbl[] = {
66 /* General Registers */
67 {E1000_CTRL, "CTRL"},
68 {E1000_STATUS, "STATUS"},
69 {E1000_CTRL_EXT, "CTRL_EXT"},
70
71 /* Interrupt Registers */
72 {E1000_ICR, "ICR"},
73
74 /* Rx Registers */
75 {E1000_RCTL, "RCTL"},
76 {E1000_RDLEN(0), "RDLEN"},
77 {E1000_RDH(0), "RDH"},
78 {E1000_RDT(0), "RDT"},
79 {E1000_RDTR, "RDTR"},
80 {E1000_RXDCTL(0), "RXDCTL"},
81 {E1000_ERT, "ERT"},
82 {E1000_RDBAL(0), "RDBAL"},
83 {E1000_RDBAH(0), "RDBAH"},
84 {E1000_RDFH, "RDFH"},
85 {E1000_RDFT, "RDFT"},
86 {E1000_RDFHS, "RDFHS"},
87 {E1000_RDFTS, "RDFTS"},
88 {E1000_RDFPC, "RDFPC"},
89
90 /* Tx Registers */
91 {E1000_TCTL, "TCTL"},
92 {E1000_TDBAL(0), "TDBAL"},
93 {E1000_TDBAH(0), "TDBAH"},
94 {E1000_TDLEN(0), "TDLEN"},
95 {E1000_TDH(0), "TDH"},
96 {E1000_TDT(0), "TDT"},
97 {E1000_TIDV, "TIDV"},
98 {E1000_TXDCTL(0), "TXDCTL"},
99 {E1000_TADV, "TADV"},
100 {E1000_TARC(0), "TARC"},
101 {E1000_TDFH, "TDFH"},
102 {E1000_TDFT, "TDFT"},
103 {E1000_TDFHS, "TDFHS"},
104 {E1000_TDFTS, "TDFTS"},
105 {E1000_TDFPC, "TDFPC"},
106
107 /* List Terminator */
108 {0, NULL}
109};
110
111/**
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
113 * @hw: pointer to the HW structure
114 *
115 * When updating the MAC CSR registers, the Manageability Engine (ME) could
116 * be accessing the registers at the same time. Normally, this is handled in
117 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
118 * accesses later than it should which could result in the register to have
119 * an incorrect value. Workaround this by checking the FWSM register which
120 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
121 * and try again a number of times.
122 **/
123static void __ew32_prepare(struct e1000_hw *hw)
124{
125 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
126
127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
128 udelay(50);
129}
130
131void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
132{
133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
134 __ew32_prepare(hw);
135
136 writel(val, addr: hw->hw_addr + reg);
137}
138
139/**
140 * e1000_regdump - register printout routine
141 * @hw: pointer to the HW structure
142 * @reginfo: pointer to the register info table
143 **/
144static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
145{
146 int n = 0;
147 char rname[16];
148 u32 regs[8];
149
150 switch (reginfo->ofs) {
151 case E1000_RXDCTL(0):
152 for (n = 0; n < 2; n++)
153 regs[n] = __er32(hw, E1000_RXDCTL(n));
154 break;
155 case E1000_TXDCTL(0):
156 for (n = 0; n < 2; n++)
157 regs[n] = __er32(hw, E1000_TXDCTL(n));
158 break;
159 case E1000_TARC(0):
160 for (n = 0; n < 2; n++)
161 regs[n] = __er32(hw, E1000_TARC(n));
162 break;
163 default:
164 pr_info("%-15s %08x\n",
165 reginfo->name, __er32(hw, reginfo->ofs));
166 return;
167 }
168
169 snprintf(buf: rname, size: 16, fmt: "%s%s", reginfo->name, "[0-1]");
170 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
171}
172
173static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
174 struct e1000_buffer *bi)
175{
176 int i;
177 struct e1000_ps_page *ps_page;
178
179 for (i = 0; i < adapter->rx_ps_pages; i++) {
180 ps_page = &bi->ps_pages[i];
181
182 if (ps_page->page) {
183 pr_info("packet dump for ps_page %d:\n", i);
184 print_hex_dump(KERN_INFO, prefix_str: "", prefix_type: DUMP_PREFIX_ADDRESS,
185 rowsize: 16, groupsize: 1, page_address(ps_page->page),
186 PAGE_SIZE, ascii: true);
187 }
188 }
189}
190
191/**
192 * e1000e_dump - Print registers, Tx-ring and Rx-ring
193 * @adapter: board private structure
194 **/
195static void e1000e_dump(struct e1000_adapter *adapter)
196{
197 struct net_device *netdev = adapter->netdev;
198 struct e1000_hw *hw = &adapter->hw;
199 struct e1000_reg_info *reginfo;
200 struct e1000_ring *tx_ring = adapter->tx_ring;
201 struct e1000_tx_desc *tx_desc;
202 struct my_u0 {
203 __le64 a;
204 __le64 b;
205 } *u0;
206 struct e1000_buffer *buffer_info;
207 struct e1000_ring *rx_ring = adapter->rx_ring;
208 union e1000_rx_desc_packet_split *rx_desc_ps;
209 union e1000_rx_desc_extended *rx_desc;
210 struct my_u1 {
211 __le64 a;
212 __le64 b;
213 __le64 c;
214 __le64 d;
215 } *u1;
216 u32 staterr;
217 int i = 0;
218
219 if (!netif_msg_hw(adapter))
220 return;
221
222 /* Print netdevice Info */
223 if (netdev) {
224 dev_info(&adapter->pdev->dev, "Net device Info\n");
225 pr_info("Device Name state trans_start\n");
226 pr_info("%-15s %016lX %016lX\n", netdev->name,
227 netdev->state, dev_trans_start(netdev));
228 }
229
230 /* Print Registers */
231 dev_info(&adapter->pdev->dev, "Register Dump\n");
232 pr_info(" Register Name Value\n");
233 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
234 reginfo->name; reginfo++) {
235 e1000_regdump(hw, reginfo);
236 }
237
238 /* Print Tx Ring Summary */
239 if (!netdev || !netif_running(dev: netdev))
240 return;
241
242 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
243 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
244 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
245 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
246 0, tx_ring->next_to_use, tx_ring->next_to_clean,
247 (unsigned long long)buffer_info->dma,
248 buffer_info->length,
249 buffer_info->next_to_watch,
250 (unsigned long long)buffer_info->time_stamp);
251
252 /* Print Tx Ring */
253 if (!netif_msg_tx_done(adapter))
254 goto rx_ring_summary;
255
256 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
257
258 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
259 *
260 * Legacy Transmit Descriptor
261 * +--------------------------------------------------------------+
262 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
263 * +--------------------------------------------------------------+
264 * 8 | Special | CSS | Status | CMD | CSO | Length |
265 * +--------------------------------------------------------------+
266 * 63 48 47 36 35 32 31 24 23 16 15 0
267 *
268 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
269 * 63 48 47 40 39 32 31 16 15 8 7 0
270 * +----------------------------------------------------------------+
271 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
272 * +----------------------------------------------------------------+
273 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
274 * +----------------------------------------------------------------+
275 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
276 *
277 * Extended Data Descriptor (DTYP=0x1)
278 * +----------------------------------------------------------------+
279 * 0 | Buffer Address [63:0] |
280 * +----------------------------------------------------------------+
281 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
282 * +----------------------------------------------------------------+
283 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
284 */
285 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
286 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
287 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
288 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
289 const char *next_desc;
290 tx_desc = E1000_TX_DESC(*tx_ring, i);
291 buffer_info = &tx_ring->buffer_info[i];
292 u0 = (struct my_u0 *)tx_desc;
293 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
294 next_desc = " NTC/U";
295 else if (i == tx_ring->next_to_use)
296 next_desc = " NTU";
297 else if (i == tx_ring->next_to_clean)
298 next_desc = " NTC";
299 else
300 next_desc = "";
301 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
302 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
303 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
304 i,
305 (unsigned long long)le64_to_cpu(u0->a),
306 (unsigned long long)le64_to_cpu(u0->b),
307 (unsigned long long)buffer_info->dma,
308 buffer_info->length, buffer_info->next_to_watch,
309 (unsigned long long)buffer_info->time_stamp,
310 buffer_info->skb, next_desc);
311
312 if (netif_msg_pktdata(adapter) && buffer_info->skb)
313 print_hex_dump(KERN_INFO, prefix_str: "", prefix_type: DUMP_PREFIX_ADDRESS,
314 rowsize: 16, groupsize: 1, buf: buffer_info->skb->data,
315 len: buffer_info->skb->len, ascii: true);
316 }
317
318 /* Print Rx Ring Summary */
319rx_ring_summary:
320 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
321 pr_info("Queue [NTU] [NTC]\n");
322 pr_info(" %5d %5X %5X\n",
323 0, rx_ring->next_to_use, rx_ring->next_to_clean);
324
325 /* Print Rx Ring */
326 if (!netif_msg_rx_status(adapter))
327 return;
328
329 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
330 switch (adapter->rx_ps_pages) {
331 case 1:
332 case 2:
333 case 3:
334 /* [Extended] Packet Split Receive Descriptor Format
335 *
336 * +-----------------------------------------------------+
337 * 0 | Buffer Address 0 [63:0] |
338 * +-----------------------------------------------------+
339 * 8 | Buffer Address 1 [63:0] |
340 * +-----------------------------------------------------+
341 * 16 | Buffer Address 2 [63:0] |
342 * +-----------------------------------------------------+
343 * 24 | Buffer Address 3 [63:0] |
344 * +-----------------------------------------------------+
345 */
346 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
347 /* [Extended] Receive Descriptor (Write-Back) Format
348 *
349 * 63 48 47 32 31 13 12 8 7 4 3 0
350 * +------------------------------------------------------+
351 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
352 * | Checksum | Ident | | Queue | | Type |
353 * +------------------------------------------------------+
354 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
355 * +------------------------------------------------------+
356 * 63 48 47 32 31 20 19 0
357 */
358 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
359 for (i = 0; i < rx_ring->count; i++) {
360 const char *next_desc;
361 buffer_info = &rx_ring->buffer_info[i];
362 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
363 u1 = (struct my_u1 *)rx_desc_ps;
364 staterr =
365 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
366
367 if (i == rx_ring->next_to_use)
368 next_desc = " NTU";
369 else if (i == rx_ring->next_to_clean)
370 next_desc = " NTC";
371 else
372 next_desc = "";
373
374 if (staterr & E1000_RXD_STAT_DD) {
375 /* Descriptor Done */
376 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
377 "RWB", i,
378 (unsigned long long)le64_to_cpu(u1->a),
379 (unsigned long long)le64_to_cpu(u1->b),
380 (unsigned long long)le64_to_cpu(u1->c),
381 (unsigned long long)le64_to_cpu(u1->d),
382 buffer_info->skb, next_desc);
383 } else {
384 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
385 "R ", i,
386 (unsigned long long)le64_to_cpu(u1->a),
387 (unsigned long long)le64_to_cpu(u1->b),
388 (unsigned long long)le64_to_cpu(u1->c),
389 (unsigned long long)le64_to_cpu(u1->d),
390 (unsigned long long)buffer_info->dma,
391 buffer_info->skb, next_desc);
392
393 if (netif_msg_pktdata(adapter))
394 e1000e_dump_ps_pages(adapter,
395 bi: buffer_info);
396 }
397 }
398 break;
399 default:
400 case 0:
401 /* Extended Receive Descriptor (Read) Format
402 *
403 * +-----------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +-----------------------------------------------------+
406 * 8 | Reserved |
407 * +-----------------------------------------------------+
408 */
409 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
410 /* Extended Receive Descriptor (Write-Back) Format
411 *
412 * 63 48 47 32 31 24 23 4 3 0
413 * +------------------------------------------------------+
414 * | RSS Hash | | | |
415 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
416 * | Packet | IP | | | Type |
417 * | Checksum | Ident | | | |
418 * +------------------------------------------------------+
419 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
420 * +------------------------------------------------------+
421 * 63 48 47 32 31 20 19 0
422 */
423 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
424
425 for (i = 0; i < rx_ring->count; i++) {
426 const char *next_desc;
427
428 buffer_info = &rx_ring->buffer_info[i];
429 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
430 u1 = (struct my_u1 *)rx_desc;
431 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
432
433 if (i == rx_ring->next_to_use)
434 next_desc = " NTU";
435 else if (i == rx_ring->next_to_clean)
436 next_desc = " NTC";
437 else
438 next_desc = "";
439
440 if (staterr & E1000_RXD_STAT_DD) {
441 /* Descriptor Done */
442 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
443 "RWB", i,
444 (unsigned long long)le64_to_cpu(u1->a),
445 (unsigned long long)le64_to_cpu(u1->b),
446 buffer_info->skb, next_desc);
447 } else {
448 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
449 "R ", i,
450 (unsigned long long)le64_to_cpu(u1->a),
451 (unsigned long long)le64_to_cpu(u1->b),
452 (unsigned long long)buffer_info->dma,
453 buffer_info->skb, next_desc);
454
455 if (netif_msg_pktdata(adapter) &&
456 buffer_info->skb)
457 print_hex_dump(KERN_INFO, prefix_str: "",
458 prefix_type: DUMP_PREFIX_ADDRESS, rowsize: 16,
459 groupsize: 1,
460 buf: buffer_info->skb->data,
461 len: adapter->rx_buffer_len,
462 ascii: true);
463 }
464 }
465 }
466}
467
468/**
469 * e1000_desc_unused - calculate if we have unused descriptors
470 * @ring: pointer to ring struct to perform calculation on
471 **/
472static int e1000_desc_unused(struct e1000_ring *ring)
473{
474 if (ring->next_to_clean > ring->next_to_use)
475 return ring->next_to_clean - ring->next_to_use - 1;
476
477 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
478}
479
480/**
481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
482 * @adapter: board private structure
483 * @hwtstamps: time stamp structure to update
484 * @systim: unsigned 64bit system time value.
485 *
486 * Convert the system time value stored in the RX/TXSTMP registers into a
487 * hwtstamp which can be used by the upper level time stamping functions.
488 *
489 * The 'systim_lock' spinlock is used to protect the consistency of the
490 * system time value. This is needed because reading the 64 bit time
491 * value involves reading two 32 bit registers. The first read latches the
492 * value.
493 **/
494static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
495 struct skb_shared_hwtstamps *hwtstamps,
496 u64 systim)
497{
498 u64 ns;
499 unsigned long flags;
500
501 spin_lock_irqsave(&adapter->systim_lock, flags);
502 ns = timecounter_cyc2time(tc: &adapter->tc, cycle_tstamp: systim);
503 spin_unlock_irqrestore(lock: &adapter->systim_lock, flags);
504
505 memset(hwtstamps, 0, sizeof(*hwtstamps));
506 hwtstamps->hwtstamp = ns_to_ktime(ns);
507}
508
509/**
510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
511 * @adapter: board private structure
512 * @status: descriptor extended error and status field
513 * @skb: particular skb to include time stamp
514 *
515 * If the time stamp is valid, convert it into the timecounter ns value
516 * and store that result into the shhwtstamps structure which is passed
517 * up the network stack.
518 **/
519static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
520 struct sk_buff *skb)
521{
522 struct e1000_hw *hw = &adapter->hw;
523 u64 rxstmp;
524
525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
526 !(status & E1000_RXDEXT_STATERR_TST) ||
527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
528 return;
529
530 /* The Rx time stamp registers contain the time stamp. No other
531 * received packet will be time stamped until the Rx time stamp
532 * registers are read. Because only one packet can be time stamped
533 * at a time, the register values must belong to this packet and
534 * therefore none of the other additional attributes need to be
535 * compared.
536 */
537 rxstmp = (u64)er32(RXSTMPL);
538 rxstmp |= (u64)er32(RXSTMPH) << 32;
539 e1000e_systim_to_hwtstamp(adapter, hwtstamps: skb_hwtstamps(skb), systim: rxstmp);
540
541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
542}
543
544/**
545 * e1000_receive_skb - helper function to handle Rx indications
546 * @adapter: board private structure
547 * @netdev: pointer to netdev struct
548 * @staterr: descriptor extended error and status field as written by hardware
549 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
550 * @skb: pointer to sk_buff to be indicated to stack
551 **/
552static void e1000_receive_skb(struct e1000_adapter *adapter,
553 struct net_device *netdev, struct sk_buff *skb,
554 u32 staterr, __le16 vlan)
555{
556 u16 tag = le16_to_cpu(vlan);
557
558 e1000e_rx_hwtstamp(adapter, status: staterr, skb);
559
560 skb->protocol = eth_type_trans(skb, dev: netdev);
561
562 if (staterr & E1000_RXD_STAT_VP)
563 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci: tag);
564
565 napi_gro_receive(napi: &adapter->napi, skb);
566}
567
568/**
569 * e1000_rx_checksum - Receive Checksum Offload
570 * @adapter: board private structure
571 * @status_err: receive descriptor status and error fields
572 * @skb: socket buffer with received data
573 **/
574static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
575 struct sk_buff *skb)
576{
577 u16 status = (u16)status_err;
578 u8 errors = (u8)(status_err >> 24);
579
580 skb_checksum_none_assert(skb);
581
582 /* Rx checksum disabled */
583 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
584 return;
585
586 /* Ignore Checksum bit is set */
587 if (status & E1000_RXD_STAT_IXSM)
588 return;
589
590 /* TCP/UDP checksum error bit or IP checksum error bit is set */
591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
592 /* let the stack verify checksum errors */
593 adapter->hw_csum_err++;
594 return;
595 }
596
597 /* TCP/UDP Checksum has not been calculated */
598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
599 return;
600
601 /* It must be a TCP or UDP packet with a valid checksum */
602 skb->ip_summed = CHECKSUM_UNNECESSARY;
603 adapter->hw_csum_good++;
604}
605
606static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
607{
608 struct e1000_adapter *adapter = rx_ring->adapter;
609 struct e1000_hw *hw = &adapter->hw;
610
611 __ew32_prepare(hw);
612 writel(val: i, addr: rx_ring->tail);
613
614 if (unlikely(i != readl(rx_ring->tail))) {
615 u32 rctl = er32(RCTL);
616
617 ew32(RCTL, rctl & ~E1000_RCTL_EN);
618 e_err("ME firmware caused invalid RDT - resetting\n");
619 schedule_work(work: &adapter->reset_task);
620 }
621}
622
623static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
624{
625 struct e1000_adapter *adapter = tx_ring->adapter;
626 struct e1000_hw *hw = &adapter->hw;
627
628 __ew32_prepare(hw);
629 writel(val: i, addr: tx_ring->tail);
630
631 if (unlikely(i != readl(tx_ring->tail))) {
632 u32 tctl = er32(TCTL);
633
634 ew32(TCTL, tctl & ~E1000_TCTL_EN);
635 e_err("ME firmware caused invalid TDT - resetting\n");
636 schedule_work(work: &adapter->reset_task);
637 }
638}
639
640/**
641 * e1000_alloc_rx_buffers - Replace used receive buffers
642 * @rx_ring: Rx descriptor ring
643 * @cleaned_count: number to reallocate
644 * @gfp: flags for allocation
645 **/
646static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
647 int cleaned_count, gfp_t gfp)
648{
649 struct e1000_adapter *adapter = rx_ring->adapter;
650 struct net_device *netdev = adapter->netdev;
651 struct pci_dev *pdev = adapter->pdev;
652 union e1000_rx_desc_extended *rx_desc;
653 struct e1000_buffer *buffer_info;
654 struct sk_buff *skb;
655 unsigned int i;
656 unsigned int bufsz = adapter->rx_buffer_len;
657
658 i = rx_ring->next_to_use;
659 buffer_info = &rx_ring->buffer_info[i];
660
661 while (cleaned_count--) {
662 skb = buffer_info->skb;
663 if (skb) {
664 skb_trim(skb, len: 0);
665 goto map_skb;
666 }
667
668 skb = __netdev_alloc_skb_ip_align(dev: netdev, length: bufsz, gfp);
669 if (!skb) {
670 /* Better luck next round */
671 adapter->alloc_rx_buff_failed++;
672 break;
673 }
674
675 buffer_info->skb = skb;
676map_skb:
677 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
678 adapter->rx_buffer_len,
679 DMA_FROM_DEVICE);
680 if (dma_mapping_error(dev: &pdev->dev, dma_addr: buffer_info->dma)) {
681 dev_err(&pdev->dev, "Rx DMA map failed\n");
682 adapter->rx_dma_failed++;
683 break;
684 }
685
686 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
687 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
688
689 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
690 /* Force memory writes to complete before letting h/w
691 * know there are new descriptors to fetch. (Only
692 * applicable for weak-ordered memory model archs,
693 * such as IA-64).
694 */
695 wmb();
696 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
697 e1000e_update_rdt_wa(rx_ring, i);
698 else
699 writel(val: i, addr: rx_ring->tail);
700 }
701 i++;
702 if (i == rx_ring->count)
703 i = 0;
704 buffer_info = &rx_ring->buffer_info[i];
705 }
706
707 rx_ring->next_to_use = i;
708}
709
710/**
711 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
712 * @rx_ring: Rx descriptor ring
713 * @cleaned_count: number to reallocate
714 * @gfp: flags for allocation
715 **/
716static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
717 int cleaned_count, gfp_t gfp)
718{
719 struct e1000_adapter *adapter = rx_ring->adapter;
720 struct net_device *netdev = adapter->netdev;
721 struct pci_dev *pdev = adapter->pdev;
722 union e1000_rx_desc_packet_split *rx_desc;
723 struct e1000_buffer *buffer_info;
724 struct e1000_ps_page *ps_page;
725 struct sk_buff *skb;
726 unsigned int i, j;
727
728 i = rx_ring->next_to_use;
729 buffer_info = &rx_ring->buffer_info[i];
730
731 while (cleaned_count--) {
732 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
733
734 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
735 ps_page = &buffer_info->ps_pages[j];
736 if (j >= adapter->rx_ps_pages) {
737 /* all unused desc entries get hw null ptr */
738 rx_desc->read.buffer_addr[j + 1] =
739 ~cpu_to_le64(0);
740 continue;
741 }
742 if (!ps_page->page) {
743 ps_page->page = alloc_page(gfp);
744 if (!ps_page->page) {
745 adapter->alloc_rx_buff_failed++;
746 goto no_buffers;
747 }
748 ps_page->dma = dma_map_page(&pdev->dev,
749 ps_page->page,
750 0, PAGE_SIZE,
751 DMA_FROM_DEVICE);
752 if (dma_mapping_error(dev: &pdev->dev,
753 dma_addr: ps_page->dma)) {
754 dev_err(&adapter->pdev->dev,
755 "Rx DMA page map failed\n");
756 adapter->rx_dma_failed++;
757 goto no_buffers;
758 }
759 }
760 /* Refresh the desc even if buffer_addrs
761 * didn't change because each write-back
762 * erases this info.
763 */
764 rx_desc->read.buffer_addr[j + 1] =
765 cpu_to_le64(ps_page->dma);
766 }
767
768 skb = __netdev_alloc_skb_ip_align(dev: netdev, length: adapter->rx_ps_bsize0,
769 gfp);
770
771 if (!skb) {
772 adapter->alloc_rx_buff_failed++;
773 break;
774 }
775
776 buffer_info->skb = skb;
777 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
778 adapter->rx_ps_bsize0,
779 DMA_FROM_DEVICE);
780 if (dma_mapping_error(dev: &pdev->dev, dma_addr: buffer_info->dma)) {
781 dev_err(&pdev->dev, "Rx DMA map failed\n");
782 adapter->rx_dma_failed++;
783 /* cleanup skb */
784 dev_kfree_skb_any(skb);
785 buffer_info->skb = NULL;
786 break;
787 }
788
789 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
790
791 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
792 /* Force memory writes to complete before letting h/w
793 * know there are new descriptors to fetch. (Only
794 * applicable for weak-ordered memory model archs,
795 * such as IA-64).
796 */
797 wmb();
798 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
799 e1000e_update_rdt_wa(rx_ring, i: i << 1);
800 else
801 writel(val: i << 1, addr: rx_ring->tail);
802 }
803
804 i++;
805 if (i == rx_ring->count)
806 i = 0;
807 buffer_info = &rx_ring->buffer_info[i];
808 }
809
810no_buffers:
811 rx_ring->next_to_use = i;
812}
813
814/**
815 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
816 * @rx_ring: Rx descriptor ring
817 * @cleaned_count: number of buffers to allocate this pass
818 * @gfp: flags for allocation
819 **/
820
821static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
822 int cleaned_count, gfp_t gfp)
823{
824 struct e1000_adapter *adapter = rx_ring->adapter;
825 struct net_device *netdev = adapter->netdev;
826 struct pci_dev *pdev = adapter->pdev;
827 union e1000_rx_desc_extended *rx_desc;
828 struct e1000_buffer *buffer_info;
829 struct sk_buff *skb;
830 unsigned int i;
831 unsigned int bufsz = 256 - 16; /* for skb_reserve */
832
833 i = rx_ring->next_to_use;
834 buffer_info = &rx_ring->buffer_info[i];
835
836 while (cleaned_count--) {
837 skb = buffer_info->skb;
838 if (skb) {
839 skb_trim(skb, len: 0);
840 goto check_page;
841 }
842
843 skb = __netdev_alloc_skb_ip_align(dev: netdev, length: bufsz, gfp);
844 if (unlikely(!skb)) {
845 /* Better luck next round */
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849
850 buffer_info->skb = skb;
851check_page:
852 /* allocate a new page if necessary */
853 if (!buffer_info->page) {
854 buffer_info->page = alloc_page(gfp);
855 if (unlikely(!buffer_info->page)) {
856 adapter->alloc_rx_buff_failed++;
857 break;
858 }
859 }
860
861 if (!buffer_info->dma) {
862 buffer_info->dma = dma_map_page(&pdev->dev,
863 buffer_info->page, 0,
864 PAGE_SIZE,
865 DMA_FROM_DEVICE);
866 if (dma_mapping_error(dev: &pdev->dev, dma_addr: buffer_info->dma)) {
867 adapter->alloc_rx_buff_failed++;
868 break;
869 }
870 }
871
872 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
873 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
874
875 if (unlikely(++i == rx_ring->count))
876 i = 0;
877 buffer_info = &rx_ring->buffer_info[i];
878 }
879
880 if (likely(rx_ring->next_to_use != i)) {
881 rx_ring->next_to_use = i;
882 if (unlikely(i-- == 0))
883 i = (rx_ring->count - 1);
884
885 /* Force memory writes to complete before letting h/w
886 * know there are new descriptors to fetch. (Only
887 * applicable for weak-ordered memory model archs,
888 * such as IA-64).
889 */
890 wmb();
891 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
892 e1000e_update_rdt_wa(rx_ring, i);
893 else
894 writel(val: i, addr: rx_ring->tail);
895 }
896}
897
898static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
899 struct sk_buff *skb)
900{
901 if (netdev->features & NETIF_F_RXHASH)
902 skb_set_hash(skb, le32_to_cpu(rss), type: PKT_HASH_TYPE_L3);
903}
904
905/**
906 * e1000_clean_rx_irq - Send received data up the network stack
907 * @rx_ring: Rx descriptor ring
908 * @work_done: output parameter for indicating completed work
909 * @work_to_do: how many packets we can clean
910 *
911 * the return value indicates whether actual cleaning was done, there
912 * is no guarantee that everything was cleaned
913 **/
914static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
915 int work_to_do)
916{
917 struct e1000_adapter *adapter = rx_ring->adapter;
918 struct net_device *netdev = adapter->netdev;
919 struct pci_dev *pdev = adapter->pdev;
920 struct e1000_hw *hw = &adapter->hw;
921 union e1000_rx_desc_extended *rx_desc, *next_rxd;
922 struct e1000_buffer *buffer_info, *next_buffer;
923 u32 length, staterr;
924 unsigned int i;
925 int cleaned_count = 0;
926 bool cleaned = false;
927 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
928
929 i = rx_ring->next_to_clean;
930 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
931 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
932 buffer_info = &rx_ring->buffer_info[i];
933
934 while (staterr & E1000_RXD_STAT_DD) {
935 struct sk_buff *skb;
936
937 if (*work_done >= work_to_do)
938 break;
939 (*work_done)++;
940 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
941
942 skb = buffer_info->skb;
943 buffer_info->skb = NULL;
944
945 prefetch(skb->data - NET_IP_ALIGN);
946
947 i++;
948 if (i == rx_ring->count)
949 i = 0;
950 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
951 prefetch(next_rxd);
952
953 next_buffer = &rx_ring->buffer_info[i];
954
955 cleaned = true;
956 cleaned_count++;
957 dma_unmap_single(&pdev->dev, buffer_info->dma,
958 adapter->rx_buffer_len, DMA_FROM_DEVICE);
959 buffer_info->dma = 0;
960
961 length = le16_to_cpu(rx_desc->wb.upper.length);
962
963 /* !EOP means multiple descriptors were used to store a single
964 * packet, if that's the case we need to toss it. In fact, we
965 * need to toss every packet with the EOP bit clear and the
966 * next frame that _does_ have the EOP bit set, as it is by
967 * definition only a frame fragment
968 */
969 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
970 adapter->flags2 |= FLAG2_IS_DISCARDING;
971
972 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
973 /* All receives must fit into a single buffer */
974 e_dbg("Receive packet consumed multiple buffers\n");
975 /* recycle */
976 buffer_info->skb = skb;
977 if (staterr & E1000_RXD_STAT_EOP)
978 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
979 goto next_desc;
980 }
981
982 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
983 !(netdev->features & NETIF_F_RXALL))) {
984 /* recycle */
985 buffer_info->skb = skb;
986 goto next_desc;
987 }
988
989 /* adjust length to remove Ethernet CRC */
990 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
991 /* If configured to store CRC, don't subtract FCS,
992 * but keep the FCS bytes out of the total_rx_bytes
993 * counter
994 */
995 if (netdev->features & NETIF_F_RXFCS)
996 total_rx_bytes -= 4;
997 else
998 length -= 4;
999 }
1000
1001 total_rx_bytes += length;
1002 total_rx_packets++;
1003
1004 /* code added for copybreak, this should improve
1005 * performance for small packets with large amounts
1006 * of reassembly being done in the stack
1007 */
1008 if (length < copybreak) {
1009 struct sk_buff *new_skb =
1010 napi_alloc_skb(napi: &adapter->napi, length);
1011 if (new_skb) {
1012 skb_copy_to_linear_data_offset(skb: new_skb,
1013 offset: -NET_IP_ALIGN,
1014 from: (skb->data -
1015 NET_IP_ALIGN),
1016 len: (length +
1017 NET_IP_ALIGN));
1018 /* save the skb in buffer_info as good */
1019 buffer_info->skb = skb;
1020 skb = new_skb;
1021 }
1022 /* else just continue with the old one */
1023 }
1024 /* end copybreak code */
1025 skb_put(skb, len: length);
1026
1027 /* Receive Checksum Offload */
1028 e1000_rx_checksum(adapter, status_err: staterr, skb);
1029
1030 e1000_rx_hash(netdev, rss: rx_desc->wb.lower.hi_dword.rss, skb);
1031
1032 e1000_receive_skb(adapter, netdev, skb, staterr,
1033 vlan: rx_desc->wb.upper.vlan);
1034
1035next_desc:
1036 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1037
1038 /* return some buffers to hardware, one at a time is too slow */
1039 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1040 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1041 GFP_ATOMIC);
1042 cleaned_count = 0;
1043 }
1044
1045 /* use prefetched values */
1046 rx_desc = next_rxd;
1047 buffer_info = next_buffer;
1048
1049 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1050 }
1051 rx_ring->next_to_clean = i;
1052
1053 cleaned_count = e1000_desc_unused(ring: rx_ring);
1054 if (cleaned_count)
1055 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1056
1057 adapter->total_rx_bytes += total_rx_bytes;
1058 adapter->total_rx_packets += total_rx_packets;
1059 return cleaned;
1060}
1061
1062static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1063 struct e1000_buffer *buffer_info,
1064 bool drop)
1065{
1066 struct e1000_adapter *adapter = tx_ring->adapter;
1067
1068 if (buffer_info->dma) {
1069 if (buffer_info->mapped_as_page)
1070 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1071 buffer_info->length, DMA_TO_DEVICE);
1072 else
1073 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1074 buffer_info->length, DMA_TO_DEVICE);
1075 buffer_info->dma = 0;
1076 }
1077 if (buffer_info->skb) {
1078 if (drop)
1079 dev_kfree_skb_any(skb: buffer_info->skb);
1080 else
1081 dev_consume_skb_any(skb: buffer_info->skb);
1082 buffer_info->skb = NULL;
1083 }
1084 buffer_info->time_stamp = 0;
1085}
1086
1087static void e1000_print_hw_hang(struct work_struct *work)
1088{
1089 struct e1000_adapter *adapter = container_of(work,
1090 struct e1000_adapter,
1091 print_hang_task);
1092 struct net_device *netdev = adapter->netdev;
1093 struct e1000_ring *tx_ring = adapter->tx_ring;
1094 unsigned int i = tx_ring->next_to_clean;
1095 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1096 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1097 struct e1000_hw *hw = &adapter->hw;
1098 u16 phy_status, phy_1000t_status, phy_ext_status;
1099 u16 pci_status;
1100
1101 if (test_bit(__E1000_DOWN, &adapter->state))
1102 return;
1103
1104 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1105 /* May be block on write-back, flush and detect again
1106 * flush pending descriptor writebacks to memory
1107 */
1108 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1109 /* execute the writes immediately */
1110 e1e_flush();
1111 /* Due to rare timing issues, write to TIDV again to ensure
1112 * the write is successful
1113 */
1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1115 /* execute the writes immediately */
1116 e1e_flush();
1117 adapter->tx_hang_recheck = true;
1118 return;
1119 }
1120 adapter->tx_hang_recheck = false;
1121
1122 if (er32(TDH(0)) == er32(TDT(0))) {
1123 e_dbg("false hang detected, ignoring\n");
1124 return;
1125 }
1126
1127 /* Real hang detected */
1128 netif_stop_queue(dev: netdev);
1129
1130 e1e_rphy(hw, MII_BMSR, data: &phy_status);
1131 e1e_rphy(hw, MII_STAT1000, data: &phy_1000t_status);
1132 e1e_rphy(hw, MII_ESTATUS, data: &phy_ext_status);
1133
1134 pci_read_config_word(dev: adapter->pdev, PCI_STATUS, val: &pci_status);
1135
1136 /* detected Hardware unit hang */
1137 e_err("Detected Hardware Unit Hang:\n"
1138 " TDH <%x>\n"
1139 " TDT <%x>\n"
1140 " next_to_use <%x>\n"
1141 " next_to_clean <%x>\n"
1142 "buffer_info[next_to_clean]:\n"
1143 " time_stamp <%lx>\n"
1144 " next_to_watch <%x>\n"
1145 " jiffies <%lx>\n"
1146 " next_to_watch.status <%x>\n"
1147 "MAC Status <%x>\n"
1148 "PHY Status <%x>\n"
1149 "PHY 1000BASE-T Status <%x>\n"
1150 "PHY Extended Status <%x>\n"
1151 "PCI Status <%x>\n",
1152 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1153 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1154 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1155 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1156
1157 e1000e_dump(adapter);
1158
1159 /* Suggest workaround for known h/w issue */
1160 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1161 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1162}
1163
1164/**
1165 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1166 * @work: pointer to work struct
1167 *
1168 * This work function polls the TSYNCTXCTL valid bit to determine when a
1169 * timestamp has been taken for the current stored skb. The timestamp must
1170 * be for this skb because only one such packet is allowed in the queue.
1171 */
1172static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1173{
1174 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1175 tx_hwtstamp_work);
1176 struct e1000_hw *hw = &adapter->hw;
1177
1178 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1179 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1180 struct skb_shared_hwtstamps shhwtstamps;
1181 u64 txstmp;
1182
1183 txstmp = er32(TXSTMPL);
1184 txstmp |= (u64)er32(TXSTMPH) << 32;
1185
1186 e1000e_systim_to_hwtstamp(adapter, hwtstamps: &shhwtstamps, systim: txstmp);
1187
1188 /* Clear the global tx_hwtstamp_skb pointer and force writes
1189 * prior to notifying the stack of a Tx timestamp.
1190 */
1191 adapter->tx_hwtstamp_skb = NULL;
1192 wmb(); /* force write prior to skb_tstamp_tx */
1193
1194 skb_tstamp_tx(orig_skb: skb, hwtstamps: &shhwtstamps);
1195 dev_consume_skb_any(skb);
1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1197 + adapter->tx_timeout_factor * HZ)) {
1198 dev_kfree_skb_any(skb: adapter->tx_hwtstamp_skb);
1199 adapter->tx_hwtstamp_skb = NULL;
1200 adapter->tx_hwtstamp_timeouts++;
1201 e_warn("clearing Tx timestamp hang\n");
1202 } else {
1203 /* reschedule to check later */
1204 schedule_work(work: &adapter->tx_hwtstamp_work);
1205 }
1206}
1207
1208/**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1210 * @tx_ring: Tx descriptor ring
1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
1215static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1216{
1217 struct e1000_adapter *adapter = tx_ring->adapter;
1218 struct net_device *netdev = adapter->netdev;
1219 struct e1000_hw *hw = &adapter->hw;
1220 struct e1000_tx_desc *tx_desc, *eop_desc;
1221 struct e1000_buffer *buffer_info;
1222 unsigned int i, eop;
1223 unsigned int count = 0;
1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1225 unsigned int bytes_compl = 0, pkts_compl = 0;
1226
1227 i = tx_ring->next_to_clean;
1228 eop = tx_ring->buffer_info[i].next_to_watch;
1229 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1230
1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1232 (count < tx_ring->count)) {
1233 bool cleaned = false;
1234
1235 dma_rmb(); /* read buffer_info after eop_desc */
1236 for (; !cleaned; count++) {
1237 tx_desc = E1000_TX_DESC(*tx_ring, i);
1238 buffer_info = &tx_ring->buffer_info[i];
1239 cleaned = (i == eop);
1240
1241 if (cleaned) {
1242 total_tx_packets += buffer_info->segs;
1243 total_tx_bytes += buffer_info->bytecount;
1244 if (buffer_info->skb) {
1245 bytes_compl += buffer_info->skb->len;
1246 pkts_compl++;
1247 }
1248 }
1249
1250 e1000_put_txbuf(tx_ring, buffer_info, drop: false);
1251 tx_desc->upper.data = 0;
1252
1253 i++;
1254 if (i == tx_ring->count)
1255 i = 0;
1256 }
1257
1258 if (i == tx_ring->next_to_use)
1259 break;
1260 eop = tx_ring->buffer_info[i].next_to_watch;
1261 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1262 }
1263
1264 tx_ring->next_to_clean = i;
1265
1266 netdev_completed_queue(dev: netdev, pkts: pkts_compl, bytes: bytes_compl);
1267
1268#define TX_WAKE_THRESHOLD 32
1269 if (count && netif_carrier_ok(dev: netdev) &&
1270 e1000_desc_unused(ring: tx_ring) >= TX_WAKE_THRESHOLD) {
1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1274 smp_mb();
1275
1276 if (netif_queue_stopped(dev: netdev) &&
1277 !(test_bit(__E1000_DOWN, &adapter->state))) {
1278 netif_wake_queue(dev: netdev);
1279 ++adapter->restart_queue;
1280 }
1281 }
1282
1283 if (adapter->detect_tx_hung) {
1284 /* Detect a transmit hang in hardware, this serializes the
1285 * check with the clearing of time_stamp and movement of i
1286 */
1287 adapter->detect_tx_hung = false;
1288 if (tx_ring->buffer_info[i].time_stamp &&
1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1290 + (adapter->tx_timeout_factor * HZ)) &&
1291 !(er32(STATUS) & E1000_STATUS_TXOFF))
1292 schedule_work(work: &adapter->print_hang_task);
1293 else
1294 adapter->tx_hang_recheck = false;
1295 }
1296 adapter->total_tx_bytes += total_tx_bytes;
1297 adapter->total_tx_packets += total_tx_packets;
1298 return count < tx_ring->count;
1299}
1300
1301/**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1303 * @rx_ring: Rx descriptor ring
1304 * @work_done: output parameter for indicating completed work
1305 * @work_to_do: how many packets we can clean
1306 *
1307 * the return value indicates whether actual cleaning was done, there
1308 * is no guarantee that everything was cleaned
1309 **/
1310static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1311 int work_to_do)
1312{
1313 struct e1000_adapter *adapter = rx_ring->adapter;
1314 struct e1000_hw *hw = &adapter->hw;
1315 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1316 struct net_device *netdev = adapter->netdev;
1317 struct pci_dev *pdev = adapter->pdev;
1318 struct e1000_buffer *buffer_info, *next_buffer;
1319 struct e1000_ps_page *ps_page;
1320 struct sk_buff *skb;
1321 unsigned int i, j;
1322 u32 length, staterr;
1323 int cleaned_count = 0;
1324 bool cleaned = false;
1325 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1326
1327 i = rx_ring->next_to_clean;
1328 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1329 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1330 buffer_info = &rx_ring->buffer_info[i];
1331
1332 while (staterr & E1000_RXD_STAT_DD) {
1333 if (*work_done >= work_to_do)
1334 break;
1335 (*work_done)++;
1336 skb = buffer_info->skb;
1337 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1338
1339 /* in the packet split case this is header only */
1340 prefetch(skb->data - NET_IP_ALIGN);
1341
1342 i++;
1343 if (i == rx_ring->count)
1344 i = 0;
1345 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1346 prefetch(next_rxd);
1347
1348 next_buffer = &rx_ring->buffer_info[i];
1349
1350 cleaned = true;
1351 cleaned_count++;
1352 dma_unmap_single(&pdev->dev, buffer_info->dma,
1353 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1354 buffer_info->dma = 0;
1355
1356 /* see !EOP comment in other Rx routine */
1357 if (!(staterr & E1000_RXD_STAT_EOP))
1358 adapter->flags2 |= FLAG2_IS_DISCARDING;
1359
1360 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1361 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1362 dev_kfree_skb_irq(skb);
1363 if (staterr & E1000_RXD_STAT_EOP)
1364 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1365 goto next_desc;
1366 }
1367
1368 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1369 !(netdev->features & NETIF_F_RXALL))) {
1370 dev_kfree_skb_irq(skb);
1371 goto next_desc;
1372 }
1373
1374 length = le16_to_cpu(rx_desc->wb.middle.length0);
1375
1376 if (!length) {
1377 e_dbg("Last part of the packet spanning multiple descriptors\n");
1378 dev_kfree_skb_irq(skb);
1379 goto next_desc;
1380 }
1381
1382 /* Good Receive */
1383 skb_put(skb, len: length);
1384
1385 {
1386 /* this looks ugly, but it seems compiler issues make
1387 * it more efficient than reusing j
1388 */
1389 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1390
1391 /* page alloc/put takes too long and effects small
1392 * packet throughput, so unsplit small packets and
1393 * save the alloc/put
1394 */
1395 if (l1 && (l1 <= copybreak) &&
1396 ((length + l1) <= adapter->rx_ps_bsize0)) {
1397 ps_page = &buffer_info->ps_pages[0];
1398
1399 dma_sync_single_for_cpu(dev: &pdev->dev,
1400 addr: ps_page->dma,
1401 PAGE_SIZE,
1402 dir: DMA_FROM_DEVICE);
1403 memcpy(skb_tail_pointer(skb),
1404 page_address(ps_page->page), l1);
1405 dma_sync_single_for_device(dev: &pdev->dev,
1406 addr: ps_page->dma,
1407 PAGE_SIZE,
1408 dir: DMA_FROM_DEVICE);
1409
1410 /* remove the CRC */
1411 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1412 if (!(netdev->features & NETIF_F_RXFCS))
1413 l1 -= 4;
1414 }
1415
1416 skb_put(skb, len: l1);
1417 goto copydone;
1418 } /* if */
1419 }
1420
1421 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1422 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1423 if (!length)
1424 break;
1425
1426 ps_page = &buffer_info->ps_pages[j];
1427 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1428 DMA_FROM_DEVICE);
1429 ps_page->dma = 0;
1430 skb_fill_page_desc(skb, i: j, page: ps_page->page, off: 0, size: length);
1431 ps_page->page = NULL;
1432 skb->len += length;
1433 skb->data_len += length;
1434 skb->truesize += PAGE_SIZE;
1435 }
1436
1437 /* strip the ethernet crc, problem is we're using pages now so
1438 * this whole operation can get a little cpu intensive
1439 */
1440 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1441 if (!(netdev->features & NETIF_F_RXFCS))
1442 pskb_trim(skb, len: skb->len - 4);
1443 }
1444
1445copydone:
1446 total_rx_bytes += skb->len;
1447 total_rx_packets++;
1448
1449 e1000_rx_checksum(adapter, status_err: staterr, skb);
1450
1451 e1000_rx_hash(netdev, rss: rx_desc->wb.lower.hi_dword.rss, skb);
1452
1453 if (rx_desc->wb.upper.header_status &
1454 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1455 adapter->rx_hdr_split++;
1456
1457 e1000_receive_skb(adapter, netdev, skb, staterr,
1458 vlan: rx_desc->wb.middle.vlan);
1459
1460next_desc:
1461 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1462 buffer_info->skb = NULL;
1463
1464 /* return some buffers to hardware, one at a time is too slow */
1465 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1466 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1467 GFP_ATOMIC);
1468 cleaned_count = 0;
1469 }
1470
1471 /* use prefetched values */
1472 rx_desc = next_rxd;
1473 buffer_info = next_buffer;
1474
1475 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1476 }
1477 rx_ring->next_to_clean = i;
1478
1479 cleaned_count = e1000_desc_unused(ring: rx_ring);
1480 if (cleaned_count)
1481 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1482
1483 adapter->total_rx_bytes += total_rx_bytes;
1484 adapter->total_rx_packets += total_rx_packets;
1485 return cleaned;
1486}
1487
1488static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1489 u16 length)
1490{
1491 bi->page = NULL;
1492 skb->len += length;
1493 skb->data_len += length;
1494 skb->truesize += PAGE_SIZE;
1495}
1496
1497/**
1498 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1499 * @rx_ring: Rx descriptor ring
1500 * @work_done: output parameter for indicating completed work
1501 * @work_to_do: how many packets we can clean
1502 *
1503 * the return value indicates whether actual cleaning was done, there
1504 * is no guarantee that everything was cleaned
1505 **/
1506static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1507 int work_to_do)
1508{
1509 struct e1000_adapter *adapter = rx_ring->adapter;
1510 struct net_device *netdev = adapter->netdev;
1511 struct pci_dev *pdev = adapter->pdev;
1512 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1513 struct e1000_buffer *buffer_info, *next_buffer;
1514 u32 length, staterr;
1515 unsigned int i;
1516 int cleaned_count = 0;
1517 bool cleaned = false;
1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1519 struct skb_shared_info *shinfo;
1520
1521 i = rx_ring->next_to_clean;
1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1524 buffer_info = &rx_ring->buffer_info[i];
1525
1526 while (staterr & E1000_RXD_STAT_DD) {
1527 struct sk_buff *skb;
1528
1529 if (*work_done >= work_to_do)
1530 break;
1531 (*work_done)++;
1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1533
1534 skb = buffer_info->skb;
1535 buffer_info->skb = NULL;
1536
1537 ++i;
1538 if (i == rx_ring->count)
1539 i = 0;
1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1541 prefetch(next_rxd);
1542
1543 next_buffer = &rx_ring->buffer_info[i];
1544
1545 cleaned = true;
1546 cleaned_count++;
1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1548 DMA_FROM_DEVICE);
1549 buffer_info->dma = 0;
1550
1551 length = le16_to_cpu(rx_desc->wb.upper.length);
1552
1553 /* errors is only valid for DD + EOP descriptors */
1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1556 !(netdev->features & NETIF_F_RXALL)))) {
1557 /* recycle both page and skb */
1558 buffer_info->skb = skb;
1559 /* an error means any chain goes out the window too */
1560 if (rx_ring->rx_skb_top)
1561 dev_kfree_skb_irq(skb: rx_ring->rx_skb_top);
1562 rx_ring->rx_skb_top = NULL;
1563 goto next_desc;
1564 }
1565#define rxtop (rx_ring->rx_skb_top)
1566 if (!(staterr & E1000_RXD_STAT_EOP)) {
1567 /* this descriptor is only the beginning (or middle) */
1568 if (!rxtop) {
1569 /* this is the beginning of a chain */
1570 rxtop = skb;
1571 skb_fill_page_desc(rxtop, i: 0, page: buffer_info->page,
1572 off: 0, size: length);
1573 } else {
1574 /* this is the middle of a chain */
1575 shinfo = skb_shinfo(rxtop);
1576 skb_fill_page_desc(rxtop, i: shinfo->nr_frags,
1577 page: buffer_info->page, off: 0,
1578 size: length);
1579 /* re-use the skb, only consumed the page */
1580 buffer_info->skb = skb;
1581 }
1582 e1000_consume_page(bi: buffer_info, rxtop, length);
1583 goto next_desc;
1584 } else {
1585 if (rxtop) {
1586 /* end of the chain */
1587 shinfo = skb_shinfo(rxtop);
1588 skb_fill_page_desc(rxtop, i: shinfo->nr_frags,
1589 page: buffer_info->page, off: 0,
1590 size: length);
1591 /* re-use the current skb, we only consumed the
1592 * page
1593 */
1594 buffer_info->skb = skb;
1595 skb = rxtop;
1596 rxtop = NULL;
1597 e1000_consume_page(bi: buffer_info, skb, length);
1598 } else {
1599 /* no chain, got EOP, this buf is the packet
1600 * copybreak to save the put_page/alloc_page
1601 */
1602 if (length <= copybreak &&
1603 skb_tailroom(skb) >= length) {
1604 memcpy(skb_tail_pointer(skb),
1605 page_address(buffer_info->page),
1606 length);
1607 /* re-use the page, so don't erase
1608 * buffer_info->page
1609 */
1610 skb_put(skb, len: length);
1611 } else {
1612 skb_fill_page_desc(skb, i: 0,
1613 page: buffer_info->page, off: 0,
1614 size: length);
1615 e1000_consume_page(bi: buffer_info, skb,
1616 length);
1617 }
1618 }
1619 }
1620
1621 /* Receive Checksum Offload */
1622 e1000_rx_checksum(adapter, status_err: staterr, skb);
1623
1624 e1000_rx_hash(netdev, rss: rx_desc->wb.lower.hi_dword.rss, skb);
1625
1626 /* probably a little skewed due to removing CRC */
1627 total_rx_bytes += skb->len;
1628 total_rx_packets++;
1629
1630 /* eth type trans needs skb->data to point to something */
1631 if (!pskb_may_pull(skb, ETH_HLEN)) {
1632 e_err("pskb_may_pull failed.\n");
1633 dev_kfree_skb_irq(skb);
1634 goto next_desc;
1635 }
1636
1637 e1000_receive_skb(adapter, netdev, skb, staterr,
1638 vlan: rx_desc->wb.upper.vlan);
1639
1640next_desc:
1641 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1642
1643 /* return some buffers to hardware, one at a time is too slow */
1644 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1645 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1646 GFP_ATOMIC);
1647 cleaned_count = 0;
1648 }
1649
1650 /* use prefetched values */
1651 rx_desc = next_rxd;
1652 buffer_info = next_buffer;
1653
1654 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1655 }
1656 rx_ring->next_to_clean = i;
1657
1658 cleaned_count = e1000_desc_unused(ring: rx_ring);
1659 if (cleaned_count)
1660 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1661
1662 adapter->total_rx_bytes += total_rx_bytes;
1663 adapter->total_rx_packets += total_rx_packets;
1664 return cleaned;
1665}
1666
1667/**
1668 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1669 * @rx_ring: Rx descriptor ring
1670 **/
1671static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1672{
1673 struct e1000_adapter *adapter = rx_ring->adapter;
1674 struct e1000_buffer *buffer_info;
1675 struct e1000_ps_page *ps_page;
1676 struct pci_dev *pdev = adapter->pdev;
1677 unsigned int i, j;
1678
1679 /* Free all the Rx ring sk_buffs */
1680 for (i = 0; i < rx_ring->count; i++) {
1681 buffer_info = &rx_ring->buffer_info[i];
1682 if (buffer_info->dma) {
1683 if (adapter->clean_rx == e1000_clean_rx_irq)
1684 dma_unmap_single(&pdev->dev, buffer_info->dma,
1685 adapter->rx_buffer_len,
1686 DMA_FROM_DEVICE);
1687 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1688 dma_unmap_page(&pdev->dev, buffer_info->dma,
1689 PAGE_SIZE, DMA_FROM_DEVICE);
1690 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1691 dma_unmap_single(&pdev->dev, buffer_info->dma,
1692 adapter->rx_ps_bsize0,
1693 DMA_FROM_DEVICE);
1694 buffer_info->dma = 0;
1695 }
1696
1697 if (buffer_info->page) {
1698 put_page(page: buffer_info->page);
1699 buffer_info->page = NULL;
1700 }
1701
1702 if (buffer_info->skb) {
1703 dev_kfree_skb(buffer_info->skb);
1704 buffer_info->skb = NULL;
1705 }
1706
1707 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1708 ps_page = &buffer_info->ps_pages[j];
1709 if (!ps_page->page)
1710 break;
1711 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1712 DMA_FROM_DEVICE);
1713 ps_page->dma = 0;
1714 put_page(page: ps_page->page);
1715 ps_page->page = NULL;
1716 }
1717 }
1718
1719 /* there also may be some cached data from a chained receive */
1720 if (rx_ring->rx_skb_top) {
1721 dev_kfree_skb(rx_ring->rx_skb_top);
1722 rx_ring->rx_skb_top = NULL;
1723 }
1724
1725 /* Zero out the descriptor ring */
1726 memset(rx_ring->desc, 0, rx_ring->size);
1727
1728 rx_ring->next_to_clean = 0;
1729 rx_ring->next_to_use = 0;
1730 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1731}
1732
1733static void e1000e_downshift_workaround(struct work_struct *work)
1734{
1735 struct e1000_adapter *adapter = container_of(work,
1736 struct e1000_adapter,
1737 downshift_task);
1738
1739 if (test_bit(__E1000_DOWN, &adapter->state))
1740 return;
1741
1742 e1000e_gig_downshift_workaround_ich8lan(hw: &adapter->hw);
1743}
1744
1745/**
1746 * e1000_intr_msi - Interrupt Handler
1747 * @irq: interrupt number
1748 * @data: pointer to a network interface device structure
1749 **/
1750static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1751{
1752 struct net_device *netdev = data;
1753 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
1754 struct e1000_hw *hw = &adapter->hw;
1755 u32 icr = er32(ICR);
1756
1757 /* read ICR disables interrupts using IAM */
1758 if (icr & E1000_ICR_LSC) {
1759 hw->mac.get_link_status = true;
1760 /* ICH8 workaround-- Call gig speed drop workaround on cable
1761 * disconnect (LSC) before accessing any PHY registers
1762 */
1763 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1764 (!(er32(STATUS) & E1000_STATUS_LU)))
1765 schedule_work(work: &adapter->downshift_task);
1766
1767 /* 80003ES2LAN workaround-- For packet buffer work-around on
1768 * link down event; disable receives here in the ISR and reset
1769 * adapter in watchdog
1770 */
1771 if (netif_carrier_ok(dev: netdev) &&
1772 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1773 /* disable receives */
1774 u32 rctl = er32(RCTL);
1775
1776 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1777 adapter->flags |= FLAG_RESTART_NOW;
1778 }
1779 /* guard against interrupt when we're going down */
1780 if (!test_bit(__E1000_DOWN, &adapter->state))
1781 mod_timer(timer: &adapter->watchdog_timer, expires: jiffies + 1);
1782 }
1783
1784 /* Reset on uncorrectable ECC error */
1785 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1786 u32 pbeccsts = er32(PBECCSTS);
1787
1788 adapter->corr_errors +=
1789 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1790 adapter->uncorr_errors +=
1791 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1792 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1793
1794 /* Do the reset outside of interrupt context */
1795 schedule_work(work: &adapter->reset_task);
1796
1797 /* return immediately since reset is imminent */
1798 return IRQ_HANDLED;
1799 }
1800
1801 if (napi_schedule_prep(n: &adapter->napi)) {
1802 adapter->total_tx_bytes = 0;
1803 adapter->total_tx_packets = 0;
1804 adapter->total_rx_bytes = 0;
1805 adapter->total_rx_packets = 0;
1806 __napi_schedule(n: &adapter->napi);
1807 }
1808
1809 return IRQ_HANDLED;
1810}
1811
1812/**
1813 * e1000_intr - Interrupt Handler
1814 * @irq: interrupt number
1815 * @data: pointer to a network interface device structure
1816 **/
1817static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1818{
1819 struct net_device *netdev = data;
1820 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
1821 struct e1000_hw *hw = &adapter->hw;
1822 u32 rctl, icr = er32(ICR);
1823
1824 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1825 return IRQ_NONE; /* Not our interrupt */
1826
1827 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1828 * not set, then the adapter didn't send an interrupt
1829 */
1830 if (!(icr & E1000_ICR_INT_ASSERTED))
1831 return IRQ_NONE;
1832
1833 /* Interrupt Auto-Mask...upon reading ICR,
1834 * interrupts are masked. No need for the
1835 * IMC write
1836 */
1837
1838 if (icr & E1000_ICR_LSC) {
1839 hw->mac.get_link_status = true;
1840 /* ICH8 workaround-- Call gig speed drop workaround on cable
1841 * disconnect (LSC) before accessing any PHY registers
1842 */
1843 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1844 (!(er32(STATUS) & E1000_STATUS_LU)))
1845 schedule_work(work: &adapter->downshift_task);
1846
1847 /* 80003ES2LAN workaround--
1848 * For packet buffer work-around on link down event;
1849 * disable receives here in the ISR and
1850 * reset adapter in watchdog
1851 */
1852 if (netif_carrier_ok(dev: netdev) &&
1853 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1854 /* disable receives */
1855 rctl = er32(RCTL);
1856 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1857 adapter->flags |= FLAG_RESTART_NOW;
1858 }
1859 /* guard against interrupt when we're going down */
1860 if (!test_bit(__E1000_DOWN, &adapter->state))
1861 mod_timer(timer: &adapter->watchdog_timer, expires: jiffies + 1);
1862 }
1863
1864 /* Reset on uncorrectable ECC error */
1865 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1866 u32 pbeccsts = er32(PBECCSTS);
1867
1868 adapter->corr_errors +=
1869 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1870 adapter->uncorr_errors +=
1871 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1872 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1873
1874 /* Do the reset outside of interrupt context */
1875 schedule_work(work: &adapter->reset_task);
1876
1877 /* return immediately since reset is imminent */
1878 return IRQ_HANDLED;
1879 }
1880
1881 if (napi_schedule_prep(n: &adapter->napi)) {
1882 adapter->total_tx_bytes = 0;
1883 adapter->total_tx_packets = 0;
1884 adapter->total_rx_bytes = 0;
1885 adapter->total_rx_packets = 0;
1886 __napi_schedule(n: &adapter->napi);
1887 }
1888
1889 return IRQ_HANDLED;
1890}
1891
1892static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1893{
1894 struct net_device *netdev = data;
1895 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
1896 struct e1000_hw *hw = &adapter->hw;
1897 u32 icr = er32(ICR);
1898
1899 if (icr & adapter->eiac_mask)
1900 ew32(ICS, (icr & adapter->eiac_mask));
1901
1902 if (icr & E1000_ICR_LSC) {
1903 hw->mac.get_link_status = true;
1904 /* guard against interrupt when we're going down */
1905 if (!test_bit(__E1000_DOWN, &adapter->state))
1906 mod_timer(timer: &adapter->watchdog_timer, expires: jiffies + 1);
1907 }
1908
1909 if (!test_bit(__E1000_DOWN, &adapter->state))
1910 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1911
1912 return IRQ_HANDLED;
1913}
1914
1915static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1916{
1917 struct net_device *netdev = data;
1918 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
1919 struct e1000_hw *hw = &adapter->hw;
1920 struct e1000_ring *tx_ring = adapter->tx_ring;
1921
1922 adapter->total_tx_bytes = 0;
1923 adapter->total_tx_packets = 0;
1924
1925 if (!e1000_clean_tx_irq(tx_ring))
1926 /* Ring was not completely cleaned, so fire another interrupt */
1927 ew32(ICS, tx_ring->ims_val);
1928
1929 if (!test_bit(__E1000_DOWN, &adapter->state))
1930 ew32(IMS, adapter->tx_ring->ims_val);
1931
1932 return IRQ_HANDLED;
1933}
1934
1935static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1936{
1937 struct net_device *netdev = data;
1938 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
1939 struct e1000_ring *rx_ring = adapter->rx_ring;
1940
1941 /* Write the ITR value calculated at the end of the
1942 * previous interrupt.
1943 */
1944 if (rx_ring->set_itr) {
1945 u32 itr = rx_ring->itr_val ?
1946 1000000000 / (rx_ring->itr_val * 256) : 0;
1947
1948 writel(val: itr, addr: rx_ring->itr_register);
1949 rx_ring->set_itr = 0;
1950 }
1951
1952 if (napi_schedule_prep(n: &adapter->napi)) {
1953 adapter->total_rx_bytes = 0;
1954 adapter->total_rx_packets = 0;
1955 __napi_schedule(n: &adapter->napi);
1956 }
1957 return IRQ_HANDLED;
1958}
1959
1960/**
1961 * e1000_configure_msix - Configure MSI-X hardware
1962 * @adapter: board private structure
1963 *
1964 * e1000_configure_msix sets up the hardware to properly
1965 * generate MSI-X interrupts.
1966 **/
1967static void e1000_configure_msix(struct e1000_adapter *adapter)
1968{
1969 struct e1000_hw *hw = &adapter->hw;
1970 struct e1000_ring *rx_ring = adapter->rx_ring;
1971 struct e1000_ring *tx_ring = adapter->tx_ring;
1972 int vector = 0;
1973 u32 ctrl_ext, ivar = 0;
1974
1975 adapter->eiac_mask = 0;
1976
1977 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1978 if (hw->mac.type == e1000_82574) {
1979 u32 rfctl = er32(RFCTL);
1980
1981 rfctl |= E1000_RFCTL_ACK_DIS;
1982 ew32(RFCTL, rfctl);
1983 }
1984
1985 /* Configure Rx vector */
1986 rx_ring->ims_val = E1000_IMS_RXQ0;
1987 adapter->eiac_mask |= rx_ring->ims_val;
1988 if (rx_ring->itr_val)
1989 writel(val: 1000000000 / (rx_ring->itr_val * 256),
1990 addr: rx_ring->itr_register);
1991 else
1992 writel(val: 1, addr: rx_ring->itr_register);
1993 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1994
1995 /* Configure Tx vector */
1996 tx_ring->ims_val = E1000_IMS_TXQ0;
1997 vector++;
1998 if (tx_ring->itr_val)
1999 writel(val: 1000000000 / (tx_ring->itr_val * 256),
2000 addr: tx_ring->itr_register);
2001 else
2002 writel(val: 1, addr: tx_ring->itr_register);
2003 adapter->eiac_mask |= tx_ring->ims_val;
2004 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2005
2006 /* set vector for Other Causes, e.g. link changes */
2007 vector++;
2008 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2009 if (rx_ring->itr_val)
2010 writel(val: 1000000000 / (rx_ring->itr_val * 256),
2011 addr: hw->hw_addr + E1000_EITR_82574(vector));
2012 else
2013 writel(val: 1, addr: hw->hw_addr + E1000_EITR_82574(vector));
2014
2015 /* Cause Tx interrupts on every write back */
2016 ivar |= BIT(31);
2017
2018 ew32(IVAR, ivar);
2019
2020 /* enable MSI-X PBA support */
2021 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2022 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2023 ew32(CTRL_EXT, ctrl_ext);
2024 e1e_flush();
2025}
2026
2027void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2028{
2029 if (adapter->msix_entries) {
2030 pci_disable_msix(dev: adapter->pdev);
2031 kfree(objp: adapter->msix_entries);
2032 adapter->msix_entries = NULL;
2033 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2034 pci_disable_msi(dev: adapter->pdev);
2035 adapter->flags &= ~FLAG_MSI_ENABLED;
2036 }
2037}
2038
2039/**
2040 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2041 * @adapter: board private structure
2042 *
2043 * Attempt to configure interrupts using the best available
2044 * capabilities of the hardware and kernel.
2045 **/
2046void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2047{
2048 int err;
2049 int i;
2050
2051 switch (adapter->int_mode) {
2052 case E1000E_INT_MODE_MSIX:
2053 if (adapter->flags & FLAG_HAS_MSIX) {
2054 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2055 adapter->msix_entries = kcalloc(n: adapter->num_vectors,
2056 size: sizeof(struct
2057 msix_entry),
2058 GFP_KERNEL);
2059 if (adapter->msix_entries) {
2060 struct e1000_adapter *a = adapter;
2061
2062 for (i = 0; i < adapter->num_vectors; i++)
2063 adapter->msix_entries[i].entry = i;
2064
2065 err = pci_enable_msix_range(dev: a->pdev,
2066 entries: a->msix_entries,
2067 minvec: a->num_vectors,
2068 maxvec: a->num_vectors);
2069 if (err > 0)
2070 return;
2071 }
2072 /* MSI-X failed, so fall through and try MSI */
2073 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2074 e1000e_reset_interrupt_capability(adapter);
2075 }
2076 adapter->int_mode = E1000E_INT_MODE_MSI;
2077 fallthrough;
2078 case E1000E_INT_MODE_MSI:
2079 if (!pci_enable_msi(dev: adapter->pdev)) {
2080 adapter->flags |= FLAG_MSI_ENABLED;
2081 } else {
2082 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2083 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2084 }
2085 fallthrough;
2086 case E1000E_INT_MODE_LEGACY:
2087 /* Don't do anything; this is the system default */
2088 break;
2089 }
2090
2091 /* store the number of vectors being used */
2092 adapter->num_vectors = 1;
2093}
2094
2095/**
2096 * e1000_request_msix - Initialize MSI-X interrupts
2097 * @adapter: board private structure
2098 *
2099 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2100 * kernel.
2101 **/
2102static int e1000_request_msix(struct e1000_adapter *adapter)
2103{
2104 struct net_device *netdev = adapter->netdev;
2105 int err = 0, vector = 0;
2106
2107 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2108 snprintf(buf: adapter->rx_ring->name,
2109 size: sizeof(adapter->rx_ring->name) - 1,
2110 fmt: "%.14s-rx-0", netdev->name);
2111 else
2112 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2113 err = request_irq(irq: adapter->msix_entries[vector].vector,
2114 handler: e1000_intr_msix_rx, flags: 0, name: adapter->rx_ring->name,
2115 dev: netdev);
2116 if (err)
2117 return err;
2118 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2119 E1000_EITR_82574(vector);
2120 adapter->rx_ring->itr_val = adapter->itr;
2121 vector++;
2122
2123 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2124 snprintf(buf: adapter->tx_ring->name,
2125 size: sizeof(adapter->tx_ring->name) - 1,
2126 fmt: "%.14s-tx-0", netdev->name);
2127 else
2128 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2129 err = request_irq(irq: adapter->msix_entries[vector].vector,
2130 handler: e1000_intr_msix_tx, flags: 0, name: adapter->tx_ring->name,
2131 dev: netdev);
2132 if (err)
2133 return err;
2134 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2135 E1000_EITR_82574(vector);
2136 adapter->tx_ring->itr_val = adapter->itr;
2137 vector++;
2138
2139 err = request_irq(irq: adapter->msix_entries[vector].vector,
2140 handler: e1000_msix_other, flags: 0, name: netdev->name, dev: netdev);
2141 if (err)
2142 return err;
2143
2144 e1000_configure_msix(adapter);
2145
2146 return 0;
2147}
2148
2149/**
2150 * e1000_request_irq - initialize interrupts
2151 * @adapter: board private structure
2152 *
2153 * Attempts to configure interrupts using the best available
2154 * capabilities of the hardware and kernel.
2155 **/
2156static int e1000_request_irq(struct e1000_adapter *adapter)
2157{
2158 struct net_device *netdev = adapter->netdev;
2159 int err;
2160
2161 if (adapter->msix_entries) {
2162 err = e1000_request_msix(adapter);
2163 if (!err)
2164 return err;
2165 /* fall back to MSI */
2166 e1000e_reset_interrupt_capability(adapter);
2167 adapter->int_mode = E1000E_INT_MODE_MSI;
2168 e1000e_set_interrupt_capability(adapter);
2169 }
2170 if (adapter->flags & FLAG_MSI_ENABLED) {
2171 err = request_irq(irq: adapter->pdev->irq, handler: e1000_intr_msi, flags: 0,
2172 name: netdev->name, dev: netdev);
2173 if (!err)
2174 return err;
2175
2176 /* fall back to legacy interrupt */
2177 e1000e_reset_interrupt_capability(adapter);
2178 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2179 }
2180
2181 err = request_irq(irq: adapter->pdev->irq, handler: e1000_intr, IRQF_SHARED,
2182 name: netdev->name, dev: netdev);
2183 if (err)
2184 e_err("Unable to allocate interrupt, Error: %d\n", err);
2185
2186 return err;
2187}
2188
2189static void e1000_free_irq(struct e1000_adapter *adapter)
2190{
2191 struct net_device *netdev = adapter->netdev;
2192
2193 if (adapter->msix_entries) {
2194 int vector = 0;
2195
2196 free_irq(adapter->msix_entries[vector].vector, netdev);
2197 vector++;
2198
2199 free_irq(adapter->msix_entries[vector].vector, netdev);
2200 vector++;
2201
2202 /* Other Causes interrupt vector */
2203 free_irq(adapter->msix_entries[vector].vector, netdev);
2204 return;
2205 }
2206
2207 free_irq(adapter->pdev->irq, netdev);
2208}
2209
2210/**
2211 * e1000_irq_disable - Mask off interrupt generation on the NIC
2212 * @adapter: board private structure
2213 **/
2214static void e1000_irq_disable(struct e1000_adapter *adapter)
2215{
2216 struct e1000_hw *hw = &adapter->hw;
2217
2218 ew32(IMC, ~0);
2219 if (adapter->msix_entries)
2220 ew32(EIAC_82574, 0);
2221 e1e_flush();
2222
2223 if (adapter->msix_entries) {
2224 int i;
2225
2226 for (i = 0; i < adapter->num_vectors; i++)
2227 synchronize_irq(irq: adapter->msix_entries[i].vector);
2228 } else {
2229 synchronize_irq(irq: adapter->pdev->irq);
2230 }
2231}
2232
2233/**
2234 * e1000_irq_enable - Enable default interrupt generation settings
2235 * @adapter: board private structure
2236 **/
2237static void e1000_irq_enable(struct e1000_adapter *adapter)
2238{
2239 struct e1000_hw *hw = &adapter->hw;
2240
2241 if (adapter->msix_entries) {
2242 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2243 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2244 IMS_OTHER_MASK);
2245 } else if (hw->mac.type >= e1000_pch_lpt) {
2246 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2247 } else {
2248 ew32(IMS, IMS_ENABLE_MASK);
2249 }
2250 e1e_flush();
2251}
2252
2253/**
2254 * e1000e_get_hw_control - get control of the h/w from f/w
2255 * @adapter: address of board private structure
2256 *
2257 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2258 * For ASF and Pass Through versions of f/w this means that
2259 * the driver is loaded. For AMT version (only with 82573)
2260 * of the f/w this means that the network i/f is open.
2261 **/
2262void e1000e_get_hw_control(struct e1000_adapter *adapter)
2263{
2264 struct e1000_hw *hw = &adapter->hw;
2265 u32 ctrl_ext;
2266 u32 swsm;
2267
2268 /* Let firmware know the driver has taken over */
2269 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2270 swsm = er32(SWSM);
2271 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2272 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2273 ctrl_ext = er32(CTRL_EXT);
2274 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2275 }
2276}
2277
2278/**
2279 * e1000e_release_hw_control - release control of the h/w to f/w
2280 * @adapter: address of board private structure
2281 *
2282 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2283 * For ASF and Pass Through versions of f/w this means that the
2284 * driver is no longer loaded. For AMT version (only with 82573) i
2285 * of the f/w this means that the network i/f is closed.
2286 *
2287 **/
2288void e1000e_release_hw_control(struct e1000_adapter *adapter)
2289{
2290 struct e1000_hw *hw = &adapter->hw;
2291 u32 ctrl_ext;
2292 u32 swsm;
2293
2294 /* Let firmware taken over control of h/w */
2295 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2296 swsm = er32(SWSM);
2297 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2298 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2299 ctrl_ext = er32(CTRL_EXT);
2300 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2301 }
2302}
2303
2304/**
2305 * e1000_alloc_ring_dma - allocate memory for a ring structure
2306 * @adapter: board private structure
2307 * @ring: ring struct for which to allocate dma
2308 **/
2309static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2310 struct e1000_ring *ring)
2311{
2312 struct pci_dev *pdev = adapter->pdev;
2313
2314 ring->desc = dma_alloc_coherent(dev: &pdev->dev, size: ring->size, dma_handle: &ring->dma,
2315 GFP_KERNEL);
2316 if (!ring->desc)
2317 return -ENOMEM;
2318
2319 return 0;
2320}
2321
2322/**
2323 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2324 * @tx_ring: Tx descriptor ring
2325 *
2326 * Return 0 on success, negative on failure
2327 **/
2328int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2329{
2330 struct e1000_adapter *adapter = tx_ring->adapter;
2331 int err = -ENOMEM, size;
2332
2333 size = sizeof(struct e1000_buffer) * tx_ring->count;
2334 tx_ring->buffer_info = vzalloc(size);
2335 if (!tx_ring->buffer_info)
2336 goto err;
2337
2338 /* round up to nearest 4K */
2339 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2340 tx_ring->size = ALIGN(tx_ring->size, 4096);
2341
2342 err = e1000_alloc_ring_dma(adapter, ring: tx_ring);
2343 if (err)
2344 goto err;
2345
2346 tx_ring->next_to_use = 0;
2347 tx_ring->next_to_clean = 0;
2348
2349 return 0;
2350err:
2351 vfree(addr: tx_ring->buffer_info);
2352 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2353 return err;
2354}
2355
2356/**
2357 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2358 * @rx_ring: Rx descriptor ring
2359 *
2360 * Returns 0 on success, negative on failure
2361 **/
2362int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2363{
2364 struct e1000_adapter *adapter = rx_ring->adapter;
2365 struct e1000_buffer *buffer_info;
2366 int i, size, desc_len, err = -ENOMEM;
2367
2368 size = sizeof(struct e1000_buffer) * rx_ring->count;
2369 rx_ring->buffer_info = vzalloc(size);
2370 if (!rx_ring->buffer_info)
2371 goto err;
2372
2373 for (i = 0; i < rx_ring->count; i++) {
2374 buffer_info = &rx_ring->buffer_info[i];
2375 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2376 size: sizeof(struct e1000_ps_page),
2377 GFP_KERNEL);
2378 if (!buffer_info->ps_pages)
2379 goto err_pages;
2380 }
2381
2382 desc_len = sizeof(union e1000_rx_desc_packet_split);
2383
2384 /* Round up to nearest 4K */
2385 rx_ring->size = rx_ring->count * desc_len;
2386 rx_ring->size = ALIGN(rx_ring->size, 4096);
2387
2388 err = e1000_alloc_ring_dma(adapter, ring: rx_ring);
2389 if (err)
2390 goto err_pages;
2391
2392 rx_ring->next_to_clean = 0;
2393 rx_ring->next_to_use = 0;
2394 rx_ring->rx_skb_top = NULL;
2395
2396 return 0;
2397
2398err_pages:
2399 for (i = 0; i < rx_ring->count; i++) {
2400 buffer_info = &rx_ring->buffer_info[i];
2401 kfree(objp: buffer_info->ps_pages);
2402 }
2403err:
2404 vfree(addr: rx_ring->buffer_info);
2405 e_err("Unable to allocate memory for the receive descriptor ring\n");
2406 return err;
2407}
2408
2409/**
2410 * e1000_clean_tx_ring - Free Tx Buffers
2411 * @tx_ring: Tx descriptor ring
2412 **/
2413static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2414{
2415 struct e1000_adapter *adapter = tx_ring->adapter;
2416 struct e1000_buffer *buffer_info;
2417 unsigned long size;
2418 unsigned int i;
2419
2420 for (i = 0; i < tx_ring->count; i++) {
2421 buffer_info = &tx_ring->buffer_info[i];
2422 e1000_put_txbuf(tx_ring, buffer_info, drop: false);
2423 }
2424
2425 netdev_reset_queue(dev_queue: adapter->netdev);
2426 size = sizeof(struct e1000_buffer) * tx_ring->count;
2427 memset(tx_ring->buffer_info, 0, size);
2428
2429 memset(tx_ring->desc, 0, tx_ring->size);
2430
2431 tx_ring->next_to_use = 0;
2432 tx_ring->next_to_clean = 0;
2433}
2434
2435/**
2436 * e1000e_free_tx_resources - Free Tx Resources per Queue
2437 * @tx_ring: Tx descriptor ring
2438 *
2439 * Free all transmit software resources
2440 **/
2441void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2442{
2443 struct e1000_adapter *adapter = tx_ring->adapter;
2444 struct pci_dev *pdev = adapter->pdev;
2445
2446 e1000_clean_tx_ring(tx_ring);
2447
2448 vfree(addr: tx_ring->buffer_info);
2449 tx_ring->buffer_info = NULL;
2450
2451 dma_free_coherent(dev: &pdev->dev, size: tx_ring->size, cpu_addr: tx_ring->desc,
2452 dma_handle: tx_ring->dma);
2453 tx_ring->desc = NULL;
2454}
2455
2456/**
2457 * e1000e_free_rx_resources - Free Rx Resources
2458 * @rx_ring: Rx descriptor ring
2459 *
2460 * Free all receive software resources
2461 **/
2462void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2463{
2464 struct e1000_adapter *adapter = rx_ring->adapter;
2465 struct pci_dev *pdev = adapter->pdev;
2466 int i;
2467
2468 e1000_clean_rx_ring(rx_ring);
2469
2470 for (i = 0; i < rx_ring->count; i++)
2471 kfree(objp: rx_ring->buffer_info[i].ps_pages);
2472
2473 vfree(addr: rx_ring->buffer_info);
2474 rx_ring->buffer_info = NULL;
2475
2476 dma_free_coherent(dev: &pdev->dev, size: rx_ring->size, cpu_addr: rx_ring->desc,
2477 dma_handle: rx_ring->dma);
2478 rx_ring->desc = NULL;
2479}
2480
2481/**
2482 * e1000_update_itr - update the dynamic ITR value based on statistics
2483 * @itr_setting: current adapter->itr
2484 * @packets: the number of packets during this measurement interval
2485 * @bytes: the number of bytes during this measurement interval
2486 *
2487 * Stores a new ITR value based on packets and byte
2488 * counts during the last interrupt. The advantage of per interrupt
2489 * computation is faster updates and more accurate ITR for the current
2490 * traffic pattern. Constants in this function were computed
2491 * based on theoretical maximum wire speed and thresholds were set based
2492 * on testing data as well as attempting to minimize response time
2493 * while increasing bulk throughput. This functionality is controlled
2494 * by the InterruptThrottleRate module parameter.
2495 **/
2496static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2497{
2498 unsigned int retval = itr_setting;
2499
2500 if (packets == 0)
2501 return itr_setting;
2502
2503 switch (itr_setting) {
2504 case lowest_latency:
2505 /* handle TSO and jumbo frames */
2506 if (bytes / packets > 8000)
2507 retval = bulk_latency;
2508 else if ((packets < 5) && (bytes > 512))
2509 retval = low_latency;
2510 break;
2511 case low_latency: /* 50 usec aka 20000 ints/s */
2512 if (bytes > 10000) {
2513 /* this if handles the TSO accounting */
2514 if (bytes / packets > 8000)
2515 retval = bulk_latency;
2516 else if ((packets < 10) || ((bytes / packets) > 1200))
2517 retval = bulk_latency;
2518 else if ((packets > 35))
2519 retval = lowest_latency;
2520 } else if (bytes / packets > 2000) {
2521 retval = bulk_latency;
2522 } else if (packets <= 2 && bytes < 512) {
2523 retval = lowest_latency;
2524 }
2525 break;
2526 case bulk_latency: /* 250 usec aka 4000 ints/s */
2527 if (bytes > 25000) {
2528 if (packets > 35)
2529 retval = low_latency;
2530 } else if (bytes < 6000) {
2531 retval = low_latency;
2532 }
2533 break;
2534 }
2535
2536 return retval;
2537}
2538
2539static void e1000_set_itr(struct e1000_adapter *adapter)
2540{
2541 u16 current_itr;
2542 u32 new_itr = adapter->itr;
2543
2544 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2545 if (adapter->link_speed != SPEED_1000) {
2546 new_itr = 4000;
2547 goto set_itr_now;
2548 }
2549
2550 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2551 new_itr = 0;
2552 goto set_itr_now;
2553 }
2554
2555 adapter->tx_itr = e1000_update_itr(itr_setting: adapter->tx_itr,
2556 packets: adapter->total_tx_packets,
2557 bytes: adapter->total_tx_bytes);
2558 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2559 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2560 adapter->tx_itr = low_latency;
2561
2562 adapter->rx_itr = e1000_update_itr(itr_setting: adapter->rx_itr,
2563 packets: adapter->total_rx_packets,
2564 bytes: adapter->total_rx_bytes);
2565 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2566 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2567 adapter->rx_itr = low_latency;
2568
2569 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2570
2571 /* counts and packets in update_itr are dependent on these numbers */
2572 switch (current_itr) {
2573 case lowest_latency:
2574 new_itr = 70000;
2575 break;
2576 case low_latency:
2577 new_itr = 20000; /* aka hwitr = ~200 */
2578 break;
2579 case bulk_latency:
2580 new_itr = 4000;
2581 break;
2582 default:
2583 break;
2584 }
2585
2586set_itr_now:
2587 if (new_itr != adapter->itr) {
2588 /* this attempts to bias the interrupt rate towards Bulk
2589 * by adding intermediate steps when interrupt rate is
2590 * increasing
2591 */
2592 new_itr = new_itr > adapter->itr ?
2593 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2594 adapter->itr = new_itr;
2595 adapter->rx_ring->itr_val = new_itr;
2596 if (adapter->msix_entries)
2597 adapter->rx_ring->set_itr = 1;
2598 else
2599 e1000e_write_itr(adapter, itr: new_itr);
2600 }
2601}
2602
2603/**
2604 * e1000e_write_itr - write the ITR value to the appropriate registers
2605 * @adapter: address of board private structure
2606 * @itr: new ITR value to program
2607 *
2608 * e1000e_write_itr determines if the adapter is in MSI-X mode
2609 * and, if so, writes the EITR registers with the ITR value.
2610 * Otherwise, it writes the ITR value into the ITR register.
2611 **/
2612void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2613{
2614 struct e1000_hw *hw = &adapter->hw;
2615 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2616
2617 if (adapter->msix_entries) {
2618 int vector;
2619
2620 for (vector = 0; vector < adapter->num_vectors; vector++)
2621 writel(val: new_itr, addr: hw->hw_addr + E1000_EITR_82574(vector));
2622 } else {
2623 ew32(ITR, new_itr);
2624 }
2625}
2626
2627/**
2628 * e1000_alloc_queues - Allocate memory for all rings
2629 * @adapter: board private structure to initialize
2630 **/
2631static int e1000_alloc_queues(struct e1000_adapter *adapter)
2632{
2633 int size = sizeof(struct e1000_ring);
2634
2635 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2636 if (!adapter->tx_ring)
2637 goto err;
2638 adapter->tx_ring->count = adapter->tx_ring_count;
2639 adapter->tx_ring->adapter = adapter;
2640
2641 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2642 if (!adapter->rx_ring)
2643 goto err;
2644 adapter->rx_ring->count = adapter->rx_ring_count;
2645 adapter->rx_ring->adapter = adapter;
2646
2647 return 0;
2648err:
2649 e_err("Unable to allocate memory for queues\n");
2650 kfree(objp: adapter->rx_ring);
2651 kfree(objp: adapter->tx_ring);
2652 return -ENOMEM;
2653}
2654
2655/**
2656 * e1000e_poll - NAPI Rx polling callback
2657 * @napi: struct associated with this polling callback
2658 * @budget: number of packets driver is allowed to process this poll
2659 **/
2660static int e1000e_poll(struct napi_struct *napi, int budget)
2661{
2662 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2663 napi);
2664 struct e1000_hw *hw = &adapter->hw;
2665 struct net_device *poll_dev = adapter->netdev;
2666 int tx_cleaned = 1, work_done = 0;
2667
2668 adapter = netdev_priv(dev: poll_dev);
2669
2670 if (!adapter->msix_entries ||
2671 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2672 tx_cleaned = e1000_clean_tx_irq(tx_ring: adapter->tx_ring);
2673
2674 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2675
2676 if (!tx_cleaned || work_done == budget)
2677 return budget;
2678
2679 /* Exit the polling mode, but don't re-enable interrupts if stack might
2680 * poll us due to busy-polling
2681 */
2682 if (likely(napi_complete_done(napi, work_done))) {
2683 if (adapter->itr_setting & 3)
2684 e1000_set_itr(adapter);
2685 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2686 if (adapter->msix_entries)
2687 ew32(IMS, adapter->rx_ring->ims_val);
2688 else
2689 e1000_irq_enable(adapter);
2690 }
2691 }
2692
2693 return work_done;
2694}
2695
2696static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2697 __always_unused __be16 proto, u16 vid)
2698{
2699 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
2700 struct e1000_hw *hw = &adapter->hw;
2701 u32 vfta, index;
2702
2703 /* don't update vlan cookie if already programmed */
2704 if ((adapter->hw.mng_cookie.status &
2705 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2706 (vid == adapter->mng_vlan_id))
2707 return 0;
2708
2709 /* add VID to filter table */
2710 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2711 index = (vid >> 5) & 0x7F;
2712 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2713 vfta |= BIT((vid & 0x1F));
2714 hw->mac.ops.write_vfta(hw, index, vfta);
2715 }
2716
2717 set_bit(nr: vid, addr: adapter->active_vlans);
2718
2719 return 0;
2720}
2721
2722static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2723 __always_unused __be16 proto, u16 vid)
2724{
2725 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
2726 struct e1000_hw *hw = &adapter->hw;
2727 u32 vfta, index;
2728
2729 if ((adapter->hw.mng_cookie.status &
2730 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2731 (vid == adapter->mng_vlan_id)) {
2732 /* release control to f/w */
2733 e1000e_release_hw_control(adapter);
2734 return 0;
2735 }
2736
2737 /* remove VID from filter table */
2738 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2739 index = (vid >> 5) & 0x7F;
2740 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2741 vfta &= ~BIT((vid & 0x1F));
2742 hw->mac.ops.write_vfta(hw, index, vfta);
2743 }
2744
2745 clear_bit(nr: vid, addr: adapter->active_vlans);
2746
2747 return 0;
2748}
2749
2750/**
2751 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2752 * @adapter: board private structure to initialize
2753 **/
2754static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2755{
2756 struct net_device *netdev = adapter->netdev;
2757 struct e1000_hw *hw = &adapter->hw;
2758 u32 rctl;
2759
2760 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2761 /* disable VLAN receive filtering */
2762 rctl = er32(RCTL);
2763 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2764 ew32(RCTL, rctl);
2765
2766 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2767 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2768 vid: adapter->mng_vlan_id);
2769 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2770 }
2771 }
2772}
2773
2774/**
2775 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2776 * @adapter: board private structure to initialize
2777 **/
2778static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2779{
2780 struct e1000_hw *hw = &adapter->hw;
2781 u32 rctl;
2782
2783 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2784 /* enable VLAN receive filtering */
2785 rctl = er32(RCTL);
2786 rctl |= E1000_RCTL_VFE;
2787 rctl &= ~E1000_RCTL_CFIEN;
2788 ew32(RCTL, rctl);
2789 }
2790}
2791
2792/**
2793 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2794 * @adapter: board private structure to initialize
2795 **/
2796static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2797{
2798 struct e1000_hw *hw = &adapter->hw;
2799 u32 ctrl;
2800
2801 /* disable VLAN tag insert/strip */
2802 ctrl = er32(CTRL);
2803 ctrl &= ~E1000_CTRL_VME;
2804 ew32(CTRL, ctrl);
2805}
2806
2807/**
2808 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2809 * @adapter: board private structure to initialize
2810 **/
2811static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2812{
2813 struct e1000_hw *hw = &adapter->hw;
2814 u32 ctrl;
2815
2816 /* enable VLAN tag insert/strip */
2817 ctrl = er32(CTRL);
2818 ctrl |= E1000_CTRL_VME;
2819 ew32(CTRL, ctrl);
2820}
2821
2822static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2823{
2824 struct net_device *netdev = adapter->netdev;
2825 u16 vid = adapter->hw.mng_cookie.vlan_id;
2826 u16 old_vid = adapter->mng_vlan_id;
2827
2828 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2829 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2830 adapter->mng_vlan_id = vid;
2831 }
2832
2833 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2834 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), vid: old_vid);
2835}
2836
2837static void e1000_restore_vlan(struct e1000_adapter *adapter)
2838{
2839 u16 vid;
2840
2841 e1000_vlan_rx_add_vid(netdev: adapter->netdev, htons(ETH_P_8021Q), vid: 0);
2842
2843 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2844 e1000_vlan_rx_add_vid(netdev: adapter->netdev, htons(ETH_P_8021Q), vid);
2845}
2846
2847static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2848{
2849 struct e1000_hw *hw = &adapter->hw;
2850 u32 manc, manc2h, mdef, i, j;
2851
2852 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2853 return;
2854
2855 manc = er32(MANC);
2856
2857 /* enable receiving management packets to the host. this will probably
2858 * generate destination unreachable messages from the host OS, but
2859 * the packets will be handled on SMBUS
2860 */
2861 manc |= E1000_MANC_EN_MNG2HOST;
2862 manc2h = er32(MANC2H);
2863
2864 switch (hw->mac.type) {
2865 default:
2866 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2867 break;
2868 case e1000_82574:
2869 case e1000_82583:
2870 /* Check if IPMI pass-through decision filter already exists;
2871 * if so, enable it.
2872 */
2873 for (i = 0, j = 0; i < 8; i++) {
2874 mdef = er32(MDEF(i));
2875
2876 /* Ignore filters with anything other than IPMI ports */
2877 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2878 continue;
2879
2880 /* Enable this decision filter in MANC2H */
2881 if (mdef)
2882 manc2h |= BIT(i);
2883
2884 j |= mdef;
2885 }
2886
2887 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2888 break;
2889
2890 /* Create new decision filter in an empty filter */
2891 for (i = 0, j = 0; i < 8; i++)
2892 if (er32(MDEF(i)) == 0) {
2893 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2894 E1000_MDEF_PORT_664));
2895 manc2h |= BIT(1);
2896 j++;
2897 break;
2898 }
2899
2900 if (!j)
2901 e_warn("Unable to create IPMI pass-through filter\n");
2902 break;
2903 }
2904
2905 ew32(MANC2H, manc2h);
2906 ew32(MANC, manc);
2907}
2908
2909/**
2910 * e1000_configure_tx - Configure Transmit Unit after Reset
2911 * @adapter: board private structure
2912 *
2913 * Configure the Tx unit of the MAC after a reset.
2914 **/
2915static void e1000_configure_tx(struct e1000_adapter *adapter)
2916{
2917 struct e1000_hw *hw = &adapter->hw;
2918 struct e1000_ring *tx_ring = adapter->tx_ring;
2919 u64 tdba;
2920 u32 tdlen, tctl, tarc;
2921
2922 /* Setup the HW Tx Head and Tail descriptor pointers */
2923 tdba = tx_ring->dma;
2924 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2925 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2926 ew32(TDBAH(0), (tdba >> 32));
2927 ew32(TDLEN(0), tdlen);
2928 ew32(TDH(0), 0);
2929 ew32(TDT(0), 0);
2930 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2931 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2932
2933 writel(val: 0, addr: tx_ring->head);
2934 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2935 e1000e_update_tdt_wa(tx_ring, i: 0);
2936 else
2937 writel(val: 0, addr: tx_ring->tail);
2938
2939 /* Set the Tx Interrupt Delay register */
2940 ew32(TIDV, adapter->tx_int_delay);
2941 /* Tx irq moderation */
2942 ew32(TADV, adapter->tx_abs_int_delay);
2943
2944 if (adapter->flags2 & FLAG2_DMA_BURST) {
2945 u32 txdctl = er32(TXDCTL(0));
2946
2947 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2948 E1000_TXDCTL_WTHRESH);
2949 /* set up some performance related parameters to encourage the
2950 * hardware to use the bus more efficiently in bursts, depends
2951 * on the tx_int_delay to be enabled,
2952 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2953 * hthresh = 1 ==> prefetch when one or more available
2954 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2955 * BEWARE: this seems to work but should be considered first if
2956 * there are Tx hangs or other Tx related bugs
2957 */
2958 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2959 ew32(TXDCTL(0), txdctl);
2960 }
2961 /* erratum work around: set txdctl the same for both queues */
2962 ew32(TXDCTL(1), er32(TXDCTL(0)));
2963
2964 /* Program the Transmit Control Register */
2965 tctl = er32(TCTL);
2966 tctl &= ~E1000_TCTL_CT;
2967 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2968 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2969
2970 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2971 tarc = er32(TARC(0));
2972 /* set the speed mode bit, we'll clear it if we're not at
2973 * gigabit link later
2974 */
2975#define SPEED_MODE_BIT BIT(21)
2976 tarc |= SPEED_MODE_BIT;
2977 ew32(TARC(0), tarc);
2978 }
2979
2980 /* errata: program both queues to unweighted RR */
2981 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2982 tarc = er32(TARC(0));
2983 tarc |= 1;
2984 ew32(TARC(0), tarc);
2985 tarc = er32(TARC(1));
2986 tarc |= 1;
2987 ew32(TARC(1), tarc);
2988 }
2989
2990 /* Setup Transmit Descriptor Settings for eop descriptor */
2991 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2992
2993 /* only set IDE if we are delaying interrupts using the timers */
2994 if (adapter->tx_int_delay)
2995 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2996
2997 /* enable Report Status bit */
2998 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2999
3000 ew32(TCTL, tctl);
3001
3002 hw->mac.ops.config_collision_dist(hw);
3003
3004 /* SPT and KBL Si errata workaround to avoid data corruption */
3005 if (hw->mac.type == e1000_pch_spt) {
3006 u32 reg_val;
3007
3008 reg_val = er32(IOSFPC);
3009 reg_val |= E1000_RCTL_RDMTS_HEX;
3010 ew32(IOSFPC, reg_val);
3011
3012 reg_val = er32(TARC(0));
3013 /* SPT and KBL Si errata workaround to avoid Tx hang.
3014 * Dropping the number of outstanding requests from
3015 * 3 to 2 in order to avoid a buffer overrun.
3016 */
3017 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3018 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3019 ew32(TARC(0), reg_val);
3020 }
3021}
3022
3023#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3024 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3025
3026/**
3027 * e1000_setup_rctl - configure the receive control registers
3028 * @adapter: Board private structure
3029 **/
3030static void e1000_setup_rctl(struct e1000_adapter *adapter)
3031{
3032 struct e1000_hw *hw = &adapter->hw;
3033 u32 rctl, rfctl;
3034 u32 pages = 0;
3035
3036 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3037 * If jumbo frames not set, program related MAC/PHY registers
3038 * to h/w defaults
3039 */
3040 if (hw->mac.type >= e1000_pch2lan) {
3041 s32 ret_val;
3042
3043 if (adapter->netdev->mtu > ETH_DATA_LEN)
3044 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, enable: true);
3045 else
3046 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, enable: false);
3047
3048 if (ret_val)
3049 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3050 }
3051
3052 /* Program MC offset vector base */
3053 rctl = er32(RCTL);
3054 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3055 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3056 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3057 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3058
3059 /* Do not Store bad packets */
3060 rctl &= ~E1000_RCTL_SBP;
3061
3062 /* Enable Long Packet receive */
3063 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3064 rctl &= ~E1000_RCTL_LPE;
3065 else
3066 rctl |= E1000_RCTL_LPE;
3067
3068 /* Some systems expect that the CRC is included in SMBUS traffic. The
3069 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3070 * host memory when this is enabled
3071 */
3072 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3073 rctl |= E1000_RCTL_SECRC;
3074
3075 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3076 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3077 u16 phy_data;
3078
3079 e1e_rphy(hw, PHY_REG(770, 26), data: &phy_data);
3080 phy_data &= 0xfff8;
3081 phy_data |= BIT(2);
3082 e1e_wphy(hw, PHY_REG(770, 26), data: phy_data);
3083
3084 e1e_rphy(hw, offset: 22, data: &phy_data);
3085 phy_data &= 0x0fff;
3086 phy_data |= BIT(14);
3087 e1e_wphy(hw, offset: 0x10, data: 0x2823);
3088 e1e_wphy(hw, offset: 0x11, data: 0x0003);
3089 e1e_wphy(hw, offset: 22, data: phy_data);
3090 }
3091
3092 /* Setup buffer sizes */
3093 rctl &= ~E1000_RCTL_SZ_4096;
3094 rctl |= E1000_RCTL_BSEX;
3095 switch (adapter->rx_buffer_len) {
3096 case 2048:
3097 default:
3098 rctl |= E1000_RCTL_SZ_2048;
3099 rctl &= ~E1000_RCTL_BSEX;
3100 break;
3101 case 4096:
3102 rctl |= E1000_RCTL_SZ_4096;
3103 break;
3104 case 8192:
3105 rctl |= E1000_RCTL_SZ_8192;
3106 break;
3107 case 16384:
3108 rctl |= E1000_RCTL_SZ_16384;
3109 break;
3110 }
3111
3112 /* Enable Extended Status in all Receive Descriptors */
3113 rfctl = er32(RFCTL);
3114 rfctl |= E1000_RFCTL_EXTEN;
3115 ew32(RFCTL, rfctl);
3116
3117 /* 82571 and greater support packet-split where the protocol
3118 * header is placed in skb->data and the packet data is
3119 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3120 * In the case of a non-split, skb->data is linearly filled,
3121 * followed by the page buffers. Therefore, skb->data is
3122 * sized to hold the largest protocol header.
3123 *
3124 * allocations using alloc_page take too long for regular MTU
3125 * so only enable packet split for jumbo frames
3126 *
3127 * Using pages when the page size is greater than 16k wastes
3128 * a lot of memory, since we allocate 3 pages at all times
3129 * per packet.
3130 */
3131 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3132 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3133 adapter->rx_ps_pages = pages;
3134 else
3135 adapter->rx_ps_pages = 0;
3136
3137 if (adapter->rx_ps_pages) {
3138 u32 psrctl = 0;
3139
3140 /* Enable Packet split descriptors */
3141 rctl |= E1000_RCTL_DTYP_PS;
3142
3143 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3144
3145 switch (adapter->rx_ps_pages) {
3146 case 3:
3147 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3148 fallthrough;
3149 case 2:
3150 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3151 fallthrough;
3152 case 1:
3153 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3154 break;
3155 }
3156
3157 ew32(PSRCTL, psrctl);
3158 }
3159
3160 /* This is useful for sniffing bad packets. */
3161 if (adapter->netdev->features & NETIF_F_RXALL) {
3162 /* UPE and MPE will be handled by normal PROMISC logic
3163 * in e1000e_set_rx_mode
3164 */
3165 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3166 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3167 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3168
3169 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3170 E1000_RCTL_DPF | /* Allow filtered pause */
3171 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3172 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3173 * and that breaks VLANs.
3174 */
3175 }
3176
3177 ew32(RCTL, rctl);
3178 /* just started the receive unit, no need to restart */
3179 adapter->flags &= ~FLAG_RESTART_NOW;
3180}
3181
3182/**
3183 * e1000_configure_rx - Configure Receive Unit after Reset
3184 * @adapter: board private structure
3185 *
3186 * Configure the Rx unit of the MAC after a reset.
3187 **/
3188static void e1000_configure_rx(struct e1000_adapter *adapter)
3189{
3190 struct e1000_hw *hw = &adapter->hw;
3191 struct e1000_ring *rx_ring = adapter->rx_ring;
3192 u64 rdba;
3193 u32 rdlen, rctl, rxcsum, ctrl_ext;
3194
3195 if (adapter->rx_ps_pages) {
3196 /* this is a 32 byte descriptor */
3197 rdlen = rx_ring->count *
3198 sizeof(union e1000_rx_desc_packet_split);
3199 adapter->clean_rx = e1000_clean_rx_irq_ps;
3200 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3201 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3202 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3203 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3204 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3205 } else {
3206 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3207 adapter->clean_rx = e1000_clean_rx_irq;
3208 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3209 }
3210
3211 /* disable receives while setting up the descriptors */
3212 rctl = er32(RCTL);
3213 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3214 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3215 e1e_flush();
3216 usleep_range(min: 10000, max: 11000);
3217
3218 if (adapter->flags2 & FLAG2_DMA_BURST) {
3219 /* set the writeback threshold (only takes effect if the RDTR
3220 * is set). set GRAN=1 and write back up to 0x4 worth, and
3221 * enable prefetching of 0x20 Rx descriptors
3222 * granularity = 01
3223 * wthresh = 04,
3224 * hthresh = 04,
3225 * pthresh = 0x20
3226 */
3227 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3228 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3229 }
3230
3231 /* set the Receive Delay Timer Register */
3232 ew32(RDTR, adapter->rx_int_delay);
3233
3234 /* irq moderation */
3235 ew32(RADV, adapter->rx_abs_int_delay);
3236 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3237 e1000e_write_itr(adapter, itr: adapter->itr);
3238
3239 ctrl_ext = er32(CTRL_EXT);
3240 /* Auto-Mask interrupts upon ICR access */
3241 ctrl_ext |= E1000_CTRL_EXT_IAME;
3242 ew32(IAM, 0xffffffff);
3243 ew32(CTRL_EXT, ctrl_ext);
3244 e1e_flush();
3245
3246 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3247 * the Base and Length of the Rx Descriptor Ring
3248 */
3249 rdba = rx_ring->dma;
3250 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3251 ew32(RDBAH(0), (rdba >> 32));
3252 ew32(RDLEN(0), rdlen);
3253 ew32(RDH(0), 0);
3254 ew32(RDT(0), 0);
3255 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3256 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3257
3258 writel(val: 0, addr: rx_ring->head);
3259 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3260 e1000e_update_rdt_wa(rx_ring, i: 0);
3261 else
3262 writel(val: 0, addr: rx_ring->tail);
3263
3264 /* Enable Receive Checksum Offload for TCP and UDP */
3265 rxcsum = er32(RXCSUM);
3266 if (adapter->netdev->features & NETIF_F_RXCSUM)
3267 rxcsum |= E1000_RXCSUM_TUOFL;
3268 else
3269 rxcsum &= ~E1000_RXCSUM_TUOFL;
3270 ew32(RXCSUM, rxcsum);
3271
3272 /* With jumbo frames, excessive C-state transition latencies result
3273 * in dropped transactions.
3274 */
3275 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3276 u32 lat =
3277 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3278 adapter->max_frame_size) * 8 / 1000;
3279
3280 if (adapter->flags & FLAG_IS_ICH) {
3281 u32 rxdctl = er32(RXDCTL(0));
3282
3283 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3284 }
3285
3286 dev_info(&adapter->pdev->dev,
3287 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3288 cpu_latency_qos_update_request(req: &adapter->pm_qos_req, new_value: lat);
3289 } else {
3290 cpu_latency_qos_update_request(req: &adapter->pm_qos_req,
3291 PM_QOS_DEFAULT_VALUE);
3292 }
3293
3294 /* Enable Receives */
3295 ew32(RCTL, rctl);
3296}
3297
3298/**
3299 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3300 * @netdev: network interface device structure
3301 *
3302 * Writes multicast address list to the MTA hash table.
3303 * Returns: -ENOMEM on failure
3304 * 0 on no addresses written
3305 * X on writing X addresses to MTA
3306 */
3307static int e1000e_write_mc_addr_list(struct net_device *netdev)
3308{
3309 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
3310 struct e1000_hw *hw = &adapter->hw;
3311 struct netdev_hw_addr *ha;
3312 u8 *mta_list;
3313 int i;
3314
3315 if (netdev_mc_empty(netdev)) {
3316 /* nothing to program, so clear mc list */
3317 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3318 return 0;
3319 }
3320
3321 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3322 if (!mta_list)
3323 return -ENOMEM;
3324
3325 /* update_mc_addr_list expects a packed array of only addresses. */
3326 i = 0;
3327 netdev_for_each_mc_addr(ha, netdev)
3328 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3329
3330 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3331 kfree(objp: mta_list);
3332
3333 return netdev_mc_count(netdev);
3334}
3335
3336/**
3337 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3338 * @netdev: network interface device structure
3339 *
3340 * Writes unicast address list to the RAR table.
3341 * Returns: -ENOMEM on failure/insufficient address space
3342 * 0 on no addresses written
3343 * X on writing X addresses to the RAR table
3344 **/
3345static int e1000e_write_uc_addr_list(struct net_device *netdev)
3346{
3347 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
3348 struct e1000_hw *hw = &adapter->hw;
3349 unsigned int rar_entries;
3350 int count = 0;
3351
3352 rar_entries = hw->mac.ops.rar_get_count(hw);
3353
3354 /* save a rar entry for our hardware address */
3355 rar_entries--;
3356
3357 /* save a rar entry for the LAA workaround */
3358 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3359 rar_entries--;
3360
3361 /* return ENOMEM indicating insufficient memory for addresses */
3362 if (netdev_uc_count(netdev) > rar_entries)
3363 return -ENOMEM;
3364
3365 if (!netdev_uc_empty(netdev) && rar_entries) {
3366 struct netdev_hw_addr *ha;
3367
3368 /* write the addresses in reverse order to avoid write
3369 * combining
3370 */
3371 netdev_for_each_uc_addr(ha, netdev) {
3372 int ret_val;
3373
3374 if (!rar_entries)
3375 break;
3376 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3377 if (ret_val < 0)
3378 return -ENOMEM;
3379 count++;
3380 }
3381 }
3382
3383 /* zero out the remaining RAR entries not used above */
3384 for (; rar_entries > 0; rar_entries--) {
3385 ew32(RAH(rar_entries), 0);
3386 ew32(RAL(rar_entries), 0);
3387 }
3388 e1e_flush();
3389
3390 return count;
3391}
3392
3393/**
3394 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3395 * @netdev: network interface device structure
3396 *
3397 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3398 * address list or the network interface flags are updated. This routine is
3399 * responsible for configuring the hardware for proper unicast, multicast,
3400 * promiscuous mode, and all-multi behavior.
3401 **/
3402static void e1000e_set_rx_mode(struct net_device *netdev)
3403{
3404 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
3405 struct e1000_hw *hw = &adapter->hw;
3406 u32 rctl;
3407
3408 if (pm_runtime_suspended(dev: netdev->dev.parent))
3409 return;
3410
3411 /* Check for Promiscuous and All Multicast modes */
3412 rctl = er32(RCTL);
3413
3414 /* clear the affected bits */
3415 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3416
3417 if (netdev->flags & IFF_PROMISC) {
3418 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3419 /* Do not hardware filter VLANs in promisc mode */
3420 e1000e_vlan_filter_disable(adapter);
3421 } else {
3422 int count;
3423
3424 if (netdev->flags & IFF_ALLMULTI) {
3425 rctl |= E1000_RCTL_MPE;
3426 } else {
3427 /* Write addresses to the MTA, if the attempt fails
3428 * then we should just turn on promiscuous mode so
3429 * that we can at least receive multicast traffic
3430 */
3431 count = e1000e_write_mc_addr_list(netdev);
3432 if (count < 0)
3433 rctl |= E1000_RCTL_MPE;
3434 }
3435 e1000e_vlan_filter_enable(adapter);
3436 /* Write addresses to available RAR registers, if there is not
3437 * sufficient space to store all the addresses then enable
3438 * unicast promiscuous mode
3439 */
3440 count = e1000e_write_uc_addr_list(netdev);
3441 if (count < 0)
3442 rctl |= E1000_RCTL_UPE;
3443 }
3444
3445 ew32(RCTL, rctl);
3446
3447 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3448 e1000e_vlan_strip_enable(adapter);
3449 else
3450 e1000e_vlan_strip_disable(adapter);
3451}
3452
3453static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3454{
3455 struct e1000_hw *hw = &adapter->hw;
3456 u32 mrqc, rxcsum;
3457 u32 rss_key[10];
3458 int i;
3459
3460 netdev_rss_key_fill(buffer: rss_key, len: sizeof(rss_key));
3461 for (i = 0; i < 10; i++)
3462 ew32(RSSRK(i), rss_key[i]);
3463
3464 /* Direct all traffic to queue 0 */
3465 for (i = 0; i < 32; i++)
3466 ew32(RETA(i), 0);
3467
3468 /* Disable raw packet checksumming so that RSS hash is placed in
3469 * descriptor on writeback.
3470 */
3471 rxcsum = er32(RXCSUM);
3472 rxcsum |= E1000_RXCSUM_PCSD;
3473
3474 ew32(RXCSUM, rxcsum);
3475
3476 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3477 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3478 E1000_MRQC_RSS_FIELD_IPV6 |
3479 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3480 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3481
3482 ew32(MRQC, mrqc);
3483}
3484
3485/**
3486 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3487 * @adapter: board private structure
3488 * @timinca: pointer to returned time increment attributes
3489 *
3490 * Get attributes for incrementing the System Time Register SYSTIML/H at
3491 * the default base frequency, and set the cyclecounter shift value.
3492 **/
3493s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3494{
3495 struct e1000_hw *hw = &adapter->hw;
3496 u32 incvalue, incperiod, shift;
3497
3498 /* Make sure clock is enabled on I217/I218/I219 before checking
3499 * the frequency
3500 */
3501 if ((hw->mac.type >= e1000_pch_lpt) &&
3502 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3503 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3504 u32 fextnvm7 = er32(FEXTNVM7);
3505
3506 if (!(fextnvm7 & BIT(0))) {
3507 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3508 e1e_flush();
3509 }
3510 }
3511
3512 switch (hw->mac.type) {
3513 case e1000_pch2lan:
3514 /* Stable 96MHz frequency */
3515 incperiod = INCPERIOD_96MHZ;
3516 incvalue = INCVALUE_96MHZ;
3517 shift = INCVALUE_SHIFT_96MHZ;
3518 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3519 break;
3520 case e1000_pch_lpt:
3521 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3522 /* Stable 96MHz frequency */
3523 incperiod = INCPERIOD_96MHZ;
3524 incvalue = INCVALUE_96MHZ;
3525 shift = INCVALUE_SHIFT_96MHZ;
3526 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3527 } else {
3528 /* Stable 25MHz frequency */
3529 incperiod = INCPERIOD_25MHZ;
3530 incvalue = INCVALUE_25MHZ;
3531 shift = INCVALUE_SHIFT_25MHZ;
3532 adapter->cc.shift = shift;
3533 }
3534 break;
3535 case e1000_pch_spt:
3536 /* Stable 24MHz frequency */
3537 incperiod = INCPERIOD_24MHZ;
3538 incvalue = INCVALUE_24MHZ;
3539 shift = INCVALUE_SHIFT_24MHZ;
3540 adapter->cc.shift = shift;
3541 break;
3542 case e1000_pch_cnp:
3543 case e1000_pch_tgp:
3544 case e1000_pch_adp:
3545 case e1000_pch_mtp:
3546 case e1000_pch_lnp:
3547 case e1000_pch_ptp:
3548 case e1000_pch_nvp:
3549 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3550 /* Stable 24MHz frequency */
3551 incperiod = INCPERIOD_24MHZ;
3552 incvalue = INCVALUE_24MHZ;
3553 shift = INCVALUE_SHIFT_24MHZ;
3554 adapter->cc.shift = shift;
3555 } else {
3556 /* Stable 38400KHz frequency */
3557 incperiod = INCPERIOD_38400KHZ;
3558 incvalue = INCVALUE_38400KHZ;
3559 shift = INCVALUE_SHIFT_38400KHZ;
3560 adapter->cc.shift = shift;
3561 }
3562 break;
3563 case e1000_82574:
3564 case e1000_82583:
3565 /* Stable 25MHz frequency */
3566 incperiod = INCPERIOD_25MHZ;
3567 incvalue = INCVALUE_25MHZ;
3568 shift = INCVALUE_SHIFT_25MHZ;
3569 adapter->cc.shift = shift;
3570 break;
3571 default:
3572 return -EINVAL;
3573 }
3574
3575 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3576 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3577
3578 return 0;
3579}
3580
3581/**
3582 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3583 * @adapter: board private structure
3584 * @config: timestamp configuration
3585 *
3586 * Outgoing time stamping can be enabled and disabled. Play nice and
3587 * disable it when requested, although it shouldn't cause any overhead
3588 * when no packet needs it. At most one packet in the queue may be
3589 * marked for time stamping, otherwise it would be impossible to tell
3590 * for sure to which packet the hardware time stamp belongs.
3591 *
3592 * Incoming time stamping has to be configured via the hardware filters.
3593 * Not all combinations are supported, in particular event type has to be
3594 * specified. Matching the kind of event packet is not supported, with the
3595 * exception of "all V2 events regardless of level 2 or 4".
3596 **/
3597static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3598 struct hwtstamp_config *config)
3599{
3600 struct e1000_hw *hw = &adapter->hw;
3601 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3602 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3603 u32 rxmtrl = 0;
3604 u16 rxudp = 0;
3605 bool is_l4 = false;
3606 bool is_l2 = false;
3607 u32 regval;
3608
3609 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3610 return -EINVAL;
3611
3612 switch (config->tx_type) {
3613 case HWTSTAMP_TX_OFF:
3614 tsync_tx_ctl = 0;
3615 break;
3616 case HWTSTAMP_TX_ON:
3617 break;
3618 default:
3619 return -ERANGE;
3620 }
3621
3622 switch (config->rx_filter) {
3623 case HWTSTAMP_FILTER_NONE:
3624 tsync_rx_ctl = 0;
3625 break;
3626 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3627 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3628 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3629 is_l4 = true;
3630 break;
3631 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3632 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3633 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3634 is_l4 = true;
3635 break;
3636 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3637 /* Also time stamps V2 L2 Path Delay Request/Response */
3638 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3639 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3640 is_l2 = true;
3641 break;
3642 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3643 /* Also time stamps V2 L2 Path Delay Request/Response. */
3644 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3645 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3646 is_l2 = true;
3647 break;
3648 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3649 /* Hardware cannot filter just V2 L4 Sync messages */
3650 fallthrough;
3651 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3652 /* Also time stamps V2 Path Delay Request/Response. */
3653 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3654 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3655 is_l2 = true;
3656 is_l4 = true;
3657 break;
3658 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3659 /* Hardware cannot filter just V2 L4 Delay Request messages */
3660 fallthrough;
3661 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3662 /* Also time stamps V2 Path Delay Request/Response. */
3663 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3664 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3665 is_l2 = true;
3666 is_l4 = true;
3667 break;
3668 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3669 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3670 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3671 fallthrough;
3672 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3673 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3674 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3675 is_l2 = true;
3676 is_l4 = true;
3677 break;
3678 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3679 /* For V1, the hardware can only filter Sync messages or
3680 * Delay Request messages but not both so fall-through to
3681 * time stamp all packets.
3682 */
3683 fallthrough;
3684 case HWTSTAMP_FILTER_NTP_ALL:
3685 case HWTSTAMP_FILTER_ALL:
3686 is_l2 = true;
3687 is_l4 = true;
3688 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3689 config->rx_filter = HWTSTAMP_FILTER_ALL;
3690 break;
3691 default:
3692 return -ERANGE;
3693 }
3694
3695 adapter->hwtstamp_config = *config;
3696
3697 /* enable/disable Tx h/w time stamping */
3698 regval = er32(TSYNCTXCTL);
3699 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3700 regval |= tsync_tx_ctl;
3701 ew32(TSYNCTXCTL, regval);
3702 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3703 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3704 e_err("Timesync Tx Control register not set as expected\n");
3705 return -EAGAIN;
3706 }
3707
3708 /* enable/disable Rx h/w time stamping */
3709 regval = er32(TSYNCRXCTL);
3710 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3711 regval |= tsync_rx_ctl;
3712 ew32(TSYNCRXCTL, regval);
3713 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3714 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3715 (regval & (E1000_TSYNCRXCTL_ENABLED |
3716 E1000_TSYNCRXCTL_TYPE_MASK))) {
3717 e_err("Timesync Rx Control register not set as expected\n");
3718 return -EAGAIN;
3719 }
3720
3721 /* L2: define ethertype filter for time stamped packets */
3722 if (is_l2)
3723 rxmtrl |= ETH_P_1588;
3724
3725 /* define which PTP packets get time stamped */
3726 ew32(RXMTRL, rxmtrl);
3727
3728 /* Filter by destination port */
3729 if (is_l4) {
3730 rxudp = PTP_EV_PORT;
3731 cpu_to_be16s(&rxudp);
3732 }
3733 ew32(RXUDP, rxudp);
3734
3735 e1e_flush();
3736
3737 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3738 er32(RXSTMPH);
3739 er32(TXSTMPH);
3740
3741 return 0;
3742}
3743
3744/**
3745 * e1000_configure - configure the hardware for Rx and Tx
3746 * @adapter: private board structure
3747 **/
3748static void e1000_configure(struct e1000_adapter *adapter)
3749{
3750 struct e1000_ring *rx_ring = adapter->rx_ring;
3751
3752 e1000e_set_rx_mode(netdev: adapter->netdev);
3753
3754 e1000_restore_vlan(adapter);
3755 e1000_init_manageability_pt(adapter);
3756
3757 e1000_configure_tx(adapter);
3758
3759 if (adapter->netdev->features & NETIF_F_RXHASH)
3760 e1000e_setup_rss_hash(adapter);
3761 e1000_setup_rctl(adapter);
3762 e1000_configure_rx(adapter);
3763 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(ring: rx_ring), GFP_KERNEL);
3764}
3765
3766/**
3767 * e1000e_power_up_phy - restore link in case the phy was powered down
3768 * @adapter: address of board private structure
3769 *
3770 * The phy may be powered down to save power and turn off link when the
3771 * driver is unloaded and wake on lan is not enabled (among others)
3772 * *** this routine MUST be followed by a call to e1000e_reset ***
3773 **/
3774void e1000e_power_up_phy(struct e1000_adapter *adapter)
3775{
3776 if (adapter->hw.phy.ops.power_up)
3777 adapter->hw.phy.ops.power_up(&adapter->hw);
3778
3779 adapter->hw.mac.ops.setup_link(&adapter->hw);
3780}
3781
3782/**
3783 * e1000_power_down_phy - Power down the PHY
3784 * @adapter: board private structure
3785 *
3786 * Power down the PHY so no link is implied when interface is down.
3787 * The PHY cannot be powered down if management or WoL is active.
3788 */
3789static void e1000_power_down_phy(struct e1000_adapter *adapter)
3790{
3791 if (adapter->hw.phy.ops.power_down)
3792 adapter->hw.phy.ops.power_down(&adapter->hw);
3793}
3794
3795/**
3796 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3797 * @adapter: board private structure
3798 *
3799 * We want to clear all pending descriptors from the TX ring.
3800 * zeroing happens when the HW reads the regs. We assign the ring itself as
3801 * the data of the next descriptor. We don't care about the data we are about
3802 * to reset the HW.
3803 */
3804static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3805{
3806 struct e1000_hw *hw = &adapter->hw;
3807 struct e1000_ring *tx_ring = adapter->tx_ring;
3808 struct e1000_tx_desc *tx_desc = NULL;
3809 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3810 u16 size = 512;
3811
3812 tctl = er32(TCTL);
3813 ew32(TCTL, tctl | E1000_TCTL_EN);
3814 tdt = er32(TDT(0));
3815 BUG_ON(tdt != tx_ring->next_to_use);
3816 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3817 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma);
3818
3819 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3820 tx_desc->upper.data = 0;
3821 /* flush descriptors to memory before notifying the HW */
3822 wmb();
3823 tx_ring->next_to_use++;
3824 if (tx_ring->next_to_use == tx_ring->count)
3825 tx_ring->next_to_use = 0;
3826 ew32(TDT(0), tx_ring->next_to_use);
3827 usleep_range(min: 200, max: 250);
3828}
3829
3830/**
3831 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3832 * @adapter: board private structure
3833 *
3834 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3835 */
3836static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3837{
3838 u32 rctl, rxdctl;
3839 struct e1000_hw *hw = &adapter->hw;
3840
3841 rctl = er32(RCTL);
3842 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3843 e1e_flush();
3844 usleep_range(min: 100, max: 150);
3845
3846 rxdctl = er32(RXDCTL(0));
3847 /* zero the lower 14 bits (prefetch and host thresholds) */
3848 rxdctl &= 0xffffc000;
3849
3850 /* update thresholds: prefetch threshold to 31, host threshold to 1
3851 * and make sure the granularity is "descriptors" and not "cache lines"
3852 */
3853 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3854
3855 ew32(RXDCTL(0), rxdctl);
3856 /* momentarily enable the RX ring for the changes to take effect */
3857 ew32(RCTL, rctl | E1000_RCTL_EN);
3858 e1e_flush();
3859 usleep_range(min: 100, max: 150);
3860 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3861}
3862
3863/**
3864 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3865 * @adapter: board private structure
3866 *
3867 * In i219, the descriptor rings must be emptied before resetting the HW
3868 * or before changing the device state to D3 during runtime (runtime PM).
3869 *
3870 * Failure to do this will cause the HW to enter a unit hang state which can
3871 * only be released by PCI reset on the device
3872 *
3873 */
3874
3875static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3876{
3877 u16 hang_state;
3878 u32 fext_nvm11, tdlen;
3879 struct e1000_hw *hw = &adapter->hw;
3880
3881 /* First, disable MULR fix in FEXTNVM11 */
3882 fext_nvm11 = er32(FEXTNVM11);
3883 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3884 ew32(FEXTNVM11, fext_nvm11);
3885 /* do nothing if we're not in faulty state, or if the queue is empty */
3886 tdlen = er32(TDLEN(0));
3887 pci_read_config_word(dev: adapter->pdev, PCICFG_DESC_RING_STATUS,
3888 val: &hang_state);
3889 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3890 return;
3891 e1000_flush_tx_ring(adapter);
3892 /* recheck, maybe the fault is caused by the rx ring */
3893 pci_read_config_word(dev: adapter->pdev, PCICFG_DESC_RING_STATUS,
3894 val: &hang_state);
3895 if (hang_state & FLUSH_DESC_REQUIRED)
3896 e1000_flush_rx_ring(adapter);
3897}
3898
3899/**
3900 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3901 * @adapter: board private structure
3902 *
3903 * When the MAC is reset, all hardware bits for timesync will be reset to the
3904 * default values. This function will restore the settings last in place.
3905 * Since the clock SYSTIME registers are reset, we will simply restore the
3906 * cyclecounter to the kernel real clock time.
3907 **/
3908static void e1000e_systim_reset(struct e1000_adapter *adapter)
3909{
3910 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3911 struct e1000_hw *hw = &adapter->hw;
3912 unsigned long flags;
3913 u32 timinca;
3914 s32 ret_val;
3915
3916 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3917 return;
3918
3919 if (info->adjfine) {
3920 /* restore the previous ptp frequency delta */
3921 ret_val = info->adjfine(info, adapter->ptp_delta);
3922 } else {
3923 /* set the default base frequency if no adjustment possible */
3924 ret_val = e1000e_get_base_timinca(adapter, timinca: &timinca);
3925 if (!ret_val)
3926 ew32(TIMINCA, timinca);
3927 }
3928
3929 if (ret_val) {
3930 dev_warn(&adapter->pdev->dev,
3931 "Failed to restore TIMINCA clock rate delta: %d\n",
3932 ret_val);
3933 return;
3934 }
3935
3936 /* reset the systim ns time counter */
3937 spin_lock_irqsave(&adapter->systim_lock, flags);
3938 timecounter_init(tc: &adapter->tc, cc: &adapter->cc,
3939 start_tstamp: ktime_to_ns(kt: ktime_get_real()));
3940 spin_unlock_irqrestore(lock: &adapter->systim_lock, flags);
3941
3942 /* restore the previous hwtstamp configuration settings */
3943 e1000e_config_hwtstamp(adapter, config: &adapter->hwtstamp_config);
3944}
3945
3946/**
3947 * e1000e_reset - bring the hardware into a known good state
3948 * @adapter: board private structure
3949 *
3950 * This function boots the hardware and enables some settings that
3951 * require a configuration cycle of the hardware - those cannot be
3952 * set/changed during runtime. After reset the device needs to be
3953 * properly configured for Rx, Tx etc.
3954 */
3955void e1000e_reset(struct e1000_adapter *adapter)
3956{
3957 struct e1000_mac_info *mac = &adapter->hw.mac;
3958 struct e1000_fc_info *fc = &adapter->hw.fc;
3959 struct e1000_hw *hw = &adapter->hw;
3960 u32 tx_space, min_tx_space, min_rx_space;
3961 u32 pba = adapter->pba;
3962 u16 hwm;
3963
3964 /* reset Packet Buffer Allocation to default */
3965 ew32(PBA, pba);
3966
3967 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3968 /* To maintain wire speed transmits, the Tx FIFO should be
3969 * large enough to accommodate two full transmit packets,
3970 * rounded up to the next 1KB and expressed in KB. Likewise,
3971 * the Rx FIFO should be large enough to accommodate at least
3972 * one full receive packet and is similarly rounded up and
3973 * expressed in KB.
3974 */
3975 pba = er32(PBA);
3976 /* upper 16 bits has Tx packet buffer allocation size in KB */
3977 tx_space = pba >> 16;
3978 /* lower 16 bits has Rx packet buffer allocation size in KB */
3979 pba &= 0xffff;
3980 /* the Tx fifo also stores 16 bytes of information about the Tx
3981 * but don't include ethernet FCS because hardware appends it
3982 */
3983 min_tx_space = (adapter->max_frame_size +
3984 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3985 min_tx_space = ALIGN(min_tx_space, 1024);
3986 min_tx_space >>= 10;
3987 /* software strips receive CRC, so leave room for it */
3988 min_rx_space = adapter->max_frame_size;
3989 min_rx_space = ALIGN(min_rx_space, 1024);
3990 min_rx_space >>= 10;
3991
3992 /* If current Tx allocation is less than the min Tx FIFO size,
3993 * and the min Tx FIFO size is less than the current Rx FIFO
3994 * allocation, take space away from current Rx allocation
3995 */
3996 if ((tx_space < min_tx_space) &&
3997 ((min_tx_space - tx_space) < pba)) {
3998 pba -= min_tx_space - tx_space;
3999
4000 /* if short on Rx space, Rx wins and must trump Tx
4001 * adjustment
4002 */
4003 if (pba < min_rx_space)
4004 pba = min_rx_space;
4005 }
4006
4007 ew32(PBA, pba);
4008 }
4009
4010 /* flow control settings
4011 *
4012 * The high water mark must be low enough to fit one full frame
4013 * (or the size used for early receive) above it in the Rx FIFO.
4014 * Set it to the lower of:
4015 * - 90% of the Rx FIFO size, and
4016 * - the full Rx FIFO size minus one full frame
4017 */
4018 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4019 fc->pause_time = 0xFFFF;
4020 else
4021 fc->pause_time = E1000_FC_PAUSE_TIME;
4022 fc->send_xon = true;
4023 fc->current_mode = fc->requested_mode;
4024
4025 switch (hw->mac.type) {
4026 case e1000_ich9lan:
4027 case e1000_ich10lan:
4028 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4029 pba = 14;
4030 ew32(PBA, pba);
4031 fc->high_water = 0x2800;
4032 fc->low_water = fc->high_water - 8;
4033 break;
4034 }
4035 fallthrough;
4036 default:
4037 hwm = min(((pba << 10) * 9 / 10),
4038 ((pba << 10) - adapter->max_frame_size));
4039
4040 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
4041 fc->low_water = fc->high_water - 8;
4042 break;
4043 case e1000_pchlan:
4044 /* Workaround PCH LOM adapter hangs with certain network
4045 * loads. If hangs persist, try disabling Tx flow control.
4046 */
4047 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4048 fc->high_water = 0x3500;
4049 fc->low_water = 0x1500;
4050 } else {
4051 fc->high_water = 0x5000;
4052 fc->low_water = 0x3000;
4053 }
4054 fc->refresh_time = 0x1000;
4055 break;
4056 case e1000_pch2lan:
4057 case e1000_pch_lpt:
4058 case e1000_pch_spt:
4059 case e1000_pch_cnp:
4060 case e1000_pch_tgp:
4061 case e1000_pch_adp:
4062 case e1000_pch_mtp:
4063 case e1000_pch_lnp:
4064 case e1000_pch_ptp:
4065 case e1000_pch_nvp:
4066 fc->refresh_time = 0xFFFF;
4067 fc->pause_time = 0xFFFF;
4068
4069 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4070 fc->high_water = 0x05C20;
4071 fc->low_water = 0x05048;
4072 break;
4073 }
4074
4075 pba = 14;
4076 ew32(PBA, pba);
4077 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4078 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4079 break;
4080 }
4081
4082 /* Alignment of Tx data is on an arbitrary byte boundary with the
4083 * maximum size per Tx descriptor limited only to the transmit
4084 * allocation of the packet buffer minus 96 bytes with an upper
4085 * limit of 24KB due to receive synchronization limitations.
4086 */
4087 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4088 24 << 10);
4089
4090 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4091 * fit in receive buffer.
4092 */
4093 if (adapter->itr_setting & 0x3) {
4094 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4095 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4096 dev_info(&adapter->pdev->dev,
4097 "Interrupt Throttle Rate off\n");
4098 adapter->flags2 |= FLAG2_DISABLE_AIM;
4099 e1000e_write_itr(adapter, itr: 0);
4100 }
4101 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4102 dev_info(&adapter->pdev->dev,
4103 "Interrupt Throttle Rate on\n");
4104 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4105 adapter->itr = 20000;
4106 e1000e_write_itr(adapter, itr: adapter->itr);
4107 }
4108 }
4109
4110 if (hw->mac.type >= e1000_pch_spt)
4111 e1000_flush_desc_rings(adapter);
4112 /* Allow time for pending master requests to run */
4113 mac->ops.reset_hw(hw);
4114
4115 /* For parts with AMT enabled, let the firmware know
4116 * that the network interface is in control
4117 */
4118 if (adapter->flags & FLAG_HAS_AMT)
4119 e1000e_get_hw_control(adapter);
4120
4121 ew32(WUC, 0);
4122
4123 if (mac->ops.init_hw(hw))
4124 e_err("Hardware Error\n");
4125
4126 e1000_update_mng_vlan(adapter);
4127
4128 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4129 ew32(VET, ETH_P_8021Q);
4130
4131 e1000e_reset_adaptive(hw);
4132
4133 /* restore systim and hwtstamp settings */
4134 e1000e_systim_reset(adapter);
4135
4136 /* Set EEE advertisement as appropriate */
4137 if (adapter->flags2 & FLAG2_HAS_EEE) {
4138 s32 ret_val;
4139 u16 adv_addr;
4140
4141 switch (hw->phy.type) {
4142 case e1000_phy_82579:
4143 adv_addr = I82579_EEE_ADVERTISEMENT;
4144 break;
4145 case e1000_phy_i217:
4146 adv_addr = I217_EEE_ADVERTISEMENT;
4147 break;
4148 default:
4149 dev_err(&adapter->pdev->dev,
4150 "Invalid PHY type setting EEE advertisement\n");
4151 return;
4152 }
4153
4154 ret_val = hw->phy.ops.acquire(hw);
4155 if (ret_val) {
4156 dev_err(&adapter->pdev->dev,
4157 "EEE advertisement - unable to acquire PHY\n");
4158 return;
4159 }
4160
4161 e1000_write_emi_reg_locked(hw, addr: adv_addr,
4162 data: hw->dev_spec.ich8lan.eee_disable ?
4163 0 : adapter->eee_advert);
4164
4165 hw->phy.ops.release(hw);
4166 }
4167
4168 if (!netif_running(dev: adapter->netdev) &&
4169 !test_bit(__E1000_TESTING, &adapter->state))
4170 e1000_power_down_phy(adapter);
4171
4172 e1000_get_phy_info(hw);
4173
4174 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4175 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4176 u16 phy_data = 0;
4177 /* speed up time to link by disabling smart power down, ignore
4178 * the return value of this function because there is nothing
4179 * different we would do if it failed
4180 */
4181 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, data: &phy_data);
4182 phy_data &= ~IGP02E1000_PM_SPD;
4183 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data: phy_data);
4184 }
4185 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4186 u32 reg;
4187
4188 /* Fextnvm7 @ 0xe4[2] = 1 */
4189 reg = er32(FEXTNVM7);
4190 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4191 ew32(FEXTNVM7, reg);
4192 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4193 reg = er32(FEXTNVM9);
4194 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4195 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4196 ew32(FEXTNVM9, reg);
4197 }
4198
4199}
4200
4201/**
4202 * e1000e_trigger_lsc - trigger an LSC interrupt
4203 * @adapter: board private structure
4204 *
4205 * Fire a link status change interrupt to start the watchdog.
4206 **/
4207static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4208{
4209 struct e1000_hw *hw = &adapter->hw;
4210
4211 if (adapter->msix_entries)
4212 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4213 else
4214 ew32(ICS, E1000_ICS_LSC);
4215}
4216
4217void e1000e_up(struct e1000_adapter *adapter)
4218{
4219 /* hardware has been reset, we need to reload some things */
4220 e1000_configure(adapter);
4221
4222 clear_bit(nr: __E1000_DOWN, addr: &adapter->state);
4223
4224 if (adapter->msix_entries)
4225 e1000_configure_msix(adapter);
4226 e1000_irq_enable(adapter);
4227
4228 /* Tx queue started by watchdog timer when link is up */
4229
4230 e1000e_trigger_lsc(adapter);
4231}
4232
4233static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4234{
4235 struct e1000_hw *hw = &adapter->hw;
4236
4237 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4238 return;
4239
4240 /* flush pending descriptor writebacks to memory */
4241 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4242 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4243
4244 /* execute the writes immediately */
4245 e1e_flush();
4246
4247 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4248 * write is successful
4249 */
4250 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4251 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4252
4253 /* execute the writes immediately */
4254 e1e_flush();
4255}
4256
4257static void e1000e_update_stats(struct e1000_adapter *adapter);
4258
4259/**
4260 * e1000e_down - quiesce the device and optionally reset the hardware
4261 * @adapter: board private structure
4262 * @reset: boolean flag to reset the hardware or not
4263 */
4264void e1000e_down(struct e1000_adapter *adapter, bool reset)
4265{
4266 struct net_device *netdev = adapter->netdev;
4267 struct e1000_hw *hw = &adapter->hw;
4268 u32 tctl, rctl;
4269
4270 /* signal that we're down so the interrupt handler does not
4271 * reschedule our watchdog timer
4272 */
4273 set_bit(nr: __E1000_DOWN, addr: &adapter->state);
4274
4275 netif_carrier_off(dev: netdev);
4276
4277 /* disable receives in the hardware */
4278 rctl = er32(RCTL);
4279 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4280 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4281 /* flush and sleep below */
4282
4283 netif_stop_queue(dev: netdev);
4284
4285 /* disable transmits in the hardware */
4286 tctl = er32(TCTL);
4287 tctl &= ~E1000_TCTL_EN;
4288 ew32(TCTL, tctl);
4289
4290 /* flush both disables and wait for them to finish */
4291 e1e_flush();
4292 usleep_range(min: 10000, max: 11000);
4293
4294 e1000_irq_disable(adapter);
4295
4296 napi_synchronize(n: &adapter->napi);
4297
4298 del_timer_sync(timer: &adapter->watchdog_timer);
4299 del_timer_sync(timer: &adapter->phy_info_timer);
4300
4301 spin_lock(lock: &adapter->stats64_lock);
4302 e1000e_update_stats(adapter);
4303 spin_unlock(lock: &adapter->stats64_lock);
4304
4305 e1000e_flush_descriptors(adapter);
4306
4307 adapter->link_speed = 0;
4308 adapter->link_duplex = 0;
4309
4310 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4311 if ((hw->mac.type >= e1000_pch2lan) &&
4312 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4313 e1000_lv_jumbo_workaround_ich8lan(hw, enable: false))
4314 e_dbg("failed to disable jumbo frame workaround mode\n");
4315
4316 if (!pci_channel_offline(pdev: adapter->pdev)) {
4317 if (reset)
4318 e1000e_reset(adapter);
4319 else if (hw->mac.type >= e1000_pch_spt)
4320 e1000_flush_desc_rings(adapter);
4321 }
4322 e1000_clean_tx_ring(tx_ring: adapter->tx_ring);
4323 e1000_clean_rx_ring(rx_ring: adapter->rx_ring);
4324}
4325
4326void e1000e_reinit_locked(struct e1000_adapter *adapter)
4327{
4328 might_sleep();
4329 while (test_and_set_bit(nr: __E1000_RESETTING, addr: &adapter->state))
4330 usleep_range(min: 1000, max: 1100);
4331 e1000e_down(adapter, reset: true);
4332 e1000e_up(adapter);
4333 clear_bit(nr: __E1000_RESETTING, addr: &adapter->state);
4334}
4335
4336/**
4337 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4338 * @hw: pointer to the HW structure
4339 * @systim: PHC time value read, sanitized and returned
4340 * @sts: structure to hold system time before and after reading SYSTIML,
4341 * may be NULL
4342 *
4343 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4344 * check to see that the time is incrementing at a reasonable
4345 * rate and is a multiple of incvalue.
4346 **/
4347static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4348 struct ptp_system_timestamp *sts)
4349{
4350 u64 time_delta, rem, temp;
4351 u64 systim_next;
4352 u32 incvalue;
4353 int i;
4354
4355 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4356 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4357 /* latch SYSTIMH on read of SYSTIML */
4358 ptp_read_system_prets(sts);
4359 systim_next = (u64)er32(SYSTIML);
4360 ptp_read_system_postts(sts);
4361 systim_next |= (u64)er32(SYSTIMH) << 32;
4362
4363 time_delta = systim_next - systim;
4364 temp = time_delta;
4365 /* VMWare users have seen incvalue of zero, don't div / 0 */
4366 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4367
4368 systim = systim_next;
4369
4370 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4371 break;
4372 }
4373
4374 return systim;
4375}
4376
4377/**
4378 * e1000e_read_systim - read SYSTIM register
4379 * @adapter: board private structure
4380 * @sts: structure which will contain system time before and after reading
4381 * SYSTIML, may be NULL
4382 **/
4383u64 e1000e_read_systim(struct e1000_adapter *adapter,
4384 struct ptp_system_timestamp *sts)
4385{
4386 struct e1000_hw *hw = &adapter->hw;
4387 u32 systimel, systimel_2, systimeh;
4388 u64 systim;
4389 /* SYSTIMH latching upon SYSTIML read does not work well.
4390 * This means that if SYSTIML overflows after we read it but before
4391 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4392 * will experience a huge non linear increment in the systime value
4393 * to fix that we test for overflow and if true, we re-read systime.
4394 */
4395 ptp_read_system_prets(sts);
4396 systimel = er32(SYSTIML);
4397 ptp_read_system_postts(sts);
4398 systimeh = er32(SYSTIMH);
4399 /* Is systimel is so large that overflow is possible? */
4400 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4401 ptp_read_system_prets(sts);
4402 systimel_2 = er32(SYSTIML);
4403 ptp_read_system_postts(sts);
4404 if (systimel > systimel_2) {
4405 /* There was an overflow, read again SYSTIMH, and use
4406 * systimel_2
4407 */
4408 systimeh = er32(SYSTIMH);
4409 systimel = systimel_2;
4410 }
4411 }
4412 systim = (u64)systimel;
4413 systim |= (u64)systimeh << 32;
4414
4415 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4416 systim = e1000e_sanitize_systim(hw, systim, sts);
4417
4418 return systim;
4419}
4420
4421/**
4422 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4423 * @cc: cyclecounter structure
4424 **/
4425static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4426{
4427 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4428 cc);
4429
4430 return e1000e_read_systim(adapter, NULL);
4431}
4432
4433/**
4434 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4435 * @adapter: board private structure to initialize
4436 *
4437 * e1000_sw_init initializes the Adapter private data structure.
4438 * Fields are initialized based on PCI device information and
4439 * OS network device settings (MTU size).
4440 **/
4441static int e1000_sw_init(struct e1000_adapter *adapter)
4442{
4443 struct net_device *netdev = adapter->netdev;
4444
4445 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4446 adapter->rx_ps_bsize0 = 128;
4447 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4448 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4449 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4450 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4451
4452 spin_lock_init(&adapter->stats64_lock);
4453
4454 e1000e_set_interrupt_capability(adapter);
4455
4456 if (e1000_alloc_queues(adapter))
4457 return -ENOMEM;
4458
4459 /* Setup hardware time stamping cyclecounter */
4460 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4461 adapter->cc.read = e1000e_cyclecounter_read;
4462 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4463 adapter->cc.mult = 1;
4464 /* cc.shift set in e1000e_get_base_tininca() */
4465
4466 spin_lock_init(&adapter->systim_lock);
4467 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4468 }
4469
4470 /* Explicitly disable IRQ since the NIC can be in any state. */
4471 e1000_irq_disable(adapter);
4472
4473 set_bit(nr: __E1000_DOWN, addr: &adapter->state);
4474 return 0;
4475}
4476
4477/**
4478 * e1000_intr_msi_test - Interrupt Handler
4479 * @irq: interrupt number
4480 * @data: pointer to a network interface device structure
4481 **/
4482static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4483{
4484 struct net_device *netdev = data;
4485 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
4486 struct e1000_hw *hw = &adapter->hw;
4487 u32 icr = er32(ICR);
4488
4489 e_dbg("icr is %08X\n", icr);
4490 if (icr & E1000_ICR_RXSEQ) {
4491 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4492 /* Force memory writes to complete before acknowledging the
4493 * interrupt is handled.
4494 */
4495 wmb();
4496 }
4497
4498 return IRQ_HANDLED;
4499}
4500
4501/**
4502 * e1000_test_msi_interrupt - Returns 0 for successful test
4503 * @adapter: board private struct
4504 *
4505 * code flow taken from tg3.c
4506 **/
4507static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4508{
4509 struct net_device *netdev = adapter->netdev;
4510 struct e1000_hw *hw = &adapter->hw;
4511 int err;
4512
4513 /* poll_enable hasn't been called yet, so don't need disable */
4514 /* clear any pending events */
4515 er32(ICR);
4516
4517 /* free the real vector and request a test handler */
4518 e1000_free_irq(adapter);
4519 e1000e_reset_interrupt_capability(adapter);
4520
4521 /* Assume that the test fails, if it succeeds then the test
4522 * MSI irq handler will unset this flag
4523 */
4524 adapter->flags |= FLAG_MSI_TEST_FAILED;
4525
4526 err = pci_enable_msi(dev: adapter->pdev);
4527 if (err)
4528 goto msi_test_failed;
4529
4530 err = request_irq(irq: adapter->pdev->irq, handler: e1000_intr_msi_test, flags: 0,
4531 name: netdev->name, dev: netdev);
4532 if (err) {
4533 pci_disable_msi(dev: adapter->pdev);
4534 goto msi_test_failed;
4535 }
4536
4537 /* Force memory writes to complete before enabling and firing an
4538 * interrupt.
4539 */
4540 wmb();
4541
4542 e1000_irq_enable(adapter);
4543
4544 /* fire an unusual interrupt on the test handler */
4545 ew32(ICS, E1000_ICS_RXSEQ);
4546 e1e_flush();
4547 msleep(msecs: 100);
4548
4549 e1000_irq_disable(adapter);
4550
4551 rmb(); /* read flags after interrupt has been fired */
4552
4553 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4554 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4555 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4556 } else {
4557 e_dbg("MSI interrupt test succeeded!\n");
4558 }
4559
4560 free_irq(adapter->pdev->irq, netdev);
4561 pci_disable_msi(dev: adapter->pdev);
4562
4563msi_test_failed:
4564 e1000e_set_interrupt_capability(adapter);
4565 return e1000_request_irq(adapter);
4566}
4567
4568/**
4569 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4570 * @adapter: board private struct
4571 *
4572 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4573 **/
4574static int e1000_test_msi(struct e1000_adapter *adapter)
4575{
4576 int err;
4577 u16 pci_cmd;
4578
4579 if (!(adapter->flags & FLAG_MSI_ENABLED))
4580 return 0;
4581
4582 /* disable SERR in case the MSI write causes a master abort */
4583 pci_read_config_word(dev: adapter->pdev, PCI_COMMAND, val: &pci_cmd);
4584 if (pci_cmd & PCI_COMMAND_SERR)
4585 pci_write_config_word(dev: adapter->pdev, PCI_COMMAND,
4586 val: pci_cmd & ~PCI_COMMAND_SERR);
4587
4588 err = e1000_test_msi_interrupt(adapter);
4589
4590 /* re-enable SERR */
4591 if (pci_cmd & PCI_COMMAND_SERR) {
4592 pci_read_config_word(dev: adapter->pdev, PCI_COMMAND, val: &pci_cmd);
4593 pci_cmd |= PCI_COMMAND_SERR;
4594 pci_write_config_word(dev: adapter->pdev, PCI_COMMAND, val: pci_cmd);
4595 }
4596
4597 return err;
4598}
4599
4600/**
4601 * e1000e_open - Called when a network interface is made active
4602 * @netdev: network interface device structure
4603 *
4604 * Returns 0 on success, negative value on failure
4605 *
4606 * The open entry point is called when a network interface is made
4607 * active by the system (IFF_UP). At this point all resources needed
4608 * for transmit and receive operations are allocated, the interrupt
4609 * handler is registered with the OS, the watchdog timer is started,
4610 * and the stack is notified that the interface is ready.
4611 **/
4612int e1000e_open(struct net_device *netdev)
4613{
4614 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
4615 struct e1000_hw *hw = &adapter->hw;
4616 struct pci_dev *pdev = adapter->pdev;
4617 int err;
4618
4619 /* disallow open during test */
4620 if (test_bit(__E1000_TESTING, &adapter->state))
4621 return -EBUSY;
4622
4623 pm_runtime_get_sync(dev: &pdev->dev);
4624
4625 netif_carrier_off(dev: netdev);
4626 netif_stop_queue(dev: netdev);
4627
4628 /* allocate transmit descriptors */
4629 err = e1000e_setup_tx_resources(tx_ring: adapter->tx_ring);
4630 if (err)
4631 goto err_setup_tx;
4632
4633 /* allocate receive descriptors */
4634 err = e1000e_setup_rx_resources(rx_ring: adapter->rx_ring);
4635 if (err)
4636 goto err_setup_rx;
4637
4638 /* If AMT is enabled, let the firmware know that the network
4639 * interface is now open and reset the part to a known state.
4640 */
4641 if (adapter->flags & FLAG_HAS_AMT) {
4642 e1000e_get_hw_control(adapter);
4643 e1000e_reset(adapter);
4644 }
4645
4646 e1000e_power_up_phy(adapter);
4647
4648 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4649 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4650 e1000_update_mng_vlan(adapter);
4651
4652 /* DMA latency requirement to workaround jumbo issue */
4653 cpu_latency_qos_add_request(req: &adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE);
4654
4655 /* before we allocate an interrupt, we must be ready to handle it.
4656 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4657 * as soon as we call pci_request_irq, so we have to setup our
4658 * clean_rx handler before we do so.
4659 */
4660 e1000_configure(adapter);
4661
4662 err = e1000_request_irq(adapter);
4663 if (err)
4664 goto err_req_irq;
4665
4666 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4667 * ignore e1000e MSI messages, which means we need to test our MSI
4668 * interrupt now
4669 */
4670 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4671 err = e1000_test_msi(adapter);
4672 if (err) {
4673 e_err("Interrupt allocation failed\n");
4674 goto err_req_irq;
4675 }
4676 }
4677
4678 /* From here on the code is the same as e1000e_up() */
4679 clear_bit(nr: __E1000_DOWN, addr: &adapter->state);
4680
4681 napi_enable(n: &adapter->napi);
4682
4683 e1000_irq_enable(adapter);
4684
4685 adapter->tx_hang_recheck = false;
4686
4687 hw->mac.get_link_status = true;
4688 pm_runtime_put(dev: &pdev->dev);
4689
4690 e1000e_trigger_lsc(adapter);
4691
4692 return 0;
4693
4694err_req_irq:
4695 cpu_latency_qos_remove_request(req: &adapter->pm_qos_req);
4696 e1000e_release_hw_control(adapter);
4697 e1000_power_down_phy(adapter);
4698 e1000e_free_rx_resources(rx_ring: adapter->rx_ring);
4699err_setup_rx:
4700 e1000e_free_tx_resources(tx_ring: adapter->tx_ring);
4701err_setup_tx:
4702 e1000e_reset(adapter);
4703 pm_runtime_put_sync(dev: &pdev->dev);
4704
4705 return err;
4706}
4707
4708/**
4709 * e1000e_close - Disables a network interface
4710 * @netdev: network interface device structure
4711 *
4712 * Returns 0, this is not allowed to fail
4713 *
4714 * The close entry point is called when an interface is de-activated
4715 * by the OS. The hardware is still under the drivers control, but
4716 * needs to be disabled. A global MAC reset is issued to stop the
4717 * hardware, and all transmit and receive resources are freed.
4718 **/
4719int e1000e_close(struct net_device *netdev)
4720{
4721 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
4722 struct pci_dev *pdev = adapter->pdev;
4723 int count = E1000_CHECK_RESET_COUNT;
4724
4725 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4726 usleep_range(min: 10000, max: 11000);
4727
4728 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4729
4730 pm_runtime_get_sync(dev: &pdev->dev);
4731
4732 if (netif_device_present(dev: netdev)) {
4733 e1000e_down(adapter, reset: true);
4734 e1000_free_irq(adapter);
4735
4736 /* Link status message must follow this format */
4737 netdev_info(dev: netdev, format: "NIC Link is Down\n");
4738 }
4739
4740 napi_disable(n: &adapter->napi);
4741
4742 e1000e_free_tx_resources(tx_ring: adapter->tx_ring);
4743 e1000e_free_rx_resources(rx_ring: adapter->rx_ring);
4744
4745 /* kill manageability vlan ID if supported, but not if a vlan with
4746 * the same ID is registered on the host OS (let 8021q kill it)
4747 */
4748 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4749 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4750 vid: adapter->mng_vlan_id);
4751
4752 /* If AMT is enabled, let the firmware know that the network
4753 * interface is now closed
4754 */
4755 if ((adapter->flags & FLAG_HAS_AMT) &&
4756 !test_bit(__E1000_TESTING, &adapter->state))
4757 e1000e_release_hw_control(adapter);
4758
4759 cpu_latency_qos_remove_request(req: &adapter->pm_qos_req);
4760
4761 pm_runtime_put_sync(dev: &pdev->dev);
4762
4763 return 0;
4764}
4765
4766/**
4767 * e1000_set_mac - Change the Ethernet Address of the NIC
4768 * @netdev: network interface device structure
4769 * @p: pointer to an address structure
4770 *
4771 * Returns 0 on success, negative on failure
4772 **/
4773static int e1000_set_mac(struct net_device *netdev, void *p)
4774{
4775 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
4776 struct e1000_hw *hw = &adapter->hw;
4777 struct sockaddr *addr = p;
4778
4779 if (!is_valid_ether_addr(addr: addr->sa_data))
4780 return -EADDRNOTAVAIL;
4781
4782 eth_hw_addr_set(dev: netdev, addr: addr->sa_data);
4783 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4784
4785 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4786
4787 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4788 /* activate the work around */
4789 e1000e_set_laa_state_82571(hw: &adapter->hw, state: 1);
4790
4791 /* Hold a copy of the LAA in RAR[14] This is done so that
4792 * between the time RAR[0] gets clobbered and the time it
4793 * gets fixed (in e1000_watchdog), the actual LAA is in one
4794 * of the RARs and no incoming packets directed to this port
4795 * are dropped. Eventually the LAA will be in RAR[0] and
4796 * RAR[14]
4797 */
4798 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4799 adapter->hw.mac.rar_entry_count - 1);
4800 }
4801
4802 return 0;
4803}
4804
4805/**
4806 * e1000e_update_phy_task - work thread to update phy
4807 * @work: pointer to our work struct
4808 *
4809 * this worker thread exists because we must acquire a
4810 * semaphore to read the phy, which we could msleep while
4811 * waiting for it, and we can't msleep in a timer.
4812 **/
4813static void e1000e_update_phy_task(struct work_struct *work)
4814{
4815 struct e1000_adapter *adapter = container_of(work,
4816 struct e1000_adapter,
4817 update_phy_task);
4818 struct e1000_hw *hw = &adapter->hw;
4819
4820 if (test_bit(__E1000_DOWN, &adapter->state))
4821 return;
4822
4823 e1000_get_phy_info(hw);
4824
4825 /* Enable EEE on 82579 after link up */
4826 if (hw->phy.type >= e1000_phy_82579)
4827 e1000_set_eee_pchlan(hw);
4828}
4829
4830/**
4831 * e1000_update_phy_info - timre call-back to update PHY info
4832 * @t: pointer to timer_list containing private info adapter
4833 *
4834 * Need to wait a few seconds after link up to get diagnostic information from
4835 * the phy
4836 **/
4837static void e1000_update_phy_info(struct timer_list *t)
4838{
4839 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4840
4841 if (test_bit(__E1000_DOWN, &adapter->state))
4842 return;
4843
4844 schedule_work(work: &adapter->update_phy_task);
4845}
4846
4847/**
4848 * e1000e_update_phy_stats - Update the PHY statistics counters
4849 * @adapter: board private structure
4850 *
4851 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4852 **/
4853static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4854{
4855 struct e1000_hw *hw = &adapter->hw;
4856 s32 ret_val;
4857 u16 phy_data;
4858
4859 ret_val = hw->phy.ops.acquire(hw);
4860 if (ret_val)
4861 return;
4862
4863 /* A page set is expensive so check if already on desired page.
4864 * If not, set to the page with the PHY status registers.
4865 */
4866 hw->phy.addr = 1;
4867 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4868 data: &phy_data);
4869 if (ret_val)
4870 goto release;
4871 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4872 ret_val = hw->phy.ops.set_page(hw,
4873 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4874 if (ret_val)
4875 goto release;
4876 }
4877
4878 /* Single Collision Count */
4879 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4880 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4881 if (!ret_val)
4882 adapter->stats.scc += phy_data;
4883
4884 /* Excessive Collision Count */
4885 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4886 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4887 if (!ret_val)
4888 adapter->stats.ecol += phy_data;
4889
4890 /* Multiple Collision Count */
4891 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4892 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4893 if (!ret_val)
4894 adapter->stats.mcc += phy_data;
4895
4896 /* Late Collision Count */
4897 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4898 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4899 if (!ret_val)
4900 adapter->stats.latecol += phy_data;
4901
4902 /* Collision Count - also used for adaptive IFS */
4903 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4904 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4905 if (!ret_val)
4906 hw->mac.collision_delta = phy_data;
4907
4908 /* Defer Count */
4909 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4910 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4911 if (!ret_val)
4912 adapter->stats.dc += phy_data;
4913
4914 /* Transmit with no CRS */
4915 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4916 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4917 if (!ret_val)
4918 adapter->stats.tncrs += phy_data;
4919
4920release:
4921 hw->phy.ops.release(hw);
4922}
4923
4924/**
4925 * e1000e_update_stats - Update the board statistics counters
4926 * @adapter: board private structure
4927 **/
4928static void e1000e_update_stats(struct e1000_adapter *adapter)
4929{
4930 struct net_device *netdev = adapter->netdev;
4931 struct e1000_hw *hw = &adapter->hw;
4932 struct pci_dev *pdev = adapter->pdev;
4933
4934 /* Prevent stats update while adapter is being reset, or if the pci
4935 * connection is down.
4936 */
4937 if (adapter->link_speed == 0)
4938 return;
4939 if (pci_channel_offline(pdev))
4940 return;
4941
4942 adapter->stats.crcerrs += er32(CRCERRS);
4943 adapter->stats.gprc += er32(GPRC);
4944 adapter->stats.gorc += er32(GORCL);
4945 er32(GORCH); /* Clear gorc */
4946 adapter->stats.bprc += er32(BPRC);
4947 adapter->stats.mprc += er32(MPRC);
4948 adapter->stats.roc += er32(ROC);
4949
4950 adapter->stats.mpc += er32(MPC);
4951
4952 /* Half-duplex statistics */
4953 if (adapter->link_duplex == HALF_DUPLEX) {
4954 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4955 e1000e_update_phy_stats(adapter);
4956 } else {
4957 adapter->stats.scc += er32(SCC);
4958 adapter->stats.ecol += er32(ECOL);
4959 adapter->stats.mcc += er32(MCC);
4960 adapter->stats.latecol += er32(LATECOL);
4961 adapter->stats.dc += er32(DC);
4962
4963 hw->mac.collision_delta = er32(COLC);
4964
4965 if ((hw->mac.type != e1000_82574) &&
4966 (hw->mac.type != e1000_82583))
4967 adapter->stats.tncrs += er32(TNCRS);
4968 }
4969 adapter->stats.colc += hw->mac.collision_delta;
4970 }
4971
4972 adapter->stats.xonrxc += er32(XONRXC);
4973 adapter->stats.xontxc += er32(XONTXC);
4974 adapter->stats.xoffrxc += er32(XOFFRXC);
4975 adapter->stats.xofftxc += er32(XOFFTXC);
4976 adapter->stats.gptc += er32(GPTC);
4977 adapter->stats.gotc += er32(GOTCL);
4978 er32(GOTCH); /* Clear gotc */
4979 adapter->stats.rnbc += er32(RNBC);
4980 adapter->stats.ruc += er32(RUC);
4981
4982 adapter->stats.mptc += er32(MPTC);
4983 adapter->stats.bptc += er32(BPTC);
4984
4985 /* used for adaptive IFS */
4986
4987 hw->mac.tx_packet_delta = er32(TPT);
4988 adapter->stats.tpt += hw->mac.tx_packet_delta;
4989
4990 adapter->stats.algnerrc += er32(ALGNERRC);
4991 adapter->stats.rxerrc += er32(RXERRC);
4992 adapter->stats.cexterr += er32(CEXTERR);
4993 adapter->stats.tsctc += er32(TSCTC);
4994 adapter->stats.tsctfc += er32(TSCTFC);
4995
4996 /* Fill out the OS statistics structure */
4997 netdev->stats.multicast = adapter->stats.mprc;
4998 netdev->stats.collisions = adapter->stats.colc;
4999
5000 /* Rx Errors */
5001
5002 /* RLEC on some newer hardware can be incorrect so build
5003 * our own version based on RUC and ROC
5004 */
5005 netdev->stats.rx_errors = adapter->stats.rxerrc +
5006 adapter->stats.crcerrs + adapter->stats.algnerrc +
5007 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5008 netdev->stats.rx_length_errors = adapter->stats.ruc +
5009 adapter->stats.roc;
5010 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5011 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
5012 netdev->stats.rx_missed_errors = adapter->stats.mpc;
5013
5014 /* Tx Errors */
5015 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5016 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5017 netdev->stats.tx_window_errors = adapter->stats.latecol;
5018 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5019
5020 /* Tx Dropped needs to be maintained elsewhere */
5021
5022 /* Management Stats */
5023 adapter->stats.mgptc += er32(MGTPTC);
5024 adapter->stats.mgprc += er32(MGTPRC);
5025 adapter->stats.mgpdc += er32(MGTPDC);
5026
5027 /* Correctable ECC Errors */
5028 if (hw->mac.type >= e1000_pch_lpt) {
5029 u32 pbeccsts = er32(PBECCSTS);
5030
5031 adapter->corr_errors +=
5032 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5033 adapter->uncorr_errors +=
5034 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
5035 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
5036 }
5037}
5038
5039/**
5040 * e1000_phy_read_status - Update the PHY register status snapshot
5041 * @adapter: board private structure
5042 **/
5043static void e1000_phy_read_status(struct e1000_adapter *adapter)
5044{
5045 struct e1000_hw *hw = &adapter->hw;
5046 struct e1000_phy_regs *phy = &adapter->phy_regs;
5047
5048 if (!pm_runtime_suspended(dev: (&adapter->pdev->dev)->parent) &&
5049 (er32(STATUS) & E1000_STATUS_LU) &&
5050 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5051 int ret_val;
5052
5053 ret_val = e1e_rphy(hw, MII_BMCR, data: &phy->bmcr);
5054 ret_val |= e1e_rphy(hw, MII_BMSR, data: &phy->bmsr);
5055 ret_val |= e1e_rphy(hw, MII_ADVERTISE, data: &phy->advertise);
5056 ret_val |= e1e_rphy(hw, MII_LPA, data: &phy->lpa);
5057 ret_val |= e1e_rphy(hw, MII_EXPANSION, data: &phy->expansion);
5058 ret_val |= e1e_rphy(hw, MII_CTRL1000, data: &phy->ctrl1000);
5059 ret_val |= e1e_rphy(hw, MII_STAT1000, data: &phy->stat1000);
5060 ret_val |= e1e_rphy(hw, MII_ESTATUS, data: &phy->estatus);
5061 if (ret_val)
5062 e_warn("Error reading PHY register\n");
5063 } else {
5064 /* Do not read PHY registers if link is not up
5065 * Set values to typical power-on defaults
5066 */
5067 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5068 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5069 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5070 BMSR_ERCAP);
5071 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5072 ADVERTISE_ALL | ADVERTISE_CSMA);
5073 phy->lpa = 0;
5074 phy->expansion = EXPANSION_ENABLENPAGE;
5075 phy->ctrl1000 = ADVERTISE_1000FULL;
5076 phy->stat1000 = 0;
5077 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5078 }
5079}
5080
5081static void e1000_print_link_info(struct e1000_adapter *adapter)
5082{
5083 struct e1000_hw *hw = &adapter->hw;
5084 u32 ctrl = er32(CTRL);
5085
5086 /* Link status message must follow this format for user tools */
5087 netdev_info(dev: adapter->netdev,
5088 format: "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5089 adapter->link_speed,
5090 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5091 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5092 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5093 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5094}
5095
5096static bool e1000e_has_link(struct e1000_adapter *adapter)
5097{
5098 struct e1000_hw *hw = &adapter->hw;
5099 bool link_active = false;
5100 s32 ret_val = 0;
5101
5102 /* get_link_status is set on LSC (link status) interrupt or
5103 * Rx sequence error interrupt. get_link_status will stay
5104 * true until the check_for_link establishes link
5105 * for copper adapters ONLY
5106 */
5107 switch (hw->phy.media_type) {
5108 case e1000_media_type_copper:
5109 if (hw->mac.get_link_status) {
5110 ret_val = hw->mac.ops.check_for_link(hw);
5111 link_active = !hw->mac.get_link_status;
5112 } else {
5113 link_active = true;
5114 }
5115 break;
5116 case e1000_media_type_fiber:
5117 ret_val = hw->mac.ops.check_for_link(hw);
5118 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5119 break;
5120 case e1000_media_type_internal_serdes:
5121 ret_val = hw->mac.ops.check_for_link(hw);
5122 link_active = hw->mac.serdes_has_link;
5123 break;
5124 default:
5125 case e1000_media_type_unknown:
5126 break;
5127 }
5128
5129 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5130 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5131 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5132 e_info("Gigabit has been disabled, downgrading speed\n");
5133 }
5134
5135 return link_active;
5136}
5137
5138static void e1000e_enable_receives(struct e1000_adapter *adapter)
5139{
5140 /* make sure the receive unit is started */
5141 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5142 (adapter->flags & FLAG_RESTART_NOW)) {
5143 struct e1000_hw *hw = &adapter->hw;
5144 u32 rctl = er32(RCTL);
5145
5146 ew32(RCTL, rctl | E1000_RCTL_EN);
5147 adapter->flags &= ~FLAG_RESTART_NOW;
5148 }
5149}
5150
5151static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5152{
5153 struct e1000_hw *hw = &adapter->hw;
5154
5155 /* With 82574 controllers, PHY needs to be checked periodically
5156 * for hung state and reset, if two calls return true
5157 */
5158 if (e1000_check_phy_82574(hw))
5159 adapter->phy_hang_count++;
5160 else
5161 adapter->phy_hang_count = 0;
5162
5163 if (adapter->phy_hang_count > 1) {
5164 adapter->phy_hang_count = 0;
5165 e_dbg("PHY appears hung - resetting\n");
5166 schedule_work(work: &adapter->reset_task);
5167 }
5168}
5169
5170/**
5171 * e1000_watchdog - Timer Call-back
5172 * @t: pointer to timer_list containing private info adapter
5173 **/
5174static void e1000_watchdog(struct timer_list *t)
5175{
5176 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5177
5178 /* Do the rest outside of interrupt context */
5179 schedule_work(work: &adapter->watchdog_task);
5180
5181 /* TODO: make this use queue_delayed_work() */
5182}
5183
5184static void e1000_watchdog_task(struct work_struct *work)
5185{
5186 struct e1000_adapter *adapter = container_of(work,
5187 struct e1000_adapter,
5188 watchdog_task);
5189 struct net_device *netdev = adapter->netdev;
5190 struct e1000_mac_info *mac = &adapter->hw.mac;
5191 struct e1000_phy_info *phy = &adapter->hw.phy;
5192 struct e1000_ring *tx_ring = adapter->tx_ring;
5193 u32 dmoff_exit_timeout = 100, tries = 0;
5194 struct e1000_hw *hw = &adapter->hw;
5195 u32 link, tctl, pcim_state;
5196
5197 if (test_bit(__E1000_DOWN, &adapter->state))
5198 return;
5199
5200 link = e1000e_has_link(adapter);
5201 if ((netif_carrier_ok(dev: netdev)) && link) {
5202 /* Cancel scheduled suspend requests. */
5203 pm_runtime_resume(dev: netdev->dev.parent);
5204
5205 e1000e_enable_receives(adapter);
5206 goto link_up;
5207 }
5208
5209 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5210 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5211 e1000_update_mng_vlan(adapter);
5212
5213 if (link) {
5214 if (!netif_carrier_ok(dev: netdev)) {
5215 bool txb2b = true;
5216
5217 /* Cancel scheduled suspend requests. */
5218 pm_runtime_resume(dev: netdev->dev.parent);
5219
5220 /* Checking if MAC is in DMoff state*/
5221 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
5222 pcim_state = er32(STATUS);
5223 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5224 if (tries++ == dmoff_exit_timeout) {
5225 e_dbg("Error in exiting dmoff\n");
5226 break;
5227 }
5228 usleep_range(min: 10000, max: 20000);
5229 pcim_state = er32(STATUS);
5230
5231 /* Checking if MAC exited DMoff state */
5232 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5233 e1000_phy_hw_reset(hw: &adapter->hw);
5234 }
5235 }
5236
5237 /* update snapshot of PHY registers on LSC */
5238 e1000_phy_read_status(adapter);
5239 mac->ops.get_link_up_info(&adapter->hw,
5240 &adapter->link_speed,
5241 &adapter->link_duplex);
5242 e1000_print_link_info(adapter);
5243
5244 /* check if SmartSpeed worked */
5245 e1000e_check_downshift(hw);
5246 if (phy->speed_downgraded)
5247 netdev_warn(dev: netdev,
5248 format: "Link Speed was downgraded by SmartSpeed\n");
5249
5250 /* On supported PHYs, check for duplex mismatch only
5251 * if link has autonegotiated at 10/100 half
5252 */
5253 if ((hw->phy.type == e1000_phy_igp_3 ||
5254 hw->phy.type == e1000_phy_bm) &&
5255 hw->mac.autoneg &&
5256 (adapter->link_speed == SPEED_10 ||
5257 adapter->link_speed == SPEED_100) &&
5258 (adapter->link_duplex == HALF_DUPLEX)) {
5259 u16 autoneg_exp;
5260
5261 e1e_rphy(hw, MII_EXPANSION, data: &autoneg_exp);
5262
5263 if (!(autoneg_exp & EXPANSION_NWAY))
5264 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5265 }
5266
5267 /* adjust timeout factor according to speed/duplex */
5268 adapter->tx_timeout_factor = 1;
5269 switch (adapter->link_speed) {
5270 case SPEED_10:
5271 txb2b = false;
5272 adapter->tx_timeout_factor = 16;
5273 break;
5274 case SPEED_100:
5275 txb2b = false;
5276 adapter->tx_timeout_factor = 10;
5277 break;
5278 }
5279
5280 /* workaround: re-program speed mode bit after
5281 * link-up event
5282 */
5283 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5284 !txb2b) {
5285 u32 tarc0;
5286
5287 tarc0 = er32(TARC(0));
5288 tarc0 &= ~SPEED_MODE_BIT;
5289 ew32(TARC(0), tarc0);
5290 }
5291
5292 /* enable transmits in the hardware, need to do this
5293 * after setting TARC(0)
5294 */
5295 tctl = er32(TCTL);
5296 tctl |= E1000_TCTL_EN;
5297 ew32(TCTL, tctl);
5298
5299 /* Perform any post-link-up configuration before
5300 * reporting link up.
5301 */
5302 if (phy->ops.cfg_on_link_up)
5303 phy->ops.cfg_on_link_up(hw);
5304
5305 netif_wake_queue(dev: netdev);
5306 netif_carrier_on(dev: netdev);
5307
5308 if (!test_bit(__E1000_DOWN, &adapter->state))
5309 mod_timer(timer: &adapter->phy_info_timer,
5310 expires: round_jiffies(j: jiffies + 2 * HZ));
5311 }
5312 } else {
5313 if (netif_carrier_ok(dev: netdev)) {
5314 adapter->link_speed = 0;
5315 adapter->link_duplex = 0;
5316 /* Link status message must follow this format */
5317 netdev_info(dev: netdev, format: "NIC Link is Down\n");
5318 netif_carrier_off(dev: netdev);
5319 netif_stop_queue(dev: netdev);
5320 if (!test_bit(__E1000_DOWN, &adapter->state))
5321 mod_timer(timer: &adapter->phy_info_timer,
5322 expires: round_jiffies(j: jiffies + 2 * HZ));
5323
5324 /* 8000ES2LAN requires a Rx packet buffer work-around
5325 * on link down event; reset the controller to flush
5326 * the Rx packet buffer.
5327 */
5328 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5329 adapter->flags |= FLAG_RESTART_NOW;
5330 else
5331 pm_schedule_suspend(dev: netdev->dev.parent,
5332 LINK_TIMEOUT);
5333 }
5334 }
5335
5336link_up:
5337 spin_lock(lock: &adapter->stats64_lock);
5338 e1000e_update_stats(adapter);
5339
5340 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5341 adapter->tpt_old = adapter->stats.tpt;
5342 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5343 adapter->colc_old = adapter->stats.colc;
5344
5345 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5346 adapter->gorc_old = adapter->stats.gorc;
5347 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5348 adapter->gotc_old = adapter->stats.gotc;
5349 spin_unlock(lock: &adapter->stats64_lock);
5350
5351 /* If the link is lost the controller stops DMA, but
5352 * if there is queued Tx work it cannot be done. So
5353 * reset the controller to flush the Tx packet buffers.
5354 */
5355 if (!netif_carrier_ok(dev: netdev) &&
5356 (e1000_desc_unused(ring: tx_ring) + 1 < tx_ring->count))
5357 adapter->flags |= FLAG_RESTART_NOW;
5358
5359 /* If reset is necessary, do it outside of interrupt context. */
5360 if (adapter->flags & FLAG_RESTART_NOW) {
5361 schedule_work(work: &adapter->reset_task);
5362 /* return immediately since reset is imminent */
5363 return;
5364 }
5365
5366 e1000e_update_adaptive(hw: &adapter->hw);
5367
5368 /* Simple mode for Interrupt Throttle Rate (ITR) */
5369 if (adapter->itr_setting == 4) {
5370 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5371 * Total asymmetrical Tx or Rx gets ITR=8000;
5372 * everyone else is between 2000-8000.
5373 */
5374 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5375 u32 dif = (adapter->gotc > adapter->gorc ?
5376 adapter->gotc - adapter->gorc :
5377 adapter->gorc - adapter->gotc) / 10000;
5378 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5379
5380 e1000e_write_itr(adapter, itr);
5381 }
5382
5383 /* Cause software interrupt to ensure Rx ring is cleaned */
5384 if (adapter->msix_entries)
5385 ew32(ICS, adapter->rx_ring->ims_val);
5386 else
5387 ew32(ICS, E1000_ICS_RXDMT0);
5388
5389 /* flush pending descriptors to memory before detecting Tx hang */
5390 e1000e_flush_descriptors(adapter);
5391
5392 /* Force detection of hung controller every watchdog period */
5393 adapter->detect_tx_hung = true;
5394
5395 /* With 82571 controllers, LAA may be overwritten due to controller
5396 * reset from the other port. Set the appropriate LAA in RAR[0]
5397 */
5398 if (e1000e_get_laa_state_82571(hw))
5399 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5400
5401 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5402 e1000e_check_82574_phy_workaround(adapter);
5403
5404 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5405 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5406 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5407 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5408 er32(RXSTMPH);
5409 adapter->rx_hwtstamp_cleared++;
5410 } else {
5411 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5412 }
5413 }
5414
5415 /* Reset the timer */
5416 if (!test_bit(__E1000_DOWN, &adapter->state))
5417 mod_timer(timer: &adapter->watchdog_timer,
5418 expires: round_jiffies(j: jiffies + 2 * HZ));
5419}
5420
5421#define E1000_TX_FLAGS_CSUM 0x00000001
5422#define E1000_TX_FLAGS_VLAN 0x00000002
5423#define E1000_TX_FLAGS_TSO 0x00000004
5424#define E1000_TX_FLAGS_IPV4 0x00000008
5425#define E1000_TX_FLAGS_NO_FCS 0x00000010
5426#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5427#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5428#define E1000_TX_FLAGS_VLAN_SHIFT 16
5429
5430static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5431 __be16 protocol)
5432{
5433 struct e1000_context_desc *context_desc;
5434 struct e1000_buffer *buffer_info;
5435 unsigned int i;
5436 u32 cmd_length = 0;
5437 u16 ipcse = 0, mss;
5438 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5439 int err;
5440
5441 if (!skb_is_gso(skb))
5442 return 0;
5443
5444 err = skb_cow_head(skb, headroom: 0);
5445 if (err < 0)
5446 return err;
5447
5448 hdr_len = skb_tcp_all_headers(skb);
5449 mss = skb_shinfo(skb)->gso_size;
5450 if (protocol == htons(ETH_P_IP)) {
5451 struct iphdr *iph = ip_hdr(skb);
5452 iph->tot_len = 0;
5453 iph->check = 0;
5454 tcp_hdr(skb)->check = ~csum_tcpudp_magic(saddr: iph->saddr, daddr: iph->daddr,
5455 len: 0, IPPROTO_TCP, sum: 0);
5456 cmd_length = E1000_TXD_CMD_IP;
5457 ipcse = skb_transport_offset(skb) - 1;
5458 } else if (skb_is_gso_v6(skb)) {
5459 tcp_v6_gso_csum_prep(skb);
5460 ipcse = 0;
5461 }
5462 ipcss = skb_network_offset(skb);
5463 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5464 tucss = skb_transport_offset(skb);
5465 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5466
5467 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5468 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5469
5470 i = tx_ring->next_to_use;
5471 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5472 buffer_info = &tx_ring->buffer_info[i];
5473
5474 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5475 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5476 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5477 context_desc->upper_setup.tcp_fields.tucss = tucss;
5478 context_desc->upper_setup.tcp_fields.tucso = tucso;
5479 context_desc->upper_setup.tcp_fields.tucse = 0;
5480 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5481 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5482 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5483
5484 buffer_info->time_stamp = jiffies;
5485 buffer_info->next_to_watch = i;
5486
5487 i++;
5488 if (i == tx_ring->count)
5489 i = 0;
5490 tx_ring->next_to_use = i;
5491
5492 return 1;
5493}
5494
5495static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5496 __be16 protocol)
5497{
5498 struct e1000_adapter *adapter = tx_ring->adapter;
5499 struct e1000_context_desc *context_desc;
5500 struct e1000_buffer *buffer_info;
5501 unsigned int i;
5502 u8 css;
5503 u32 cmd_len = E1000_TXD_CMD_DEXT;
5504
5505 if (skb->ip_summed != CHECKSUM_PARTIAL)
5506 return false;
5507
5508 switch (protocol) {
5509 case cpu_to_be16(ETH_P_IP):
5510 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5511 cmd_len |= E1000_TXD_CMD_TCP;
5512 break;
5513 case cpu_to_be16(ETH_P_IPV6):
5514 /* XXX not handling all IPV6 headers */
5515 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5516 cmd_len |= E1000_TXD_CMD_TCP;
5517 break;
5518 default:
5519 if (unlikely(net_ratelimit()))
5520 e_warn("checksum_partial proto=%x!\n",
5521 be16_to_cpu(protocol));
5522 break;
5523 }
5524
5525 css = skb_checksum_start_offset(skb);
5526
5527 i = tx_ring->next_to_use;
5528 buffer_info = &tx_ring->buffer_info[i];
5529 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5530
5531 context_desc->lower_setup.ip_config = 0;
5532 context_desc->upper_setup.tcp_fields.tucss = css;
5533 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5534 context_desc->upper_setup.tcp_fields.tucse = 0;
5535 context_desc->tcp_seg_setup.data = 0;
5536 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5537
5538 buffer_info->time_stamp = jiffies;
5539 buffer_info->next_to_watch = i;
5540
5541 i++;
5542 if (i == tx_ring->count)
5543 i = 0;
5544 tx_ring->next_to_use = i;
5545
5546 return true;
5547}
5548
5549static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5550 unsigned int first, unsigned int max_per_txd,
5551 unsigned int nr_frags)
5552{
5553 struct e1000_adapter *adapter = tx_ring->adapter;
5554 struct pci_dev *pdev = adapter->pdev;
5555 struct e1000_buffer *buffer_info;
5556 unsigned int len = skb_headlen(skb);
5557 unsigned int offset = 0, size, count = 0, i;
5558 unsigned int f, bytecount, segs;
5559
5560 i = tx_ring->next_to_use;
5561
5562 while (len) {
5563 buffer_info = &tx_ring->buffer_info[i];
5564 size = min(len, max_per_txd);
5565
5566 buffer_info->length = size;
5567 buffer_info->time_stamp = jiffies;
5568 buffer_info->next_to_watch = i;
5569 buffer_info->dma = dma_map_single(&pdev->dev,
5570 skb->data + offset,
5571 size, DMA_TO_DEVICE);
5572 buffer_info->mapped_as_page = false;
5573 if (dma_mapping_error(dev: &pdev->dev, dma_addr: buffer_info->dma))
5574 goto dma_error;
5575
5576 len -= size;
5577 offset += size;
5578 count++;
5579
5580 if (len) {
5581 i++;
5582 if (i == tx_ring->count)
5583 i = 0;
5584 }
5585 }
5586
5587 for (f = 0; f < nr_frags; f++) {
5588 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5589
5590 len = skb_frag_size(frag);
5591 offset = 0;
5592
5593 while (len) {
5594 i++;
5595 if (i == tx_ring->count)
5596 i = 0;
5597
5598 buffer_info = &tx_ring->buffer_info[i];
5599 size = min(len, max_per_txd);
5600
5601 buffer_info->length = size;
5602 buffer_info->time_stamp = jiffies;
5603 buffer_info->next_to_watch = i;
5604 buffer_info->dma = skb_frag_dma_map(dev: &pdev->dev, frag,
5605 offset, size,
5606 dir: DMA_TO_DEVICE);
5607 buffer_info->mapped_as_page = true;
5608 if (dma_mapping_error(dev: &pdev->dev, dma_addr: buffer_info->dma))
5609 goto dma_error;
5610
5611 len -= size;
5612 offset += size;
5613 count++;
5614 }
5615 }
5616
5617 segs = skb_shinfo(skb)->gso_segs ? : 1;
5618 /* multiply data chunks by size of headers */
5619 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5620
5621 tx_ring->buffer_info[i].skb = skb;
5622 tx_ring->buffer_info[i].segs = segs;
5623 tx_ring->buffer_info[i].bytecount = bytecount;
5624 tx_ring->buffer_info[first].next_to_watch = i;
5625
5626 return count;
5627
5628dma_error:
5629 dev_err(&pdev->dev, "Tx DMA map failed\n");
5630 buffer_info->dma = 0;
5631 if (count)
5632 count--;
5633
5634 while (count--) {
5635 if (i == 0)
5636 i += tx_ring->count;
5637 i--;
5638 buffer_info = &tx_ring->buffer_info[i];
5639 e1000_put_txbuf(tx_ring, buffer_info, drop: true);
5640 }
5641
5642 return 0;
5643}
5644
5645static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5646{
5647 struct e1000_adapter *adapter = tx_ring->adapter;
5648 struct e1000_tx_desc *tx_desc = NULL;
5649 struct e1000_buffer *buffer_info;
5650 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5651 unsigned int i;
5652
5653 if (tx_flags & E1000_TX_FLAGS_TSO) {
5654 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5655 E1000_TXD_CMD_TSE;
5656 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5657
5658 if (tx_flags & E1000_TX_FLAGS_IPV4)
5659 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5660 }
5661
5662 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5663 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5664 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5665 }
5666
5667 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5668 txd_lower |= E1000_TXD_CMD_VLE;
5669 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5670 }
5671
5672 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5673 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5674
5675 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5676 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5677 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5678 }
5679
5680 i = tx_ring->next_to_use;
5681
5682 do {
5683 buffer_info = &tx_ring->buffer_info[i];
5684 tx_desc = E1000_TX_DESC(*tx_ring, i);
5685 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5686 tx_desc->lower.data = cpu_to_le32(txd_lower |
5687 buffer_info->length);
5688 tx_desc->upper.data = cpu_to_le32(txd_upper);
5689
5690 i++;
5691 if (i == tx_ring->count)
5692 i = 0;
5693 } while (--count > 0);
5694
5695 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5696
5697 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5698 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5699 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5700
5701 /* Force memory writes to complete before letting h/w
5702 * know there are new descriptors to fetch. (Only
5703 * applicable for weak-ordered memory model archs,
5704 * such as IA-64).
5705 */
5706 wmb();
5707
5708 tx_ring->next_to_use = i;
5709}
5710
5711#define MINIMUM_DHCP_PACKET_SIZE 282
5712static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5713 struct sk_buff *skb)
5714{
5715 struct e1000_hw *hw = &adapter->hw;
5716 u16 length, offset;
5717
5718 if (skb_vlan_tag_present(skb) &&
5719 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5720 (adapter->hw.mng_cookie.status &
5721 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5722 return 0;
5723
5724 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5725 return 0;
5726
5727 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5728 return 0;
5729
5730 {
5731 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5732 struct udphdr *udp;
5733
5734 if (ip->protocol != IPPROTO_UDP)
5735 return 0;
5736
5737 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5738 if (ntohs(udp->dest) != 67)
5739 return 0;
5740
5741 offset = (u8 *)udp + 8 - skb->data;
5742 length = skb->len - offset;
5743 return e1000e_mng_write_dhcp_info(hw, buffer: (u8 *)udp + 8, length);
5744 }
5745
5746 return 0;
5747}
5748
5749static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5750{
5751 struct e1000_adapter *adapter = tx_ring->adapter;
5752
5753 netif_stop_queue(dev: adapter->netdev);
5754 /* Herbert's original patch had:
5755 * smp_mb__after_netif_stop_queue();
5756 * but since that doesn't exist yet, just open code it.
5757 */
5758 smp_mb();
5759
5760 /* We need to check again in a case another CPU has just
5761 * made room available.
5762 */
5763 if (e1000_desc_unused(ring: tx_ring) < size)
5764 return -EBUSY;
5765
5766 /* A reprieve! */
5767 netif_start_queue(dev: adapter->netdev);
5768 ++adapter->restart_queue;
5769 return 0;
5770}
5771
5772static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5773{
5774 BUG_ON(size > tx_ring->count);
5775
5776 if (e1000_desc_unused(ring: tx_ring) >= size)
5777 return 0;
5778 return __e1000_maybe_stop_tx(tx_ring, size);
5779}
5780
5781static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5782 struct net_device *netdev)
5783{
5784 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
5785 struct e1000_ring *tx_ring = adapter->tx_ring;
5786 unsigned int first;
5787 unsigned int tx_flags = 0;
5788 unsigned int len = skb_headlen(skb);
5789 unsigned int nr_frags;
5790 unsigned int mss;
5791 int count = 0;
5792 int tso;
5793 unsigned int f;
5794 __be16 protocol = vlan_get_protocol(skb);
5795
5796 if (test_bit(__E1000_DOWN, &adapter->state)) {
5797 dev_kfree_skb_any(skb);
5798 return NETDEV_TX_OK;
5799 }
5800
5801 if (skb->len <= 0) {
5802 dev_kfree_skb_any(skb);
5803 return NETDEV_TX_OK;
5804 }
5805
5806 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5807 * pad skb in order to meet this minimum size requirement
5808 */
5809 if (skb_put_padto(skb, len: 17))
5810 return NETDEV_TX_OK;
5811
5812 mss = skb_shinfo(skb)->gso_size;
5813 if (mss) {
5814 u8 hdr_len;
5815
5816 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5817 * points to just header, pull a few bytes of payload from
5818 * frags into skb->data
5819 */
5820 hdr_len = skb_tcp_all_headers(skb);
5821 /* we do this workaround for ES2LAN, but it is un-necessary,
5822 * avoiding it could save a lot of cycles
5823 */
5824 if (skb->data_len && (hdr_len == len)) {
5825 unsigned int pull_size;
5826
5827 pull_size = min_t(unsigned int, 4, skb->data_len);
5828 if (!__pskb_pull_tail(skb, delta: pull_size)) {
5829 e_err("__pskb_pull_tail failed.\n");
5830 dev_kfree_skb_any(skb);
5831 return NETDEV_TX_OK;
5832 }
5833 len = skb_headlen(skb);
5834 }
5835 }
5836
5837 /* reserve a descriptor for the offload context */
5838 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5839 count++;
5840 count++;
5841
5842 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5843
5844 nr_frags = skb_shinfo(skb)->nr_frags;
5845 for (f = 0; f < nr_frags; f++)
5846 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5847 adapter->tx_fifo_limit);
5848
5849 if (adapter->hw.mac.tx_pkt_filtering)
5850 e1000_transfer_dhcp_info(adapter, skb);
5851
5852 /* need: count + 2 desc gap to keep tail from touching
5853 * head, otherwise try next time
5854 */
5855 if (e1000_maybe_stop_tx(tx_ring, size: count + 2))
5856 return NETDEV_TX_BUSY;
5857
5858 if (skb_vlan_tag_present(skb)) {
5859 tx_flags |= E1000_TX_FLAGS_VLAN;
5860 tx_flags |= (skb_vlan_tag_get(skb) <<
5861 E1000_TX_FLAGS_VLAN_SHIFT);
5862 }
5863
5864 first = tx_ring->next_to_use;
5865
5866 tso = e1000_tso(tx_ring, skb, protocol);
5867 if (tso < 0) {
5868 dev_kfree_skb_any(skb);
5869 return NETDEV_TX_OK;
5870 }
5871
5872 if (tso)
5873 tx_flags |= E1000_TX_FLAGS_TSO;
5874 else if (e1000_tx_csum(tx_ring, skb, protocol))
5875 tx_flags |= E1000_TX_FLAGS_CSUM;
5876
5877 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5878 * 82571 hardware supports TSO capabilities for IPv6 as well...
5879 * no longer assume, we must.
5880 */
5881 if (protocol == htons(ETH_P_IP))
5882 tx_flags |= E1000_TX_FLAGS_IPV4;
5883
5884 if (unlikely(skb->no_fcs))
5885 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5886
5887 /* if count is 0 then mapping error has occurred */
5888 count = e1000_tx_map(tx_ring, skb, first, max_per_txd: adapter->tx_fifo_limit,
5889 nr_frags);
5890 if (count) {
5891 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5892 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5893 if (!adapter->tx_hwtstamp_skb) {
5894 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5895 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5896 adapter->tx_hwtstamp_skb = skb_get(skb);
5897 adapter->tx_hwtstamp_start = jiffies;
5898 schedule_work(work: &adapter->tx_hwtstamp_work);
5899 } else {
5900 adapter->tx_hwtstamp_skipped++;
5901 }
5902 }
5903
5904 skb_tx_timestamp(skb);
5905
5906 netdev_sent_queue(dev: netdev, bytes: skb->len);
5907 e1000_tx_queue(tx_ring, tx_flags, count);
5908 /* Make sure there is space in the ring for the next send. */
5909 e1000_maybe_stop_tx(tx_ring,
5910 size: ((MAX_SKB_FRAGS + 1) *
5911 DIV_ROUND_UP(PAGE_SIZE,
5912 adapter->tx_fifo_limit) + 4));
5913
5914 if (!netdev_xmit_more() ||
5915 netif_xmit_stopped(dev_queue: netdev_get_tx_queue(dev: netdev, index: 0))) {
5916 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5917 e1000e_update_tdt_wa(tx_ring,
5918 i: tx_ring->next_to_use);
5919 else
5920 writel(val: tx_ring->next_to_use, addr: tx_ring->tail);
5921 }
5922 } else {
5923 dev_kfree_skb_any(skb);
5924 tx_ring->buffer_info[first].time_stamp = 0;
5925 tx_ring->next_to_use = first;
5926 }
5927
5928 return NETDEV_TX_OK;
5929}
5930
5931/**
5932 * e1000_tx_timeout - Respond to a Tx Hang
5933 * @netdev: network interface device structure
5934 * @txqueue: index of the hung queue (unused)
5935 **/
5936static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
5937{
5938 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
5939
5940 /* Do the reset outside of interrupt context */
5941 adapter->tx_timeout_count++;
5942 schedule_work(work: &adapter->reset_task);
5943}
5944
5945static void e1000_reset_task(struct work_struct *work)
5946{
5947 struct e1000_adapter *adapter;
5948 adapter = container_of(work, struct e1000_adapter, reset_task);
5949
5950 rtnl_lock();
5951 /* don't run the task if already down */
5952 if (test_bit(__E1000_DOWN, &adapter->state)) {
5953 rtnl_unlock();
5954 return;
5955 }
5956
5957 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5958 e1000e_dump(adapter);
5959 e_err("Reset adapter unexpectedly\n");
5960 }
5961 e1000e_reinit_locked(adapter);
5962 rtnl_unlock();
5963}
5964
5965/**
5966 * e1000e_get_stats64 - Get System Network Statistics
5967 * @netdev: network interface device structure
5968 * @stats: rtnl_link_stats64 pointer
5969 *
5970 * Returns the address of the device statistics structure.
5971 **/
5972void e1000e_get_stats64(struct net_device *netdev,
5973 struct rtnl_link_stats64 *stats)
5974{
5975 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
5976
5977 spin_lock(lock: &adapter->stats64_lock);
5978 e1000e_update_stats(adapter);
5979 /* Fill out the OS statistics structure */
5980 stats->rx_bytes = adapter->stats.gorc;
5981 stats->rx_packets = adapter->stats.gprc;
5982 stats->tx_bytes = adapter->stats.gotc;
5983 stats->tx_packets = adapter->stats.gptc;
5984 stats->multicast = adapter->stats.mprc;
5985 stats->collisions = adapter->stats.colc;
5986
5987 /* Rx Errors */
5988
5989 /* RLEC on some newer hardware can be incorrect so build
5990 * our own version based on RUC and ROC
5991 */
5992 stats->rx_errors = adapter->stats.rxerrc +
5993 adapter->stats.crcerrs + adapter->stats.algnerrc +
5994 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5995 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
5996 stats->rx_crc_errors = adapter->stats.crcerrs;
5997 stats->rx_frame_errors = adapter->stats.algnerrc;
5998 stats->rx_missed_errors = adapter->stats.mpc;
5999
6000 /* Tx Errors */
6001 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
6002 stats->tx_aborted_errors = adapter->stats.ecol;
6003 stats->tx_window_errors = adapter->stats.latecol;
6004 stats->tx_carrier_errors = adapter->stats.tncrs;
6005
6006 /* Tx Dropped needs to be maintained elsewhere */
6007
6008 spin_unlock(lock: &adapter->stats64_lock);
6009}
6010
6011/**
6012 * e1000_change_mtu - Change the Maximum Transfer Unit
6013 * @netdev: network interface device structure
6014 * @new_mtu: new value for maximum frame size
6015 *
6016 * Returns 0 on success, negative on failure
6017 **/
6018static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6019{
6020 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
6021 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6022
6023 /* Jumbo frame support */
6024 if ((new_mtu > ETH_DATA_LEN) &&
6025 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6026 e_err("Jumbo Frames not supported.\n");
6027 return -EINVAL;
6028 }
6029
6030 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6031 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6032 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6033 (new_mtu > ETH_DATA_LEN)) {
6034 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6035 return -EINVAL;
6036 }
6037
6038 while (test_and_set_bit(nr: __E1000_RESETTING, addr: &adapter->state))
6039 usleep_range(min: 1000, max: 1100);
6040 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6041 adapter->max_frame_size = max_frame;
6042 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6043 netdev->mtu, new_mtu);
6044 netdev->mtu = new_mtu;
6045
6046 pm_runtime_get_sync(dev: netdev->dev.parent);
6047
6048 if (netif_running(dev: netdev))
6049 e1000e_down(adapter, reset: true);
6050
6051 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6052 * means we reserve 2 more, this pushes us to allocate from the next
6053 * larger slab size.
6054 * i.e. RXBUFFER_2048 --> size-4096 slab
6055 * However with the new *_jumbo_rx* routines, jumbo receives will use
6056 * fragmented skbs
6057 */
6058
6059 if (max_frame <= 2048)
6060 adapter->rx_buffer_len = 2048;
6061 else
6062 adapter->rx_buffer_len = 4096;
6063
6064 /* adjust allocation if LPE protects us, and we aren't using SBP */
6065 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6066 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6067
6068 if (netif_running(dev: netdev))
6069 e1000e_up(adapter);
6070 else
6071 e1000e_reset(adapter);
6072
6073 pm_runtime_put_sync(dev: netdev->dev.parent);
6074
6075 clear_bit(nr: __E1000_RESETTING, addr: &adapter->state);
6076
6077 return 0;
6078}
6079
6080static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6081 int cmd)
6082{
6083 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
6084 struct mii_ioctl_data *data = if_mii(rq: ifr);
6085
6086 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6087 return -EOPNOTSUPP;
6088
6089 switch (cmd) {
6090 case SIOCGMIIPHY:
6091 data->phy_id = adapter->hw.phy.addr;
6092 break;
6093 case SIOCGMIIREG:
6094 e1000_phy_read_status(adapter);
6095
6096 switch (data->reg_num & 0x1F) {
6097 case MII_BMCR:
6098 data->val_out = adapter->phy_regs.bmcr;
6099 break;
6100 case MII_BMSR:
6101 data->val_out = adapter->phy_regs.bmsr;
6102 break;
6103 case MII_PHYSID1:
6104 data->val_out = (adapter->hw.phy.id >> 16);
6105 break;
6106 case MII_PHYSID2:
6107 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6108 break;
6109 case MII_ADVERTISE:
6110 data->val_out = adapter->phy_regs.advertise;
6111 break;
6112 case MII_LPA:
6113 data->val_out = adapter->phy_regs.lpa;
6114 break;
6115 case MII_EXPANSION:
6116 data->val_out = adapter->phy_regs.expansion;
6117 break;
6118 case MII_CTRL1000:
6119 data->val_out = adapter->phy_regs.ctrl1000;
6120 break;
6121 case MII_STAT1000:
6122 data->val_out = adapter->phy_regs.stat1000;
6123 break;
6124 case MII_ESTATUS:
6125 data->val_out = adapter->phy_regs.estatus;
6126 break;
6127 default:
6128 return -EIO;
6129 }
6130 break;
6131 case SIOCSMIIREG:
6132 default:
6133 return -EOPNOTSUPP;
6134 }
6135 return 0;
6136}
6137
6138/**
6139 * e1000e_hwtstamp_set - control hardware time stamping
6140 * @netdev: network interface device structure
6141 * @ifr: interface request
6142 *
6143 * Outgoing time stamping can be enabled and disabled. Play nice and
6144 * disable it when requested, although it shouldn't cause any overhead
6145 * when no packet needs it. At most one packet in the queue may be
6146 * marked for time stamping, otherwise it would be impossible to tell
6147 * for sure to which packet the hardware time stamp belongs.
6148 *
6149 * Incoming time stamping has to be configured via the hardware filters.
6150 * Not all combinations are supported, in particular event type has to be
6151 * specified. Matching the kind of event packet is not supported, with the
6152 * exception of "all V2 events regardless of level 2 or 4".
6153 **/
6154static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6155{
6156 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
6157 struct hwtstamp_config config;
6158 int ret_val;
6159
6160 if (copy_from_user(to: &config, from: ifr->ifr_data, n: sizeof(config)))
6161 return -EFAULT;
6162
6163 ret_val = e1000e_config_hwtstamp(adapter, config: &config);
6164 if (ret_val)
6165 return ret_val;
6166
6167 switch (config.rx_filter) {
6168 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6169 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6170 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6171 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6172 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6173 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6174 /* With V2 type filters which specify a Sync or Delay Request,
6175 * Path Delay Request/Response messages are also time stamped
6176 * by hardware so notify the caller the requested packets plus
6177 * some others are time stamped.
6178 */
6179 config.rx_filter = HWTSTAMP_FILTER_SOME;
6180 break;
6181 default:
6182 break;
6183 }
6184
6185 return copy_to_user(to: ifr->ifr_data, from: &config,
6186 n: sizeof(config)) ? -EFAULT : 0;
6187}
6188
6189static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6190{
6191 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
6192
6193 return copy_to_user(to: ifr->ifr_data, from: &adapter->hwtstamp_config,
6194 n: sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6195}
6196
6197static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6198{
6199 switch (cmd) {
6200 case SIOCGMIIPHY:
6201 case SIOCGMIIREG:
6202 case SIOCSMIIREG:
6203 return e1000_mii_ioctl(netdev, ifr, cmd);
6204 case SIOCSHWTSTAMP:
6205 return e1000e_hwtstamp_set(netdev, ifr);
6206 case SIOCGHWTSTAMP:
6207 return e1000e_hwtstamp_get(netdev, ifr);
6208 default:
6209 return -EOPNOTSUPP;
6210 }
6211}
6212
6213static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6214{
6215 struct e1000_hw *hw = &adapter->hw;
6216 u32 i, mac_reg, wuc;
6217 u16 phy_reg, wuc_enable;
6218 int retval;
6219
6220 /* copy MAC RARs to PHY RARs */
6221 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6222
6223 retval = hw->phy.ops.acquire(hw);
6224 if (retval) {
6225 e_err("Could not acquire PHY\n");
6226 return retval;
6227 }
6228
6229 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6230 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, phy_reg: &wuc_enable);
6231 if (retval)
6232 goto release;
6233
6234 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6235 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6236 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6237 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6238 (u16)(mac_reg & 0xFFFF));
6239 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6240 (u16)((mac_reg >> 16) & 0xFFFF));
6241 }
6242
6243 /* configure PHY Rx Control register */
6244 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6245 mac_reg = er32(RCTL);
6246 if (mac_reg & E1000_RCTL_UPE)
6247 phy_reg |= BM_RCTL_UPE;
6248 if (mac_reg & E1000_RCTL_MPE)
6249 phy_reg |= BM_RCTL_MPE;
6250 phy_reg &= ~(BM_RCTL_MO_MASK);
6251 if (mac_reg & E1000_RCTL_MO_3)
6252 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
6253 << BM_RCTL_MO_SHIFT);
6254 if (mac_reg & E1000_RCTL_BAM)
6255 phy_reg |= BM_RCTL_BAM;
6256 if (mac_reg & E1000_RCTL_PMCF)
6257 phy_reg |= BM_RCTL_PMCF;
6258 mac_reg = er32(CTRL);
6259 if (mac_reg & E1000_CTRL_RFCE)
6260 phy_reg |= BM_RCTL_RFCE;
6261 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6262
6263 wuc = E1000_WUC_PME_EN;
6264 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6265 wuc |= E1000_WUC_APME;
6266
6267 /* enable PHY wakeup in MAC register */
6268 ew32(WUFC, wufc);
6269 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6270 E1000_WUC_PME_STATUS | wuc));
6271
6272 /* configure and enable PHY wakeup in PHY registers */
6273 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6274 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6275
6276 /* activate PHY wakeup */
6277 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6278 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, phy_reg: &wuc_enable);
6279 if (retval)
6280 e_err("Could not set PHY Host Wakeup bit\n");
6281release:
6282 hw->phy.ops.release(hw);
6283
6284 return retval;
6285}
6286
6287static void e1000e_flush_lpic(struct pci_dev *pdev)
6288{
6289 struct net_device *netdev = pci_get_drvdata(pdev);
6290 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
6291 struct e1000_hw *hw = &adapter->hw;
6292 u32 ret_val;
6293
6294 pm_runtime_get_sync(dev: netdev->dev.parent);
6295
6296 ret_val = hw->phy.ops.acquire(hw);
6297 if (ret_val)
6298 goto fl_out;
6299
6300 pr_info("EEE TX LPI TIMER: %08X\n",
6301 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6302
6303 hw->phy.ops.release(hw);
6304
6305fl_out:
6306 pm_runtime_put_sync(dev: netdev->dev.parent);
6307}
6308
6309/* S0ix implementation */
6310static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
6311{
6312 struct e1000_hw *hw = &adapter->hw;
6313 u32 mac_data;
6314 u16 phy_data;
6315
6316 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6317 hw->mac.type >= e1000_pch_adp) {
6318 /* Request ME configure the device for S0ix */
6319 mac_data = er32(H2ME);
6320 mac_data |= E1000_H2ME_START_DPG;
6321 mac_data &= ~E1000_H2ME_EXIT_DPG;
6322 trace_e1000e_trace_mac_register(reg: mac_data);
6323 ew32(H2ME, mac_data);
6324 } else {
6325 /* Request driver configure the device to S0ix */
6326 /* Disable the periodic inband message,
6327 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6328 */
6329 e1e_rphy(hw, HV_PM_CTRL, data: &phy_data);
6330 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
6331 phy_data |= BIT(10);
6332 e1e_wphy(hw, HV_PM_CTRL, data: phy_data);
6333
6334 /* Make sure we don't exit K1 every time a new packet arrives
6335 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6336 */
6337 e1e_rphy(hw, I217_CGFREG, data: &phy_data);
6338 phy_data |= BIT(5);
6339 e1e_wphy(hw, I217_CGFREG, data: phy_data);
6340
6341 /* Change the MAC/PHY interface to SMBus
6342 * Force the SMBus in PHY page769_23[0] = 1
6343 * Force the SMBus in MAC CTRL_EXT[11] = 1
6344 */
6345 e1e_rphy(hw, CV_SMB_CTRL, data: &phy_data);
6346 phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
6347 e1e_wphy(hw, CV_SMB_CTRL, data: phy_data);
6348 mac_data = er32(CTRL_EXT);
6349 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
6350 ew32(CTRL_EXT, mac_data);
6351
6352 /* DFT control: PHY bit: page769_20[0] = 1
6353 * page769_20[7] - PHY PLL stop
6354 * page769_20[8] - PHY go to the electrical idle
6355 * page769_20[9] - PHY serdes disable
6356 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6357 */
6358 e1e_rphy(hw, I82579_DFT_CTRL, data: &phy_data);
6359 phy_data |= BIT(0);
6360 phy_data |= BIT(7);
6361 phy_data |= BIT(8);
6362 phy_data |= BIT(9);
6363 e1e_wphy(hw, I82579_DFT_CTRL, data: phy_data);
6364
6365 mac_data = er32(EXTCNF_CTRL);
6366 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
6367 ew32(EXTCNF_CTRL, mac_data);
6368
6369 /* Enable the Dynamic Power Gating in the MAC */
6370 mac_data = er32(FEXTNVM7);
6371 mac_data |= BIT(22);
6372 ew32(FEXTNVM7, mac_data);
6373
6374 /* Disable disconnected cable conditioning for Power Gating */
6375 mac_data = er32(DPGFR);
6376 mac_data |= BIT(2);
6377 ew32(DPGFR, mac_data);
6378
6379 /* Don't wake from dynamic Power Gating with clock request */
6380 mac_data = er32(FEXTNVM12);
6381 mac_data |= BIT(12);
6382 ew32(FEXTNVM12, mac_data);
6383
6384 /* Ungate PGCB clock */
6385 mac_data = er32(FEXTNVM9);
6386 mac_data &= ~BIT(28);
6387 ew32(FEXTNVM9, mac_data);
6388
6389 /* Enable K1 off to enable mPHY Power Gating */
6390 mac_data = er32(FEXTNVM6);
6391 mac_data |= BIT(31);
6392 ew32(FEXTNVM6, mac_data);
6393
6394 /* Enable mPHY power gating for any link and speed */
6395 mac_data = er32(FEXTNVM8);
6396 mac_data |= BIT(9);
6397 ew32(FEXTNVM8, mac_data);
6398
6399 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6400 mac_data = er32(CTRL_EXT);
6401 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
6402 ew32(CTRL_EXT, mac_data);
6403
6404 /* No MAC DPG gating SLP_S0 in modern standby
6405 * Switch the logic of the lanphypc to use PMC counter
6406 */
6407 mac_data = er32(FEXTNVM5);
6408 mac_data |= BIT(7);
6409 ew32(FEXTNVM5, mac_data);
6410 }
6411
6412 /* Disable the time synchronization clock */
6413 mac_data = er32(FEXTNVM7);
6414 mac_data |= BIT(31);
6415 mac_data &= ~BIT(0);
6416 ew32(FEXTNVM7, mac_data);
6417
6418 /* Dynamic Power Gating Enable */
6419 mac_data = er32(CTRL_EXT);
6420 mac_data |= BIT(3);
6421 ew32(CTRL_EXT, mac_data);
6422
6423 /* Check MAC Tx/Rx packet buffer pointers.
6424 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6425 * pending traffic indication that would prevent power gating.
6426 */
6427 mac_data = er32(TDFH);
6428 if (mac_data)
6429 ew32(TDFH, 0);
6430 mac_data = er32(TDFT);
6431 if (mac_data)
6432 ew32(TDFT, 0);
6433 mac_data = er32(TDFHS);
6434 if (mac_data)
6435 ew32(TDFHS, 0);
6436 mac_data = er32(TDFTS);
6437 if (mac_data)
6438 ew32(TDFTS, 0);
6439 mac_data = er32(TDFPC);
6440 if (mac_data)
6441 ew32(TDFPC, 0);
6442 mac_data = er32(RDFH);
6443 if (mac_data)
6444 ew32(RDFH, 0);
6445 mac_data = er32(RDFT);
6446 if (mac_data)
6447 ew32(RDFT, 0);
6448 mac_data = er32(RDFHS);
6449 if (mac_data)
6450 ew32(RDFHS, 0);
6451 mac_data = er32(RDFTS);
6452 if (mac_data)
6453 ew32(RDFTS, 0);
6454 mac_data = er32(RDFPC);
6455 if (mac_data)
6456 ew32(RDFPC, 0);
6457}
6458
6459static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
6460{
6461 struct e1000_hw *hw = &adapter->hw;
6462 bool firmware_bug = false;
6463 u32 mac_data;
6464 u16 phy_data;
6465 u32 i = 0;
6466
6467 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6468 hw->mac.type >= e1000_pch_adp) {
6469 /* Keep the GPT clock enabled for CSME */
6470 mac_data = er32(FEXTNVM);
6471 mac_data |= BIT(3);
6472 ew32(FEXTNVM, mac_data);
6473 /* Request ME unconfigure the device from S0ix */
6474 mac_data = er32(H2ME);
6475 mac_data &= ~E1000_H2ME_START_DPG;
6476 mac_data |= E1000_H2ME_EXIT_DPG;
6477 trace_e1000e_trace_mac_register(reg: mac_data);
6478 ew32(H2ME, mac_data);
6479
6480 /* Poll up to 2.5 seconds for ME to unconfigure DPG.
6481 * If this takes more than 1 second, show a warning indicating a
6482 * firmware bug
6483 */
6484 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) {
6485 if (i > 100 && !firmware_bug)
6486 firmware_bug = true;
6487
6488 if (i++ == 250) {
6489 e_dbg("Timeout (firmware bug): %d msec\n",
6490 i * 10);
6491 break;
6492 }
6493
6494 usleep_range(min: 10000, max: 11000);
6495 }
6496 if (firmware_bug)
6497 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n",
6498 i * 10);
6499 else
6500 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10);
6501 } else {
6502 /* Request driver unconfigure the device from S0ix */
6503
6504 /* Disable the Dynamic Power Gating in the MAC */
6505 mac_data = er32(FEXTNVM7);
6506 mac_data &= 0xFFBFFFFF;
6507 ew32(FEXTNVM7, mac_data);
6508
6509 /* Disable mPHY power gating for any link and speed */
6510 mac_data = er32(FEXTNVM8);
6511 mac_data &= ~BIT(9);
6512 ew32(FEXTNVM8, mac_data);
6513
6514 /* Disable K1 off */
6515 mac_data = er32(FEXTNVM6);
6516 mac_data &= ~BIT(31);
6517 ew32(FEXTNVM6, mac_data);
6518
6519 /* Disable Ungate PGCB clock */
6520 mac_data = er32(FEXTNVM9);
6521 mac_data |= BIT(28);
6522 ew32(FEXTNVM9, mac_data);
6523
6524 /* Cancel not waking from dynamic
6525 * Power Gating with clock request
6526 */
6527 mac_data = er32(FEXTNVM12);
6528 mac_data &= ~BIT(12);
6529 ew32(FEXTNVM12, mac_data);
6530
6531 /* Cancel disable disconnected cable conditioning
6532 * for Power Gating
6533 */
6534 mac_data = er32(DPGFR);
6535 mac_data &= ~BIT(2);
6536 ew32(DPGFR, mac_data);
6537
6538 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6539 mac_data = er32(CTRL_EXT);
6540 mac_data &= 0xFFF7FFFF;
6541 ew32(CTRL_EXT, mac_data);
6542
6543 /* Revert the lanphypc logic to use the internal Gbe counter
6544 * and not the PMC counter
6545 */
6546 mac_data = er32(FEXTNVM5);
6547 mac_data &= 0xFFFFFF7F;
6548 ew32(FEXTNVM5, mac_data);
6549
6550 /* Enable the periodic inband message,
6551 * Request PCIe clock in K1 page770_17[10:9] =01b
6552 */
6553 e1e_rphy(hw, HV_PM_CTRL, data: &phy_data);
6554 phy_data &= 0xFBFF;
6555 phy_data |= HV_PM_CTRL_K1_CLK_REQ;
6556 e1e_wphy(hw, HV_PM_CTRL, data: phy_data);
6557
6558 /* Return back configuration
6559 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6560 */
6561 e1e_rphy(hw, I217_CGFREG, data: &phy_data);
6562 phy_data &= 0xFFDF;
6563 e1e_wphy(hw, I217_CGFREG, data: phy_data);
6564
6565 /* Change the MAC/PHY interface to Kumeran
6566 * Unforce the SMBus in PHY page769_23[0] = 0
6567 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6568 */
6569 e1e_rphy(hw, CV_SMB_CTRL, data: &phy_data);
6570 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
6571 e1e_wphy(hw, CV_SMB_CTRL, data: phy_data);
6572 mac_data = er32(CTRL_EXT);
6573 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
6574 ew32(CTRL_EXT, mac_data);
6575 }
6576
6577 /* Disable Dynamic Power Gating */
6578 mac_data = er32(CTRL_EXT);
6579 mac_data &= 0xFFFFFFF7;
6580 ew32(CTRL_EXT, mac_data);
6581
6582 /* Enable the time synchronization clock */
6583 mac_data = er32(FEXTNVM7);
6584 mac_data &= ~BIT(31);
6585 mac_data |= BIT(0);
6586 ew32(FEXTNVM7, mac_data);
6587}
6588
6589static int e1000e_pm_freeze(struct device *dev)
6590{
6591 struct net_device *netdev = dev_get_drvdata(dev);
6592 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
6593 bool present;
6594
6595 rtnl_lock();
6596
6597 present = netif_device_present(dev: netdev);
6598 netif_device_detach(dev: netdev);
6599
6600 if (present && netif_running(dev: netdev)) {
6601 int count = E1000_CHECK_RESET_COUNT;
6602
6603 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6604 usleep_range(min: 10000, max: 11000);
6605
6606 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6607
6608 /* Quiesce the device without resetting the hardware */
6609 e1000e_down(adapter, reset: false);
6610 e1000_free_irq(adapter);
6611 }
6612 rtnl_unlock();
6613
6614 e1000e_reset_interrupt_capability(adapter);
6615
6616 /* Allow time for pending master requests to run */
6617 e1000e_disable_pcie_master(hw: &adapter->hw);
6618
6619 return 0;
6620}
6621
6622static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6623{
6624 struct net_device *netdev = pci_get_drvdata(pdev);
6625 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
6626 struct e1000_hw *hw = &adapter->hw;
6627 u32 ctrl, ctrl_ext, rctl, status, wufc;
6628 int retval = 0;
6629
6630 /* Runtime suspend should only enable wakeup for link changes */
6631 if (runtime)
6632 wufc = E1000_WUFC_LNKC;
6633 else if (device_may_wakeup(dev: &pdev->dev))
6634 wufc = adapter->wol;
6635 else
6636 wufc = 0;
6637
6638 status = er32(STATUS);
6639 if (status & E1000_STATUS_LU)
6640 wufc &= ~E1000_WUFC_LNKC;
6641
6642 if (wufc) {
6643 e1000_setup_rctl(adapter);
6644 e1000e_set_rx_mode(netdev);
6645
6646 /* turn on all-multi mode if wake on multicast is enabled */
6647 if (wufc & E1000_WUFC_MC) {
6648 rctl = er32(RCTL);
6649 rctl |= E1000_RCTL_MPE;
6650 ew32(RCTL, rctl);
6651 }
6652
6653 ctrl = er32(CTRL);
6654 ctrl |= E1000_CTRL_ADVD3WUC;
6655 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6656 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6657 ew32(CTRL, ctrl);
6658
6659 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6660 adapter->hw.phy.media_type ==
6661 e1000_media_type_internal_serdes) {
6662 /* keep the laser running in D3 */
6663 ctrl_ext = er32(CTRL_EXT);
6664 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6665 ew32(CTRL_EXT, ctrl_ext);
6666 }
6667
6668 if (!runtime)
6669 e1000e_power_up_phy(adapter);
6670
6671 if (adapter->flags & FLAG_IS_ICH)
6672 e1000_suspend_workarounds_ich8lan(hw: &adapter->hw);
6673
6674 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6675 /* enable wakeup by the PHY */
6676 retval = e1000_init_phy_wakeup(adapter, wufc);
6677 if (retval)
6678 return retval;
6679 } else {
6680 /* enable wakeup by the MAC */
6681 ew32(WUFC, wufc);
6682 ew32(WUC, E1000_WUC_PME_EN);
6683 }
6684 } else {
6685 ew32(WUC, 0);
6686 ew32(WUFC, 0);
6687
6688 e1000_power_down_phy(adapter);
6689 }
6690
6691 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6692 e1000e_igp3_phy_powerdown_workaround_ich8lan(hw: &adapter->hw);
6693 } else if (hw->mac.type >= e1000_pch_lpt) {
6694 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6695 /* ULP does not support wake from unicast, multicast
6696 * or broadcast.
6697 */
6698 retval = e1000_enable_ulp_lpt_lp(hw, to_sx: !runtime);
6699
6700 if (retval)
6701 return retval;
6702 }
6703
6704 /* Ensure that the appropriate bits are set in LPI_CTRL
6705 * for EEE in Sx
6706 */
6707 if ((hw->phy.type >= e1000_phy_i217) &&
6708 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6709 u16 lpi_ctrl = 0;
6710
6711 retval = hw->phy.ops.acquire(hw);
6712 if (!retval) {
6713 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6714 data: &lpi_ctrl);
6715 if (!retval) {
6716 if (adapter->eee_advert &
6717 hw->dev_spec.ich8lan.eee_lp_ability &
6718 I82579_EEE_100_SUPPORTED)
6719 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6720 if (adapter->eee_advert &
6721 hw->dev_spec.ich8lan.eee_lp_ability &
6722 I82579_EEE_1000_SUPPORTED)
6723 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6724
6725 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6726 data: lpi_ctrl);
6727 }
6728 }
6729 hw->phy.ops.release(hw);
6730 }
6731
6732 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6733 * would have already happened in close and is redundant.
6734 */
6735 e1000e_release_hw_control(adapter);
6736
6737 pci_clear_master(dev: pdev);
6738
6739 /* The pci-e switch on some quad port adapters will report a
6740 * correctable error when the MAC transitions from D0 to D3. To
6741 * prevent this we need to mask off the correctable errors on the
6742 * downstream port of the pci-e switch.
6743 *
6744 * We don't have the associated upstream bridge while assigning
6745 * the PCI device into guest. For example, the KVM on power is
6746 * one of the cases.
6747 */
6748 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6749 struct pci_dev *us_dev = pdev->bus->self;
6750 u16 devctl;
6751
6752 if (!us_dev)
6753 return 0;
6754
6755 pcie_capability_read_word(dev: us_dev, PCI_EXP_DEVCTL, val: &devctl);
6756 pcie_capability_write_word(dev: us_dev, PCI_EXP_DEVCTL,
6757 val: (devctl & ~PCI_EXP_DEVCTL_CERE));
6758
6759 pci_save_state(dev: pdev);
6760 pci_prepare_to_sleep(dev: pdev);
6761
6762 pcie_capability_write_word(dev: us_dev, PCI_EXP_DEVCTL, val: devctl);
6763 }
6764
6765 return 0;
6766}
6767
6768/**
6769 * __e1000e_disable_aspm - Disable ASPM states
6770 * @pdev: pointer to PCI device struct
6771 * @state: bit-mask of ASPM states to disable
6772 * @locked: indication if this context holds pci_bus_sem locked.
6773 *
6774 * Some devices *must* have certain ASPM states disabled per hardware errata.
6775 **/
6776static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6777{
6778 struct pci_dev *parent = pdev->bus->self;
6779 u16 aspm_dis_mask = 0;
6780 u16 pdev_aspmc, parent_aspmc;
6781
6782 switch (state) {
6783 case PCIE_LINK_STATE_L0S:
6784 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6785 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6786 fallthrough; /* can't have L1 without L0s */
6787 case PCIE_LINK_STATE_L1:
6788 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6789 break;
6790 default:
6791 return;
6792 }
6793
6794 pcie_capability_read_word(dev: pdev, PCI_EXP_LNKCTL, val: &pdev_aspmc);
6795 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6796
6797 if (parent) {
6798 pcie_capability_read_word(dev: parent, PCI_EXP_LNKCTL,
6799 val: &parent_aspmc);
6800 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6801 }
6802
6803 /* Nothing to do if the ASPM states to be disabled already are */
6804 if (!(pdev_aspmc & aspm_dis_mask) &&
6805 (!parent || !(parent_aspmc & aspm_dis_mask)))
6806 return;
6807
6808 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6809 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6810 "L0s" : "",
6811 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6812 "L1" : "");
6813
6814#ifdef CONFIG_PCIEASPM
6815 if (locked)
6816 pci_disable_link_state_locked(pdev, state);
6817 else
6818 pci_disable_link_state(pdev, state);
6819
6820 /* Double-check ASPM control. If not disabled by the above, the
6821 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6822 * not enabled); override by writing PCI config space directly.
6823 */
6824 pcie_capability_read_word(dev: pdev, PCI_EXP_LNKCTL, val: &pdev_aspmc);
6825 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6826
6827 if (!(aspm_dis_mask & pdev_aspmc))
6828 return;
6829#endif
6830
6831 /* Both device and parent should have the same ASPM setting.
6832 * Disable ASPM in downstream component first and then upstream.
6833 */
6834 pcie_capability_clear_word(dev: pdev, PCI_EXP_LNKCTL, clear: aspm_dis_mask);
6835
6836 if (parent)
6837 pcie_capability_clear_word(dev: parent, PCI_EXP_LNKCTL,
6838 clear: aspm_dis_mask);
6839}
6840
6841/**
6842 * e1000e_disable_aspm - Disable ASPM states.
6843 * @pdev: pointer to PCI device struct
6844 * @state: bit-mask of ASPM states to disable
6845 *
6846 * This function acquires the pci_bus_sem!
6847 * Some devices *must* have certain ASPM states disabled per hardware errata.
6848 **/
6849static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6850{
6851 __e1000e_disable_aspm(pdev, state, locked: 0);
6852}
6853
6854/**
6855 * e1000e_disable_aspm_locked - Disable ASPM states.
6856 * @pdev: pointer to PCI device struct
6857 * @state: bit-mask of ASPM states to disable
6858 *
6859 * This function must be called with pci_bus_sem acquired!
6860 * Some devices *must* have certain ASPM states disabled per hardware errata.
6861 **/
6862static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6863{
6864 __e1000e_disable_aspm(pdev, state, locked: 1);
6865}
6866
6867static int e1000e_pm_thaw(struct device *dev)
6868{
6869 struct net_device *netdev = dev_get_drvdata(dev);
6870 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
6871 int rc = 0;
6872
6873 e1000e_set_interrupt_capability(adapter);
6874
6875 rtnl_lock();
6876 if (netif_running(dev: netdev)) {
6877 rc = e1000_request_irq(adapter);
6878 if (rc)
6879 goto err_irq;
6880
6881 e1000e_up(adapter);
6882 }
6883
6884 netif_device_attach(dev: netdev);
6885err_irq:
6886 rtnl_unlock();
6887
6888 return rc;
6889}
6890
6891static int __e1000_resume(struct pci_dev *pdev)
6892{
6893 struct net_device *netdev = pci_get_drvdata(pdev);
6894 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
6895 struct e1000_hw *hw = &adapter->hw;
6896 u16 aspm_disable_flag = 0;
6897
6898 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6899 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6900 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6901 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6902 if (aspm_disable_flag)
6903 e1000e_disable_aspm(pdev, state: aspm_disable_flag);
6904
6905 pci_set_master(dev: pdev);
6906
6907 if (hw->mac.type >= e1000_pch2lan)
6908 e1000_resume_workarounds_pchlan(hw: &adapter->hw);
6909
6910 e1000e_power_up_phy(adapter);
6911
6912 /* report the system wakeup cause from S3/S4 */
6913 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6914 u16 phy_data;
6915
6916 e1e_rphy(hw: &adapter->hw, BM_WUS, data: &phy_data);
6917 if (phy_data) {
6918 e_info("PHY Wakeup cause - %s\n",
6919 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6920 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6921 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6922 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6923 phy_data & E1000_WUS_LNKC ?
6924 "Link Status Change" : "other");
6925 }
6926 e1e_wphy(hw: &adapter->hw, BM_WUS, data: ~0);
6927 } else {
6928 u32 wus = er32(WUS);
6929
6930 if (wus) {
6931 e_info("MAC Wakeup cause - %s\n",
6932 wus & E1000_WUS_EX ? "Unicast Packet" :
6933 wus & E1000_WUS_MC ? "Multicast Packet" :
6934 wus & E1000_WUS_BC ? "Broadcast Packet" :
6935 wus & E1000_WUS_MAG ? "Magic Packet" :
6936 wus & E1000_WUS_LNKC ? "Link Status Change" :
6937 "other");
6938 }
6939 ew32(WUS, ~0);
6940 }
6941
6942 e1000e_reset(adapter);
6943
6944 e1000_init_manageability_pt(adapter);
6945
6946 /* If the controller has AMT, do not set DRV_LOAD until the interface
6947 * is up. For all other cases, let the f/w know that the h/w is now
6948 * under the control of the driver.
6949 */
6950 if (!(adapter->flags & FLAG_HAS_AMT))
6951 e1000e_get_hw_control(adapter);
6952
6953 return 0;
6954}
6955
6956static __maybe_unused int e1000e_pm_prepare(struct device *dev)
6957{
6958 return pm_runtime_suspended(dev) &&
6959 pm_suspend_via_firmware();
6960}
6961
6962static __maybe_unused int e1000e_pm_suspend(struct device *dev)
6963{
6964 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6965 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
6966 struct pci_dev *pdev = to_pci_dev(dev);
6967 int rc;
6968
6969 e1000e_flush_lpic(pdev);
6970
6971 e1000e_pm_freeze(dev);
6972
6973 rc = __e1000_shutdown(pdev, runtime: false);
6974 if (rc) {
6975 e1000e_pm_thaw(dev);
6976 } else {
6977 /* Introduce S0ix implementation */
6978 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6979 e1000e_s0ix_entry_flow(adapter);
6980 }
6981
6982 return rc;
6983}
6984
6985static __maybe_unused int e1000e_pm_resume(struct device *dev)
6986{
6987 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6988 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
6989 struct pci_dev *pdev = to_pci_dev(dev);
6990 int rc;
6991
6992 /* Introduce S0ix implementation */
6993 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6994 e1000e_s0ix_exit_flow(adapter);
6995
6996 rc = __e1000_resume(pdev);
6997 if (rc)
6998 return rc;
6999
7000 return e1000e_pm_thaw(dev);
7001}
7002
7003static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev)
7004{
7005 struct net_device *netdev = dev_get_drvdata(dev);
7006 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
7007 u16 eee_lp;
7008
7009 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
7010
7011 if (!e1000e_has_link(adapter)) {
7012 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
7013 pm_schedule_suspend(dev, delay: 5 * MSEC_PER_SEC);
7014 }
7015
7016 return -EBUSY;
7017}
7018
7019static __maybe_unused int e1000e_pm_runtime_resume(struct device *dev)
7020{
7021 struct pci_dev *pdev = to_pci_dev(dev);
7022 struct net_device *netdev = pci_get_drvdata(pdev);
7023 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
7024 int rc;
7025
7026 pdev->pme_poll = true;
7027
7028 rc = __e1000_resume(pdev);
7029 if (rc)
7030 return rc;
7031
7032 if (netdev->flags & IFF_UP)
7033 e1000e_up(adapter);
7034
7035 return rc;
7036}
7037
7038static __maybe_unused int e1000e_pm_runtime_suspend(struct device *dev)
7039{
7040 struct pci_dev *pdev = to_pci_dev(dev);
7041 struct net_device *netdev = pci_get_drvdata(pdev);
7042 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
7043
7044 if (netdev->flags & IFF_UP) {
7045 int count = E1000_CHECK_RESET_COUNT;
7046
7047 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
7048 usleep_range(min: 10000, max: 11000);
7049
7050 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
7051
7052 /* Down the device without resetting the hardware */
7053 e1000e_down(adapter, reset: false);
7054 }
7055
7056 if (__e1000_shutdown(pdev, runtime: true)) {
7057 e1000e_pm_runtime_resume(dev);
7058 return -EBUSY;
7059 }
7060
7061 return 0;
7062}
7063
7064static void e1000_shutdown(struct pci_dev *pdev)
7065{
7066 e1000e_flush_lpic(pdev);
7067
7068 e1000e_pm_freeze(dev: &pdev->dev);
7069
7070 __e1000_shutdown(pdev, runtime: false);
7071}
7072
7073#ifdef CONFIG_NET_POLL_CONTROLLER
7074
7075static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
7076{
7077 struct net_device *netdev = data;
7078 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
7079
7080 if (adapter->msix_entries) {
7081 int vector, msix_irq;
7082
7083 vector = 0;
7084 msix_irq = adapter->msix_entries[vector].vector;
7085 if (disable_hardirq(irq: msix_irq))
7086 e1000_intr_msix_rx(irq: msix_irq, data: netdev);
7087 enable_irq(irq: msix_irq);
7088
7089 vector++;
7090 msix_irq = adapter->msix_entries[vector].vector;
7091 if (disable_hardirq(irq: msix_irq))
7092 e1000_intr_msix_tx(irq: msix_irq, data: netdev);
7093 enable_irq(irq: msix_irq);
7094
7095 vector++;
7096 msix_irq = adapter->msix_entries[vector].vector;
7097 if (disable_hardirq(irq: msix_irq))
7098 e1000_msix_other(irq: msix_irq, data: netdev);
7099 enable_irq(irq: msix_irq);
7100 }
7101
7102 return IRQ_HANDLED;
7103}
7104
7105/**
7106 * e1000_netpoll
7107 * @netdev: network interface device structure
7108 *
7109 * Polling 'interrupt' - used by things like netconsole to send skbs
7110 * without having to re-enable interrupts. It's not called while
7111 * the interrupt routine is executing.
7112 */
7113static void e1000_netpoll(struct net_device *netdev)
7114{
7115 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
7116
7117 switch (adapter->int_mode) {
7118 case E1000E_INT_MODE_MSIX:
7119 e1000_intr_msix(irq: adapter->pdev->irq, data: netdev);
7120 break;
7121 case E1000E_INT_MODE_MSI:
7122 if (disable_hardirq(irq: adapter->pdev->irq))
7123 e1000_intr_msi(irq: adapter->pdev->irq, data: netdev);
7124 enable_irq(irq: adapter->pdev->irq);
7125 break;
7126 default: /* E1000E_INT_MODE_LEGACY */
7127 if (disable_hardirq(irq: adapter->pdev->irq))
7128 e1000_intr(irq: adapter->pdev->irq, data: netdev);
7129 enable_irq(irq: adapter->pdev->irq);
7130 break;
7131 }
7132}
7133#endif
7134
7135/**
7136 * e1000_io_error_detected - called when PCI error is detected
7137 * @pdev: Pointer to PCI device
7138 * @state: The current pci connection state
7139 *
7140 * This function is called after a PCI bus error affecting
7141 * this device has been detected.
7142 */
7143static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
7144 pci_channel_state_t state)
7145{
7146 e1000e_pm_freeze(dev: &pdev->dev);
7147
7148 if (state == pci_channel_io_perm_failure)
7149 return PCI_ERS_RESULT_DISCONNECT;
7150
7151 pci_disable_device(dev: pdev);
7152
7153 /* Request a slot reset. */
7154 return PCI_ERS_RESULT_NEED_RESET;
7155}
7156
7157/**
7158 * e1000_io_slot_reset - called after the pci bus has been reset.
7159 * @pdev: Pointer to PCI device
7160 *
7161 * Restart the card from scratch, as if from a cold-boot. Implementation
7162 * resembles the first-half of the e1000e_pm_resume routine.
7163 */
7164static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
7165{
7166 struct net_device *netdev = pci_get_drvdata(pdev);
7167 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
7168 struct e1000_hw *hw = &adapter->hw;
7169 u16 aspm_disable_flag = 0;
7170 int err;
7171 pci_ers_result_t result;
7172
7173 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
7174 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7175 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
7176 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7177 if (aspm_disable_flag)
7178 e1000e_disable_aspm_locked(pdev, state: aspm_disable_flag);
7179
7180 err = pci_enable_device_mem(dev: pdev);
7181 if (err) {
7182 dev_err(&pdev->dev,
7183 "Cannot re-enable PCI device after reset.\n");
7184 result = PCI_ERS_RESULT_DISCONNECT;
7185 } else {
7186 pdev->state_saved = true;
7187 pci_restore_state(dev: pdev);
7188 pci_set_master(dev: pdev);
7189
7190 pci_enable_wake(dev: pdev, PCI_D3hot, enable: 0);
7191 pci_enable_wake(dev: pdev, PCI_D3cold, enable: 0);
7192
7193 e1000e_reset(adapter);
7194 ew32(WUS, ~0);
7195 result = PCI_ERS_RESULT_RECOVERED;
7196 }
7197
7198 return result;
7199}
7200
7201/**
7202 * e1000_io_resume - called when traffic can start flowing again.
7203 * @pdev: Pointer to PCI device
7204 *
7205 * This callback is called when the error recovery driver tells us that
7206 * its OK to resume normal operation. Implementation resembles the
7207 * second-half of the e1000e_pm_resume routine.
7208 */
7209static void e1000_io_resume(struct pci_dev *pdev)
7210{
7211 struct net_device *netdev = pci_get_drvdata(pdev);
7212 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
7213
7214 e1000_init_manageability_pt(adapter);
7215
7216 e1000e_pm_thaw(dev: &pdev->dev);
7217
7218 /* If the controller has AMT, do not set DRV_LOAD until the interface
7219 * is up. For all other cases, let the f/w know that the h/w is now
7220 * under the control of the driver.
7221 */
7222 if (!(adapter->flags & FLAG_HAS_AMT))
7223 e1000e_get_hw_control(adapter);
7224}
7225
7226static void e1000_print_device_info(struct e1000_adapter *adapter)
7227{
7228 struct e1000_hw *hw = &adapter->hw;
7229 struct net_device *netdev = adapter->netdev;
7230 u32 ret_val;
7231 u8 pba_str[E1000_PBANUM_LENGTH];
7232
7233 /* print bus type/speed/width info */
7234 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
7235 /* bus width */
7236 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
7237 "Width x1"),
7238 /* MAC address */
7239 netdev->dev_addr);
7240 e_info("Intel(R) PRO/%s Network Connection\n",
7241 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
7242 ret_val = e1000_read_pba_string_generic(hw, pba_num: pba_str,
7243 E1000_PBANUM_LENGTH);
7244 if (ret_val)
7245 strscpy(p: (char *)pba_str, q: "Unknown", size: sizeof(pba_str));
7246 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
7247 hw->mac.type, hw->phy.type, pba_str);
7248}
7249
7250static void e1000_eeprom_checks(struct e1000_adapter *adapter)
7251{
7252 struct e1000_hw *hw = &adapter->hw;
7253 int ret_val;
7254 u16 buf = 0;
7255
7256 if (hw->mac.type != e1000_82573)
7257 return;
7258
7259 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, words: 1, data: &buf);
7260 le16_to_cpus(&buf);
7261 if (!ret_val && (!(buf & BIT(0)))) {
7262 /* Deep Smart Power Down (DSPD) */
7263 dev_warn(&adapter->pdev->dev,
7264 "Warning: detected DSPD enabled in EEPROM\n");
7265 }
7266}
7267
7268static netdev_features_t e1000_fix_features(struct net_device *netdev,
7269 netdev_features_t features)
7270{
7271 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
7272 struct e1000_hw *hw = &adapter->hw;
7273
7274 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7275 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
7276 features &= ~NETIF_F_RXFCS;
7277
7278 /* Since there is no support for separate Rx/Tx vlan accel
7279 * enable/disable make sure Tx flag is always in same state as Rx.
7280 */
7281 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7282 features |= NETIF_F_HW_VLAN_CTAG_TX;
7283 else
7284 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
7285
7286 return features;
7287}
7288
7289static int e1000_set_features(struct net_device *netdev,
7290 netdev_features_t features)
7291{
7292 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
7293 netdev_features_t changed = features ^ netdev->features;
7294
7295 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
7296 adapter->flags |= FLAG_TSO_FORCE;
7297
7298 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7299 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
7300 NETIF_F_RXALL)))
7301 return 0;
7302
7303 if (changed & NETIF_F_RXFCS) {
7304 if (features & NETIF_F_RXFCS) {
7305 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7306 } else {
7307 /* We need to take it back to defaults, which might mean
7308 * stripping is still disabled at the adapter level.
7309 */
7310 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7311 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7312 else
7313 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7314 }
7315 }
7316
7317 netdev->features = features;
7318
7319 if (netif_running(dev: netdev))
7320 e1000e_reinit_locked(adapter);
7321 else
7322 e1000e_reset(adapter);
7323
7324 return 1;
7325}
7326
7327static const struct net_device_ops e1000e_netdev_ops = {
7328 .ndo_open = e1000e_open,
7329 .ndo_stop = e1000e_close,
7330 .ndo_start_xmit = e1000_xmit_frame,
7331 .ndo_get_stats64 = e1000e_get_stats64,
7332 .ndo_set_rx_mode = e1000e_set_rx_mode,
7333 .ndo_set_mac_address = e1000_set_mac,
7334 .ndo_change_mtu = e1000_change_mtu,
7335 .ndo_eth_ioctl = e1000_ioctl,
7336 .ndo_tx_timeout = e1000_tx_timeout,
7337 .ndo_validate_addr = eth_validate_addr,
7338
7339 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7340 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7341#ifdef CONFIG_NET_POLL_CONTROLLER
7342 .ndo_poll_controller = e1000_netpoll,
7343#endif
7344 .ndo_set_features = e1000_set_features,
7345 .ndo_fix_features = e1000_fix_features,
7346 .ndo_features_check = passthru_features_check,
7347};
7348
7349/**
7350 * e1000_probe - Device Initialization Routine
7351 * @pdev: PCI device information struct
7352 * @ent: entry in e1000_pci_tbl
7353 *
7354 * Returns 0 on success, negative on failure
7355 *
7356 * e1000_probe initializes an adapter identified by a pci_dev structure.
7357 * The OS initialization, configuring of the adapter private structure,
7358 * and a hardware reset occur.
7359 **/
7360static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7361{
7362 struct net_device *netdev;
7363 struct e1000_adapter *adapter;
7364 struct e1000_hw *hw;
7365 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7366 resource_size_t mmio_start, mmio_len;
7367 resource_size_t flash_start, flash_len;
7368 static int cards_found;
7369 u16 aspm_disable_flag = 0;
7370 u16 eeprom_data = 0;
7371 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7372 int bars, i, err;
7373 s32 ret_val = 0;
7374
7375 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7376 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7377 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7378 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7379 if (aspm_disable_flag)
7380 e1000e_disable_aspm(pdev, state: aspm_disable_flag);
7381
7382 err = pci_enable_device_mem(dev: pdev);
7383 if (err)
7384 return err;
7385
7386 err = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(64));
7387 if (err) {
7388 dev_err(&pdev->dev,
7389 "No usable DMA configuration, aborting\n");
7390 goto err_dma;
7391 }
7392
7393 bars = pci_select_bars(dev: pdev, IORESOURCE_MEM);
7394 err = pci_request_selected_regions_exclusive(pdev, bars,
7395 e1000e_driver_name);
7396 if (err)
7397 goto err_pci_reg;
7398
7399 pci_set_master(dev: pdev);
7400 /* PCI config space info */
7401 err = pci_save_state(dev: pdev);
7402 if (err)
7403 goto err_alloc_etherdev;
7404
7405 err = -ENOMEM;
7406 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7407 if (!netdev)
7408 goto err_alloc_etherdev;
7409
7410 SET_NETDEV_DEV(netdev, &pdev->dev);
7411
7412 netdev->irq = pdev->irq;
7413
7414 pci_set_drvdata(pdev, data: netdev);
7415 adapter = netdev_priv(dev: netdev);
7416 hw = &adapter->hw;
7417 adapter->netdev = netdev;
7418 adapter->pdev = pdev;
7419 adapter->ei = ei;
7420 adapter->pba = ei->pba;
7421 adapter->flags = ei->flags;
7422 adapter->flags2 = ei->flags2;
7423 adapter->hw.adapter = adapter;
7424 adapter->hw.mac.type = ei->mac;
7425 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7426 adapter->msg_enable = netif_msg_init(debug_value: debug, DEFAULT_MSG_ENABLE);
7427
7428 mmio_start = pci_resource_start(pdev, 0);
7429 mmio_len = pci_resource_len(pdev, 0);
7430
7431 err = -EIO;
7432 adapter->hw.hw_addr = ioremap(offset: mmio_start, size: mmio_len);
7433 if (!adapter->hw.hw_addr)
7434 goto err_ioremap;
7435
7436 if ((adapter->flags & FLAG_HAS_FLASH) &&
7437 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7438 (hw->mac.type < e1000_pch_spt)) {
7439 flash_start = pci_resource_start(pdev, 1);
7440 flash_len = pci_resource_len(pdev, 1);
7441 adapter->hw.flash_address = ioremap(offset: flash_start, size: flash_len);
7442 if (!adapter->hw.flash_address)
7443 goto err_flashmap;
7444 }
7445
7446 /* Set default EEE advertisement */
7447 if (adapter->flags2 & FLAG2_HAS_EEE)
7448 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7449
7450 /* construct the net_device struct */
7451 netdev->netdev_ops = &e1000e_netdev_ops;
7452 e1000e_set_ethtool_ops(netdev);
7453 netdev->watchdog_timeo = 5 * HZ;
7454 netif_napi_add(dev: netdev, napi: &adapter->napi, poll: e1000e_poll);
7455 strscpy(p: netdev->name, q: pci_name(pdev), size: sizeof(netdev->name));
7456
7457 netdev->mem_start = mmio_start;
7458 netdev->mem_end = mmio_start + mmio_len;
7459
7460 adapter->bd_number = cards_found++;
7461
7462 e1000e_check_options(adapter);
7463
7464 /* setup adapter struct */
7465 err = e1000_sw_init(adapter);
7466 if (err)
7467 goto err_sw_init;
7468
7469 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7470 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7471 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7472
7473 err = ei->get_variants(adapter);
7474 if (err)
7475 goto err_hw_init;
7476
7477 if ((adapter->flags & FLAG_IS_ICH) &&
7478 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7479 (hw->mac.type < e1000_pch_spt))
7480 e1000e_write_protect_nvm_ich8lan(hw: &adapter->hw);
7481
7482 hw->mac.ops.get_bus_info(&adapter->hw);
7483
7484 adapter->hw.phy.autoneg_wait_to_complete = 0;
7485
7486 /* Copper options */
7487 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7488 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7489 adapter->hw.phy.disable_polarity_correction = 0;
7490 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7491 }
7492
7493 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7494 dev_info(&pdev->dev,
7495 "PHY reset is blocked due to SOL/IDER session.\n");
7496
7497 /* Set initial default active device features */
7498 netdev->features = (NETIF_F_SG |
7499 NETIF_F_HW_VLAN_CTAG_RX |
7500 NETIF_F_HW_VLAN_CTAG_TX |
7501 NETIF_F_TSO |
7502 NETIF_F_TSO6 |
7503 NETIF_F_RXHASH |
7504 NETIF_F_RXCSUM |
7505 NETIF_F_HW_CSUM);
7506
7507 /* disable TSO for pcie and 10/100 speeds to avoid
7508 * some hardware issues and for i219 to fix transfer
7509 * speed being capped at 60%
7510 */
7511 if (!(adapter->flags & FLAG_TSO_FORCE)) {
7512 switch (adapter->link_speed) {
7513 case SPEED_10:
7514 case SPEED_100:
7515 e_info("10/100 speed: disabling TSO\n");
7516 netdev->features &= ~NETIF_F_TSO;
7517 netdev->features &= ~NETIF_F_TSO6;
7518 break;
7519 case SPEED_1000:
7520 netdev->features |= NETIF_F_TSO;
7521 netdev->features |= NETIF_F_TSO6;
7522 break;
7523 default:
7524 /* oops */
7525 break;
7526 }
7527 if (hw->mac.type == e1000_pch_spt) {
7528 netdev->features &= ~NETIF_F_TSO;
7529 netdev->features &= ~NETIF_F_TSO6;
7530 }
7531 }
7532
7533 /* Set user-changeable features (subset of all device features) */
7534 netdev->hw_features = netdev->features;
7535 netdev->hw_features |= NETIF_F_RXFCS;
7536 netdev->priv_flags |= IFF_SUPP_NOFCS;
7537 netdev->hw_features |= NETIF_F_RXALL;
7538
7539 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7540 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7541
7542 netdev->vlan_features |= (NETIF_F_SG |
7543 NETIF_F_TSO |
7544 NETIF_F_TSO6 |
7545 NETIF_F_HW_CSUM);
7546
7547 netdev->priv_flags |= IFF_UNICAST_FLT;
7548
7549 netdev->features |= NETIF_F_HIGHDMA;
7550 netdev->vlan_features |= NETIF_F_HIGHDMA;
7551
7552 /* MTU range: 68 - max_hw_frame_size */
7553 netdev->min_mtu = ETH_MIN_MTU;
7554 netdev->max_mtu = adapter->max_hw_frame_size -
7555 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7556
7557 if (e1000e_enable_mng_pass_thru(hw: &adapter->hw))
7558 adapter->flags |= FLAG_MNG_PT_ENABLED;
7559
7560 /* before reading the NVM, reset the controller to
7561 * put the device in a known good starting state
7562 */
7563 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7564
7565 /* systems with ASPM and others may see the checksum fail on the first
7566 * attempt. Let's give it a few tries
7567 */
7568 for (i = 0;; i++) {
7569 if (e1000_validate_nvm_checksum(hw: &adapter->hw) >= 0)
7570 break;
7571 if (i == 2) {
7572 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7573 err = -EIO;
7574 goto err_eeprom;
7575 }
7576 }
7577
7578 e1000_eeprom_checks(adapter);
7579
7580 /* copy the MAC address */
7581 if (e1000e_read_mac_addr(hw: &adapter->hw))
7582 dev_err(&pdev->dev,
7583 "NVM Read Error while reading MAC address\n");
7584
7585 eth_hw_addr_set(dev: netdev, addr: adapter->hw.mac.addr);
7586
7587 if (!is_valid_ether_addr(addr: netdev->dev_addr)) {
7588 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7589 netdev->dev_addr);
7590 err = -EIO;
7591 goto err_eeprom;
7592 }
7593
7594 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7595 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7596
7597 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7598 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7599 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7600 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7601 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7602
7603 /* Initialize link parameters. User can change them with ethtool */
7604 adapter->hw.mac.autoneg = 1;
7605 adapter->fc_autoneg = true;
7606 adapter->hw.fc.requested_mode = e1000_fc_default;
7607 adapter->hw.fc.current_mode = e1000_fc_default;
7608 adapter->hw.phy.autoneg_advertised = 0x2f;
7609
7610 /* Initial Wake on LAN setting - If APM wake is enabled in
7611 * the EEPROM, enable the ACPI Magic Packet filter
7612 */
7613 if (adapter->flags & FLAG_APME_IN_WUC) {
7614 /* APME bit in EEPROM is mapped to WUC.APME */
7615 eeprom_data = er32(WUC);
7616 eeprom_apme_mask = E1000_WUC_APME;
7617 if ((hw->mac.type > e1000_ich10lan) &&
7618 (eeprom_data & E1000_WUC_PHY_WAKE))
7619 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7620 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7621 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7622 (adapter->hw.bus.func == 1))
7623 ret_val = e1000_read_nvm(hw: &adapter->hw,
7624 NVM_INIT_CONTROL3_PORT_B,
7625 words: 1, data: &eeprom_data);
7626 else
7627 ret_val = e1000_read_nvm(hw: &adapter->hw,
7628 NVM_INIT_CONTROL3_PORT_A,
7629 words: 1, data: &eeprom_data);
7630 }
7631
7632 /* fetch WoL from EEPROM */
7633 if (ret_val)
7634 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7635 else if (eeprom_data & eeprom_apme_mask)
7636 adapter->eeprom_wol |= E1000_WUFC_MAG;
7637
7638 /* now that we have the eeprom settings, apply the special cases
7639 * where the eeprom may be wrong or the board simply won't support
7640 * wake on lan on a particular port
7641 */
7642 if (!(adapter->flags & FLAG_HAS_WOL))
7643 adapter->eeprom_wol = 0;
7644
7645 /* initialize the wol settings based on the eeprom settings */
7646 adapter->wol = adapter->eeprom_wol;
7647
7648 /* make sure adapter isn't asleep if manageability is enabled */
7649 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7650 (hw->mac.ops.check_mng_mode(hw)))
7651 device_wakeup_enable(dev: &pdev->dev);
7652
7653 /* save off EEPROM version number */
7654 ret_val = e1000_read_nvm(hw: &adapter->hw, offset: 5, words: 1, data: &adapter->eeprom_vers);
7655
7656 if (ret_val) {
7657 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7658 adapter->eeprom_vers = 0;
7659 }
7660
7661 /* init PTP hardware clock */
7662 e1000e_ptp_init(adapter);
7663
7664 /* reset the hardware with the new settings */
7665 e1000e_reset(adapter);
7666
7667 /* If the controller has AMT, do not set DRV_LOAD until the interface
7668 * is up. For all other cases, let the f/w know that the h/w is now
7669 * under the control of the driver.
7670 */
7671 if (!(adapter->flags & FLAG_HAS_AMT))
7672 e1000e_get_hw_control(adapter);
7673
7674 if (hw->mac.type >= e1000_pch_cnp)
7675 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS;
7676
7677 strscpy(p: netdev->name, q: "eth%d", size: sizeof(netdev->name));
7678 err = register_netdev(dev: netdev);
7679 if (err)
7680 goto err_register;
7681
7682 /* carrier off reporting is important to ethtool even BEFORE open */
7683 netif_carrier_off(dev: netdev);
7684
7685 e1000_print_device_info(adapter);
7686
7687 dev_pm_set_driver_flags(dev: &pdev->dev, DPM_FLAG_SMART_PREPARE);
7688
7689 if (pci_dev_run_wake(dev: pdev))
7690 pm_runtime_put_noidle(dev: &pdev->dev);
7691
7692 return 0;
7693
7694err_register:
7695 if (!(adapter->flags & FLAG_HAS_AMT))
7696 e1000e_release_hw_control(adapter);
7697err_eeprom:
7698 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7699 e1000_phy_hw_reset(hw: &adapter->hw);
7700err_hw_init:
7701 kfree(objp: adapter->tx_ring);
7702 kfree(objp: adapter->rx_ring);
7703err_sw_init:
7704 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7705 iounmap(addr: adapter->hw.flash_address);
7706 e1000e_reset_interrupt_capability(adapter);
7707err_flashmap:
7708 iounmap(addr: adapter->hw.hw_addr);
7709err_ioremap:
7710 free_netdev(dev: netdev);
7711err_alloc_etherdev:
7712 pci_release_mem_regions(pdev);
7713err_pci_reg:
7714err_dma:
7715 pci_disable_device(dev: pdev);
7716 return err;
7717}
7718
7719/**
7720 * e1000_remove - Device Removal Routine
7721 * @pdev: PCI device information struct
7722 *
7723 * e1000_remove is called by the PCI subsystem to alert the driver
7724 * that it should release a PCI device. This could be caused by a
7725 * Hot-Plug event, or because the driver is going to be removed from
7726 * memory.
7727 **/
7728static void e1000_remove(struct pci_dev *pdev)
7729{
7730 struct net_device *netdev = pci_get_drvdata(pdev);
7731 struct e1000_adapter *adapter = netdev_priv(dev: netdev);
7732
7733 e1000e_ptp_remove(adapter);
7734
7735 /* The timers may be rescheduled, so explicitly disable them
7736 * from being rescheduled.
7737 */
7738 set_bit(nr: __E1000_DOWN, addr: &adapter->state);
7739 del_timer_sync(timer: &adapter->watchdog_timer);
7740 del_timer_sync(timer: &adapter->phy_info_timer);
7741
7742 cancel_work_sync(work: &adapter->reset_task);
7743 cancel_work_sync(work: &adapter->watchdog_task);
7744 cancel_work_sync(work: &adapter->downshift_task);
7745 cancel_work_sync(work: &adapter->update_phy_task);
7746 cancel_work_sync(work: &adapter->print_hang_task);
7747
7748 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7749 cancel_work_sync(work: &adapter->tx_hwtstamp_work);
7750 if (adapter->tx_hwtstamp_skb) {
7751 dev_consume_skb_any(skb: adapter->tx_hwtstamp_skb);
7752 adapter->tx_hwtstamp_skb = NULL;
7753 }
7754 }
7755
7756 unregister_netdev(dev: netdev);
7757
7758 if (pci_dev_run_wake(dev: pdev))
7759 pm_runtime_get_noresume(dev: &pdev->dev);
7760
7761 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7762 * would have already happened in close and is redundant.
7763 */
7764 e1000e_release_hw_control(adapter);
7765
7766 e1000e_reset_interrupt_capability(adapter);
7767 kfree(objp: adapter->tx_ring);
7768 kfree(objp: adapter->rx_ring);
7769
7770 iounmap(addr: adapter->hw.hw_addr);
7771 if ((adapter->hw.flash_address) &&
7772 (adapter->hw.mac.type < e1000_pch_spt))
7773 iounmap(addr: adapter->hw.flash_address);
7774 pci_release_mem_regions(pdev);
7775
7776 free_netdev(dev: netdev);
7777
7778 pci_disable_device(dev: pdev);
7779}
7780
7781/* PCI Error Recovery (ERS) */
7782static const struct pci_error_handlers e1000_err_handler = {
7783 .error_detected = e1000_io_error_detected,
7784 .slot_reset = e1000_io_slot_reset,
7785 .resume = e1000_io_resume,
7786};
7787
7788static const struct pci_device_id e1000_pci_tbl[] = {
7789 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7790 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7791 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7792 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7793 board_82571 },
7794 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7795 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7796 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7798 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7799
7800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7802 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7804
7805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7807 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7808
7809 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7811 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7812
7813 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7814 board_80003es2lan },
7815 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7816 board_80003es2lan },
7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7818 board_80003es2lan },
7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7820 board_80003es2lan },
7821
7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7826 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7830
7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7840
7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7844
7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7848
7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7853
7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7856
7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7858 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7865 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7867 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7868 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7870 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7871 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7872 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7876 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7881 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp },
7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp },
7884 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp },
7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp },
7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt },
7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt },
7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp },
7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp },
7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp },
7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp },
7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp },
7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp },
7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_adp },
7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_adp },
7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_adp },
7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_adp },
7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_adp },
7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_adp },
7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_adp },
7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_adp },
7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_mtp },
7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_mtp },
7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_mtp },
7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V19), board_pch_mtp },
7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_mtp },
7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_mtp },
7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_mtp },
7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_mtp },
7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), board_pch_mtp },
7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), board_pch_mtp },
7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), board_pch_mtp },
7913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), board_pch_mtp },
7914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM26), board_pch_mtp },
7915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp },
7916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp },
7917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp },
7918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29), board_pch_mtp },
7919 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29), board_pch_mtp },
7920
7921 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
7922};
7923MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7924
7925static const struct dev_pm_ops e1000_pm_ops = {
7926#ifdef CONFIG_PM_SLEEP
7927 .prepare = e1000e_pm_prepare,
7928 .suspend = e1000e_pm_suspend,
7929 .resume = e1000e_pm_resume,
7930 .freeze = e1000e_pm_freeze,
7931 .thaw = e1000e_pm_thaw,
7932 .poweroff = e1000e_pm_suspend,
7933 .restore = e1000e_pm_resume,
7934#endif
7935 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7936 e1000e_pm_runtime_idle)
7937};
7938
7939/* PCI Device API Driver */
7940static struct pci_driver e1000_driver = {
7941 .name = e1000e_driver_name,
7942 .id_table = e1000_pci_tbl,
7943 .probe = e1000_probe,
7944 .remove = e1000_remove,
7945 .driver = {
7946 .pm = &e1000_pm_ops,
7947 },
7948 .shutdown = e1000_shutdown,
7949 .err_handler = &e1000_err_handler
7950};
7951
7952/**
7953 * e1000_init_module - Driver Registration Routine
7954 *
7955 * e1000_init_module is the first routine called when the driver is
7956 * loaded. All it does is register with the PCI subsystem.
7957 **/
7958static int __init e1000_init_module(void)
7959{
7960 pr_info("Intel(R) PRO/1000 Network Driver\n");
7961 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7962
7963 return pci_register_driver(&e1000_driver);
7964}
7965module_init(e1000_init_module);
7966
7967/**
7968 * e1000_exit_module - Driver Exit Cleanup Routine
7969 *
7970 * e1000_exit_module is called just before the driver is removed
7971 * from memory.
7972 **/
7973static void __exit e1000_exit_module(void)
7974{
7975 pci_unregister_driver(dev: &e1000_driver);
7976}
7977module_exit(e1000_exit_module);
7978
7979MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7980MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7981MODULE_LICENSE("GPL v2");
7982
7983/* netdev.c */
7984

source code of linux/drivers/net/ethernet/intel/e1000e/netdev.c