1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright(c) 2013 - 2018 Intel Corporation. */ |
3 | |
4 | #ifndef _I40E_TXRX_H_ |
5 | #define _I40E_TXRX_H_ |
6 | |
7 | #include <net/xdp.h> |
8 | #include "i40e_type.h" |
9 | |
10 | /* Interrupt Throttling and Rate Limiting Goodies */ |
11 | #define I40E_DEFAULT_IRQ_WORK 256 |
12 | |
13 | /* The datasheet for the X710 and XL710 indicate that the maximum value for |
14 | * the ITR is 8160usec which is then called out as 0xFF0 with a 2usec |
15 | * resolution. 8160 is 0x1FE0 when written out in hex. So instead of storing |
16 | * the register value which is divided by 2 lets use the actual values and |
17 | * avoid an excessive amount of translation. |
18 | */ |
19 | #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ |
20 | #define I40E_ITR_MASK 0x1FFE /* mask for ITR register value */ |
21 | #define I40E_MIN_ITR 2 /* reg uses 2 usec resolution */ |
22 | #define I40E_ITR_20K 50 |
23 | #define I40E_ITR_8K 122 |
24 | #define I40E_MAX_ITR 8160 /* maximum value as per datasheet */ |
25 | #define ITR_TO_REG(setting) ((setting) & ~I40E_ITR_DYNAMIC) |
26 | #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~I40E_ITR_MASK) |
27 | #define ITR_IS_DYNAMIC(setting) (!!((setting) & I40E_ITR_DYNAMIC)) |
28 | |
29 | #define I40E_ITR_RX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC) |
30 | #define I40E_ITR_TX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC) |
31 | |
32 | /* 0x40 is the enable bit for interrupt rate limiting, and must be set if |
33 | * the value of the rate limit is non-zero |
34 | */ |
35 | #define INTRL_ENA BIT(6) |
36 | #define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */ |
37 | #define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2) |
38 | |
39 | /** |
40 | * i40e_intrl_usec_to_reg - convert interrupt rate limit to register |
41 | * @intrl: interrupt rate limit to convert |
42 | * |
43 | * This function converts a decimal interrupt rate limit to the appropriate |
44 | * register format expected by the firmware when setting interrupt rate limit. |
45 | */ |
46 | static inline u16 i40e_intrl_usec_to_reg(int intrl) |
47 | { |
48 | if (intrl >> 2) |
49 | return ((intrl >> 2) | INTRL_ENA); |
50 | else |
51 | return 0; |
52 | } |
53 | |
54 | #define I40E_QUEUE_END_OF_LIST 0x7FF |
55 | |
56 | /* this enum matches hardware bits and is meant to be used by DYN_CTLN |
57 | * registers and QINT registers or more generally anywhere in the manual |
58 | * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any |
59 | * register but instead is a special value meaning "don't update" ITR0/1/2. |
60 | */ |
61 | enum i40e_dyn_idx_t { |
62 | I40E_IDX_ITR0 = 0, |
63 | I40E_IDX_ITR1 = 1, |
64 | I40E_IDX_ITR2 = 2, |
65 | I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ |
66 | }; |
67 | |
68 | /* these are indexes into ITRN registers */ |
69 | #define I40E_RX_ITR I40E_IDX_ITR0 |
70 | #define I40E_TX_ITR I40E_IDX_ITR1 |
71 | |
72 | /* Supported RSS offloads */ |
73 | #define ( \ |
74 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ |
75 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ |
76 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ |
77 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ |
78 | BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ |
79 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ |
80 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ |
81 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ |
82 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ |
83 | BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ |
84 | BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) |
85 | |
86 | #define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \ |
87 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ |
88 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ |
89 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ |
90 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ |
91 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ |
92 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP)) |
93 | |
94 | #define (pf) \ |
95 | (((pf)->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \ |
96 | I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA) |
97 | |
98 | /* Supported Rx Buffer Sizes (a multiple of 128) */ |
99 | #define I40E_RXBUFFER_256 256 |
100 | #define I40E_RXBUFFER_1536 1536 /* 128B aligned standard Ethernet frame */ |
101 | #define I40E_RXBUFFER_2048 2048 |
102 | #define I40E_RXBUFFER_3072 3072 /* Used for large frames w/ padding */ |
103 | #define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ |
104 | |
105 | /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we |
106 | * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, |
107 | * this adds up to 512 bytes of extra data meaning the smallest allocation |
108 | * we could have is 1K. |
109 | * i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab) |
110 | * i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab) |
111 | */ |
112 | #define I40E_RX_HDR_SIZE I40E_RXBUFFER_256 |
113 | #define I40E_PACKET_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)) |
114 | #define i40e_rx_desc i40e_16byte_rx_desc |
115 | |
116 | #define I40E_RX_DMA_ATTR \ |
117 | (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) |
118 | |
119 | /* Attempt to maximize the headroom available for incoming frames. We |
120 | * use a 2K buffer for receives and need 1536/1534 to store the data for |
121 | * the frame. This leaves us with 512 bytes of room. From that we need |
122 | * to deduct the space needed for the shared info and the padding needed |
123 | * to IP align the frame. |
124 | * |
125 | * Note: For cache line sizes 256 or larger this value is going to end |
126 | * up negative. In these cases we should fall back to the legacy |
127 | * receive path. |
128 | */ |
129 | #if (PAGE_SIZE < 8192) |
130 | #define I40E_2K_TOO_SMALL_WITH_PADDING \ |
131 | ((NET_SKB_PAD + I40E_RXBUFFER_1536) > SKB_WITH_OVERHEAD(I40E_RXBUFFER_2048)) |
132 | |
133 | static inline int i40e_compute_pad(int rx_buf_len) |
134 | { |
135 | int page_size, pad_size; |
136 | |
137 | page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); |
138 | pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; |
139 | |
140 | return pad_size; |
141 | } |
142 | |
143 | static inline int i40e_skb_pad(void) |
144 | { |
145 | int rx_buf_len; |
146 | |
147 | /* If a 2K buffer cannot handle a standard Ethernet frame then |
148 | * optimize padding for a 3K buffer instead of a 1.5K buffer. |
149 | * |
150 | * For a 3K buffer we need to add enough padding to allow for |
151 | * tailroom due to NET_IP_ALIGN possibly shifting us out of |
152 | * cache-line alignment. |
153 | */ |
154 | if (I40E_2K_TOO_SMALL_WITH_PADDING) |
155 | rx_buf_len = I40E_RXBUFFER_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN); |
156 | else |
157 | rx_buf_len = I40E_RXBUFFER_1536; |
158 | |
159 | /* if needed make room for NET_IP_ALIGN */ |
160 | rx_buf_len -= NET_IP_ALIGN; |
161 | |
162 | return i40e_compute_pad(rx_buf_len); |
163 | } |
164 | |
165 | #define I40E_SKB_PAD i40e_skb_pad() |
166 | #else |
167 | #define I40E_2K_TOO_SMALL_WITH_PADDING false |
168 | #define I40E_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) |
169 | #endif |
170 | |
171 | /** |
172 | * i40e_test_staterr - tests bits in Rx descriptor status and error fields |
173 | * @rx_desc: pointer to receive descriptor (in le64 format) |
174 | * @stat_err_bits: value to mask |
175 | * |
176 | * This function does some fast chicanery in order to return the |
177 | * value of the mask which is really only used for boolean tests. |
178 | * The status_error_len doesn't need to be shifted because it begins |
179 | * at offset zero. |
180 | */ |
181 | static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc, |
182 | const u64 stat_err_bits) |
183 | { |
184 | return !!(rx_desc->wb.qword1.status_error_len & |
185 | cpu_to_le64(stat_err_bits)); |
186 | } |
187 | |
188 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
189 | #define I40E_RX_BUFFER_WRITE 32 /* Must be power of 2 */ |
190 | |
191 | #define I40E_RX_NEXT_DESC(r, i, n) \ |
192 | do { \ |
193 | (i)++; \ |
194 | if ((i) == (r)->count) \ |
195 | i = 0; \ |
196 | (n) = I40E_RX_DESC((r), (i)); \ |
197 | } while (0) |
198 | |
199 | |
200 | #define I40E_MAX_BUFFER_TXD 8 |
201 | #define I40E_MIN_TX_LEN 17 |
202 | |
203 | /* The size limit for a transmit buffer in a descriptor is (16K - 1). |
204 | * In order to align with the read requests we will align the value to |
205 | * the nearest 4K which represents our maximum read request size. |
206 | */ |
207 | #define I40E_MAX_READ_REQ_SIZE 4096 |
208 | #define I40E_MAX_DATA_PER_TXD (16 * 1024 - 1) |
209 | #define I40E_MAX_DATA_PER_TXD_ALIGNED \ |
210 | (I40E_MAX_DATA_PER_TXD & ~(I40E_MAX_READ_REQ_SIZE - 1)) |
211 | |
212 | /** |
213 | * i40e_txd_use_count - estimate the number of descriptors needed for Tx |
214 | * @size: transmit request size in bytes |
215 | * |
216 | * Due to hardware alignment restrictions (4K alignment), we need to |
217 | * assume that we can have no more than 12K of data per descriptor, even |
218 | * though each descriptor can take up to 16K - 1 bytes of aligned memory. |
219 | * Thus, we need to divide by 12K. But division is slow! Instead, |
220 | * we decompose the operation into shifts and one relatively cheap |
221 | * multiply operation. |
222 | * |
223 | * To divide by 12K, we first divide by 4K, then divide by 3: |
224 | * To divide by 4K, shift right by 12 bits |
225 | * To divide by 3, multiply by 85, then divide by 256 |
226 | * (Divide by 256 is done by shifting right by 8 bits) |
227 | * Finally, we add one to round up. Because 256 isn't an exact multiple of |
228 | * 3, we'll underestimate near each multiple of 12K. This is actually more |
229 | * accurate as we have 4K - 1 of wiggle room that we can fit into the last |
230 | * segment. For our purposes this is accurate out to 1M which is orders of |
231 | * magnitude greater than our largest possible GSO size. |
232 | * |
233 | * This would then be implemented as: |
234 | * return (((size >> 12) * 85) >> 8) + 1; |
235 | * |
236 | * Since multiplication and division are commutative, we can reorder |
237 | * operations into: |
238 | * return ((size * 85) >> 20) + 1; |
239 | */ |
240 | static inline unsigned int i40e_txd_use_count(unsigned int size) |
241 | { |
242 | return ((size * 85) >> 20) + 1; |
243 | } |
244 | |
245 | /* Tx Descriptors needed, worst case */ |
246 | #define DESC_NEEDED (MAX_SKB_FRAGS + 6) |
247 | |
248 | #define I40E_TX_FLAGS_HW_VLAN BIT(1) |
249 | #define I40E_TX_FLAGS_SW_VLAN BIT(2) |
250 | #define I40E_TX_FLAGS_TSO BIT(3) |
251 | #define I40E_TX_FLAGS_IPV4 BIT(4) |
252 | #define I40E_TX_FLAGS_IPV6 BIT(5) |
253 | #define I40E_TX_FLAGS_TSYN BIT(8) |
254 | #define I40E_TX_FLAGS_FD_SB BIT(9) |
255 | #define I40E_TX_FLAGS_UDP_TUNNEL BIT(10) |
256 | #define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 |
257 | #define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
258 | #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 |
259 | #define I40E_TX_FLAGS_VLAN_SHIFT 16 |
260 | |
261 | struct i40e_tx_buffer { |
262 | struct i40e_tx_desc *next_to_watch; |
263 | union { |
264 | struct xdp_frame *xdpf; |
265 | struct sk_buff *skb; |
266 | void *raw_buf; |
267 | }; |
268 | unsigned int bytecount; |
269 | unsigned short gso_segs; |
270 | |
271 | DEFINE_DMA_UNMAP_ADDR(dma); |
272 | DEFINE_DMA_UNMAP_LEN(len); |
273 | u32 tx_flags; |
274 | }; |
275 | |
276 | struct i40e_rx_buffer { |
277 | dma_addr_t dma; |
278 | struct page *page; |
279 | __u32 page_offset; |
280 | __u16 pagecnt_bias; |
281 | __u32 page_count; |
282 | }; |
283 | |
284 | struct i40e_queue_stats { |
285 | u64 packets; |
286 | u64 bytes; |
287 | }; |
288 | |
289 | struct i40e_tx_queue_stats { |
290 | u64 restart_queue; |
291 | u64 tx_busy; |
292 | u64 tx_done_old; |
293 | u64 tx_linearize; |
294 | u64 tx_force_wb; |
295 | u64 tx_stopped; |
296 | int prev_pkt_ctr; |
297 | }; |
298 | |
299 | struct i40e_rx_queue_stats { |
300 | u64 non_eop_descs; |
301 | u64 alloc_page_failed; |
302 | u64 alloc_buff_failed; |
303 | u64 page_reuse_count; |
304 | u64 page_alloc_count; |
305 | u64 page_waive_count; |
306 | u64 page_busy_count; |
307 | }; |
308 | |
309 | enum i40e_ring_state_t { |
310 | __I40E_TX_FDIR_INIT_DONE, |
311 | __I40E_TX_XPS_INIT_DONE, |
312 | __I40E_RING_STATE_NBITS /* must be last */ |
313 | }; |
314 | |
315 | /* some useful defines for virtchannel interface, which |
316 | * is the only remaining user of header split |
317 | */ |
318 | #define 1 |
319 | #define I40E_RX_SPLIT_L2 0x1 |
320 | #define I40E_RX_SPLIT_IP 0x2 |
321 | #define I40E_RX_SPLIT_TCP_UDP 0x4 |
322 | #define I40E_RX_SPLIT_SCTP 0x8 |
323 | |
324 | /* struct that defines a descriptor ring, associated with a VSI */ |
325 | struct i40e_ring { |
326 | struct i40e_ring *next; /* pointer to next ring in q_vector */ |
327 | void *desc; /* Descriptor ring memory */ |
328 | struct device *dev; /* Used for DMA mapping */ |
329 | struct net_device *netdev; /* netdev ring maps to */ |
330 | struct bpf_prog *xdp_prog; |
331 | union { |
332 | struct i40e_tx_buffer *tx_bi; |
333 | struct i40e_rx_buffer *rx_bi; |
334 | struct xdp_buff **rx_bi_zc; |
335 | }; |
336 | DECLARE_BITMAP(state, __I40E_RING_STATE_NBITS); |
337 | u16 queue_index; /* Queue number of ring */ |
338 | u8 dcb_tc; /* Traffic class of ring */ |
339 | u8 __iomem *tail; |
340 | |
341 | /* Storing xdp_buff on ring helps in saving the state of partially built |
342 | * packet when i40e_clean_rx_ring_irq() must return before it sees EOP |
343 | * and to resume packet building for this ring in the next call to |
344 | * i40e_clean_rx_ring_irq(). |
345 | */ |
346 | struct xdp_buff xdp; |
347 | |
348 | /* Next descriptor to be processed; next_to_clean is updated only on |
349 | * processing EOP descriptor |
350 | */ |
351 | u16 next_to_process; |
352 | /* high bit set means dynamic, use accessor routines to read/write. |
353 | * hardware only supports 2us resolution for the ITR registers. |
354 | * these values always store the USER setting, and must be converted |
355 | * before programming to a register. |
356 | */ |
357 | u16 itr_setting; |
358 | |
359 | u16 count; /* Number of descriptors */ |
360 | u16 reg_idx; /* HW register index of the ring */ |
361 | u16 rx_buf_len; |
362 | |
363 | /* used in interrupt processing */ |
364 | u16 next_to_use; |
365 | u16 next_to_clean; |
366 | u16 xdp_tx_active; |
367 | |
368 | u8 atr_sample_rate; |
369 | u8 atr_count; |
370 | |
371 | bool ring_active; /* is ring online or not */ |
372 | bool arm_wb; /* do something to arm write back */ |
373 | u8 packet_stride; |
374 | |
375 | u16 flags; |
376 | #define I40E_TXR_FLAGS_WB_ON_ITR BIT(0) |
377 | #define I40E_RXR_FLAGS_BUILD_SKB_ENABLED BIT(1) |
378 | #define I40E_TXR_FLAGS_XDP BIT(2) |
379 | |
380 | /* stats structs */ |
381 | struct i40e_queue_stats stats; |
382 | struct u64_stats_sync syncp; |
383 | union { |
384 | struct i40e_tx_queue_stats tx_stats; |
385 | struct i40e_rx_queue_stats rx_stats; |
386 | }; |
387 | |
388 | unsigned int size; /* length of descriptor ring in bytes */ |
389 | dma_addr_t dma; /* physical address of ring */ |
390 | |
391 | struct i40e_vsi *vsi; /* Backreference to associated VSI */ |
392 | struct i40e_q_vector *q_vector; /* Backreference to associated vector */ |
393 | |
394 | struct rcu_head rcu; /* to avoid race on free */ |
395 | u16 next_to_alloc; |
396 | |
397 | struct i40e_channel *ch; |
398 | u16 rx_offset; |
399 | struct xdp_rxq_info xdp_rxq; |
400 | struct xsk_buff_pool *xsk_pool; |
401 | } ____cacheline_internodealigned_in_smp; |
402 | |
403 | static inline bool ring_uses_build_skb(struct i40e_ring *ring) |
404 | { |
405 | return !!(ring->flags & I40E_RXR_FLAGS_BUILD_SKB_ENABLED); |
406 | } |
407 | |
408 | static inline void set_ring_build_skb_enabled(struct i40e_ring *ring) |
409 | { |
410 | ring->flags |= I40E_RXR_FLAGS_BUILD_SKB_ENABLED; |
411 | } |
412 | |
413 | static inline void clear_ring_build_skb_enabled(struct i40e_ring *ring) |
414 | { |
415 | ring->flags &= ~I40E_RXR_FLAGS_BUILD_SKB_ENABLED; |
416 | } |
417 | |
418 | static inline bool ring_is_xdp(struct i40e_ring *ring) |
419 | { |
420 | return !!(ring->flags & I40E_TXR_FLAGS_XDP); |
421 | } |
422 | |
423 | static inline void set_ring_xdp(struct i40e_ring *ring) |
424 | { |
425 | ring->flags |= I40E_TXR_FLAGS_XDP; |
426 | } |
427 | |
428 | #define I40E_ITR_ADAPTIVE_MIN_INC 0x0002 |
429 | #define I40E_ITR_ADAPTIVE_MIN_USECS 0x0002 |
430 | #define I40E_ITR_ADAPTIVE_MAX_USECS 0x007e |
431 | #define I40E_ITR_ADAPTIVE_LATENCY 0x8000 |
432 | #define I40E_ITR_ADAPTIVE_BULK 0x0000 |
433 | |
434 | struct i40e_ring_container { |
435 | struct i40e_ring *ring; /* pointer to linked list of ring(s) */ |
436 | unsigned long next_update; /* jiffies value of next update */ |
437 | unsigned int total_bytes; /* total bytes processed this int */ |
438 | unsigned int total_packets; /* total packets processed this int */ |
439 | u16 count; |
440 | u16 target_itr; /* target ITR setting for ring(s) */ |
441 | u16 current_itr; /* current ITR setting for ring(s) */ |
442 | }; |
443 | |
444 | /* iterator for handling rings in ring container */ |
445 | #define i40e_for_each_ring(pos, head) \ |
446 | for (pos = (head).ring; pos != NULL; pos = pos->next) |
447 | |
448 | static inline unsigned int i40e_rx_pg_order(struct i40e_ring *ring) |
449 | { |
450 | #if (PAGE_SIZE < 8192) |
451 | if (ring->rx_buf_len > (PAGE_SIZE / 2)) |
452 | return 1; |
453 | #endif |
454 | return 0; |
455 | } |
456 | |
457 | #define i40e_rx_pg_size(_ring) (PAGE_SIZE << i40e_rx_pg_order(_ring)) |
458 | |
459 | bool i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); |
460 | netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); |
461 | u16 i40e_lan_select_queue(struct net_device *netdev, struct sk_buff *skb, |
462 | struct net_device *sb_dev); |
463 | void i40e_clean_tx_ring(struct i40e_ring *tx_ring); |
464 | void i40e_clean_rx_ring(struct i40e_ring *rx_ring); |
465 | int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); |
466 | int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); |
467 | void i40e_free_tx_resources(struct i40e_ring *tx_ring); |
468 | void i40e_free_rx_resources(struct i40e_ring *rx_ring); |
469 | int i40e_napi_poll(struct napi_struct *napi, int budget); |
470 | void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector); |
471 | u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw); |
472 | void i40e_detect_recover_hung(struct i40e_vsi *vsi); |
473 | int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size); |
474 | bool __i40e_chk_linearize(struct sk_buff *skb); |
475 | int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames, |
476 | u32 flags); |
477 | bool i40e_is_non_eop(struct i40e_ring *rx_ring, |
478 | union i40e_rx_desc *rx_desc); |
479 | |
480 | /** |
481 | * i40e_get_head - Retrieve head from head writeback |
482 | * @tx_ring: tx ring to fetch head of |
483 | * |
484 | * Returns value of Tx ring head based on value stored |
485 | * in head write-back location |
486 | **/ |
487 | static inline u32 i40e_get_head(struct i40e_ring *tx_ring) |
488 | { |
489 | void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count; |
490 | |
491 | return le32_to_cpu(*(volatile __le32 *)head); |
492 | } |
493 | |
494 | /** |
495 | * i40e_xmit_descriptor_count - calculate number of Tx descriptors needed |
496 | * @skb: send buffer |
497 | * |
498 | * Returns number of data descriptors needed for this skb. Returns 0 to indicate |
499 | * there is not enough descriptors available in this ring since we need at least |
500 | * one descriptor. |
501 | **/ |
502 | static inline int i40e_xmit_descriptor_count(struct sk_buff *skb) |
503 | { |
504 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; |
505 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; |
506 | int count = 0, size = skb_headlen(skb); |
507 | |
508 | for (;;) { |
509 | count += i40e_txd_use_count(size); |
510 | |
511 | if (!nr_frags--) |
512 | break; |
513 | |
514 | size = skb_frag_size(frag: frag++); |
515 | } |
516 | |
517 | return count; |
518 | } |
519 | |
520 | /** |
521 | * i40e_maybe_stop_tx - 1st level check for Tx stop conditions |
522 | * @tx_ring: the ring to be checked |
523 | * @size: the size buffer we want to assure is available |
524 | * |
525 | * Returns 0 if stop is not needed |
526 | **/ |
527 | static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) |
528 | { |
529 | if (likely(I40E_DESC_UNUSED(tx_ring) >= size)) |
530 | return 0; |
531 | return __i40e_maybe_stop_tx(tx_ring, size); |
532 | } |
533 | |
534 | /** |
535 | * i40e_chk_linearize - Check if there are more than 8 fragments per packet |
536 | * @skb: send buffer |
537 | * @count: number of buffers used |
538 | * |
539 | * Note: Our HW can't scatter-gather more than 8 fragments to build |
540 | * a packet on the wire and so we need to figure out the cases where we |
541 | * need to linearize the skb. |
542 | **/ |
543 | static inline bool i40e_chk_linearize(struct sk_buff *skb, int count) |
544 | { |
545 | /* Both TSO and single send will work if count is less than 8 */ |
546 | if (likely(count < I40E_MAX_BUFFER_TXD)) |
547 | return false; |
548 | |
549 | if (skb_is_gso(skb)) |
550 | return __i40e_chk_linearize(skb); |
551 | |
552 | /* we can support up to 8 data buffers for a single send */ |
553 | return count != I40E_MAX_BUFFER_TXD; |
554 | } |
555 | |
556 | /** |
557 | * txring_txq - Find the netdev Tx ring based on the i40e Tx ring |
558 | * @ring: Tx ring to find the netdev equivalent of |
559 | **/ |
560 | static inline struct netdev_queue *txring_txq(const struct i40e_ring *ring) |
561 | { |
562 | return netdev_get_tx_queue(dev: ring->netdev, index: ring->queue_index); |
563 | } |
564 | #endif /* _I40E_TXRX_H_ */ |
565 | |