1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright(c) 2013 - 2018 Intel Corporation. */ |
3 | |
4 | #ifndef _IAVF_ADMINQ_CMD_H_ |
5 | #define _IAVF_ADMINQ_CMD_H_ |
6 | |
7 | /* This header file defines the iavf Admin Queue commands and is shared between |
8 | * iavf Firmware and Software. |
9 | * |
10 | * This file needs to comply with the Linux Kernel coding style. |
11 | */ |
12 | |
13 | #define IAVF_FW_API_VERSION_MAJOR 0x0001 |
14 | #define IAVF_FW_API_VERSION_MINOR_X722 0x0005 |
15 | #define IAVF_FW_API_VERSION_MINOR_X710 0x0008 |
16 | |
17 | #define IAVF_FW_MINOR_VERSION(_h) ((_h)->mac.type == IAVF_MAC_XL710 ? \ |
18 | IAVF_FW_API_VERSION_MINOR_X710 : \ |
19 | IAVF_FW_API_VERSION_MINOR_X722) |
20 | |
21 | /* API version 1.7 implements additional link and PHY-specific APIs */ |
22 | #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007 |
23 | |
24 | struct iavf_aq_desc { |
25 | __le16 flags; |
26 | __le16 opcode; |
27 | __le16 datalen; |
28 | __le16 retval; |
29 | __le32 cookie_high; |
30 | __le32 cookie_low; |
31 | union { |
32 | struct { |
33 | __le32 param0; |
34 | __le32 param1; |
35 | __le32 param2; |
36 | __le32 param3; |
37 | } internal; |
38 | struct { |
39 | __le32 param0; |
40 | __le32 param1; |
41 | __le32 addr_high; |
42 | __le32 addr_low; |
43 | } external; |
44 | u8 raw[16]; |
45 | } params; |
46 | }; |
47 | |
48 | /* Flags sub-structure |
49 | * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | |
50 | * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | |
51 | */ |
52 | |
53 | /* command flags and offsets*/ |
54 | #define IAVF_AQ_FLAG_DD_SHIFT 0 |
55 | #define IAVF_AQ_FLAG_CMP_SHIFT 1 |
56 | #define IAVF_AQ_FLAG_ERR_SHIFT 2 |
57 | #define IAVF_AQ_FLAG_VFE_SHIFT 3 |
58 | #define IAVF_AQ_FLAG_LB_SHIFT 9 |
59 | #define IAVF_AQ_FLAG_RD_SHIFT 10 |
60 | #define IAVF_AQ_FLAG_VFC_SHIFT 11 |
61 | #define IAVF_AQ_FLAG_BUF_SHIFT 12 |
62 | #define IAVF_AQ_FLAG_SI_SHIFT 13 |
63 | #define IAVF_AQ_FLAG_EI_SHIFT 14 |
64 | #define IAVF_AQ_FLAG_FE_SHIFT 15 |
65 | |
66 | #define IAVF_AQ_FLAG_DD BIT(IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */ |
67 | #define IAVF_AQ_FLAG_CMP BIT(IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */ |
68 | #define IAVF_AQ_FLAG_ERR BIT(IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */ |
69 | #define IAVF_AQ_FLAG_VFE BIT(IAVF_AQ_FLAG_VFE_SHIFT) /* 0x8 */ |
70 | #define IAVF_AQ_FLAG_LB BIT(IAVF_AQ_FLAG_LB_SHIFT) /* 0x200 */ |
71 | #define IAVF_AQ_FLAG_RD BIT(IAVF_AQ_FLAG_RD_SHIFT) /* 0x400 */ |
72 | #define IAVF_AQ_FLAG_VFC BIT(IAVF_AQ_FLAG_VFC_SHIFT) /* 0x800 */ |
73 | #define IAVF_AQ_FLAG_BUF BIT(IAVF_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ |
74 | #define IAVF_AQ_FLAG_SI BIT(IAVF_AQ_FLAG_SI_SHIFT) /* 0x2000 */ |
75 | #define IAVF_AQ_FLAG_EI BIT(IAVF_AQ_FLAG_EI_SHIFT) /* 0x4000 */ |
76 | #define IAVF_AQ_FLAG_FE BIT(IAVF_AQ_FLAG_FE_SHIFT) /* 0x8000 */ |
77 | |
78 | /* error codes */ |
79 | enum iavf_admin_queue_err { |
80 | IAVF_AQ_RC_OK = 0, /* success */ |
81 | IAVF_AQ_RC_EPERM = 1, /* Operation not permitted */ |
82 | IAVF_AQ_RC_ENOENT = 2, /* No such element */ |
83 | IAVF_AQ_RC_ESRCH = 3, /* Bad opcode */ |
84 | IAVF_AQ_RC_EINTR = 4, /* operation interrupted */ |
85 | IAVF_AQ_RC_EIO = 5, /* I/O error */ |
86 | IAVF_AQ_RC_ENXIO = 6, /* No such resource */ |
87 | IAVF_AQ_RC_E2BIG = 7, /* Arg too long */ |
88 | IAVF_AQ_RC_EAGAIN = 8, /* Try again */ |
89 | IAVF_AQ_RC_ENOMEM = 9, /* Out of memory */ |
90 | IAVF_AQ_RC_EACCES = 10, /* Permission denied */ |
91 | IAVF_AQ_RC_EFAULT = 11, /* Bad address */ |
92 | IAVF_AQ_RC_EBUSY = 12, /* Device or resource busy */ |
93 | IAVF_AQ_RC_EEXIST = 13, /* object already exists */ |
94 | IAVF_AQ_RC_EINVAL = 14, /* Invalid argument */ |
95 | IAVF_AQ_RC_ENOTTY = 15, /* Not a typewriter */ |
96 | IAVF_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ |
97 | IAVF_AQ_RC_ENOSYS = 17, /* Function not implemented */ |
98 | IAVF_AQ_RC_ERANGE = 18, /* Parameter out of range */ |
99 | IAVF_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ |
100 | IAVF_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ |
101 | IAVF_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ |
102 | IAVF_AQ_RC_EFBIG = 22, /* File too large */ |
103 | }; |
104 | |
105 | /* Admin Queue command opcodes */ |
106 | enum iavf_admin_queue_opc { |
107 | /* aq commands */ |
108 | iavf_aqc_opc_get_version = 0x0001, |
109 | iavf_aqc_opc_driver_version = 0x0002, |
110 | iavf_aqc_opc_queue_shutdown = 0x0003, |
111 | iavf_aqc_opc_set_pf_context = 0x0004, |
112 | |
113 | /* resource ownership */ |
114 | iavf_aqc_opc_request_resource = 0x0008, |
115 | iavf_aqc_opc_release_resource = 0x0009, |
116 | |
117 | iavf_aqc_opc_list_func_capabilities = 0x000A, |
118 | iavf_aqc_opc_list_dev_capabilities = 0x000B, |
119 | |
120 | /* Proxy commands */ |
121 | iavf_aqc_opc_set_proxy_config = 0x0104, |
122 | iavf_aqc_opc_set_ns_proxy_table_entry = 0x0105, |
123 | |
124 | /* LAA */ |
125 | iavf_aqc_opc_mac_address_read = 0x0107, |
126 | iavf_aqc_opc_mac_address_write = 0x0108, |
127 | |
128 | /* PXE */ |
129 | iavf_aqc_opc_clear_pxe_mode = 0x0110, |
130 | |
131 | /* WoL commands */ |
132 | iavf_aqc_opc_set_wol_filter = 0x0120, |
133 | iavf_aqc_opc_get_wake_reason = 0x0121, |
134 | |
135 | /* internal switch commands */ |
136 | iavf_aqc_opc_get_switch_config = 0x0200, |
137 | iavf_aqc_opc_add_statistics = 0x0201, |
138 | iavf_aqc_opc_remove_statistics = 0x0202, |
139 | iavf_aqc_opc_set_port_parameters = 0x0203, |
140 | iavf_aqc_opc_get_switch_resource_alloc = 0x0204, |
141 | iavf_aqc_opc_set_switch_config = 0x0205, |
142 | iavf_aqc_opc_rx_ctl_reg_read = 0x0206, |
143 | iavf_aqc_opc_rx_ctl_reg_write = 0x0207, |
144 | |
145 | iavf_aqc_opc_add_vsi = 0x0210, |
146 | iavf_aqc_opc_update_vsi_parameters = 0x0211, |
147 | iavf_aqc_opc_get_vsi_parameters = 0x0212, |
148 | |
149 | iavf_aqc_opc_add_pv = 0x0220, |
150 | iavf_aqc_opc_update_pv_parameters = 0x0221, |
151 | iavf_aqc_opc_get_pv_parameters = 0x0222, |
152 | |
153 | iavf_aqc_opc_add_veb = 0x0230, |
154 | iavf_aqc_opc_update_veb_parameters = 0x0231, |
155 | iavf_aqc_opc_get_veb_parameters = 0x0232, |
156 | |
157 | iavf_aqc_opc_delete_element = 0x0243, |
158 | |
159 | iavf_aqc_opc_add_macvlan = 0x0250, |
160 | iavf_aqc_opc_remove_macvlan = 0x0251, |
161 | iavf_aqc_opc_add_vlan = 0x0252, |
162 | iavf_aqc_opc_remove_vlan = 0x0253, |
163 | iavf_aqc_opc_set_vsi_promiscuous_modes = 0x0254, |
164 | iavf_aqc_opc_add_tag = 0x0255, |
165 | iavf_aqc_opc_remove_tag = 0x0256, |
166 | iavf_aqc_opc_add_multicast_etag = 0x0257, |
167 | iavf_aqc_opc_remove_multicast_etag = 0x0258, |
168 | iavf_aqc_opc_update_tag = 0x0259, |
169 | iavf_aqc_opc_add_control_packet_filter = 0x025A, |
170 | iavf_aqc_opc_remove_control_packet_filter = 0x025B, |
171 | iavf_aqc_opc_add_cloud_filters = 0x025C, |
172 | iavf_aqc_opc_remove_cloud_filters = 0x025D, |
173 | iavf_aqc_opc_clear_wol_switch_filters = 0x025E, |
174 | |
175 | iavf_aqc_opc_add_mirror_rule = 0x0260, |
176 | iavf_aqc_opc_delete_mirror_rule = 0x0261, |
177 | |
178 | /* Dynamic Device Personalization */ |
179 | iavf_aqc_opc_write_personalization_profile = 0x0270, |
180 | iavf_aqc_opc_get_personalization_profile_list = 0x0271, |
181 | |
182 | /* DCB commands */ |
183 | iavf_aqc_opc_dcb_ignore_pfc = 0x0301, |
184 | iavf_aqc_opc_dcb_updated = 0x0302, |
185 | iavf_aqc_opc_set_dcb_parameters = 0x0303, |
186 | |
187 | /* TX scheduler */ |
188 | iavf_aqc_opc_configure_vsi_bw_limit = 0x0400, |
189 | iavf_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, |
190 | iavf_aqc_opc_configure_vsi_tc_bw = 0x0407, |
191 | iavf_aqc_opc_query_vsi_bw_config = 0x0408, |
192 | iavf_aqc_opc_query_vsi_ets_sla_config = 0x040A, |
193 | iavf_aqc_opc_configure_switching_comp_bw_limit = 0x0410, |
194 | |
195 | iavf_aqc_opc_enable_switching_comp_ets = 0x0413, |
196 | iavf_aqc_opc_modify_switching_comp_ets = 0x0414, |
197 | iavf_aqc_opc_disable_switching_comp_ets = 0x0415, |
198 | iavf_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, |
199 | iavf_aqc_opc_configure_switching_comp_bw_config = 0x0417, |
200 | iavf_aqc_opc_query_switching_comp_ets_config = 0x0418, |
201 | iavf_aqc_opc_query_port_ets_config = 0x0419, |
202 | iavf_aqc_opc_query_switching_comp_bw_config = 0x041A, |
203 | iavf_aqc_opc_suspend_port_tx = 0x041B, |
204 | iavf_aqc_opc_resume_port_tx = 0x041C, |
205 | iavf_aqc_opc_configure_partition_bw = 0x041D, |
206 | /* hmc */ |
207 | iavf_aqc_opc_query_hmc_resource_profile = 0x0500, |
208 | iavf_aqc_opc_set_hmc_resource_profile = 0x0501, |
209 | |
210 | /* phy commands*/ |
211 | iavf_aqc_opc_get_phy_abilities = 0x0600, |
212 | iavf_aqc_opc_set_phy_config = 0x0601, |
213 | iavf_aqc_opc_set_mac_config = 0x0603, |
214 | iavf_aqc_opc_set_link_restart_an = 0x0605, |
215 | iavf_aqc_opc_get_link_status = 0x0607, |
216 | iavf_aqc_opc_set_phy_int_mask = 0x0613, |
217 | iavf_aqc_opc_get_local_advt_reg = 0x0614, |
218 | iavf_aqc_opc_set_local_advt_reg = 0x0615, |
219 | iavf_aqc_opc_get_partner_advt = 0x0616, |
220 | iavf_aqc_opc_set_lb_modes = 0x0618, |
221 | iavf_aqc_opc_get_phy_wol_caps = 0x0621, |
222 | iavf_aqc_opc_set_phy_debug = 0x0622, |
223 | iavf_aqc_opc_upload_ext_phy_fm = 0x0625, |
224 | iavf_aqc_opc_run_phy_activity = 0x0626, |
225 | iavf_aqc_opc_set_phy_register = 0x0628, |
226 | iavf_aqc_opc_get_phy_register = 0x0629, |
227 | |
228 | /* NVM commands */ |
229 | iavf_aqc_opc_nvm_read = 0x0701, |
230 | iavf_aqc_opc_nvm_erase = 0x0702, |
231 | iavf_aqc_opc_nvm_update = 0x0703, |
232 | iavf_aqc_opc_nvm_config_read = 0x0704, |
233 | iavf_aqc_opc_nvm_config_write = 0x0705, |
234 | iavf_aqc_opc_oem_post_update = 0x0720, |
235 | iavf_aqc_opc_thermal_sensor = 0x0721, |
236 | |
237 | /* virtualization commands */ |
238 | iavf_aqc_opc_send_msg_to_pf = 0x0801, |
239 | iavf_aqc_opc_send_msg_to_vf = 0x0802, |
240 | iavf_aqc_opc_send_msg_to_peer = 0x0803, |
241 | |
242 | /* alternate structure */ |
243 | iavf_aqc_opc_alternate_write = 0x0900, |
244 | iavf_aqc_opc_alternate_write_indirect = 0x0901, |
245 | iavf_aqc_opc_alternate_read = 0x0902, |
246 | iavf_aqc_opc_alternate_read_indirect = 0x0903, |
247 | iavf_aqc_opc_alternate_write_done = 0x0904, |
248 | iavf_aqc_opc_alternate_set_mode = 0x0905, |
249 | iavf_aqc_opc_alternate_clear_port = 0x0906, |
250 | |
251 | /* LLDP commands */ |
252 | iavf_aqc_opc_lldp_get_mib = 0x0A00, |
253 | iavf_aqc_opc_lldp_update_mib = 0x0A01, |
254 | iavf_aqc_opc_lldp_add_tlv = 0x0A02, |
255 | iavf_aqc_opc_lldp_update_tlv = 0x0A03, |
256 | iavf_aqc_opc_lldp_delete_tlv = 0x0A04, |
257 | iavf_aqc_opc_lldp_stop = 0x0A05, |
258 | iavf_aqc_opc_lldp_start = 0x0A06, |
259 | |
260 | /* Tunnel commands */ |
261 | iavf_aqc_opc_add_udp_tunnel = 0x0B00, |
262 | iavf_aqc_opc_del_udp_tunnel = 0x0B01, |
263 | = 0x0B02, |
264 | = 0x0B03, |
265 | = 0x0B04, |
266 | = 0x0B05, |
267 | |
268 | /* Async Events */ |
269 | iavf_aqc_opc_event_lan_overflow = 0x1001, |
270 | |
271 | /* OEM commands */ |
272 | iavf_aqc_opc_oem_parameter_change = 0xFE00, |
273 | iavf_aqc_opc_oem_device_status_change = 0xFE01, |
274 | iavf_aqc_opc_oem_ocsd_initialize = 0xFE02, |
275 | iavf_aqc_opc_oem_ocbb_initialize = 0xFE03, |
276 | |
277 | /* debug commands */ |
278 | iavf_aqc_opc_debug_read_reg = 0xFF03, |
279 | iavf_aqc_opc_debug_write_reg = 0xFF04, |
280 | iavf_aqc_opc_debug_modify_reg = 0xFF07, |
281 | iavf_aqc_opc_debug_dump_internals = 0xFF08, |
282 | }; |
283 | |
284 | /* command structures and indirect data structures */ |
285 | |
286 | /* Structure naming conventions: |
287 | * - no suffix for direct command descriptor structures |
288 | * - _data for indirect sent data |
289 | * - _resp for indirect return data (data which is both will use _data) |
290 | * - _completion for direct return data |
291 | * - _element_ for repeated elements (may also be _data or _resp) |
292 | * |
293 | * Command structures are expected to overlay the params.raw member of the basic |
294 | * descriptor, and as such cannot exceed 16 bytes in length. |
295 | */ |
296 | |
297 | /* This macro is used to generate a compilation error if a structure |
298 | * is not exactly the correct length. It gives a divide by zero error if the |
299 | * structure is not of the correct size, otherwise it creates an enum that is |
300 | * never used. |
301 | */ |
302 | #define IAVF_CHECK_STRUCT_LEN(n, X) enum iavf_static_assert_enum_##X \ |
303 | { iavf_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) } |
304 | |
305 | /* This macro is used extensively to ensure that command structures are 16 |
306 | * bytes in length as they have to map to the raw array of that size. |
307 | */ |
308 | #define IAVF_CHECK_CMD_LENGTH(X) IAVF_CHECK_STRUCT_LEN(16, X) |
309 | |
310 | /* Queue Shutdown (direct 0x0003) */ |
311 | struct iavf_aqc_queue_shutdown { |
312 | __le32 driver_unloading; |
313 | #define IAVF_AQ_DRIVER_UNLOADING 0x1 |
314 | u8 reserved[12]; |
315 | }; |
316 | |
317 | IAVF_CHECK_CMD_LENGTH(iavf_aqc_queue_shutdown); |
318 | |
319 | struct iavf_aqc_vsi_properties_data { |
320 | /* first 96 byte are written by SW */ |
321 | __le16 valid_sections; |
322 | #define IAVF_AQ_VSI_PROP_SWITCH_VALID 0x0001 |
323 | #define IAVF_AQ_VSI_PROP_SECURITY_VALID 0x0002 |
324 | #define IAVF_AQ_VSI_PROP_VLAN_VALID 0x0004 |
325 | #define IAVF_AQ_VSI_PROP_CAS_PV_VALID 0x0008 |
326 | #define IAVF_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 |
327 | #define IAVF_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 |
328 | #define IAVF_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 |
329 | #define IAVF_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 |
330 | #define IAVF_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 |
331 | #define IAVF_AQ_VSI_PROP_SCHED_VALID 0x0200 |
332 | /* switch section */ |
333 | __le16 switch_id; /* 12bit id combined with flags below */ |
334 | #define IAVF_AQ_VSI_SW_ID_SHIFT 0x0000 |
335 | #define IAVF_AQ_VSI_SW_ID_MASK (0xFFF << IAVF_AQ_VSI_SW_ID_SHIFT) |
336 | #define IAVF_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 |
337 | #define IAVF_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 |
338 | #define IAVF_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 |
339 | u8 sw_reserved[2]; |
340 | /* security section */ |
341 | u8 sec_flags; |
342 | #define IAVF_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 |
343 | #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 |
344 | #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 |
345 | u8 sec_reserved; |
346 | /* VLAN section */ |
347 | __le16 pvid; /* VLANS include priority bits */ |
348 | __le16 fcoe_pvid; |
349 | u8 port_vlan_flags; |
350 | #define IAVF_AQ_VSI_PVLAN_MODE_SHIFT 0x00 |
351 | #define IAVF_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ |
352 | IAVF_AQ_VSI_PVLAN_MODE_SHIFT) |
353 | #define IAVF_AQ_VSI_PVLAN_MODE_TAGGED 0x01 |
354 | #define IAVF_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 |
355 | #define IAVF_AQ_VSI_PVLAN_MODE_ALL 0x03 |
356 | #define IAVF_AQ_VSI_PVLAN_INSERT_PVID 0x04 |
357 | #define IAVF_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 |
358 | #define IAVF_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ |
359 | IAVF_AQ_VSI_PVLAN_EMOD_SHIFT) |
360 | #define IAVF_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 |
361 | #define IAVF_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 |
362 | #define IAVF_AQ_VSI_PVLAN_EMOD_STR 0x10 |
363 | #define IAVF_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 |
364 | u8 pvlan_reserved[3]; |
365 | /* ingress egress up sections */ |
366 | __le32 ingress_table; /* bitmap, 3 bits per up */ |
367 | #define IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT 0 |
368 | #define IAVF_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ |
369 | IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT) |
370 | #define IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT 3 |
371 | #define IAVF_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ |
372 | IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT) |
373 | #define IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT 6 |
374 | #define IAVF_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ |
375 | IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT) |
376 | #define IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT 9 |
377 | #define IAVF_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ |
378 | IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT) |
379 | #define IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT 12 |
380 | #define IAVF_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ |
381 | IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT) |
382 | #define IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT 15 |
383 | #define IAVF_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ |
384 | IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT) |
385 | #define IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT 18 |
386 | #define IAVF_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ |
387 | IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT) |
388 | #define IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT 21 |
389 | #define IAVF_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ |
390 | IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT) |
391 | __le32 egress_table; /* same defines as for ingress table */ |
392 | /* cascaded PV section */ |
393 | __le16 cas_pv_tag; |
394 | u8 cas_pv_flags; |
395 | #define IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 |
396 | #define IAVF_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ |
397 | IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT) |
398 | #define IAVF_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 |
399 | #define IAVF_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 |
400 | #define IAVF_AQ_VSI_CAS_PV_TAGX_COPY 0x02 |
401 | #define IAVF_AQ_VSI_CAS_PV_INSERT_TAG 0x10 |
402 | #define IAVF_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 |
403 | #define IAVF_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 |
404 | u8 cas_pv_reserved; |
405 | /* queue mapping section */ |
406 | __le16 mapping_flags; |
407 | #define IAVF_AQ_VSI_QUE_MAP_CONTIG 0x0 |
408 | #define IAVF_AQ_VSI_QUE_MAP_NONCONTIG 0x1 |
409 | __le16 queue_mapping[16]; |
410 | #define IAVF_AQ_VSI_QUEUE_SHIFT 0x0 |
411 | #define IAVF_AQ_VSI_QUEUE_MASK (0x7FF << IAVF_AQ_VSI_QUEUE_SHIFT) |
412 | __le16 tc_mapping[8]; |
413 | #define IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 |
414 | #define IAVF_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ |
415 | IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
416 | #define IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 |
417 | #define IAVF_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ |
418 | IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT) |
419 | /* queueing option section */ |
420 | u8 queueing_opt_flags; |
421 | #define IAVF_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 |
422 | #define IAVF_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 |
423 | #define IAVF_AQ_VSI_QUE_OPT_TCP_ENA 0x10 |
424 | #define IAVF_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 |
425 | #define 0x00 |
426 | #define 0x40 |
427 | u8 queueing_opt_reserved[3]; |
428 | /* scheduler section */ |
429 | u8 up_enable_bits; |
430 | u8 sched_reserved; |
431 | /* outer up section */ |
432 | __le32 outer_up_table; /* same structure and defines as ingress tbl */ |
433 | u8 cmd_reserved[8]; |
434 | /* last 32 bytes are written by FW */ |
435 | __le16 qs_handle[8]; |
436 | #define IAVF_AQ_VSI_QS_HANDLE_INVALID 0xFFFF |
437 | __le16 stat_counter_idx; |
438 | __le16 sched_id; |
439 | u8 resp_reserved[12]; |
440 | }; |
441 | |
442 | IAVF_CHECK_STRUCT_LEN(128, iavf_aqc_vsi_properties_data); |
443 | |
444 | /* Get VEB Parameters (direct 0x0232) |
445 | * uses iavf_aqc_switch_seid for the descriptor |
446 | */ |
447 | struct iavf_aqc_get_veb_parameters_completion { |
448 | __le16 seid; |
449 | __le16 switch_id; |
450 | __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ |
451 | __le16 statistic_index; |
452 | __le16 vebs_used; |
453 | __le16 vebs_free; |
454 | u8 reserved[4]; |
455 | }; |
456 | |
457 | IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion); |
458 | |
459 | #define IAVF_LINK_SPEED_100MB_SHIFT 0x1 |
460 | #define IAVF_LINK_SPEED_1000MB_SHIFT 0x2 |
461 | #define IAVF_LINK_SPEED_10GB_SHIFT 0x3 |
462 | #define IAVF_LINK_SPEED_40GB_SHIFT 0x4 |
463 | #define IAVF_LINK_SPEED_20GB_SHIFT 0x5 |
464 | #define IAVF_LINK_SPEED_25GB_SHIFT 0x6 |
465 | |
466 | enum iavf_aq_link_speed { |
467 | IAVF_LINK_SPEED_UNKNOWN = 0, |
468 | IAVF_LINK_SPEED_100MB = BIT(IAVF_LINK_SPEED_100MB_SHIFT), |
469 | IAVF_LINK_SPEED_1GB = BIT(IAVF_LINK_SPEED_1000MB_SHIFT), |
470 | IAVF_LINK_SPEED_10GB = BIT(IAVF_LINK_SPEED_10GB_SHIFT), |
471 | IAVF_LINK_SPEED_40GB = BIT(IAVF_LINK_SPEED_40GB_SHIFT), |
472 | IAVF_LINK_SPEED_20GB = BIT(IAVF_LINK_SPEED_20GB_SHIFT), |
473 | IAVF_LINK_SPEED_25GB = BIT(IAVF_LINK_SPEED_25GB_SHIFT), |
474 | }; |
475 | |
476 | /* Send to PF command (indirect 0x0801) id is only used by PF |
477 | * Send to VF command (indirect 0x0802) id is only used by PF |
478 | * Send to Peer PF command (indirect 0x0803) |
479 | */ |
480 | struct iavf_aqc_pf_vf_message { |
481 | __le32 id; |
482 | u8 reserved[4]; |
483 | __le32 addr_high; |
484 | __le32 addr_low; |
485 | }; |
486 | |
487 | IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message); |
488 | |
489 | struct { |
490 | #define BIT(15) |
491 | #define 0 |
492 | #define (0x3FF << \ |
493 | IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT) |
494 | __le16 ; |
495 | u8 [6]; |
496 | __le32 ; |
497 | __le32 ; |
498 | }; |
499 | |
500 | IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_key); |
501 | |
502 | struct { |
503 | u8 standard_rss_key[0x28]; |
504 | u8 [0xc]; |
505 | }; |
506 | |
507 | IAVF_CHECK_STRUCT_LEN(0x34, iavf_aqc_get_set_rss_key_data); |
508 | |
509 | struct { |
510 | #define BIT(15) |
511 | #define 0 |
512 | #define (0x3FF << \ |
513 | IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT) |
514 | __le16 ; |
515 | #define 0 |
516 | #define \ |
517 | BIT(IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) |
518 | |
519 | #define 0 |
520 | #define 1 |
521 | __le16 ; |
522 | u8 [4]; |
523 | __le32 ; |
524 | __le32 ; |
525 | }; |
526 | |
527 | IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_lut); |
528 | #endif /* _IAVF_ADMINQ_CMD_H_ */ |
529 | |