| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Copyright(c) 2013 - 2018 Intel Corporation. */ |
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| 3 | |
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| 4 | #ifndef _IAVF_REGISTER_H_ |
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| 5 | #define _IAVF_REGISTER_H_ |
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| 6 | |
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| 7 | #define IAVF_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ |
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| 8 | #define IAVF_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ |
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| 9 | #define IAVF_VF_ARQH1 0x00007400 /* Reset: EMPR */ |
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| 10 | #define IAVF_VF_ARQH1_ARQH_SHIFT 0 |
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| 11 | #define IAVF_VF_ARQH1_ARQH_MASK IAVF_MASK(0x3FF, IAVF_VF_ARQH1_ARQH_SHIFT) |
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| 12 | #define IAVF_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ |
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| 13 | #define IAVF_VF_ARQLEN1_ARQVFE_SHIFT 28 |
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| 14 | #define IAVF_VF_ARQLEN1_ARQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQVFE_SHIFT) |
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| 15 | #define IAVF_VF_ARQLEN1_ARQOVFL_SHIFT 29 |
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| 16 | #define IAVF_VF_ARQLEN1_ARQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQOVFL_SHIFT) |
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| 17 | #define IAVF_VF_ARQLEN1_ARQCRIT_SHIFT 30 |
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| 18 | #define IAVF_VF_ARQLEN1_ARQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQCRIT_SHIFT) |
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| 19 | #define IAVF_VF_ARQLEN1_ARQENABLE_SHIFT 31 |
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| 20 | #define IAVF_VF_ARQLEN1_ARQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQENABLE_SHIFT) |
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| 21 | #define IAVF_VF_ARQT1 0x00007000 /* Reset: EMPR */ |
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| 22 | #define IAVF_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ |
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| 23 | #define IAVF_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ |
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| 24 | #define IAVF_VF_ATQH1 0x00006400 /* Reset: EMPR */ |
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| 25 | #define IAVF_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ |
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| 26 | #define IAVF_VF_ATQLEN1_ATQVFE_SHIFT 28 |
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| 27 | #define IAVF_VF_ATQLEN1_ATQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQVFE_SHIFT) |
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| 28 | #define IAVF_VF_ATQLEN1_ATQOVFL_SHIFT 29 |
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| 29 | #define IAVF_VF_ATQLEN1_ATQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQOVFL_SHIFT) |
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| 30 | #define IAVF_VF_ATQLEN1_ATQCRIT_SHIFT 30 |
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| 31 | #define IAVF_VF_ATQLEN1_ATQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQCRIT_SHIFT) |
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| 32 | #define IAVF_VF_ATQLEN1_ATQENABLE_SHIFT 31 |
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| 33 | #define IAVF_VF_ATQLEN1_ATQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQENABLE_SHIFT) |
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| 34 | #define IAVF_VF_ATQT1 0x00008400 /* Reset: EMPR */ |
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| 35 | #define IAVF_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ |
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| 36 | #define IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT 0 |
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| 37 | #define IAVF_VFGEN_RSTAT_VFR_STATE_MASK IAVF_MASK(0x3, IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT) |
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| 38 | #define IAVF_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ |
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| 39 | #define IAVF_VFINT_DYN_CTL01_INTENA_SHIFT 0 |
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| 40 | #define IAVF_VFINT_DYN_CTL01_INTENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTL01_INTENA_SHIFT) |
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| 41 | #define IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3 |
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| 42 | #define IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
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| 43 | #define IAVF_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...63 */ /* Reset: VFR */ |
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| 44 | #define IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT 0 |
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| 45 | #define IAVF_VFINT_DYN_CTLN1_INTENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT) |
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| 46 | #define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 |
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| 47 | #define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) |
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| 48 | #define IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 |
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| 49 | #define IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
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| 50 | #define IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5 |
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| 51 | #define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 |
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| 52 | #define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) |
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| 53 | #define IAVF_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */ |
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| 54 | #define IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30 |
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| 55 | #define IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK IAVF_MASK(0x1, IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT) |
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| 56 | #define IAVF_VFINT_ICR0_ENA1_RSVD_SHIFT 31 |
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| 57 | #define IAVF_VFINT_ICR01 0x00004800 /* Reset: CORER */ |
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| 58 | #define IAVF_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ |
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| 59 | #define IAVF_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ |
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| 60 | #define IAVF_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ |
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| 61 | #define IAVF_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ |
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| 62 | #define IAVF_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ |
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| 63 | #define IAVF_VFQF_HKEY_MAX_INDEX 12 |
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| 64 | #define IAVF_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ |
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| 65 | #define IAVF_VFQF_HLUT_MAX_INDEX 15 |
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| 66 | #define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30 |
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| 67 | #define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT) |
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| 68 | #endif /* _IAVF_REGISTER_H_ */ |
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| 69 | |
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