1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_COMMON_H_
5#define _ICE_COMMON_H_
6
7#include <linux/bitfield.h>
8
9#include "ice_type.h"
10#include "ice_nvm.h"
11#include "ice_flex_pipe.h"
12#include <linux/avf/virtchnl.h>
13#include "ice_switch.h"
14#include "ice_fdir.h"
15
16#define ICE_SQ_SEND_DELAY_TIME_MS 10
17#define ICE_SQ_SEND_MAX_EXECUTE 3
18
19int ice_init_hw(struct ice_hw *hw);
20void ice_deinit_hw(struct ice_hw *hw);
21int ice_check_reset(struct ice_hw *hw);
22int ice_reset(struct ice_hw *hw, enum ice_reset_req req);
23int ice_create_all_ctrlq(struct ice_hw *hw);
24int ice_init_all_ctrlq(struct ice_hw *hw);
25void ice_shutdown_all_ctrlq(struct ice_hw *hw);
26void ice_destroy_all_ctrlq(struct ice_hw *hw);
27int
28ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
29 struct ice_rq_event_info *e, u16 *pending);
30int
31ice_get_link_status(struct ice_port_info *pi, bool *link_up);
32int ice_update_link_info(struct ice_port_info *pi);
33int
34ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
35 enum ice_aq_res_access_type access, u32 timeout);
36void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
37int
38ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
39int
40ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
41int ice_aq_alloc_free_res(struct ice_hw *hw,
42 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
43 enum ice_adminq_opc opc);
44bool ice_is_sbq_supported(struct ice_hw *hw);
45struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw);
46int
47ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
48 struct ice_aq_desc *desc, void *buf, u16 buf_size,
49 struct ice_sq_cd *cd);
50void ice_clear_pxe_mode(struct ice_hw *hw);
51int ice_get_caps(struct ice_hw *hw);
52
53void ice_set_safe_mode_caps(struct ice_hw *hw);
54
55int
56ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
57 u32 rxq_index);
58
59int
60ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);
61int
62ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params);
63int
64ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
65 struct ice_aqc_get_set_rss_keys *keys);
66int
67ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
68 struct ice_aqc_get_set_rss_keys *keys);
69
70bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
71int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
72void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
73extern const struct ice_ctx_ele ice_tlan_ctx_info[];
74int
75ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
76 const struct ice_ctx_ele *ce_info);
77
78extern struct mutex ice_global_cfg_lock_sw;
79
80int
81ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
82 void *buf, u16 buf_size, struct ice_sq_cd *cd);
83int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
84
85int
86ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
87 struct ice_sq_cd *cd);
88int
89ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,
90 struct ice_sq_cd *cd);
91int
92ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
93 struct ice_aqc_get_phy_caps_data *caps,
94 struct ice_sq_cd *cd);
95bool ice_is_pf_c827(struct ice_hw *hw);
96bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw);
97bool ice_is_clock_mux_in_netlist(struct ice_hw *hw);
98bool ice_is_cgu_in_netlist(struct ice_hw *hw);
99bool ice_is_gps_in_netlist(struct ice_hw *hw);
100int
101ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd,
102 u8 *node_part_number, u16 *node_handle);
103int
104ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
105 enum ice_adminq_opc opc, struct ice_sq_cd *cd);
106int
107ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps);
108void
109ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
110 u16 link_speeds_bitmap);
111int
112ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
113 struct ice_sq_cd *cd);
114bool ice_is_e810(struct ice_hw *hw);
115int ice_clear_pf_cfg(struct ice_hw *hw);
116int
117ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
118 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
119bool ice_fw_supports_link_override(struct ice_hw *hw);
120int
121ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
122 struct ice_port_info *pi);
123bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
124
125enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
126enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
127int
128ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
129 bool ena_auto_link_update);
130int
131ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
132 enum ice_fc_mode req_mode);
133bool
134ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
135 struct ice_aqc_set_phy_cfg_data *cfg);
136void
137ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
138 struct ice_aqc_get_phy_caps_data *caps,
139 struct ice_aqc_set_phy_cfg_data *cfg);
140int
141ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
142 enum ice_fec_mode fec);
143int
144ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
145 struct ice_sq_cd *cd);
146int
147ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
148int
149ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
150 struct ice_link_status *link, struct ice_sq_cd *cd);
151int
152ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
153 struct ice_sq_cd *cd);
154int
155ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
156
157int
158ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
159 struct ice_sq_cd *cd);
160int
161ice_aq_get_port_options(struct ice_hw *hw,
162 struct ice_aqc_get_port_options_elem *options,
163 u8 *option_count, u8 lport, bool lport_valid,
164 u8 *active_option_idx, bool *active_option_valid,
165 u8 *pending_option_idx, bool *pending_option_valid);
166int
167ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
168 u8 new_option);
169int
170ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
171 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
172 bool write, struct ice_sq_cd *cd);
173u32 ice_get_link_speed(u16 index);
174
175int
176ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
177 u16 *max_rdmaqs);
178int
179ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
180 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid);
181int
182ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid,
183 u16 *q_id);
184int
185ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
186 u16 *q_handle, u16 *q_ids, u32 *q_teids,
187 enum ice_disq_rst_src rst_src, u16 vmvf_num,
188 struct ice_sq_cd *cd);
189int
190ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
191 u16 *max_lanqs);
192int
193ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
194 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
195 struct ice_sq_cd *cd);
196int
197ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,
198 u16 buf_size, u16 num_qs, u8 oldport, u8 newport,
199 struct ice_sq_cd *cd);
200int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
201void ice_replay_post(struct ice_hw *hw);
202void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf);
203struct ice_q_ctx *
204ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
205int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in);
206int
207ice_aq_get_cgu_abilities(struct ice_hw *hw,
208 struct ice_aqc_get_cgu_abilities *abilities);
209int
210ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2,
211 u32 freq, s32 phase_delay);
212int
213ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type,
214 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay);
215int
216ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags,
217 u8 src_sel, u32 freq, s32 phase_delay);
218int
219ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags,
220 u8 *src_sel, u32 *freq, u32 *src_freq);
221int
222ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
223 u8 *dpll_state, u8 *config, s64 *phase_offset,
224 u8 *eec_mode);
225int
226ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state,
227 u8 config, u8 eec_mode);
228int
229ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
230 u8 ref_priority);
231int
232ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
233 u8 *ref_prio);
234int
235ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver,
236 u32 *cgu_fw_ver);
237
238int
239ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,
240 u32 *freq);
241int
242ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,
243 u8 *flags, u16 *node_handle);
244void
245ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
246 u64 *prev_stat, u64 *cur_stat);
247void
248ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
249 u64 *prev_stat, u64 *cur_stat);
250bool ice_is_e810t(struct ice_hw *hw);
251bool ice_is_e823(struct ice_hw *hw);
252int
253ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
254 struct ice_aqc_txsched_elem_data *buf);
255int
256ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
257 struct ice_sq_cd *cd);
258int
259ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
260 bool *value, struct ice_sq_cd *cd);
261bool ice_is_100m_speed_supported(struct ice_hw *hw);
262int
263ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
264 struct ice_sq_cd *cd);
265bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
266int
267ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
268int ice_lldp_execute_pending_mib(struct ice_hw *hw);
269int
270ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
271 u16 bus_addr, __le16 addr, u8 params, u8 *data,
272 struct ice_sq_cd *cd);
273int
274ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
275 u16 bus_addr, __le16 addr, u8 params, const u8 *data,
276 struct ice_sq_cd *cd);
277bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
278#endif /* _ICE_COMMON_H_ */
279

source code of linux/drivers/net/ethernet/intel/ice/ice_common.h