1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (c) 2018, Intel Corporation. */ |
3 | |
4 | #ifndef _ICE_CONTROLQ_H_ |
5 | #define _ICE_CONTROLQ_H_ |
6 | |
7 | #include "ice_adminq_cmd.h" |
8 | |
9 | /* Maximum buffer lengths for all control queue types */ |
10 | #define ICE_AQ_MAX_BUF_LEN 4096 |
11 | #define ICE_MBXQ_MAX_BUF_LEN 4096 |
12 | #define ICE_SBQ_MAX_BUF_LEN 512 |
13 | |
14 | #define ICE_CTL_Q_DESC(R, i) \ |
15 | (&(((struct ice_aq_desc *)((R).desc_buf.va))[i])) |
16 | |
17 | #define ICE_CTL_Q_DESC_UNUSED(R) \ |
18 | ((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ |
19 | (R)->next_to_clean - (R)->next_to_use - 1)) |
20 | |
21 | /* Defines that help manage the driver vs FW API checks. |
22 | * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage. |
23 | */ |
24 | #define EXP_FW_API_VER_BRANCH 0x00 |
25 | #define EXP_FW_API_VER_MAJOR 0x01 |
26 | #define EXP_FW_API_VER_MINOR 0x05 |
27 | |
28 | /* Different control queue types: These are mainly for SW consumption. */ |
29 | enum ice_ctl_q { |
30 | ICE_CTL_Q_UNKNOWN = 0, |
31 | ICE_CTL_Q_ADMIN, |
32 | ICE_CTL_Q_MAILBOX, |
33 | ICE_CTL_Q_SB, |
34 | }; |
35 | |
36 | /* Control Queue timeout settings - max delay 1s */ |
37 | #define ICE_CTL_Q_SQ_CMD_TIMEOUT HZ /* Wait max 1s */ |
38 | #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */ |
39 | #define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */ |
40 | |
41 | struct ice_ctl_q_ring { |
42 | void *dma_head; /* Virtual address to DMA head */ |
43 | struct ice_dma_mem desc_buf; /* descriptor ring memory */ |
44 | void *cmd_buf; /* command buffer memory */ |
45 | |
46 | union { |
47 | struct ice_dma_mem *sq_bi; |
48 | struct ice_dma_mem *rq_bi; |
49 | } r; |
50 | |
51 | u16 count; /* Number of descriptors */ |
52 | |
53 | /* used for interrupt processing */ |
54 | u16 next_to_use; |
55 | u16 next_to_clean; |
56 | |
57 | /* used for queue tracking */ |
58 | u32 head; |
59 | u32 tail; |
60 | u32 len; |
61 | u32 bah; |
62 | u32 bal; |
63 | u32 len_mask; |
64 | u32 len_ena_mask; |
65 | u32 len_crit_mask; |
66 | u32 head_mask; |
67 | }; |
68 | |
69 | /* sq transaction details */ |
70 | struct ice_sq_cd { |
71 | struct ice_aq_desc *wb_desc; |
72 | }; |
73 | |
74 | #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i])) |
75 | |
76 | /* rq event information */ |
77 | struct ice_rq_event_info { |
78 | struct ice_aq_desc desc; |
79 | u16 msg_len; |
80 | u16 buf_len; |
81 | u8 *msg_buf; |
82 | }; |
83 | |
84 | /* Control Queue information */ |
85 | struct ice_ctl_q_info { |
86 | enum ice_ctl_q qtype; |
87 | struct ice_ctl_q_ring rq; /* receive queue */ |
88 | struct ice_ctl_q_ring sq; /* send queue */ |
89 | u16 num_rq_entries; /* receive queue depth */ |
90 | u16 num_sq_entries; /* send queue depth */ |
91 | u16 rq_buf_size; /* receive queue buffer size */ |
92 | u16 sq_buf_size; /* send queue buffer size */ |
93 | enum ice_aq_err sq_last_status; /* last status on send queue */ |
94 | struct mutex sq_lock; /* Send queue lock */ |
95 | struct mutex rq_lock; /* Receive queue lock */ |
96 | }; |
97 | |
98 | #endif /* _ICE_CONTROLQ_H_ */ |
99 | |