| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Copyright (c) 2018-2023, Intel Corporation. */ |
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| 3 | |
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| 4 | /* Machine-generated file */ |
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| 5 | |
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| 6 | #ifndef _ICE_HW_AUTOGEN_H_ |
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| 7 | #define _ICE_HW_AUTOGEN_H_ |
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| 8 | |
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| 9 | #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4)) |
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| 10 | #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4)) |
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| 11 | #define QTX_COMM_HEAD_HEAD_S 0 |
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| 12 | #define QTX_COMM_HEAD_HEAD_M ICE_M(0x1FFF, 0) |
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| 13 | #define PF_FW_ARQBAH 0x00080180 |
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| 14 | #define PF_FW_ARQBAL 0x00080080 |
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| 15 | #define PF_FW_ARQH 0x00080380 |
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| 16 | #define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, 0) |
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| 17 | #define PF_FW_ARQLEN 0x00080280 |
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| 18 | #define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0) |
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| 19 | #define PF_FW_ARQLEN_ARQVFE_M BIT(28) |
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| 20 | #define PF_FW_ARQLEN_ARQOVFL_M BIT(29) |
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| 21 | #define PF_FW_ARQLEN_ARQCRIT_M BIT(30) |
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| 22 | #define PF_FW_ARQLEN_ARQENABLE_M BIT(31) |
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| 23 | #define PF_FW_ARQT 0x00080480 |
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| 24 | #define PF_FW_ATQBAH 0x00080100 |
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| 25 | #define PF_FW_ATQBAL 0x00080000 |
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| 26 | #define PF_FW_ATQH 0x00080300 |
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| 27 | #define PF_FW_ATQH_ATQH_M ICE_M(0x3FF, 0) |
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| 28 | #define PF_FW_ATQLEN 0x00080200 |
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| 29 | #define PF_FW_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0) |
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| 30 | #define PF_FW_ATQLEN_ATQVFE_M BIT(28) |
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| 31 | #define PF_FW_ATQLEN_ATQOVFL_M BIT(29) |
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| 32 | #define PF_FW_ATQLEN_ATQCRIT_M BIT(30) |
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| 33 | #define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4)) |
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| 34 | #define VF_MBX_ATQLEN(_VF) (0x0022A800 + ((_VF) * 4)) |
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| 35 | #define PF_FW_ATQLEN_ATQENABLE_M BIT(31) |
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| 36 | #define PF_FW_ATQT 0x00080400 |
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| 37 | #define PF_MBX_ARQBAH 0x0022E400 |
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| 38 | #define PF_MBX_ARQBAL 0x0022E380 |
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| 39 | #define PF_MBX_ARQH 0x0022E500 |
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| 40 | #define PF_MBX_ARQH_ARQH_M ICE_M(0x3FF, 0) |
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| 41 | #define PF_MBX_ARQLEN 0x0022E480 |
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| 42 | #define PF_MBX_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0) |
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| 43 | #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30) |
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| 44 | #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31) |
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| 45 | #define PF_MBX_ARQT 0x0022E580 |
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| 46 | #define PF_MBX_ATQBAH 0x0022E180 |
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| 47 | #define PF_MBX_ATQBAL 0x0022E100 |
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| 48 | #define PF_MBX_ATQH 0x0022E280 |
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| 49 | #define PF_MBX_ATQH_ATQH_M ICE_M(0x3FF, 0) |
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| 50 | #define PF_MBX_ATQLEN 0x0022E200 |
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| 51 | #define PF_MBX_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0) |
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| 52 | #define PF_MBX_ATQLEN_ATQCRIT_M BIT(30) |
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| 53 | #define PF_MBX_ATQLEN_ATQENABLE_M BIT(31) |
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| 54 | #define PF_MBX_ATQT 0x0022E300 |
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| 55 | #define PF_SB_ARQBAH 0x0022FF00 |
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| 56 | #define PF_SB_ARQBAH_ARQBAH_S 0 |
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| 57 | #define PF_SB_ARQBAH_ARQBAH_M ICE_M(0xFFFFFFFF, 0) |
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| 58 | #define PF_SB_ARQBAL 0x0022FE80 |
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| 59 | #define PF_SB_ARQBAL_ARQBAL_LSB_S 0 |
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| 60 | #define PF_SB_ARQBAL_ARQBAL_LSB_M ICE_M(0x3F, 0) |
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| 61 | #define PF_SB_ARQBAL_ARQBAL_S 6 |
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| 62 | #define PF_SB_ARQBAL_ARQBAL_M ICE_M(0x3FFFFFF, 6) |
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| 63 | #define PF_SB_ARQH 0x00230000 |
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| 64 | #define PF_SB_ARQH_ARQH_S 0 |
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| 65 | #define PF_SB_ARQH_ARQH_M ICE_M(0x3FF, 0) |
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| 66 | #define PF_SB_ARQLEN 0x0022FF80 |
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| 67 | #define PF_SB_ARQLEN_ARQLEN_S 0 |
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| 68 | #define PF_SB_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0) |
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| 69 | #define PF_SB_ARQLEN_ARQVFE_S 28 |
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| 70 | #define PF_SB_ARQLEN_ARQVFE_M BIT(28) |
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| 71 | #define PF_SB_ARQLEN_ARQOVFL_S 29 |
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| 72 | #define PF_SB_ARQLEN_ARQOVFL_M BIT(29) |
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| 73 | #define PF_SB_ARQLEN_ARQCRIT_S 30 |
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| 74 | #define PF_SB_ARQLEN_ARQCRIT_M BIT(30) |
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| 75 | #define PF_SB_ARQLEN_ARQENABLE_S 31 |
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| 76 | #define PF_SB_ARQLEN_ARQENABLE_M BIT(31) |
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| 77 | #define PF_SB_ARQT 0x00230080 |
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| 78 | #define PF_SB_ARQT_ARQT_S 0 |
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| 79 | #define PF_SB_ARQT_ARQT_M ICE_M(0x3FF, 0) |
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| 80 | #define PF_SB_ATQBAH 0x0022FC80 |
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| 81 | #define PF_SB_ATQBAH_ATQBAH_S 0 |
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| 82 | #define PF_SB_ATQBAH_ATQBAH_M ICE_M(0xFFFFFFFF, 0) |
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| 83 | #define PF_SB_ATQBAL 0x0022FC00 |
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| 84 | #define PF_SB_ATQBAL_ATQBAL_S 6 |
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| 85 | #define PF_SB_ATQBAL_ATQBAL_M ICE_M(0x3FFFFFF, 6) |
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| 86 | #define PF_SB_ATQH 0x0022FD80 |
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| 87 | #define PF_SB_ATQH_ATQH_S 0 |
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| 88 | #define PF_SB_ATQH_ATQH_M ICE_M(0x3FF, 0) |
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| 89 | #define PF_SB_ATQLEN 0x0022FD00 |
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| 90 | #define PF_SB_ATQLEN_ATQLEN_S 0 |
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| 91 | #define PF_SB_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0) |
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| 92 | #define PF_SB_ATQLEN_ATQVFE_S 28 |
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| 93 | #define PF_SB_ATQLEN_ATQVFE_M BIT(28) |
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| 94 | #define PF_SB_ATQLEN_ATQOVFL_S 29 |
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| 95 | #define PF_SB_ATQLEN_ATQOVFL_M BIT(29) |
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| 96 | #define PF_SB_ATQLEN_ATQCRIT_S 30 |
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| 97 | #define PF_SB_ATQLEN_ATQCRIT_M BIT(30) |
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| 98 | #define PF_SB_ATQLEN_ATQENABLE_S 31 |
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| 99 | #define PF_SB_ATQLEN_ATQENABLE_M BIT(31) |
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| 100 | #define PF_SB_ATQT 0x0022FE00 |
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| 101 | #define PF_SB_ATQT_ATQT_S 0 |
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| 102 | #define PF_SB_ATQT_ATQT_M ICE_M(0x3FF, 0) |
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| 103 | #define PF_SB_REM_DEV_CTL 0x002300F0 |
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| 104 | #define PRTDCB_GENC 0x00083000 |
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| 105 | #define PRTDCB_GENC_PFCLDA_S 16 |
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| 106 | #define PRTDCB_GENC_PFCLDA_M ICE_M(0xFFFF, 16) |
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| 107 | #define PRTDCB_GENS 0x00083020 |
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| 108 | #define PRTDCB_GENS_DCBX_STATUS_S 0 |
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| 109 | #define PRTDCB_GENS_DCBX_STATUS_M ICE_M(0x7, 0) |
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| 110 | #define PRTDCB_TUP2TC 0x001D26C0 |
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| 111 | #define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4)) |
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| 112 | #define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4)) |
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| 113 | #define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256)) |
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| 114 | #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S 0 |
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| 115 | #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M ICE_M(0x3F, 0) |
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| 116 | #define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045c800 + ((_i) * 4)) |
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| 117 | #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0 |
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| 118 | #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M ICE_M(0xFF, 0) |
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| 119 | #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30 |
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| 120 | #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M ICE_M(0x3, 30) |
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| 121 | #define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045c900 + ((_i) * 4)) |
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| 122 | #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0 |
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| 123 | #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M ICE_M(0xFF, 0) |
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| 124 | #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30 |
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| 125 | #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M ICE_M(0x3, 30) |
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| 126 | #define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045ca00 + ((_i) * 4)) |
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| 127 | #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0 |
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| 128 | #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M ICE_M(0xFF, 0) |
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| 129 | #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30 |
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| 130 | #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M ICE_M(0x3, 30) |
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| 131 | #define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045cb00 + ((_i) * 4)) |
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| 132 | #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0 |
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| 133 | #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M ICE_M(0xFF, 0) |
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| 134 | #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30 |
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| 135 | #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M ICE_M(0x3, 30) |
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| 136 | #define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4)) |
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| 137 | #define QRXFLXP_CNTXT_RXDID_IDX_S 0 |
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| 138 | #define QRXFLXP_CNTXT_RXDID_IDX_M ICE_M(0x3F, 0) |
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| 139 | #define QRXFLXP_CNTXT_RXDID_PRIO_S 8 |
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| 140 | #define QRXFLXP_CNTXT_RXDID_PRIO_M ICE_M(0x7, 8) |
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| 141 | #define QRXFLXP_CNTXT_TS_M BIT(11) |
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| 142 | #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S 4 |
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| 143 | #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M ICE_M(0x3, 4) |
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| 144 | #define GLGEN_CLKSTAT_SRC 0x000B826C |
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| 145 | #define GLGEN_GPIO_CTL(_i) (0x000880C8 + ((_i) * 4)) |
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| 146 | #define GLGEN_GPIO_CTL_PIN_DIR_M BIT(4) |
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| 147 | #define GLGEN_GPIO_CTL_PIN_FUNC_S 8 |
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| 148 | #define GLGEN_GPIO_CTL_PIN_FUNC_M ICE_M(0xF, 8) |
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| 149 | #define GLGEN_RSTAT 0x000B8188 |
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| 150 | #define GLGEN_RSTAT_DEVSTATE_M ICE_M(0x3, 0) |
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| 151 | #define GLGEN_RSTCTL 0x000B8180 |
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| 152 | #define GLGEN_RSTCTL_GRSTDEL_S 0 |
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| 153 | #define GLGEN_RSTCTL_GRSTDEL_M ICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S) |
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| 154 | #define GLGEN_RSTAT_RESET_TYPE_S 2 |
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| 155 | #define GLGEN_RSTAT_RESET_TYPE_M ICE_M(0x3, 2) |
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| 156 | #define GLGEN_RTRIG 0x000B8190 |
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| 157 | #define GLGEN_RTRIG_CORER_M BIT(0) |
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| 158 | #define GLGEN_RTRIG_GLOBR_M BIT(1) |
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| 159 | #define GLGEN_STAT 0x000B612C |
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| 160 | #define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4)) |
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| 161 | #define PFGEN_CTRL 0x00091000 |
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| 162 | #define PFGEN_CTRL_PFSWR_M BIT(0) |
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| 163 | #define PFGEN_STATE 0x00088000 |
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| 164 | #define PRTGEN_STATUS 0x000B8100 |
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| 165 | #define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4)) |
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| 166 | #define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4)) |
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| 167 | #define VPGEN_VFRSTAT_VFRD_M BIT(0) |
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| 168 | #define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4)) |
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| 169 | #define VPGEN_VFRTRIG_VFSWR_M BIT(0) |
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| 170 | #define GLINT_CTL 0x0016CC54 |
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| 171 | #define GLINT_CTL_DIS_AUTOMASK_M BIT(0) |
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| 172 | #define GLINT_CTL_ITR_GRAN_200_S 16 |
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| 173 | #define GLINT_CTL_ITR_GRAN_200_M ICE_M(0xF, 16) |
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| 174 | #define GLINT_CTL_ITR_GRAN_100_S 20 |
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| 175 | #define GLINT_CTL_ITR_GRAN_100_M ICE_M(0xF, 20) |
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| 176 | #define GLINT_CTL_ITR_GRAN_50_S 24 |
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| 177 | #define GLINT_CTL_ITR_GRAN_50_M ICE_M(0xF, 24) |
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| 178 | #define GLINT_CTL_ITR_GRAN_25_S 28 |
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| 179 | #define GLINT_CTL_ITR_GRAN_25_M ICE_M(0xF, 28) |
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| 180 | #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) |
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| 181 | #define GLINT_DYN_CTL_INTENA_M BIT(0) |
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| 182 | #define GLINT_DYN_CTL_CLEARPBA_M BIT(1) |
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| 183 | #define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2) |
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| 184 | #define GLINT_DYN_CTL_ITR_INDX_S 3 |
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| 185 | #define GLINT_DYN_CTL_ITR_INDX_M ICE_M(0x3, 3) |
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| 186 | #define GLINT_DYN_CTL_INTERVAL_S 5 |
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| 187 | #define GLINT_DYN_CTL_INTERVAL_M ICE_M(0xFFF, 5) |
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| 188 | #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24) |
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| 189 | #define GLINT_DYN_CTL_SW_ITR_INDX_S 25 |
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| 190 | #define GLINT_DYN_CTL_SW_ITR_INDX_M ICE_M(0x3, 25) |
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| 191 | #define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30) |
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| 192 | #define GLINT_DYN_CTL_INTENA_MSK_M BIT(31) |
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| 193 | #define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4)) |
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| 194 | #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) |
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| 195 | #define GLINT_RATE_INTRL_ENA_M BIT(6) |
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| 196 | #define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4)) |
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| 197 | #define GLINT_VECT2FUNC_VF_NUM_S 0 |
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| 198 | #define GLINT_VECT2FUNC_VF_NUM_M ICE_M(0xFF, 0) |
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| 199 | #define GLINT_VECT2FUNC_PF_NUM_S 12 |
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| 200 | #define GLINT_VECT2FUNC_PF_NUM_M ICE_M(0x7, 12) |
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| 201 | #define GLINT_VECT2FUNC_IS_PF_S 16 |
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| 202 | #define GLINT_VECT2FUNC_IS_PF_M BIT(16) |
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| 203 | #define PFINT_FW_CTL 0x0016C800 |
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| 204 | #define PFINT_FW_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) |
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| 205 | #define PFINT_FW_CTL_ITR_INDX_S 11 |
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| 206 | #define PFINT_FW_CTL_ITR_INDX_M ICE_M(0x3, 11) |
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| 207 | #define PFINT_FW_CTL_CAUSE_ENA_M BIT(30) |
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| 208 | #define PFINT_MBX_CTL 0x0016B280 |
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| 209 | #define PFINT_MBX_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) |
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| 210 | #define PFINT_MBX_CTL_ITR_INDX_S 11 |
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| 211 | #define PFINT_MBX_CTL_ITR_INDX_M ICE_M(0x3, 11) |
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| 212 | #define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30) |
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| 213 | #define PFINT_OICR 0x0016CA00 |
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| 214 | #define PFINT_OICR_TSYN_TX_M BIT(11) |
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| 215 | #define PFINT_OICR_TSYN_EVNT_M BIT(12) |
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| 216 | #define PFINT_OICR_ECC_ERR_M BIT(16) |
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| 217 | #define PFINT_OICR_MAL_DETECT_M BIT(19) |
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| 218 | #define PFINT_OICR_GRST_M BIT(20) |
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| 219 | #define PFINT_OICR_PCI_EXCEPTION_M BIT(21) |
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| 220 | #define PFINT_OICR_HMC_ERR_M BIT(26) |
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| 221 | #define PFINT_OICR_PE_PUSH_M BIT(27) |
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| 222 | #define PFINT_OICR_PE_CRITERR_M BIT(28) |
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| 223 | #define PFINT_OICR_VFLR_M BIT(29) |
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| 224 | #define PFINT_OICR_SWINT_M BIT(31) |
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| 225 | #define PFINT_OICR_CTL 0x0016CA80 |
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| 226 | #define PFINT_OICR_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) |
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| 227 | #define PFINT_OICR_CTL_ITR_INDX_S 11 |
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| 228 | #define PFINT_OICR_CTL_ITR_INDX_M ICE_M(0x3, 11) |
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| 229 | #define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30) |
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| 230 | #define PFINT_OICR_ENA 0x0016C900 |
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| 231 | #define PFINT_SB_CTL 0x0016B600 |
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| 232 | #define PFINT_SB_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) |
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| 233 | #define PFINT_SB_CTL_CAUSE_ENA_M BIT(30) |
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| 234 | #define PFINT_TSYN_MSK 0x0016C980 |
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| 235 | #define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4)) |
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| 236 | #define QINT_RQCTL_MSIX_INDX_S 0 |
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| 237 | #define QINT_RQCTL_MSIX_INDX_M ICE_M(0x7FF, 0) |
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| 238 | #define QINT_RQCTL_ITR_INDX_S 11 |
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| 239 | #define QINT_RQCTL_ITR_INDX_M ICE_M(0x3, 11) |
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| 240 | #define QINT_RQCTL_CAUSE_ENA_M BIT(30) |
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| 241 | #define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4)) |
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| 242 | #define QINT_TQCTL_MSIX_INDX_S 0 |
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| 243 | #define QINT_TQCTL_MSIX_INDX_M ICE_M(0x7FF, 0) |
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| 244 | #define QINT_TQCTL_ITR_INDX_S 11 |
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| 245 | #define QINT_TQCTL_ITR_INDX_M ICE_M(0x3, 11) |
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| 246 | #define QINT_TQCTL_CAUSE_ENA_M BIT(30) |
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| 247 | #define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4)) |
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| 248 | #define VPINT_ALLOC_FIRST_S 0 |
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| 249 | #define VPINT_ALLOC_FIRST_M ICE_M(0x7FF, 0) |
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| 250 | #define VPINT_ALLOC_LAST_S 12 |
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| 251 | #define VPINT_ALLOC_LAST_M ICE_M(0x7FF, 12) |
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| 252 | #define VPINT_ALLOC_VALID_M BIT(31) |
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| 253 | #define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4)) |
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| 254 | #define VPINT_ALLOC_PCI_FIRST_S 0 |
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| 255 | #define VPINT_ALLOC_PCI_FIRST_M ICE_M(0x7FF, 0) |
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| 256 | #define VPINT_ALLOC_PCI_LAST_S 12 |
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| 257 | #define VPINT_ALLOC_PCI_LAST_M ICE_M(0x7FF, 12) |
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| 258 | #define VPINT_ALLOC_PCI_VALID_M BIT(31) |
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| 259 | #define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4)) |
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| 260 | #define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30) |
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| 261 | #define GLLAN_RCTL_0 0x002941F8 |
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| 262 | #define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4)) |
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| 263 | #define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4)) |
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| 264 | #define QRX_CTRL_MAX_INDEX 2047 |
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| 265 | #define QRX_CTRL_QENA_REQ_S 0 |
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| 266 | #define QRX_CTRL_QENA_REQ_M BIT(0) |
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| 267 | #define QRX_CTRL_QENA_STAT_S 2 |
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| 268 | #define QRX_CTRL_QENA_STAT_M BIT(2) |
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| 269 | #define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4)) |
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| 270 | #define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4)) |
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| 271 | #define QRX_TAIL_MAX_INDEX 2047 |
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| 272 | #define QRX_TAIL_TAIL_S 0 |
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| 273 | #define QRX_TAIL_TAIL_M ICE_M(0x1FFF, 0) |
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| 274 | #define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4)) |
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| 275 | #define VPLAN_RX_QBASE_VFFIRSTQ_S 0 |
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| 276 | #define VPLAN_RX_QBASE_VFFIRSTQ_M ICE_M(0x7FF, 0) |
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| 277 | #define VPLAN_RX_QBASE_VFNUMQ_S 16 |
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| 278 | #define VPLAN_RX_QBASE_VFNUMQ_M ICE_M(0xFF, 16) |
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| 279 | #define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4)) |
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| 280 | #define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0) |
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| 281 | #define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4)) |
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| 282 | #define VPLAN_TX_QBASE_VFFIRSTQ_S 0 |
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| 283 | #define VPLAN_TX_QBASE_VFFIRSTQ_M ICE_M(0x3FFF, 0) |
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| 284 | #define VPLAN_TX_QBASE_VFNUMQ_S 16 |
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| 285 | #define VPLAN_TX_QBASE_VFNUMQ_M ICE_M(0xFF, 16) |
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| 286 | #define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4)) |
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| 287 | #define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0) |
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| 288 | #define E800_PRTMAC_HSEC_CTL_TX_PS_QNT(_i) (0x001E36E0 + ((_i) * 32)) |
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| 289 | #define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 8 |
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| 290 | #define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M GENMASK(15, 0) |
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| 291 | #define E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR(_i) (0x001E3800 + ((_i) * 32)) |
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| 292 | #define E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M GENMASK(15, 0) |
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| 293 | #define GL_MDCK_TX_TDPU 0x00049348 |
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| 294 | #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1) |
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| 295 | #define GL_MDET_RX 0x00294C00 |
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| 296 | #define GL_MDET_RX_QNUM_S 0 |
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| 297 | #define GL_MDET_RX_QNUM_M ICE_M(0x7FFF, 0) |
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| 298 | #define GL_MDET_RX_VF_NUM_S 15 |
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| 299 | #define GL_MDET_RX_VF_NUM_M ICE_M(0xFF, 15) |
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| 300 | #define GL_MDET_RX_PF_NUM_S 23 |
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| 301 | #define GL_MDET_RX_PF_NUM_M ICE_M(0x7, 23) |
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| 302 | #define GL_MDET_RX_MAL_TYPE_S 26 |
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| 303 | #define GL_MDET_RX_MAL_TYPE_M ICE_M(0x1F, 26) |
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| 304 | #define GL_MDET_RX_VALID_M BIT(31) |
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| 305 | #define GL_MDET_TX_PQM 0x002D2E00 |
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| 306 | #define GL_MDET_TX_PQM_PF_NUM_S 0 |
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| 307 | #define GL_MDET_TX_PQM_PF_NUM_M ICE_M(0x7, 0) |
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| 308 | #define GL_MDET_TX_PQM_VF_NUM_S 4 |
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| 309 | #define GL_MDET_TX_PQM_VF_NUM_M ICE_M(0xFF, 4) |
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| 310 | #define GL_MDET_TX_PQM_QNUM_S 12 |
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| 311 | #define GL_MDET_TX_PQM_QNUM_M ICE_M(0x3FFF, 12) |
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| 312 | #define GL_MDET_TX_PQM_MAL_TYPE_S 26 |
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| 313 | #define GL_MDET_TX_PQM_MAL_TYPE_M ICE_M(0x1F, 26) |
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| 314 | #define GL_MDET_TX_PQM_VALID_M BIT(31) |
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| 315 | #define GL_MDET_TX_TCLAN_BY_MAC(hw) \ |
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| 316 | ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MDET_TX_TCLAN : \ |
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| 317 | E800_GL_MDET_TX_TCLAN) |
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| 318 | #define E800_GL_MDET_TX_TCLAN 0x000FC068 |
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| 319 | #define E830_GL_MDET_TX_TCLAN 0x000FCCC0 |
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| 320 | #define GL_MDET_TX_TCLAN_QNUM_S 0 |
|---|
| 321 | #define GL_MDET_TX_TCLAN_QNUM_M ICE_M(0x7FFF, 0) |
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| 322 | #define GL_MDET_TX_TCLAN_VF_NUM_S 15 |
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| 323 | #define GL_MDET_TX_TCLAN_VF_NUM_M ICE_M(0xFF, 15) |
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| 324 | #define GL_MDET_TX_TCLAN_PF_NUM_S 23 |
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| 325 | #define GL_MDET_TX_TCLAN_PF_NUM_M ICE_M(0x7, 23) |
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| 326 | #define GL_MDET_TX_TCLAN_MAL_TYPE_S 26 |
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| 327 | #define GL_MDET_TX_TCLAN_MAL_TYPE_M ICE_M(0x1F, 26) |
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| 328 | #define GL_MDET_TX_TCLAN_VALID_M BIT(31) |
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| 329 | #define PF_MDET_RX 0x00294280 |
|---|
| 330 | #define PF_MDET_RX_VALID_M BIT(0) |
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| 331 | #define PF_MDET_TX_PQM 0x002D2C80 |
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| 332 | #define PF_MDET_TX_PQM_VALID_M BIT(0) |
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| 333 | #define PF_MDET_TX_TCLAN_BY_MAC(hw) \ |
|---|
| 334 | ((hw)->mac_type == ICE_MAC_E830 ? E830_PF_MDET_TX_TCLAN : \ |
|---|
| 335 | E800_PF_MDET_TX_TCLAN) |
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| 336 | #define E800_PF_MDET_TX_TCLAN 0x000FC000 |
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| 337 | #define E830_PF_MDET_TX_TCLAN 0x000FCC00 |
|---|
| 338 | #define PF_MDET_TX_TCLAN_VALID_M BIT(0) |
|---|
| 339 | #define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4)) |
|---|
| 340 | #define VP_MDET_RX_VALID_M BIT(0) |
|---|
| 341 | #define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4)) |
|---|
| 342 | #define VP_MDET_TX_PQM_VALID_M BIT(0) |
|---|
| 343 | #define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4)) |
|---|
| 344 | #define VP_MDET_TX_TCLAN_VALID_M BIT(0) |
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| 345 | #define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4)) |
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| 346 | #define VP_MDET_TX_TDPU_VALID_M BIT(0) |
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| 347 | #define E800_GL_MNG_FWSM_FW_MODES_M GENMASK(2, 0) |
|---|
| 348 | #define E830_GL_MNG_FWSM_FW_MODES_M GENMASK(1, 0) |
|---|
| 349 | #define GL_MNG_FWSM 0x000B6134 |
|---|
| 350 | #define GL_MNG_FWSM_FW_LOADING_M BIT(30) |
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| 351 | #define GLNVM_FLA 0x000B6108 |
|---|
| 352 | #define GLNVM_FLA_LOCKED_M BIT(6) |
|---|
| 353 | #define GLNVM_GENS 0x000B6100 |
|---|
| 354 | #define GLNVM_GENS_SR_SIZE_S 5 |
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| 355 | #define GLNVM_GENS_SR_SIZE_M ICE_M(0x7, 5) |
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| 356 | #define GLNVM_ULD 0x000B6008 |
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| 357 | #define GLNVM_ULD_PCIER_DONE_M BIT(0) |
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| 358 | #define GLNVM_ULD_PCIER_DONE_1_M BIT(1) |
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| 359 | #define GLNVM_ULD_CORER_DONE_M BIT(3) |
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| 360 | #define GLNVM_ULD_GLOBR_DONE_M BIT(4) |
|---|
| 361 | #define GLNVM_ULD_POR_DONE_M BIT(5) |
|---|
| 362 | #define GLNVM_ULD_POR_DONE_1_M BIT(8) |
|---|
| 363 | #define GLNVM_ULD_PCIER_DONE_2_M BIT(9) |
|---|
| 364 | #define GLNVM_ULD_PE_DONE_M BIT(10) |
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| 365 | #define GLPCI_CNF2 0x000BE004 |
|---|
| 366 | #define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1) |
|---|
| 367 | #define PF_FUNC_RID 0x0009E880 |
|---|
| 368 | #define PF_FUNC_RID_FUNC_NUM_S 0 |
|---|
| 369 | #define PF_FUNC_RID_FUNC_NUM_M ICE_M(0x7, 0) |
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| 370 | #define PF_PCI_CIAA 0x0009E580 |
|---|
| 371 | #define PF_PCI_CIAA_VF_NUM_S 12 |
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| 372 | #define PF_PCI_CIAD 0x0009E500 |
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| 373 | #define GL_PWR_MODE_CTL 0x000B820C |
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| 374 | #define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30 |
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| 375 | #define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30) |
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| 376 | #define GLQF_FD_CNT 0x00460018 |
|---|
| 377 | #define E800_GLQF_FD_CNT_FD_GCNT_M GENMASK(14, 0) |
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| 378 | #define E830_GLQF_FD_CNT_FD_GCNT_M GENMASK(15, 0) |
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| 379 | #define GLQF_FD_CNT_FD_BCNT_S 16 |
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| 380 | #define E800_GLQF_FD_CNT_FD_BCNT_M GENMASK(30, 16) |
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| 381 | #define E830_GLQF_FD_CNT_FD_BCNT_M GENMASK(31, 16) |
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| 382 | #define GLQF_FD_SIZE 0x00460010 |
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| 383 | #define GLQF_FD_SIZE_FD_GSIZE_S 0 |
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| 384 | #define E800_GLQF_FD_SIZE_FD_GSIZE_M GENMASK(14, 0) |
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| 385 | #define E830_GLQF_FD_SIZE_FD_GSIZE_M GENMASK(15, 0) |
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| 386 | #define GLQF_FD_SIZE_FD_BSIZE_S 16 |
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| 387 | #define E800_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(30, 16) |
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| 388 | #define E830_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(31, 16) |
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| 389 | #define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512)) |
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| 390 | #define GLQF_FDMASK(_i) (0x00410800 + ((_i) * 4)) |
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| 391 | #define GLQF_FDMASK_MAX_INDEX 31 |
|---|
| 392 | #define GLQF_FDMASK_MSK_INDEX_S 0 |
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| 393 | #define GLQF_FDMASK_MSK_INDEX_M ICE_M(0x1F, 0) |
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| 394 | #define GLQF_FDMASK_MASK_S 16 |
|---|
| 395 | #define GLQF_FDMASK_MASK_M ICE_M(0xFFFF, 16) |
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| 396 | #define GLQF_FDMASK_SEL(_i) (0x00410400 + ((_i) * 4)) |
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| 397 | #define GLQF_FDSWAP(_i, _j) (0x00413000 + ((_i) * 4 + (_j) * 512)) |
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| 398 | #define GLQF_HMASK(_i) (0x0040FC00 + ((_i) * 4)) |
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| 399 | #define GLQF_HMASK_MAX_INDEX 31 |
|---|
| 400 | #define GLQF_HMASK_MSK_INDEX_S 0 |
|---|
| 401 | #define GLQF_HMASK_MSK_INDEX_M ICE_M(0x1F, 0) |
|---|
| 402 | #define GLQF_HMASK_MASK_S 16 |
|---|
| 403 | #define GLQF_HMASK_MASK_M ICE_M(0xFFFF, 16) |
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| 404 | #define GLQF_HMASK_SEL(_i) (0x00410000 + ((_i) * 4)) |
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| 405 | #define GLQF_HMASK_SEL_MAX_INDEX 127 |
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| 406 | #define GLQF_HMASK_SEL_MASK_SEL_S 0 |
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| 407 | #define E800_PFQF_FD_CNT_FD_GCNT_M GENMASK(14, 0) |
|---|
| 408 | #define E830_PFQF_FD_CNT_FD_GCNT_M GENMASK(15, 0) |
|---|
| 409 | #define E800_PFQF_FD_CNT_FD_BCNT_M GENMASK(30, 16) |
|---|
| 410 | #define E830_PFQF_FD_CNT_FD_BCNT_M GENMASK(31, 16) |
|---|
| 411 | #define PFQF_FD_ENA 0x0043A000 |
|---|
| 412 | #define PFQF_FD_ENA_FD_ENA_M BIT(0) |
|---|
| 413 | #define PFQF_FD_SIZE 0x00460100 |
|---|
| 414 | #define GLDCB_RTCTQ_RXQNUM_S 0 |
|---|
| 415 | #define GLDCB_RTCTQ_RXQNUM_M ICE_M(0x7FF, 0) |
|---|
| 416 | #define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8)) |
|---|
| 417 | #define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8)) |
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| 418 | #define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8)) |
|---|
| 419 | #define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8)) |
|---|
| 420 | #define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8)) |
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| 421 | #define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8)) |
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| 422 | #define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8)) |
|---|
| 423 | #define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8)) |
|---|
| 424 | #define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8)) |
|---|
| 425 | #define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8)) |
|---|
| 426 | #define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8)) |
|---|
| 427 | #define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8)) |
|---|
| 428 | #define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8)) |
|---|
| 429 | #define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8)) |
|---|
| 430 | #define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8)) |
|---|
| 431 | #define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8)) |
|---|
| 432 | #define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8)) |
|---|
| 433 | #define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8)) |
|---|
| 434 | #define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8)) |
|---|
| 435 | #define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8)) |
|---|
| 436 | #define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8)) |
|---|
| 437 | #define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8)) |
|---|
| 438 | #define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8)) |
|---|
| 439 | #define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8)) |
|---|
| 440 | #define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8)) |
|---|
| 441 | #define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8)) |
|---|
| 442 | #define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8)) |
|---|
| 443 | #define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8)) |
|---|
| 444 | #define GLPRT_PXOFFRXC(_i, _j) (0x00380500 + ((_i) * 8 + (_j) * 64)) |
|---|
| 445 | #define GLPRT_PXOFFTXC(_i, _j) (0x00380F40 + ((_i) * 8 + (_j) * 64)) |
|---|
| 446 | #define GLPRT_PXONRXC(_i, _j) (0x00380300 + ((_i) * 8 + (_j) * 64)) |
|---|
| 447 | #define GLPRT_PXONTXC(_i, _j) (0x00380D40 + ((_i) * 8 + (_j) * 64)) |
|---|
| 448 | #define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8)) |
|---|
| 449 | #define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8)) |
|---|
| 450 | #define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8)) |
|---|
| 451 | #define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8)) |
|---|
| 452 | #define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8)) |
|---|
| 453 | #define GLPRT_RXON2OFFCNT(_i, _j) (0x00380700 + ((_i) * 8 + (_j) * 64)) |
|---|
| 454 | #define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8)) |
|---|
| 455 | #define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8)) |
|---|
| 456 | #define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8)) |
|---|
| 457 | #define GLSTAT_FD_CNT0L(_i) (0x003A0000 + ((_i) * 8)) |
|---|
| 458 | #define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8)) |
|---|
| 459 | #define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8)) |
|---|
| 460 | #define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8)) |
|---|
| 461 | #define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8)) |
|---|
| 462 | #define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8)) |
|---|
| 463 | #define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8)) |
|---|
| 464 | #define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4)) |
|---|
| 465 | #define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4)) |
|---|
| 466 | #define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8)) |
|---|
| 467 | #define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8)) |
|---|
| 468 | #define PRTRPB_RDPC 0x000AC260 |
|---|
| 469 | #define GLHH_ART_CTL 0x000A41D4 |
|---|
| 470 | #define GLHH_ART_CTL_ACTIVE_M BIT(0) |
|---|
| 471 | #define GLHH_ART_TIME_H 0x000A41D8 |
|---|
| 472 | #define GLHH_ART_TIME_L 0x000A41DC |
|---|
| 473 | #define GLTSYN_AUX_IN_0(_i) (0x000889D8 + ((_i) * 4)) |
|---|
| 474 | #define GLTSYN_AUX_IN_0_INT_ENA_M BIT(4) |
|---|
| 475 | #define GLTSYN_AUX_OUT_0(_i) (0x00088998 + ((_i) * 4)) |
|---|
| 476 | #define GLTSYN_AUX_OUT_0_OUT_ENA_M BIT(0) |
|---|
| 477 | #define GLTSYN_AUX_OUT_0_OUTMOD_M ICE_M(0x3, 1) |
|---|
| 478 | #define GLTSYN_CLKO_0(_i) (0x000889B8 + ((_i) * 4)) |
|---|
| 479 | #define GLTSYN_CMD 0x00088810 |
|---|
| 480 | #define GLTSYN_CMD_SYNC 0x00088814 |
|---|
| 481 | #define GLTSYN_ENA(_i) (0x00088808 + ((_i) * 4)) |
|---|
| 482 | #define GLTSYN_ENA_TSYN_ENA_M BIT(0) |
|---|
| 483 | #define GLTSYN_EVNT_H_0(_i) (0x00088970 + ((_i) * 4)) |
|---|
| 484 | #define GLTSYN_EVNT_L_0(_i) (0x00088968 + ((_i) * 4)) |
|---|
| 485 | #define GLTSYN_HHTIME_H(_i) (0x00088900 + ((_i) * 4)) |
|---|
| 486 | #define GLTSYN_HHTIME_L(_i) (0x000888F8 + ((_i) * 4)) |
|---|
| 487 | #define GLTSYN_INCVAL_H(_i) (0x00088920 + ((_i) * 4)) |
|---|
| 488 | #define GLTSYN_INCVAL_L(_i) (0x00088918 + ((_i) * 4)) |
|---|
| 489 | #define GLTSYN_SHADJ_H(_i) (0x00088910 + ((_i) * 4)) |
|---|
| 490 | #define GLTSYN_SHADJ_L(_i) (0x00088908 + ((_i) * 4)) |
|---|
| 491 | #define GLTSYN_SHTIME_0(_i) (0x000888E0 + ((_i) * 4)) |
|---|
| 492 | #define GLTSYN_SHTIME_H(_i) (0x000888F0 + ((_i) * 4)) |
|---|
| 493 | #define GLTSYN_SHTIME_L(_i) (0x000888E8 + ((_i) * 4)) |
|---|
| 494 | #define GLTSYN_STAT(_i) (0x000888C0 + ((_i) * 4)) |
|---|
| 495 | #define GLTSYN_STAT_EVENT0_M BIT(0) |
|---|
| 496 | #define GLTSYN_STAT_EVENT1_M BIT(1) |
|---|
| 497 | #define GLTSYN_STAT_EVENT2_M BIT(2) |
|---|
| 498 | #define GLTSYN_SYNC_DLAY 0x00088818 |
|---|
| 499 | #define GLTSYN_TGT_H_0(_i) (0x00088930 + ((_i) * 4)) |
|---|
| 500 | #define GLTSYN_TGT_L_0(_i) (0x00088928 + ((_i) * 4)) |
|---|
| 501 | #define GLTSYN_TIME_0(_i) (0x000888C8 + ((_i) * 4)) |
|---|
| 502 | #define GLTSYN_TIME_H(_i) (0x000888D8 + ((_i) * 4)) |
|---|
| 503 | #define GLTSYN_TIME_L(_i) (0x000888D0 + ((_i) * 4)) |
|---|
| 504 | #define PFHH_SEM 0x000A4200 /* Reset Source: PFR */ |
|---|
| 505 | #define PFHH_SEM_BUSY_M BIT(0) |
|---|
| 506 | #define PFTSYN_SEM 0x00088880 |
|---|
| 507 | #define PFTSYN_SEM_BUSY_M BIT(0) |
|---|
| 508 | #define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4)) |
|---|
| 509 | #define VSIQF_FD_CNT_FD_GCNT_S 0 |
|---|
| 510 | #define E800_VSIQF_FD_CNT_FD_GCNT_M GENMASK(13, 0) |
|---|
| 511 | #define E830_VSIQF_FD_CNT_FD_GCNT_M GENMASK(15, 0) |
|---|
| 512 | #define VSIQF_FD_CNT_FD_BCNT_S 16 |
|---|
| 513 | #define E800_VSIQF_FD_CNT_FD_BCNT_M GENMASK(29, 16) |
|---|
| 514 | #define E830_VSIQF_FD_CNT_FD_BCNT_M GENMASK(31, 16) |
|---|
| 515 | #define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4)) |
|---|
| 516 | #define VSIQF_HKEY_MAX_INDEX 12 |
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| 517 | #define PFPM_APM 0x000B8080 |
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| 518 | #define PFPM_APM_APME_M BIT(0) |
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| 519 | #define PFPM_WUFC 0x0009DC00 |
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| 520 | #define PFPM_WUFC_MAG_M BIT(1) |
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| 521 | #define PFPM_WUS 0x0009DB80 |
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| 522 | #define PFPM_WUS_LNKC_M BIT(0) |
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| 523 | #define PFPM_WUS_MAG_M BIT(1) |
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| 524 | #define PFPM_WUS_MNG_M BIT(3) |
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| 525 | #define PFPM_WUS_FW_RST_WK_M BIT(31) |
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| 526 | #define E830_PRTMAC_CL01_PS_QNT 0x001E32A0 |
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| 527 | #define E830_PRTMAC_CL01_PS_QNT_CL0_M GENMASK(15, 0) |
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| 528 | #define E830_PRTMAC_CL01_QNT_THR 0x001E3320 |
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| 529 | #define E830_PRTMAC_CL01_QNT_THR_CL0_M GENMASK(15, 0) |
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| 530 | #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) |
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| 531 | #define VFINT_DYN_CTLN_CLEARPBA_M BIT(1) |
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| 532 | |
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| 533 | #endif /* _ICE_HW_AUTOGEN_H_ */ |
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| 534 | |
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