1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (c) 2018, Intel Corporation. */ |
3 | |
4 | #ifndef _ICE_SCHED_H_ |
5 | #define _ICE_SCHED_H_ |
6 | |
7 | #include "ice_common.h" |
8 | |
9 | #define SCHED_NODE_NAME_MAX_LEN 32 |
10 | |
11 | #define ICE_QGRP_LAYER_OFFSET 2 |
12 | #define ICE_VSI_LAYER_OFFSET 4 |
13 | #define ICE_AGG_LAYER_OFFSET 6 |
14 | #define ICE_SCHED_INVAL_LAYER_NUM 0xFF |
15 | /* Burst size is a 12 bits register that is configured while creating the RL |
16 | * profile(s). MSB is a granularity bit and tells the granularity type |
17 | * 0 - LSB bits are in 64 bytes granularity |
18 | * 1 - LSB bits are in 1K bytes granularity |
19 | */ |
20 | #define ICE_64_BYTE_GRANULARITY 0 |
21 | #define ICE_KBYTE_GRANULARITY BIT(11) |
22 | #define ICE_MIN_BURST_SIZE_ALLOWED 64 /* In Bytes */ |
23 | #define ICE_MAX_BURST_SIZE_ALLOWED \ |
24 | ((BIT(11) - 1) * 1024) /* In Bytes */ |
25 | #define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \ |
26 | ((BIT(11) - 1) * 64) /* In Bytes */ |
27 | #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY ICE_MAX_BURST_SIZE_ALLOWED |
28 | |
29 | #define ICE_RL_PROF_ACCURACY_BYTES 128 |
30 | #define ICE_RL_PROF_MULTIPLIER 10000 |
31 | #define ICE_RL_PROF_TS_MULTIPLIER 32 |
32 | #define ICE_RL_PROF_FRACTION 512 |
33 | |
34 | #define ICE_PSM_CLK_367MHZ_IN_HZ 367647059 |
35 | #define ICE_PSM_CLK_416MHZ_IN_HZ 416666667 |
36 | #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571 |
37 | #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000 |
38 | |
39 | /* BW rate limit profile parameters list entry along |
40 | * with bandwidth maintained per layer in port info |
41 | */ |
42 | struct ice_aqc_rl_profile_info { |
43 | struct ice_aqc_rl_profile_elem profile; |
44 | struct list_head list_entry; |
45 | u32 bw; /* requested */ |
46 | u16 prof_id_ref; /* profile ID to node association ref count */ |
47 | }; |
48 | |
49 | struct ice_sched_agg_vsi_info { |
50 | struct list_head list_entry; |
51 | DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); |
52 | u16 vsi_handle; |
53 | /* save aggregator VSI TC bitmap */ |
54 | DECLARE_BITMAP(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS); |
55 | }; |
56 | |
57 | struct ice_sched_agg_info { |
58 | struct list_head agg_vsi_list; |
59 | struct list_head list_entry; |
60 | DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); |
61 | u32 agg_id; |
62 | enum ice_agg_type agg_type; |
63 | /* bw_t_info saves aggregator BW information */ |
64 | struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; |
65 | /* save aggregator TC bitmap */ |
66 | DECLARE_BITMAP(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS); |
67 | }; |
68 | |
69 | /* FW AQ command calls */ |
70 | int |
71 | ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, |
72 | struct ice_aqc_txsched_elem_data *buf, u16 buf_size, |
73 | u16 *elems_ret, struct ice_sq_cd *cd); |
74 | |
75 | int |
76 | ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node, |
77 | enum ice_rl_type rl_type, u32 bw); |
78 | |
79 | int |
80 | ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node, |
81 | enum ice_rl_type rl_type, u32 bw, u8 layer_num); |
82 | |
83 | int |
84 | ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, |
85 | struct ice_sched_node *parent, u8 layer, u16 num_nodes, |
86 | u16 *num_nodes_added, u32 *first_node_teid, |
87 | struct ice_sched_node **prealloc_node); |
88 | |
89 | int |
90 | ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent, |
91 | u16 num_items, u32 *list); |
92 | |
93 | int ice_sched_set_node_priority(struct ice_port_info *pi, struct ice_sched_node *node, |
94 | u16 priority); |
95 | int ice_sched_set_node_weight(struct ice_port_info *pi, struct ice_sched_node *node, u16 weight); |
96 | |
97 | int ice_sched_init_port(struct ice_port_info *pi); |
98 | int ice_sched_query_res_alloc(struct ice_hw *hw); |
99 | void ice_sched_get_psm_clk_freq(struct ice_hw *hw); |
100 | |
101 | void ice_sched_clear_port(struct ice_port_info *pi); |
102 | void ice_sched_cleanup_all(struct ice_hw *hw); |
103 | void ice_sched_clear_agg(struct ice_hw *hw); |
104 | |
105 | struct ice_sched_node * |
106 | ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid); |
107 | int |
108 | ice_sched_add_node(struct ice_port_info *pi, u8 layer, |
109 | struct ice_aqc_txsched_elem_data *info, |
110 | struct ice_sched_node *prealloc_node); |
111 | void |
112 | ice_sched_update_parent(struct ice_sched_node *new_parent, |
113 | struct ice_sched_node *node); |
114 | void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node); |
115 | struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc); |
116 | struct ice_sched_node * |
117 | ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, |
118 | u8 owner); |
119 | int |
120 | ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs, |
121 | u8 owner, bool enable); |
122 | int ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle); |
123 | int ice_rm_vsi_rdma_cfg(struct ice_port_info *pi, u16 vsi_handle); |
124 | |
125 | /* Tx scheduler rate limiter functions */ |
126 | int |
127 | ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, |
128 | enum ice_agg_type agg_type, u8 tc_bitmap); |
129 | int |
130 | ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, |
131 | u8 tc_bitmap); |
132 | int |
133 | ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, |
134 | u16 q_handle, enum ice_rl_type rl_type, u32 bw); |
135 | int |
136 | ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, |
137 | u16 q_handle, enum ice_rl_type rl_type); |
138 | int |
139 | ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, |
140 | enum ice_rl_type rl_type, u32 bw); |
141 | int |
142 | ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, |
143 | enum ice_rl_type rl_type); |
144 | int ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes); |
145 | int |
146 | ice_sched_suspend_resume_elems(struct ice_hw *hw, u8 num_nodes, u32 *node_teids, |
147 | bool suspend); |
148 | struct ice_sched_node * |
149 | ice_sched_get_agg_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, |
150 | u32 agg_id); |
151 | u8 ice_sched_get_agg_layer(struct ice_hw *hw); |
152 | u8 ice_sched_get_vsi_layer(struct ice_hw *hw); |
153 | struct ice_sched_node * |
154 | ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node, |
155 | u16 *num_nodes); |
156 | int |
157 | ice_sched_add_nodes_to_layer(struct ice_port_info *pi, |
158 | struct ice_sched_node *tc_node, |
159 | struct ice_sched_node *parent, u8 layer, |
160 | u16 num_nodes, u32 *first_node_teid, |
161 | u16 *num_nodes_added); |
162 | void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw); |
163 | void ice_sched_replay_agg(struct ice_hw *hw); |
164 | int ice_aq_move_sched_elems(struct ice_hw *hw, struct ice_aqc_move_elem *buf, |
165 | u16 buf_size, u16 *grps_movd); |
166 | int ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle); |
167 | int ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx); |
168 | #endif /* _ICE_SCHED_H_ */ |
169 | |