1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (c) 2018-2023, Intel Corporation. */ |
3 | |
4 | #ifndef _ICE_TYPE_H_ |
5 | #define _ICE_TYPE_H_ |
6 | |
7 | #define ICE_BYTES_PER_WORD 2 |
8 | #define ICE_BYTES_PER_DWORD 4 |
9 | #define ICE_CHNL_MAX_TC 16 |
10 | |
11 | #include "ice_hw_autogen.h" |
12 | #include "ice_devids.h" |
13 | #include "ice_osdep.h" |
14 | #include "ice_controlq.h" |
15 | #include "ice_lan_tx_rx.h" |
16 | #include "ice_flex_type.h" |
17 | #include "ice_protocol_type.h" |
18 | #include "ice_sbq_cmd.h" |
19 | #include "ice_vlan_mode.h" |
20 | |
21 | static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) |
22 | { |
23 | return test_bit(tc, &bitmap); |
24 | } |
25 | |
26 | static inline u64 round_up_64bit(u64 a, u32 b) |
27 | { |
28 | return div64_long(((a) + (b) / 2), (b)); |
29 | } |
30 | |
31 | static inline u32 ice_round_to_num(u32 N, u32 R) |
32 | { |
33 | return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : |
34 | ((((N) + (R) - 1) / (R)) * (R))); |
35 | } |
36 | |
37 | /* Driver always calls main vsi_handle first */ |
38 | #define ICE_MAIN_VSI_HANDLE 0 |
39 | |
40 | /* debug masks - set these bits in hw->debug_mask to control output */ |
41 | #define ICE_DBG_INIT BIT_ULL(1) |
42 | #define ICE_DBG_FW_LOG BIT_ULL(3) |
43 | #define ICE_DBG_LINK BIT_ULL(4) |
44 | #define ICE_DBG_PHY BIT_ULL(5) |
45 | #define ICE_DBG_QCTX BIT_ULL(6) |
46 | #define ICE_DBG_NVM BIT_ULL(7) |
47 | #define ICE_DBG_LAN BIT_ULL(8) |
48 | #define ICE_DBG_FLOW BIT_ULL(9) |
49 | #define ICE_DBG_SW BIT_ULL(13) |
50 | #define ICE_DBG_SCHED BIT_ULL(14) |
51 | #define ICE_DBG_RDMA BIT_ULL(15) |
52 | #define ICE_DBG_PKG BIT_ULL(16) |
53 | #define ICE_DBG_RES BIT_ULL(17) |
54 | #define ICE_DBG_PTP BIT_ULL(19) |
55 | #define ICE_DBG_AQ_MSG BIT_ULL(24) |
56 | #define ICE_DBG_AQ_DESC BIT_ULL(25) |
57 | #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) |
58 | #define ICE_DBG_AQ_CMD BIT_ULL(27) |
59 | #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \ |
60 | ICE_DBG_AQ_DESC | \ |
61 | ICE_DBG_AQ_DESC_BUF | \ |
62 | ICE_DBG_AQ_CMD) |
63 | |
64 | #define ICE_DBG_USER BIT_ULL(31) |
65 | |
66 | enum ice_aq_res_ids { |
67 | ICE_NVM_RES_ID = 1, |
68 | ICE_SPD_RES_ID, |
69 | ICE_CHANGE_LOCK_RES_ID, |
70 | ICE_GLOBAL_CFG_LOCK_RES_ID |
71 | }; |
72 | |
73 | /* FW update timeout definitions are in milliseconds */ |
74 | #define ICE_NVM_TIMEOUT 180000 |
75 | #define ICE_CHANGE_LOCK_TIMEOUT 1000 |
76 | #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000 |
77 | |
78 | enum ice_aq_res_access_type { |
79 | ICE_RES_READ = 1, |
80 | ICE_RES_WRITE |
81 | }; |
82 | |
83 | struct ice_driver_ver { |
84 | u8 major_ver; |
85 | u8 minor_ver; |
86 | u8 build_ver; |
87 | u8 subbuild_ver; |
88 | u8 driver_string[32]; |
89 | }; |
90 | |
91 | enum ice_fc_mode { |
92 | ICE_FC_NONE = 0, |
93 | ICE_FC_RX_PAUSE, |
94 | ICE_FC_TX_PAUSE, |
95 | ICE_FC_FULL, |
96 | ICE_FC_PFC, |
97 | ICE_FC_DFLT |
98 | }; |
99 | |
100 | enum ice_phy_cache_mode { |
101 | ICE_FC_MODE = 0, |
102 | ICE_SPEED_MODE, |
103 | ICE_FEC_MODE |
104 | }; |
105 | |
106 | enum ice_fec_mode { |
107 | ICE_FEC_NONE = 0, |
108 | ICE_FEC_RS, |
109 | ICE_FEC_BASER, |
110 | ICE_FEC_AUTO |
111 | }; |
112 | |
113 | struct ice_phy_cache_mode_data { |
114 | union { |
115 | enum ice_fec_mode curr_user_fec_req; |
116 | enum ice_fc_mode curr_user_fc_req; |
117 | u16 curr_user_speed_req; |
118 | } data; |
119 | }; |
120 | |
121 | enum ice_set_fc_aq_failures { |
122 | ICE_SET_FC_AQ_FAIL_NONE = 0, |
123 | ICE_SET_FC_AQ_FAIL_GET, |
124 | ICE_SET_FC_AQ_FAIL_SET, |
125 | ICE_SET_FC_AQ_FAIL_UPDATE |
126 | }; |
127 | |
128 | /* Various MAC types */ |
129 | enum ice_mac_type { |
130 | ICE_MAC_UNKNOWN = 0, |
131 | ICE_MAC_E810, |
132 | ICE_MAC_E830, |
133 | ICE_MAC_GENERIC, |
134 | }; |
135 | |
136 | /* Media Types */ |
137 | enum ice_media_type { |
138 | ICE_MEDIA_UNKNOWN = 0, |
139 | ICE_MEDIA_FIBER, |
140 | ICE_MEDIA_BASET, |
141 | ICE_MEDIA_BACKPLANE, |
142 | ICE_MEDIA_DA, |
143 | }; |
144 | |
145 | enum ice_vsi_type { |
146 | ICE_VSI_PF = 0, |
147 | ICE_VSI_VF = 1, |
148 | ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */ |
149 | ICE_VSI_CHNL = 4, |
150 | ICE_VSI_LB = 6, |
151 | ICE_VSI_SWITCHDEV_CTRL = 7, |
152 | }; |
153 | |
154 | struct ice_link_status { |
155 | /* Refer to ice_aq_phy_type for bits definition */ |
156 | u64 phy_type_low; |
157 | u64 phy_type_high; |
158 | u8 topo_media_conflict; |
159 | u16 max_frame_size; |
160 | u16 link_speed; |
161 | u16 req_speeds; |
162 | u8 link_cfg_err; |
163 | u8 lse_ena; /* Link Status Event notification */ |
164 | u8 link_info; |
165 | u8 an_info; |
166 | u8 ext_info; |
167 | u8 fec_info; |
168 | u8 pacing; |
169 | /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of |
170 | * ice_aqc_get_phy_caps structure |
171 | */ |
172 | u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; |
173 | }; |
174 | |
175 | /* Different reset sources for which a disable queue AQ call has to be made in |
176 | * order to clean the Tx scheduler as a part of the reset |
177 | */ |
178 | enum ice_disq_rst_src { |
179 | ICE_NO_RESET = 0, |
180 | ICE_VM_RESET, |
181 | ICE_VF_RESET, |
182 | }; |
183 | |
184 | /* PHY info such as phy_type, etc... */ |
185 | struct ice_phy_info { |
186 | struct ice_link_status link_info; |
187 | struct ice_link_status link_info_old; |
188 | u64 phy_type_low; |
189 | u64 phy_type_high; |
190 | enum ice_media_type media_type; |
191 | u8 get_link_info; |
192 | /* Please refer to struct ice_aqc_get_link_status_data to get |
193 | * detail of enable bit in curr_user_speed_req |
194 | */ |
195 | u16 curr_user_speed_req; |
196 | enum ice_fec_mode curr_user_fec_req; |
197 | enum ice_fc_mode curr_user_fc_req; |
198 | struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; |
199 | }; |
200 | |
201 | /* protocol enumeration for filters */ |
202 | enum ice_fltr_ptype { |
203 | /* NONE - used for undef/error */ |
204 | ICE_FLTR_PTYPE_NONF_NONE = 0, |
205 | ICE_FLTR_PTYPE_NONF_IPV4_UDP, |
206 | ICE_FLTR_PTYPE_NONF_IPV4_TCP, |
207 | ICE_FLTR_PTYPE_NONF_IPV4_SCTP, |
208 | ICE_FLTR_PTYPE_NONF_IPV4_OTHER, |
209 | ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, |
210 | ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, |
211 | ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, |
212 | ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER, |
213 | ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER, |
214 | ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3, |
215 | ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3, |
216 | ICE_FLTR_PTYPE_NONF_IPV4_ESP, |
217 | ICE_FLTR_PTYPE_NONF_IPV6_ESP, |
218 | ICE_FLTR_PTYPE_NONF_IPV4_AH, |
219 | ICE_FLTR_PTYPE_NONF_IPV6_AH, |
220 | ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP, |
221 | ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP, |
222 | ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE, |
223 | ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION, |
224 | ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE, |
225 | ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION, |
226 | ICE_FLTR_PTYPE_NON_IP_L2, |
227 | ICE_FLTR_PTYPE_FRAG_IPV4, |
228 | ICE_FLTR_PTYPE_NONF_IPV6_UDP, |
229 | ICE_FLTR_PTYPE_NONF_IPV6_TCP, |
230 | ICE_FLTR_PTYPE_NONF_IPV6_SCTP, |
231 | ICE_FLTR_PTYPE_NONF_IPV6_OTHER, |
232 | ICE_FLTR_PTYPE_MAX, |
233 | }; |
234 | |
235 | enum ice_fd_hw_seg { |
236 | ICE_FD_HW_SEG_NON_TUN = 0, |
237 | ICE_FD_HW_SEG_TUN, |
238 | ICE_FD_HW_SEG_MAX, |
239 | }; |
240 | |
241 | /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */ |
242 | #define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC) |
243 | |
244 | struct ice_fd_hw_prof { |
245 | struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; |
246 | int cnt; |
247 | u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; |
248 | u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; |
249 | }; |
250 | |
251 | /* Common HW capabilities for SW use */ |
252 | struct ice_hw_common_caps { |
253 | u32 valid_functions; |
254 | /* DCB capabilities */ |
255 | u32 active_tc_bitmap; |
256 | u32 maxtc; |
257 | |
258 | /* Tx/Rx queues */ |
259 | u16 num_rxq; /* Number/Total Rx queues */ |
260 | u16 rxq_first_id; /* First queue ID for Rx queues */ |
261 | u16 num_txq; /* Number/Total Tx queues */ |
262 | u16 txq_first_id; /* First queue ID for Tx queues */ |
263 | |
264 | /* MSI-X vectors */ |
265 | u16 num_msix_vectors; |
266 | u16 msix_vector_first_id; |
267 | |
268 | /* Max MTU for function or device */ |
269 | u16 max_mtu; |
270 | |
271 | /* Virtualization support */ |
272 | u8 sr_iov_1_1; /* SR-IOV enabled */ |
273 | |
274 | /* RSS related capabilities */ |
275 | u16 ; /* 512 for PFs and 64 for VFs */ |
276 | u8 ; /* RSS Entry width in bits */ |
277 | |
278 | u8 dcb; |
279 | u8 ieee_1588; |
280 | u8 rdma; |
281 | u8 roce_lag; |
282 | u8 sriov_lag; |
283 | |
284 | bool nvm_update_pending_nvm; |
285 | bool nvm_update_pending_orom; |
286 | bool nvm_update_pending_netlist; |
287 | #define ICE_NVM_PENDING_NVM_IMAGE BIT(0) |
288 | #define ICE_NVM_PENDING_OROM BIT(1) |
289 | #define ICE_NVM_PENDING_NETLIST BIT(2) |
290 | bool nvm_unified_update; |
291 | #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) |
292 | /* PCIe reset avoidance */ |
293 | bool pcie_reset_avoidance; |
294 | /* Post update reset restriction */ |
295 | bool reset_restrict_support; |
296 | }; |
297 | |
298 | /* IEEE 1588 TIME_SYNC specific info */ |
299 | /* Function specific definitions */ |
300 | #define ICE_TS_FUNC_ENA_M BIT(0) |
301 | #define ICE_TS_SRC_TMR_OWND_M BIT(1) |
302 | #define ICE_TS_TMR_ENA_M BIT(2) |
303 | #define ICE_TS_TMR_IDX_OWND_S 4 |
304 | #define ICE_TS_TMR_IDX_OWND_M BIT(4) |
305 | #define ICE_TS_CLK_FREQ_S 16 |
306 | #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S) |
307 | #define ICE_TS_CLK_SRC_S 20 |
308 | #define ICE_TS_CLK_SRC_M BIT(20) |
309 | #define ICE_TS_TMR_IDX_ASSOC_S 24 |
310 | #define ICE_TS_TMR_IDX_ASSOC_M BIT(24) |
311 | |
312 | /* TIME_REF clock rate specification */ |
313 | enum ice_time_ref_freq { |
314 | ICE_TIME_REF_FREQ_25_000 = 0, |
315 | ICE_TIME_REF_FREQ_122_880 = 1, |
316 | ICE_TIME_REF_FREQ_125_000 = 2, |
317 | ICE_TIME_REF_FREQ_153_600 = 3, |
318 | ICE_TIME_REF_FREQ_156_250 = 4, |
319 | ICE_TIME_REF_FREQ_245_760 = 5, |
320 | |
321 | NUM_ICE_TIME_REF_FREQ |
322 | }; |
323 | |
324 | /* Clock source specification */ |
325 | enum ice_clk_src { |
326 | ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */ |
327 | ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */ |
328 | |
329 | NUM_ICE_CLK_SRC |
330 | }; |
331 | |
332 | struct ice_ts_func_info { |
333 | /* Function specific info */ |
334 | enum ice_time_ref_freq time_ref; |
335 | u8 clk_freq; |
336 | u8 clk_src; |
337 | u8 tmr_index_assoc; |
338 | u8 ena; |
339 | u8 tmr_index_owned; |
340 | u8 src_tmr_owned; |
341 | u8 tmr_ena; |
342 | }; |
343 | |
344 | /* Device specific definitions */ |
345 | #define ICE_TS_TMR0_OWNR_M 0x7 |
346 | #define ICE_TS_TMR0_OWND_M BIT(3) |
347 | #define ICE_TS_TMR1_OWNR_S 4 |
348 | #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S) |
349 | #define ICE_TS_TMR1_OWND_M BIT(7) |
350 | #define ICE_TS_DEV_ENA_M BIT(24) |
351 | #define ICE_TS_TMR0_ENA_M BIT(25) |
352 | #define ICE_TS_TMR1_ENA_M BIT(26) |
353 | #define ICE_TS_LL_TX_TS_READ_M BIT(28) |
354 | |
355 | struct ice_ts_dev_info { |
356 | /* Device specific info */ |
357 | u32 ena_ports; |
358 | u32 tmr_own_map; |
359 | u32 tmr0_owner; |
360 | u32 tmr1_owner; |
361 | u8 tmr0_owned; |
362 | u8 tmr1_owned; |
363 | u8 ena; |
364 | u8 tmr0_ena; |
365 | u8 tmr1_ena; |
366 | u8 ts_ll_read; |
367 | }; |
368 | |
369 | /* Function specific capabilities */ |
370 | struct ice_hw_func_caps { |
371 | struct ice_hw_common_caps common_cap; |
372 | u32 num_allocd_vfs; /* Number of allocated VFs */ |
373 | u32 vf_base_id; /* Logical ID of the first VF */ |
374 | u32 guar_num_vsi; |
375 | u32 fd_fltr_guar; /* Number of filters guaranteed */ |
376 | u32 fd_fltr_best_effort; /* Number of best effort filters */ |
377 | struct ice_ts_func_info ts_func_info; |
378 | }; |
379 | |
380 | /* Device wide capabilities */ |
381 | struct ice_hw_dev_caps { |
382 | struct ice_hw_common_caps common_cap; |
383 | u32 num_vfs_exposed; /* Total number of VFs exposed */ |
384 | u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ |
385 | u32 num_flow_director_fltr; /* Number of FD filters available */ |
386 | struct ice_ts_dev_info ts_dev_info; |
387 | u32 num_funcs; |
388 | }; |
389 | |
390 | /* MAC info */ |
391 | struct ice_mac_info { |
392 | u8 lan_addr[ETH_ALEN]; |
393 | u8 perm_addr[ETH_ALEN]; |
394 | }; |
395 | |
396 | /* Reset types used to determine which kind of reset was requested. These |
397 | * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. |
398 | * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register |
399 | * because its reset source is different than the other types listed. |
400 | */ |
401 | enum ice_reset_req { |
402 | ICE_RESET_POR = 0, |
403 | ICE_RESET_INVAL = 0, |
404 | ICE_RESET_CORER = 1, |
405 | ICE_RESET_GLOBR = 2, |
406 | ICE_RESET_EMPR = 3, |
407 | ICE_RESET_PFR = 4, |
408 | }; |
409 | |
410 | /* Bus parameters */ |
411 | struct ice_bus_info { |
412 | u16 device; |
413 | u8 func; |
414 | }; |
415 | |
416 | /* Flow control (FC) parameters */ |
417 | struct ice_fc_info { |
418 | enum ice_fc_mode current_mode; /* FC mode in effect */ |
419 | enum ice_fc_mode req_mode; /* FC mode requested by caller */ |
420 | }; |
421 | |
422 | /* Option ROM version information */ |
423 | struct ice_orom_info { |
424 | u8 major; /* Major version of OROM */ |
425 | u8 patch; /* Patch version of OROM */ |
426 | u16 build; /* Build version of OROM */ |
427 | }; |
428 | |
429 | /* NVM version information */ |
430 | struct ice_nvm_info { |
431 | u32 eetrack; |
432 | u8 major; |
433 | u8 minor; |
434 | }; |
435 | |
436 | /* netlist version information */ |
437 | struct ice_netlist_info { |
438 | u32 major; /* major high/low */ |
439 | u32 minor; /* minor high/low */ |
440 | u32 type; /* type high/low */ |
441 | u32 rev; /* revision high/low */ |
442 | u32 hash; /* SHA-1 hash word */ |
443 | u16 cust_ver; /* customer version */ |
444 | }; |
445 | |
446 | /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules |
447 | * of the flash image. |
448 | */ |
449 | enum ice_flash_bank { |
450 | ICE_INVALID_FLASH_BANK, |
451 | ICE_1ST_FLASH_BANK, |
452 | ICE_2ND_FLASH_BANK, |
453 | }; |
454 | |
455 | /* Enumeration of which flash bank is desired to read from, either the active |
456 | * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from |
457 | * code which just wants to read the active or inactive flash bank. |
458 | */ |
459 | enum ice_bank_select { |
460 | ICE_ACTIVE_FLASH_BANK, |
461 | ICE_INACTIVE_FLASH_BANK, |
462 | }; |
463 | |
464 | /* information for accessing NVM, OROM, and Netlist flash banks */ |
465 | struct ice_bank_info { |
466 | u32 nvm_ptr; /* Pointer to 1st NVM bank */ |
467 | u32 nvm_size; /* Size of NVM bank */ |
468 | u32 orom_ptr; /* Pointer to 1st OROM bank */ |
469 | u32 orom_size; /* Size of OROM bank */ |
470 | u32 netlist_ptr; /* Pointer to 1st Netlist bank */ |
471 | u32 netlist_size; /* Size of Netlist bank */ |
472 | enum ice_flash_bank nvm_bank; /* Active NVM bank */ |
473 | enum ice_flash_bank orom_bank; /* Active OROM bank */ |
474 | enum ice_flash_bank netlist_bank; /* Active Netlist bank */ |
475 | }; |
476 | |
477 | /* Flash Chip Information */ |
478 | struct ice_flash_info { |
479 | struct ice_orom_info orom; /* Option ROM version info */ |
480 | struct ice_nvm_info nvm; /* NVM version information */ |
481 | struct ice_netlist_info netlist;/* Netlist version info */ |
482 | struct ice_bank_info banks; /* Flash Bank information */ |
483 | u16 sr_words; /* Shadow RAM size in words */ |
484 | u32 flash_size; /* Size of available flash in bytes */ |
485 | u8 blank_nvm_mode; /* is NVM empty (no FW present) */ |
486 | }; |
487 | |
488 | struct ice_link_default_override_tlv { |
489 | u8 options; |
490 | #define ICE_LINK_OVERRIDE_OPT_M 0x3F |
491 | #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) |
492 | #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) |
493 | #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) |
494 | #define ICE_LINK_OVERRIDE_EN BIT(3) |
495 | #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) |
496 | #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) |
497 | u8 phy_config; |
498 | #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 |
499 | #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) |
500 | #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 |
501 | #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) |
502 | #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) |
503 | u8 fec_options; |
504 | #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF |
505 | u8 rsvd1; |
506 | u64 phy_type_low; |
507 | u64 phy_type_high; |
508 | }; |
509 | |
510 | #define ICE_NVM_VER_LEN 32 |
511 | |
512 | /* Max number of port to queue branches w.r.t topology */ |
513 | #define ICE_MAX_TRAFFIC_CLASS 8 |
514 | #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS |
515 | |
516 | #define ice_for_each_traffic_class(_i) \ |
517 | for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) |
518 | |
519 | /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects |
520 | * to driver defined policy for default aggregator |
521 | */ |
522 | #define ICE_INVAL_TEID 0xFFFFFFFF |
523 | #define ICE_DFLT_AGG_ID 0 |
524 | |
525 | struct ice_sched_node { |
526 | struct ice_sched_node *parent; |
527 | struct ice_sched_node *sibling; /* next sibling in the same layer */ |
528 | struct ice_sched_node **children; |
529 | struct ice_aqc_txsched_elem_data info; |
530 | char *name; |
531 | struct devlink_rate *rate_node; |
532 | u64 tx_max; |
533 | u64 tx_share; |
534 | u32 agg_id; /* aggregator group ID */ |
535 | u32 id; |
536 | u32 tx_priority; |
537 | u32 tx_weight; |
538 | u16 vsi_handle; |
539 | u8 in_use; /* suspended or in use */ |
540 | u8 tx_sched_layer; /* Logical Layer (1-9) */ |
541 | u8 num_children; |
542 | u8 tc_num; |
543 | u8 owner; |
544 | #define ICE_SCHED_NODE_OWNER_LAN 0 |
545 | #define ICE_SCHED_NODE_OWNER_RDMA 2 |
546 | }; |
547 | |
548 | /* Access Macros for Tx Sched Elements data */ |
549 | #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) |
550 | |
551 | /* The aggregator type determines if identifier is for a VSI group, |
552 | * aggregator group, aggregator of queues, or queue group. |
553 | */ |
554 | enum ice_agg_type { |
555 | ICE_AGG_TYPE_UNKNOWN = 0, |
556 | ICE_AGG_TYPE_VSI, |
557 | ICE_AGG_TYPE_AGG, /* aggregator */ |
558 | ICE_AGG_TYPE_Q, |
559 | ICE_AGG_TYPE_QG |
560 | }; |
561 | |
562 | /* Rate limit types */ |
563 | enum ice_rl_type { |
564 | ICE_UNKNOWN_BW = 0, |
565 | ICE_MIN_BW, /* for CIR profile */ |
566 | ICE_MAX_BW, /* for EIR profile */ |
567 | ICE_SHARED_BW /* for shared profile */ |
568 | }; |
569 | |
570 | #define ICE_SCHED_MIN_BW 500 /* in Kbps */ |
571 | #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ |
572 | #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ |
573 | #define ICE_SCHED_DFLT_RL_PROF_ID 0 |
574 | #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF |
575 | #define ICE_SCHED_DFLT_BW_WT 4 |
576 | #define ICE_SCHED_INVAL_PROF_ID 0xFFFF |
577 | #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ |
578 | |
579 | #define ICE_MAX_PORT_PER_PCI_DEV 8 |
580 | |
581 | /* Data structure for saving BW information */ |
582 | enum ice_bw_type { |
583 | ICE_BW_TYPE_PRIO, |
584 | ICE_BW_TYPE_CIR, |
585 | ICE_BW_TYPE_CIR_WT, |
586 | ICE_BW_TYPE_EIR, |
587 | ICE_BW_TYPE_EIR_WT, |
588 | ICE_BW_TYPE_SHARED, |
589 | ICE_BW_TYPE_CNT /* This must be last */ |
590 | }; |
591 | |
592 | struct ice_bw { |
593 | u32 bw; |
594 | u16 bw_alloc; |
595 | }; |
596 | |
597 | struct ice_bw_type_info { |
598 | DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); |
599 | u8 generic; |
600 | struct ice_bw cir_bw; |
601 | struct ice_bw eir_bw; |
602 | u32 shared_bw; |
603 | }; |
604 | |
605 | /* VSI queue context structure for given TC */ |
606 | struct ice_q_ctx { |
607 | u16 q_handle; |
608 | u32 q_teid; |
609 | /* bw_t_info saves queue BW information */ |
610 | struct ice_bw_type_info bw_t_info; |
611 | }; |
612 | |
613 | /* VSI type list entry to locate corresponding VSI/aggregator nodes */ |
614 | struct ice_sched_vsi_info { |
615 | struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; |
616 | struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; |
617 | struct list_head list_entry; |
618 | u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; |
619 | u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS]; |
620 | /* bw_t_info saves VSI BW information */ |
621 | struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; |
622 | }; |
623 | |
624 | /* driver defines the policy */ |
625 | struct ice_sched_tx_policy { |
626 | u16 max_num_vsis; |
627 | u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; |
628 | u8 rdma_ena; |
629 | }; |
630 | |
631 | /* CEE or IEEE 802.1Qaz ETS Configuration data */ |
632 | struct ice_dcb_ets_cfg { |
633 | u8 willing; |
634 | u8 cbs; |
635 | u8 maxtcs; |
636 | u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; |
637 | u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; |
638 | u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; |
639 | }; |
640 | |
641 | /* CEE or IEEE 802.1Qaz PFC Configuration data */ |
642 | struct ice_dcb_pfc_cfg { |
643 | u8 willing; |
644 | u8 mbc; |
645 | u8 pfccap; |
646 | u8 pfcena; |
647 | }; |
648 | |
649 | /* CEE or IEEE 802.1Qaz Application Priority data */ |
650 | struct ice_dcb_app_priority_table { |
651 | u16 prot_id; |
652 | u8 priority; |
653 | u8 selector; |
654 | }; |
655 | |
656 | #define ICE_MAX_USER_PRIORITY 8 |
657 | #define ICE_DCBX_MAX_APPS 64 |
658 | #define ICE_DSCP_NUM_VAL 64 |
659 | #define ICE_LLDPDU_SIZE 1500 |
660 | #define ICE_TLV_STATUS_OPER 0x1 |
661 | #define ICE_TLV_STATUS_SYNC 0x2 |
662 | #define ICE_TLV_STATUS_ERR 0x4 |
663 | #define ICE_APP_PROT_ID_ISCSI_860 0x035c |
664 | #define ICE_APP_SEL_ETHTYPE 0x1 |
665 | #define ICE_APP_SEL_TCPIP 0x2 |
666 | #define ICE_CEE_APP_SEL_ETHTYPE 0x0 |
667 | #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 |
668 | #define ICE_CEE_APP_SEL_TCPIP 0x1 |
669 | |
670 | struct ice_dcbx_cfg { |
671 | u32 numapps; |
672 | u32 tlv_status; /* CEE mode TLV status */ |
673 | struct ice_dcb_ets_cfg etscfg; |
674 | struct ice_dcb_ets_cfg etsrec; |
675 | struct ice_dcb_pfc_cfg pfc; |
676 | #define ICE_QOS_MODE_VLAN 0x0 |
677 | #define ICE_QOS_MODE_DSCP 0x1 |
678 | u8 pfc_mode; |
679 | struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; |
680 | /* when DSCP mapping defined by user set its bit to 1 */ |
681 | DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL); |
682 | /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */ |
683 | u8 dscp_map[ICE_DSCP_NUM_VAL]; |
684 | u8 dcbx_mode; |
685 | #define ICE_DCBX_MODE_CEE 0x1 |
686 | #define ICE_DCBX_MODE_IEEE 0x2 |
687 | u8 app_mode; |
688 | #define ICE_DCBX_APPS_NON_WILLING 0x1 |
689 | }; |
690 | |
691 | struct ice_qos_cfg { |
692 | struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ |
693 | struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ |
694 | struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ |
695 | u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ |
696 | u8 is_sw_lldp : 1; |
697 | }; |
698 | |
699 | struct ice_port_info { |
700 | struct ice_sched_node *root; /* Root Node per Port */ |
701 | struct ice_hw *hw; /* back pointer to HW instance */ |
702 | u32 last_node_teid; /* scheduler last node info */ |
703 | u16 sw_id; /* Initial switch ID belongs to port */ |
704 | u16 pf_vf_num; |
705 | u8 port_state; |
706 | #define ICE_SCHED_PORT_STATE_INIT 0x0 |
707 | #define ICE_SCHED_PORT_STATE_READY 0x1 |
708 | u8 lport; |
709 | #define ICE_LPORT_MASK 0xff |
710 | struct ice_fc_info fc; |
711 | struct ice_mac_info mac; |
712 | struct ice_phy_info phy; |
713 | struct mutex sched_lock; /* protect access to TXSched tree */ |
714 | struct ice_sched_node * |
715 | sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; |
716 | /* List contain profile ID(s) and other params per layer */ |
717 | struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; |
718 | struct ice_qos_cfg qos_cfg; |
719 | struct xarray sched_node_ids; |
720 | u8 is_vf:1; |
721 | u8 is_custom_tx_enabled:1; |
722 | }; |
723 | |
724 | struct ice_switch_info { |
725 | struct list_head vsi_list_map_head; |
726 | struct ice_sw_recipe *recp_list; |
727 | u16 prof_res_bm_init; |
728 | u16 max_used_prof_index; |
729 | |
730 | DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); |
731 | }; |
732 | |
733 | /* FW logging configuration */ |
734 | struct ice_fw_log_evnt { |
735 | u8 cfg : 4; /* New event enables to configure */ |
736 | u8 cur : 4; /* Current/active event enables */ |
737 | }; |
738 | |
739 | struct ice_fw_log_cfg { |
740 | u8 cq_en : 1; /* FW logging is enabled via the control queue */ |
741 | u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ |
742 | u8 actv_evnts; /* Cumulation of currently enabled log events */ |
743 | |
744 | #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) |
745 | #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) |
746 | #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) |
747 | #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) |
748 | struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; |
749 | }; |
750 | |
751 | /* Enum defining the different states of the mailbox snapshot in the |
752 | * PF-VF mailbox overflow detection algorithm. The snapshot can be in |
753 | * states: |
754 | * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot |
755 | * within the mailbox buffer. |
756 | * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot |
757 | * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the |
758 | * mailbox and mark any VFs sending more messages than the threshold limit set. |
759 | * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. |
760 | */ |
761 | enum ice_mbx_snapshot_state { |
762 | ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, |
763 | ICE_MAL_VF_DETECT_STATE_TRAVERSE, |
764 | ICE_MAL_VF_DETECT_STATE_DETECT, |
765 | ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, |
766 | }; |
767 | |
768 | /* Structure to hold information of the static snapshot and the mailbox |
769 | * buffer data used to generate and track the snapshot. |
770 | * 1. state: the state of the mailbox snapshot in the malicious VF |
771 | * detection state handler ice_mbx_vf_state_handler() |
772 | * 2. head: head of the mailbox snapshot in a circular mailbox buffer |
773 | * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer |
774 | * 4. num_iterations: number of messages traversed in circular mailbox buffer |
775 | * 5. num_msg_proc: number of messages processed in mailbox |
776 | * 6. num_pending_arq: number of pending asynchronous messages |
777 | * 7. max_num_msgs_mbx: maximum messages in mailbox for currently |
778 | * serviced work item or interrupt. |
779 | */ |
780 | struct ice_mbx_snap_buffer_data { |
781 | enum ice_mbx_snapshot_state state; |
782 | u32 head; |
783 | u32 tail; |
784 | u32 num_iterations; |
785 | u16 num_msg_proc; |
786 | u16 num_pending_arq; |
787 | u16 max_num_msgs_mbx; |
788 | }; |
789 | |
790 | /* Structure used to track a single VF's messages on the mailbox: |
791 | * 1. list_entry: linked list entry node |
792 | * 2. msg_count: the number of asynchronous messages sent by this VF |
793 | * 3. malicious: whether this VF has been detected as malicious before |
794 | */ |
795 | struct ice_mbx_vf_info { |
796 | struct list_head list_entry; |
797 | u32 msg_count; |
798 | u8 malicious : 1; |
799 | }; |
800 | |
801 | /* Structure to hold data relevant to the captured static snapshot |
802 | * of the PF-VF mailbox. |
803 | */ |
804 | struct ice_mbx_snapshot { |
805 | struct ice_mbx_snap_buffer_data mbx_buf; |
806 | struct list_head mbx_vf; |
807 | }; |
808 | |
809 | /* Structure to hold data to be used for capturing or updating a |
810 | * static snapshot. |
811 | * 1. num_msg_proc: number of messages processed in mailbox |
812 | * 2. num_pending_arq: number of pending asynchronous messages |
813 | * 3. max_num_msgs_mbx: maximum messages in mailbox for currently |
814 | * serviced work item or interrupt. |
815 | * 4. async_watermark_val: An upper threshold set by caller to determine |
816 | * if the pending arq count is large enough to assume that there is |
817 | * the possibility of a mailicious VF. |
818 | */ |
819 | struct ice_mbx_data { |
820 | u16 num_msg_proc; |
821 | u16 num_pending_arq; |
822 | u16 max_num_msgs_mbx; |
823 | u16 async_watermark_val; |
824 | }; |
825 | |
826 | /* PHY model */ |
827 | enum ice_phy_model { |
828 | ICE_PHY_UNSUP = -1, |
829 | ICE_PHY_E810 = 1, |
830 | ICE_PHY_E822, |
831 | }; |
832 | |
833 | /* Port hardware description */ |
834 | struct ice_hw { |
835 | u8 __iomem *hw_addr; |
836 | void *back; |
837 | struct ice_aqc_layer_props *layer_info; |
838 | struct ice_port_info *port_info; |
839 | /* PSM clock frequency for calculating RL profile params */ |
840 | u32 psm_clk_freq; |
841 | u64 debug_mask; /* bitmap for debug mask */ |
842 | enum ice_mac_type mac_type; |
843 | |
844 | u16 fd_ctr_base; /* FD counter base index */ |
845 | |
846 | /* pci info */ |
847 | u16 device_id; |
848 | u16 vendor_id; |
849 | u16 subsystem_device_id; |
850 | u16 subsystem_vendor_id; |
851 | u8 revision_id; |
852 | |
853 | u8 pf_id; /* device profile info */ |
854 | enum ice_phy_model phy_model; |
855 | |
856 | u16 max_burst_size; /* driver sets this value */ |
857 | |
858 | /* Tx Scheduler values */ |
859 | u8 num_tx_sched_layers; |
860 | u8 num_tx_sched_phys_layers; |
861 | u8 flattened_layers; |
862 | u8 max_cgds; |
863 | u8 sw_entry_point_layer; |
864 | u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; |
865 | struct list_head agg_list; /* lists all aggregator */ |
866 | |
867 | struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; |
868 | u8 evb_veb; /* true for VEB, false for VEPA */ |
869 | u8 reset_ongoing; /* true if HW is in reset, false otherwise */ |
870 | struct ice_bus_info bus; |
871 | struct ice_flash_info flash; |
872 | struct ice_hw_dev_caps dev_caps; /* device capabilities */ |
873 | struct ice_hw_func_caps func_caps; /* function capabilities */ |
874 | |
875 | struct ice_switch_info *switch_info; /* switch filter lists */ |
876 | |
877 | /* Control Queue info */ |
878 | struct ice_ctl_q_info adminq; |
879 | struct ice_ctl_q_info sbq; |
880 | struct ice_ctl_q_info mailboxq; |
881 | |
882 | u8 api_branch; /* API branch version */ |
883 | u8 api_maj_ver; /* API major version */ |
884 | u8 api_min_ver; /* API minor version */ |
885 | u8 api_patch; /* API patch version */ |
886 | u8 fw_branch; /* firmware branch version */ |
887 | u8 fw_maj_ver; /* firmware major version */ |
888 | u8 fw_min_ver; /* firmware minor version */ |
889 | u8 fw_patch; /* firmware patch version */ |
890 | u32 fw_build; /* firmware build number */ |
891 | |
892 | struct ice_fw_log_cfg fw_log; |
893 | |
894 | /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL |
895 | * register. Used for determining the ITR/INTRL granularity during |
896 | * initialization. |
897 | */ |
898 | #define ICE_MAX_AGG_BW_200G 0x0 |
899 | #define ICE_MAX_AGG_BW_100G 0X1 |
900 | #define ICE_MAX_AGG_BW_50G 0x2 |
901 | #define ICE_MAX_AGG_BW_25G 0x3 |
902 | /* ITR granularity for different speeds */ |
903 | #define ICE_ITR_GRAN_ABOVE_25 2 |
904 | #define ICE_ITR_GRAN_MAX_25 4 |
905 | /* ITR granularity in 1 us */ |
906 | u8 itr_gran; |
907 | /* INTRL granularity for different speeds */ |
908 | #define ICE_INTRL_GRAN_ABOVE_25 4 |
909 | #define ICE_INTRL_GRAN_MAX_25 8 |
910 | /* INTRL granularity in 1 us */ |
911 | u8 intrl_gran; |
912 | |
913 | #define ICE_PHY_PER_NAC_E822 1 |
914 | #define ICE_MAX_QUAD 2 |
915 | #define ICE_QUADS_PER_PHY_E822 2 |
916 | #define ICE_PORTS_PER_PHY_E822 8 |
917 | #define ICE_PORTS_PER_QUAD 4 |
918 | #define ICE_PORTS_PER_PHY_E810 4 |
919 | #define ICE_NUM_EXTERNAL_PORTS (ICE_MAX_QUAD * ICE_PORTS_PER_QUAD) |
920 | |
921 | /* Active package version (currently active) */ |
922 | struct ice_pkg_ver active_pkg_ver; |
923 | u32 pkg_seg_id; |
924 | u32 pkg_sign_type; |
925 | u32 active_track_id; |
926 | u8 pkg_has_signing_seg:1; |
927 | u8 active_pkg_name[ICE_PKG_NAME_SIZE]; |
928 | u8 active_pkg_in_nvm; |
929 | |
930 | /* Driver's package ver - (from the Ice Metadata section) */ |
931 | struct ice_pkg_ver pkg_ver; |
932 | u8 pkg_name[ICE_PKG_NAME_SIZE]; |
933 | |
934 | /* Driver's Ice segment format version and ID (from the Ice seg) */ |
935 | struct ice_pkg_ver ice_seg_fmt_ver; |
936 | u8 ice_seg_id[ICE_SEG_ID_SIZE]; |
937 | |
938 | /* Pointer to the ice segment */ |
939 | struct ice_seg *seg; |
940 | |
941 | /* Pointer to allocated copy of pkg memory */ |
942 | u8 *pkg_copy; |
943 | u32 pkg_size; |
944 | |
945 | /* tunneling info */ |
946 | struct mutex tnl_lock; |
947 | struct ice_tunnel_table tnl; |
948 | |
949 | struct udp_tunnel_nic_shared udp_tunnel_shared; |
950 | struct udp_tunnel_nic_info udp_tunnel_nic; |
951 | |
952 | /* dvm boost update information */ |
953 | struct ice_dvm_table dvm_upd; |
954 | |
955 | /* HW block tables */ |
956 | struct ice_blk_info blk[ICE_BLK_COUNT]; |
957 | struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ |
958 | struct list_head fl_profs[ICE_BLK_COUNT]; |
959 | |
960 | /* Flow Director filter info */ |
961 | int fdir_active_fltr; |
962 | |
963 | struct mutex fdir_fltr_lock; /* protect Flow Director */ |
964 | struct list_head fdir_list_head; |
965 | |
966 | /* Book-keeping of side-band filter count per flow-type. |
967 | * This is used to detect and handle input set changes for |
968 | * respective flow-type. |
969 | */ |
970 | u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX]; |
971 | |
972 | struct ice_fd_hw_prof **fdir_prof; |
973 | DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); |
974 | struct mutex ; /* protect RSS configuration */ |
975 | struct list_head ; |
976 | struct ice_mbx_snapshot mbx_snapshot; |
977 | DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX); |
978 | u8 dvm_ena; |
979 | u16 io_expander_handle; |
980 | u8 cgu_part_number; |
981 | }; |
982 | |
983 | /* Statistics collected by each port, VSI, VEB, and S-channel */ |
984 | struct ice_eth_stats { |
985 | u64 rx_bytes; /* gorc */ |
986 | u64 rx_unicast; /* uprc */ |
987 | u64 rx_multicast; /* mprc */ |
988 | u64 rx_broadcast; /* bprc */ |
989 | u64 rx_discards; /* rdpc */ |
990 | u64 rx_unknown_protocol; /* rupp */ |
991 | u64 tx_bytes; /* gotc */ |
992 | u64 tx_unicast; /* uptc */ |
993 | u64 tx_multicast; /* mptc */ |
994 | u64 tx_broadcast; /* bptc */ |
995 | u64 tx_discards; /* tdpc */ |
996 | u64 tx_errors; /* tepc */ |
997 | }; |
998 | |
999 | #define ICE_MAX_UP 8 |
1000 | |
1001 | /* Statistics collected by the MAC */ |
1002 | struct ice_hw_port_stats { |
1003 | /* eth stats collected by the port */ |
1004 | struct ice_eth_stats eth; |
1005 | /* additional port specific stats */ |
1006 | u64 tx_dropped_link_down; /* tdold */ |
1007 | u64 crc_errors; /* crcerrs */ |
1008 | u64 illegal_bytes; /* illerrc */ |
1009 | u64 error_bytes; /* errbc */ |
1010 | u64 mac_local_faults; /* mlfc */ |
1011 | u64 mac_remote_faults; /* mrfc */ |
1012 | u64 rx_len_errors; /* rlec */ |
1013 | u64 link_xon_rx; /* lxonrxc */ |
1014 | u64 link_xoff_rx; /* lxoffrxc */ |
1015 | u64 link_xon_tx; /* lxontxc */ |
1016 | u64 link_xoff_tx; /* lxofftxc */ |
1017 | u64 priority_xon_rx[8]; /* pxonrxc[8] */ |
1018 | u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ |
1019 | u64 priority_xon_tx[8]; /* pxontxc[8] */ |
1020 | u64 priority_xoff_tx[8]; /* pxofftxc[8] */ |
1021 | u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ |
1022 | u64 rx_size_64; /* prc64 */ |
1023 | u64 rx_size_127; /* prc127 */ |
1024 | u64 rx_size_255; /* prc255 */ |
1025 | u64 rx_size_511; /* prc511 */ |
1026 | u64 rx_size_1023; /* prc1023 */ |
1027 | u64 rx_size_1522; /* prc1522 */ |
1028 | u64 rx_size_big; /* prc9522 */ |
1029 | u64 rx_undersize; /* ruc */ |
1030 | u64 rx_fragments; /* rfc */ |
1031 | u64 rx_oversize; /* roc */ |
1032 | u64 rx_jabber; /* rjc */ |
1033 | u64 tx_size_64; /* ptc64 */ |
1034 | u64 tx_size_127; /* ptc127 */ |
1035 | u64 tx_size_255; /* ptc255 */ |
1036 | u64 tx_size_511; /* ptc511 */ |
1037 | u64 tx_size_1023; /* ptc1023 */ |
1038 | u64 tx_size_1522; /* ptc1522 */ |
1039 | u64 tx_size_big; /* ptc9522 */ |
1040 | /* flow director stats */ |
1041 | u32 fd_sb_status; |
1042 | u64 fd_sb_match; |
1043 | }; |
1044 | |
1045 | enum ice_sw_fwd_act_type { |
1046 | ICE_FWD_TO_VSI = 0, |
1047 | ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */ |
1048 | ICE_FWD_TO_Q, |
1049 | ICE_FWD_TO_QGRP, |
1050 | ICE_DROP_PACKET, |
1051 | ICE_NOP, |
1052 | ICE_INVAL_ACT |
1053 | }; |
1054 | |
1055 | struct { |
1056 | u8 *; /* input RSS LUT for set and output RSS LUT for get */ |
1057 | enum ice_lut_size ; /* size of the LUT buffer */ |
1058 | enum ice_lut_type ; /* type of the LUT (i.e. VSI, PF, Global) */ |
1059 | u16 vsi_handle; /* software VSI handle */ |
1060 | u8 ; /* only valid when lut_type is global */ |
1061 | }; |
1062 | |
1063 | /* Checksum and Shadow RAM pointers */ |
1064 | #define ICE_SR_NVM_CTRL_WORD 0x00 |
1065 | #define ICE_SR_BOOT_CFG_PTR 0x132 |
1066 | #define ICE_SR_NVM_WOL_CFG 0x19 |
1067 | #define ICE_NVM_OROM_VER_OFF 0x02 |
1068 | #define ICE_SR_PBA_BLOCK_PTR 0x16 |
1069 | #define ICE_SR_NVM_DEV_STARTER_VER 0x18 |
1070 | #define ICE_SR_NVM_EETRACK_LO 0x2D |
1071 | #define ICE_SR_NVM_EETRACK_HI 0x2E |
1072 | #define ICE_NVM_VER_LO_SHIFT 0 |
1073 | #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) |
1074 | #define ICE_NVM_VER_HI_SHIFT 12 |
1075 | #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) |
1076 | #define ICE_OROM_VER_PATCH_SHIFT 0 |
1077 | #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) |
1078 | #define ICE_OROM_VER_BUILD_SHIFT 8 |
1079 | #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) |
1080 | #define ICE_OROM_VER_SHIFT 24 |
1081 | #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) |
1082 | #define ICE_SR_PFA_PTR 0x40 |
1083 | #define ICE_SR_1ST_NVM_BANK_PTR 0x42 |
1084 | #define ICE_SR_NVM_BANK_SIZE 0x43 |
1085 | #define ICE_SR_1ST_OROM_BANK_PTR 0x44 |
1086 | #define ICE_SR_OROM_BANK_SIZE 0x45 |
1087 | #define ICE_SR_NETLIST_BANK_PTR 0x46 |
1088 | #define ICE_SR_NETLIST_BANK_SIZE 0x47 |
1089 | #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 |
1090 | |
1091 | /* CSS Header words */ |
1092 | #define ICE_NVM_CSS_SREV_L 0x14 |
1093 | #define ICE_NVM_CSS_SREV_H 0x15 |
1094 | |
1095 | /* Length of CSS header section in words */ |
1096 | #define 330 |
1097 | |
1098 | /* Offset of Shadow RAM copy in the NVM bank area. */ |
1099 | #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32) |
1100 | |
1101 | /* Size in bytes of Option ROM trailer */ |
1102 | #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) |
1103 | |
1104 | /* The Link Topology Netlist section is stored as a series of words. It is |
1105 | * stored in the NVM as a TLV, with the first two words containing the type |
1106 | * and length. |
1107 | */ |
1108 | #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B |
1109 | #define ICE_NETLIST_TYPE_OFFSET 0x0000 |
1110 | #define ICE_NETLIST_LEN_OFFSET 0x0001 |
1111 | |
1112 | /* The Link Topology section follows the TLV header. When reading the netlist |
1113 | * using ice_read_netlist_module, we need to account for the 2-word TLV |
1114 | * header. |
1115 | */ |
1116 | #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) |
1117 | |
1118 | #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) |
1119 | #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) |
1120 | |
1121 | #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0) |
1122 | |
1123 | /* The Netlist ID Block is located after all of the Link Topology nodes. */ |
1124 | #define ICE_NETLIST_ID_BLK_SIZE 0x30 |
1125 | #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) |
1126 | |
1127 | /* netlist ID block field offsets (word offsets) */ |
1128 | #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 |
1129 | #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 |
1130 | #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 |
1131 | #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 |
1132 | #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 |
1133 | #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 |
1134 | #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 |
1135 | #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 |
1136 | #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) |
1137 | #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F |
1138 | |
1139 | /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */ |
1140 | #define ICE_SR_CTRL_WORD_1_S 0x06 |
1141 | #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) |
1142 | #define ICE_SR_CTRL_WORD_VALID 0x1 |
1143 | #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) |
1144 | #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) |
1145 | #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) |
1146 | |
1147 | #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) |
1148 | |
1149 | /* Link override related */ |
1150 | #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 |
1151 | #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 |
1152 | #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 |
1153 | #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 |
1154 | #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 |
1155 | #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 |
1156 | #define ICE_FW_API_LINK_OVERRIDE_MIN 5 |
1157 | #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 |
1158 | |
1159 | #define ICE_SR_WORDS_IN_1KB 512 |
1160 | |
1161 | /* AQ API version for LLDP_FILTER_CONTROL */ |
1162 | #define ICE_FW_API_LLDP_FLTR_MAJ 1 |
1163 | #define ICE_FW_API_LLDP_FLTR_MIN 7 |
1164 | #define ICE_FW_API_LLDP_FLTR_PATCH 1 |
1165 | |
1166 | /* AQ API version for report default configuration */ |
1167 | #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 |
1168 | #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 |
1169 | #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 |
1170 | |
1171 | #endif /* _ICE_TYPE_H_ */ |
1172 | |