1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (c) 2018 Intel Corporation */ |
3 | |
4 | #ifndef _IGC_BASE_H_ |
5 | #define _IGC_BASE_H_ |
6 | |
7 | /* forward declaration */ |
8 | void igc_rx_fifo_flush_base(struct igc_hw *hw); |
9 | void igc_power_down_phy_copper_base(struct igc_hw *hw); |
10 | bool igc_is_device_id_i225(struct igc_hw *hw); |
11 | bool igc_is_device_id_i226(struct igc_hw *hw); |
12 | |
13 | /* Transmit Descriptor - Advanced */ |
14 | union igc_adv_tx_desc { |
15 | struct { |
16 | __le64 buffer_addr; /* Address of descriptor's data buf */ |
17 | __le32 cmd_type_len; |
18 | __le32 olinfo_status; |
19 | } read; |
20 | struct { |
21 | __le64 rsvd; /* Reserved */ |
22 | __le32 nxtseq_seed; |
23 | __le32 status; |
24 | } wb; |
25 | }; |
26 | |
27 | /* Context descriptors */ |
28 | struct igc_adv_tx_context_desc { |
29 | __le32 vlan_macip_lens; |
30 | __le32 launch_time; |
31 | __le32 type_tucmd_mlhl; |
32 | __le32 mss_l4len_idx; |
33 | }; |
34 | |
35 | /* Adv Transmit Descriptor Config Masks */ |
36 | #define IGC_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ |
37 | #define IGC_ADVTXD_TSTAMP_REG_1 0x00010000 /* Select register 1 for timestamp */ |
38 | #define IGC_ADVTXD_TSTAMP_REG_2 0x00020000 /* Select register 2 for timestamp */ |
39 | #define IGC_ADVTXD_TSTAMP_REG_3 0x00030000 /* Select register 3 for timestamp */ |
40 | #define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ |
41 | #define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ |
42 | #define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ |
43 | #define IGC_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ |
44 | #define IGC_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ |
45 | #define IGC_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ |
46 | #define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ |
47 | #define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ |
48 | #define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ |
49 | |
50 | #define IGC_RAR_ENTRIES 16 |
51 | |
52 | /* Receive Descriptor - Advanced */ |
53 | union igc_adv_rx_desc { |
54 | struct { |
55 | __le64 pkt_addr; /* Packet buffer address */ |
56 | __le64 hdr_addr; /* Header buffer address */ |
57 | } read; |
58 | struct { |
59 | struct { |
60 | union { |
61 | __le32 data; |
62 | struct { |
63 | __le16 pkt_info; /*RSS type, Pkt type*/ |
64 | /* Split Header, header buffer len */ |
65 | __le16 hdr_info; |
66 | } ; |
67 | } lo_dword; |
68 | union { |
69 | __le32 ; /* RSS Hash */ |
70 | struct { |
71 | __le16 ip_id; /* IP id */ |
72 | __le16 csum; /* Packet Checksum */ |
73 | } csum_ip; |
74 | } hi_dword; |
75 | } lower; |
76 | struct { |
77 | __le32 status_error; /* ext status/error */ |
78 | __le16 length; /* Packet length */ |
79 | __le16 vlan; /* VLAN tag */ |
80 | } upper; |
81 | } wb; /* writeback */ |
82 | }; |
83 | |
84 | /* Additional Transmit Descriptor Control definitions */ |
85 | #define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ |
86 | #define IGC_TXDCTL_SWFLUSH 0x04000000 /* Transmit Software Flush */ |
87 | |
88 | /* Additional Receive Descriptor Control definitions */ |
89 | #define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ |
90 | #define IGC_RXDCTL_SWFLUSH 0x04000000 /* Receive Software Flush */ |
91 | |
92 | /* SRRCTL bit definitions */ |
93 | #define IGC_SRRCTL_BSIZEPKT_MASK GENMASK(6, 0) |
94 | #define IGC_SRRCTL_BSIZEPKT(x) FIELD_PREP(IGC_SRRCTL_BSIZEPKT_MASK, \ |
95 | (x) / 1024) /* in 1 KB resolution */ |
96 | #define IGC_SRRCTL_BSIZEHDR_MASK GENMASK(13, 8) |
97 | #define IGC_SRRCTL_BSIZEHDR(x) FIELD_PREP(IGC_SRRCTL_BSIZEHDR_MASK, \ |
98 | (x) / 64) /* in 64 bytes resolution */ |
99 | #define IGC_SRRCTL_DESCTYPE_MASK GENMASK(27, 25) |
100 | #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF FIELD_PREP(IGC_SRRCTL_DESCTYPE_MASK, 1) |
101 | |
102 | #endif /* _IGC_BASE_H */ |
103 | |