1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (c) 2018 Intel Corporation */ |
3 | |
4 | #ifndef _IGC_HW_H_ |
5 | #define _IGC_HW_H_ |
6 | |
7 | #include <linux/types.h> |
8 | #include <linux/if_ether.h> |
9 | #include <linux/netdevice.h> |
10 | |
11 | #include "igc_regs.h" |
12 | #include "igc_defines.h" |
13 | #include "igc_mac.h" |
14 | #include "igc_phy.h" |
15 | #include "igc_nvm.h" |
16 | #include "igc_i225.h" |
17 | #include "igc_base.h" |
18 | |
19 | #define IGC_DEV_ID_I225_LM 0x15F2 |
20 | #define IGC_DEV_ID_I225_V 0x15F3 |
21 | #define IGC_DEV_ID_I225_I 0x15F8 |
22 | #define IGC_DEV_ID_I220_V 0x15F7 |
23 | #define IGC_DEV_ID_I225_K 0x3100 |
24 | #define IGC_DEV_ID_I225_K2 0x3101 |
25 | #define IGC_DEV_ID_I226_K 0x3102 |
26 | #define IGC_DEV_ID_I225_LMVP 0x5502 |
27 | #define IGC_DEV_ID_I226_LMVP 0x5503 |
28 | #define IGC_DEV_ID_I225_IT 0x0D9F |
29 | #define IGC_DEV_ID_I226_LM 0x125B |
30 | #define IGC_DEV_ID_I226_V 0x125C |
31 | #define IGC_DEV_ID_I226_IT 0x125D |
32 | #define IGC_DEV_ID_I221_V 0x125E |
33 | #define IGC_DEV_ID_I226_BLANK_NVM 0x125F |
34 | #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD |
35 | |
36 | /* Function pointers for the MAC. */ |
37 | struct igc_mac_operations { |
38 | s32 (*check_for_link)(struct igc_hw *hw); |
39 | s32 (*reset_hw)(struct igc_hw *hw); |
40 | s32 (*init_hw)(struct igc_hw *hw); |
41 | s32 (*setup_physical_interface)(struct igc_hw *hw); |
42 | void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); |
43 | s32 (*read_mac_addr)(struct igc_hw *hw); |
44 | s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, |
45 | u16 *duplex); |
46 | s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); |
47 | void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); |
48 | }; |
49 | |
50 | enum igc_mac_type { |
51 | igc_undefined = 0, |
52 | igc_i225, |
53 | igc_num_macs /* List is 1-based, so subtract 1 for true count. */ |
54 | }; |
55 | |
56 | enum igc_media_type { |
57 | igc_media_type_unknown = 0, |
58 | igc_media_type_copper = 1, |
59 | igc_num_media_types |
60 | }; |
61 | |
62 | enum igc_nvm_type { |
63 | igc_nvm_unknown = 0, |
64 | igc_nvm_eeprom_spi, |
65 | }; |
66 | |
67 | struct igc_info { |
68 | s32 (*get_invariants)(struct igc_hw *hw); |
69 | struct igc_mac_operations *mac_ops; |
70 | const struct igc_phy_operations *phy_ops; |
71 | struct igc_nvm_operations *nvm_ops; |
72 | }; |
73 | |
74 | extern const struct igc_info igc_base_info; |
75 | |
76 | struct igc_mac_info { |
77 | struct igc_mac_operations ops; |
78 | |
79 | u8 addr[ETH_ALEN]; |
80 | u8 perm_addr[ETH_ALEN]; |
81 | |
82 | enum igc_mac_type type; |
83 | |
84 | u32 mc_filter_type; |
85 | |
86 | u16 mta_reg_count; |
87 | u16 uta_reg_count; |
88 | |
89 | u32 mta_shadow[MAX_MTA_REG]; |
90 | u16 rar_entry_count; |
91 | |
92 | bool asf_firmware_present; |
93 | bool arc_subsystem_valid; |
94 | |
95 | bool autoneg; |
96 | bool autoneg_failed; |
97 | bool get_link_status; |
98 | }; |
99 | |
100 | struct igc_nvm_operations { |
101 | s32 (*acquire)(struct igc_hw *hw); |
102 | s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); |
103 | void (*release)(struct igc_hw *hw); |
104 | s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); |
105 | s32 (*update)(struct igc_hw *hw); |
106 | s32 (*validate)(struct igc_hw *hw); |
107 | }; |
108 | |
109 | struct igc_phy_operations { |
110 | s32 (*acquire)(struct igc_hw *hw); |
111 | s32 (*check_reset_block)(struct igc_hw *hw); |
112 | s32 (*force_speed_duplex)(struct igc_hw *hw); |
113 | s32 (*get_phy_info)(struct igc_hw *hw); |
114 | s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data); |
115 | void (*release)(struct igc_hw *hw); |
116 | s32 (*reset)(struct igc_hw *hw); |
117 | s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data); |
118 | }; |
119 | |
120 | struct igc_nvm_info { |
121 | struct igc_nvm_operations ops; |
122 | enum igc_nvm_type type; |
123 | |
124 | u16 word_size; |
125 | u16 delay_usec; |
126 | u16 address_bits; |
127 | u16 opcode_bits; |
128 | u16 page_size; |
129 | }; |
130 | |
131 | struct igc_phy_info { |
132 | struct igc_phy_operations ops; |
133 | |
134 | u32 addr; |
135 | u32 id; |
136 | u32 reset_delay_us; /* in usec */ |
137 | u32 revision; |
138 | |
139 | enum igc_media_type media_type; |
140 | |
141 | u16 autoneg_advertised; |
142 | u16 autoneg_mask; |
143 | |
144 | u8 mdix; |
145 | |
146 | bool is_mdix; |
147 | bool speed_downgraded; |
148 | bool autoneg_wait_to_complete; |
149 | }; |
150 | |
151 | struct igc_bus_info { |
152 | u16 func; |
153 | u16 pci_cmd_word; |
154 | }; |
155 | |
156 | enum igc_fc_mode { |
157 | igc_fc_none = 0, |
158 | igc_fc_rx_pause, |
159 | igc_fc_tx_pause, |
160 | igc_fc_full, |
161 | igc_fc_default = 0xFF |
162 | }; |
163 | |
164 | struct igc_fc_info { |
165 | u32 high_water; /* Flow control high-water mark */ |
166 | u32 low_water; /* Flow control low-water mark */ |
167 | u16 pause_time; /* Flow control pause timer */ |
168 | bool send_xon; /* Flow control send XON */ |
169 | bool strict_ieee; /* Strict IEEE mode */ |
170 | enum igc_fc_mode current_mode; /* Type of flow control */ |
171 | enum igc_fc_mode requested_mode; |
172 | }; |
173 | |
174 | struct igc_dev_spec_base { |
175 | bool clear_semaphore_once; |
176 | bool eee_enable; |
177 | }; |
178 | |
179 | struct igc_hw { |
180 | void *back; |
181 | |
182 | u8 __iomem *hw_addr; |
183 | unsigned long io_base; |
184 | |
185 | struct igc_mac_info mac; |
186 | struct igc_fc_info fc; |
187 | struct igc_nvm_info nvm; |
188 | struct igc_phy_info phy; |
189 | |
190 | struct igc_bus_info bus; |
191 | |
192 | union { |
193 | struct igc_dev_spec_base _base; |
194 | } dev_spec; |
195 | |
196 | u16 device_id; |
197 | u16 subsystem_vendor_id; |
198 | u16 subsystem_device_id; |
199 | u16 vendor_id; |
200 | |
201 | u8 revision_id; |
202 | }; |
203 | |
204 | /* Statistics counters collected by the MAC */ |
205 | struct igc_hw_stats { |
206 | u64 crcerrs; |
207 | u64 algnerrc; |
208 | u64 symerrs; |
209 | u64 rxerrc; |
210 | u64 mpc; |
211 | u64 scc; |
212 | u64 ecol; |
213 | u64 mcc; |
214 | u64 latecol; |
215 | u64 colc; |
216 | u64 dc; |
217 | u64 tncrs; |
218 | u64 sec; |
219 | u64 cexterr; |
220 | u64 rlec; |
221 | u64 xonrxc; |
222 | u64 xontxc; |
223 | u64 xoffrxc; |
224 | u64 xofftxc; |
225 | u64 fcruc; |
226 | u64 prc64; |
227 | u64 prc127; |
228 | u64 prc255; |
229 | u64 prc511; |
230 | u64 prc1023; |
231 | u64 prc1522; |
232 | u64 tlpic; |
233 | u64 rlpic; |
234 | u64 gprc; |
235 | u64 bprc; |
236 | u64 mprc; |
237 | u64 gptc; |
238 | u64 gorc; |
239 | u64 gotc; |
240 | u64 rnbc; |
241 | u64 ruc; |
242 | u64 rfc; |
243 | u64 roc; |
244 | u64 rjc; |
245 | u64 mgprc; |
246 | u64 mgpdc; |
247 | u64 mgptc; |
248 | u64 tor; |
249 | u64 tot; |
250 | u64 tpr; |
251 | u64 tpt; |
252 | u64 ptc64; |
253 | u64 ptc127; |
254 | u64 ptc255; |
255 | u64 ptc511; |
256 | u64 ptc1023; |
257 | u64 ptc1522; |
258 | u64 mptc; |
259 | u64 bptc; |
260 | u64 tsctc; |
261 | u64 tsctfc; |
262 | u64 iac; |
263 | u64 htdpmc; |
264 | u64 rpthc; |
265 | u64 hgptc; |
266 | u64 hgorc; |
267 | u64 hgotc; |
268 | u64 lenerrs; |
269 | u64 scvpc; |
270 | u64 hrmpc; |
271 | u64 doosync; |
272 | u64 o2bgptc; |
273 | u64 o2bspc; |
274 | u64 b2ospc; |
275 | u64 b2ogprc; |
276 | u64 txdrop; |
277 | }; |
278 | |
279 | struct net_device *igc_get_hw_dev(struct igc_hw *hw); |
280 | #define hw_dbg(format, arg...) \ |
281 | netdev_dbg(igc_get_hw_dev(hw), format, ##arg) |
282 | |
283 | s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); |
284 | s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); |
285 | void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); |
286 | void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); |
287 | |
288 | #endif /* _IGC_HW_H_ */ |
289 | |