1	// SPDX-License-Identifier: GPL-2.0
2	/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4	#include <linux/pci.h>
5	#include <linux/delay.h>
6	#include <linux/iopoll.h>
7	#include <linux/sched.h>
8
9	#include "ixgbe.h"
10	#include "ixgbe_phy.h"
11
12	static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13	static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14	static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15	static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16	static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17	static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18	static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19	static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20	static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21	static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22	static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23	static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
24	static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
25	static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
26	static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
27
28	/**
29	* ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30	* @hw: pointer to the hardware structure
31	* @byte: byte to send
32	*
33	* Returns an error code on error.
34	**/
35	static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
36	{
37	s32 status;
38
39	status = ixgbe_clock_out_i2c_byte(hw, data: byte);
40	if (status)
41	return status;
42	return ixgbe_get_i2c_ack(hw);
43	}
44
45	/**
46	* ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47	* @hw: pointer to the hardware structure
48	* @byte: pointer to a u8 to receive the byte
49	*
50	* Returns an error code on error.
51	**/
52	static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
53	{
54	s32 status;
55
56	status = ixgbe_clock_in_i2c_byte(hw, data: byte);
57	if (status)
58	return status;
59	/* ACK */
60	return ixgbe_clock_out_i2c_bit(hw, data: false);
61	}
62
63	/**
64	* ixgbe_ones_comp_byte_add - Perform one's complement addition
65	* @add1: addend 1
66	* @add2: addend 2
67	*
68	* Returns one's complement 8-bit sum.
69	**/
70	static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
71	{
72	u16 sum = add1 + add2;
73
74	sum = (sum & 0xFF) + (sum >> 8);
75	return sum & 0xFF;
76	}
77
78	/**
79	* ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80	* @hw: pointer to the hardware structure
81	* @addr: I2C bus address to read from
82	* @reg: I2C device register to read from
83	* @val: pointer to location to receive read value
84	* @lock: true if to take and release semaphore
85	*
86	* Returns an error code on error.
87	*/
88	s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
89	u16 reg, u16 *val, bool lock)
90	{
91	u32 swfw_mask = hw->phy.phy_semaphore_mask;
92	int max_retry = 3;
93	int retry = 0;
94	u8 csum_byte;
95	u8 high_bits;
96	u8 low_bits;
97	u8 reg_high;
98	u8 csum;
99
100	reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
101	csum = ixgbe_ones_comp_byte_add(add1: reg_high, add2: reg & 0xFF);
102	csum = ~csum;
103	do {
104	if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
105	return IXGBE_ERR_SWFW_SYNC;
106	ixgbe_i2c_start(hw);
107	/* Device Address and write indication */
108	if (ixgbe_out_i2c_byte_ack(hw, byte: addr))
109	goto fail;
110	/* Write bits 14:8 */
111	if (ixgbe_out_i2c_byte_ack(hw, byte: reg_high))
112	goto fail;
113	/* Write bits 7:0 */
114	if (ixgbe_out_i2c_byte_ack(hw, byte: reg & 0xFF))
115	goto fail;
116	/* Write csum */
117	if (ixgbe_out_i2c_byte_ack(hw, byte: csum))
118	goto fail;
119	/* Re-start condition */
120	ixgbe_i2c_start(hw);
121	/* Device Address and read indication */
122	if (ixgbe_out_i2c_byte_ack(hw, byte: addr | 1))
123	goto fail;
124	/* Get upper bits */
125	if (ixgbe_in_i2c_byte_ack(hw, byte: &high_bits))
126	goto fail;
127	/* Get low bits */
128	if (ixgbe_in_i2c_byte_ack(hw, byte: &low_bits))
129	goto fail;
130	/* Get csum */
131	if (ixgbe_clock_in_i2c_byte(hw, data: &csum_byte))
132	goto fail;
133	/* NACK */
134	if (ixgbe_clock_out_i2c_bit(hw, data: false))
135	goto fail;
136	ixgbe_i2c_stop(hw);
137	if (lock)
138	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
139	*val = (high_bits << 8) | low_bits;
140	return 0;
141
142	fail:
143	ixgbe_i2c_bus_clear(hw);
144	if (lock)
145	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
146	retry++;
147	if (retry < max_retry)
148	hw_dbg(hw, "I2C byte read combined error - Retry.\n");
149	else
150	hw_dbg(hw, "I2C byte read combined error.\n");
151	} while (retry < max_retry);
152
153	return IXGBE_ERR_I2C;
154	}
155
156	/**
157	* ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158	* @hw: pointer to the hardware structure
159	* @addr: I2C bus address to write to
160	* @reg: I2C device register to write to
161	* @val: value to write
162	* @lock: true if to take and release semaphore
163	*
164	* Returns an error code on error.
165	*/
166	s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
167	u16 reg, u16 val, bool lock)
168	{
169	u32 swfw_mask = hw->phy.phy_semaphore_mask;
170	int max_retry = 1;
171	int retry = 0;
172	u8 reg_high;
173	u8 csum;
174
175	reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
176	csum = ixgbe_ones_comp_byte_add(add1: reg_high, add2: reg & 0xFF);
177	csum = ixgbe_ones_comp_byte_add(add1: csum, add2: val >> 8);
178	csum = ixgbe_ones_comp_byte_add(add1: csum, add2: val & 0xFF);
179	csum = ~csum;
180	do {
181	if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
182	return IXGBE_ERR_SWFW_SYNC;
183	ixgbe_i2c_start(hw);
184	/* Device Address and write indication */
185	if (ixgbe_out_i2c_byte_ack(hw, byte: addr))
186	goto fail;
187	/* Write bits 14:8 */
188	if (ixgbe_out_i2c_byte_ack(hw, byte: reg_high))
189	goto fail;
190	/* Write bits 7:0 */
191	if (ixgbe_out_i2c_byte_ack(hw, byte: reg & 0xFF))
192	goto fail;
193	/* Write data 15:8 */
194	if (ixgbe_out_i2c_byte_ack(hw, byte: val >> 8))
195	goto fail;
196	/* Write data 7:0 */
197	if (ixgbe_out_i2c_byte_ack(hw, byte: val & 0xFF))
198	goto fail;
199	/* Write csum */
200	if (ixgbe_out_i2c_byte_ack(hw, byte: csum))
201	goto fail;
202	ixgbe_i2c_stop(hw);
203	if (lock)
204	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
205	return 0;
206
207	fail:
208	ixgbe_i2c_bus_clear(hw);
209	if (lock)
210	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
211	retry++;
212	if (retry < max_retry)
213	hw_dbg(hw, "I2C byte write combined error - Retry.\n");
214	else
215	hw_dbg(hw, "I2C byte write combined error.\n");
216	} while (retry < max_retry);
217
218	return IXGBE_ERR_I2C;
219	}
220
221	/**
222	* ixgbe_probe_phy - Probe a single address for a PHY
223	* @hw: pointer to hardware structure
224	* @phy_addr: PHY address to probe
225	*
226	* Returns true if PHY found
227	**/
228	static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
229	{
230	u16 ext_ability = 0;
231
232	hw->phy.mdio.prtad = phy_addr;
233	if (mdio45_probe(mdio: &hw->phy.mdio, prtad: phy_addr) != 0)
234	return false;
235
236	if (ixgbe_get_phy_id(hw))
237	return false;
238
239	hw->phy.type = ixgbe_get_phy_type_from_id(phy_id: hw->phy.id);
240
241	if (hw->phy.type == ixgbe_phy_unknown) {
242	hw->phy.ops.read_reg(hw,
243	MDIO_PMA_EXTABLE,
244	MDIO_MMD_PMAPMD,
245	&ext_ability);
246	if (ext_ability &
247	(MDIO_PMA_EXTABLE_10GBT |
248	MDIO_PMA_EXTABLE_1000BT))
249	hw->phy.type = ixgbe_phy_cu_unknown;
250	else
251	hw->phy.type = ixgbe_phy_generic;
252	}
253
254	return true;
255	}
256
257	/**
258	* ixgbe_identify_phy_generic - Get physical layer module
259	* @hw: pointer to hardware structure
260	*
261	* Determines the physical layer module found on the current adapter.
262	**/
263	s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
264	{
265	u32 phy_addr;
266	u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
267
268	if (!hw->phy.phy_semaphore_mask) {
269	if (hw->bus.lan_id)
270	hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
271	else
272	hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
273	}
274
275	if (hw->phy.type != ixgbe_phy_unknown)
276	return 0;
277
278	if (hw->phy.nw_mng_if_sel) {
279	phy_addr = (hw->phy.nw_mng_if_sel &
280	IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
281	IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
282	if (ixgbe_probe_phy(hw, phy_addr))
283	return 0;
284	else
285	return IXGBE_ERR_PHY_ADDR_INVALID;
286	}
287
288	for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
289	if (ixgbe_probe_phy(hw, phy_addr)) {
290	status = 0;
291	break;
292	}
293	}
294
295	/* Certain media types do not have a phy so an address will not
296	* be found and the code will take this path. Caller has to
297	* decide if it is an error or not.
298	*/
299	if (status)
300	hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
301
302	return status;
303	}
304
305	/**
306	* ixgbe_check_reset_blocked - check status of MNG FW veto bit
307	* @hw: pointer to the hardware structure
308	*
309	* This function checks the MMNGC.MNG_VETO bit to see if there are
310	* any constraints on link from manageability. For MAC's that don't
311	* have this bit just return false since the link can not be blocked
312	* via this method.
313	**/
314	bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
315	{
316	u32 mmngc;
317
318	/* If we don't have this bit, it can't be blocking */
319	if (hw->mac.type == ixgbe_mac_82598EB)
320	return false;
321
322	mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
323	if (mmngc & IXGBE_MMNGC_MNG_VETO) {
324	hw_dbg(hw, "MNG_VETO bit detected.\n");
325	return true;
326	}
327
328	return false;
329	}
330
331	/**
332	* ixgbe_get_phy_id - Get the phy type
333	* @hw: pointer to hardware structure
334	*
335	**/
336	static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
337	{
338	s32 status;
339	u16 phy_id_high = 0;
340	u16 phy_id_low = 0;
341
342	status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
343	&phy_id_high);
344
345	if (!status) {
346	hw->phy.id = (u32)(phy_id_high << 16);
347	status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
348	&phy_id_low);
349	hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
350	hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
351	}
352	return status;
353	}
354
355	/**
356	* ixgbe_get_phy_type_from_id - Get the phy type
357	* @phy_id: hardware phy id
358	*
359	**/
360	static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
361	{
362	enum ixgbe_phy_type phy_type;
363
364	switch (phy_id) {
365	case TN1010_PHY_ID:
366	phy_type = ixgbe_phy_tn;
367	break;
368	case X550_PHY_ID2:
369	case X550_PHY_ID3:
370	case X540_PHY_ID:
371	phy_type = ixgbe_phy_aq;
372	break;
373	case QT2022_PHY_ID:
374	phy_type = ixgbe_phy_qt;
375	break;
376	case ATH_PHY_ID:
377	phy_type = ixgbe_phy_nl;
378	break;
379	case X557_PHY_ID:
380	case X557_PHY_ID2:
381	phy_type = ixgbe_phy_x550em_ext_t;
382	break;
383	case BCM54616S_E_PHY_ID:
384	phy_type = ixgbe_phy_ext_1g_t;
385	break;
386	default:
387	phy_type = ixgbe_phy_unknown;
388	break;
389	}
390
391	return phy_type;
392	}
393
394	/**
395	* ixgbe_reset_phy_generic - Performs a PHY reset
396	* @hw: pointer to hardware structure
397	**/
398	s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
399	{
400	u32 i;
401	u16 ctrl = 0;
402	s32 status = 0;
403
404	if (hw->phy.type == ixgbe_phy_unknown)
405	status = ixgbe_identify_phy_generic(hw);
406
407	if (status != 0 || hw->phy.type == ixgbe_phy_none)
408	return status;
409
410	/* Don't reset PHY if it's shut down due to overtemp. */
411	if (!hw->phy.reset_if_overtemp &&
412	(IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
413	return 0;
414
415	/* Blocked by MNG FW so bail */
416	if (ixgbe_check_reset_blocked(hw))
417	return 0;
418
419	/*
420	* Perform soft PHY reset to the PHY_XS.
421	* This will cause a soft reset to the PHY
422	*/
423	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
424	MDIO_MMD_PHYXS,
425	MDIO_CTRL1_RESET);
426
427	/*
428	* Poll for reset bit to self-clear indicating reset is complete.
429	* Some PHYs could take up to 3 seconds to complete and need about
430	* 1.7 usec delay after the reset is complete.
431	*/
432	for (i = 0; i < 30; i++) {
433	msleep(msecs: 100);
434	if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
435	status = hw->phy.ops.read_reg(hw,
436	IXGBE_MDIO_TX_VENDOR_ALARMS_3,
437	MDIO_MMD_PMAPMD, &ctrl);
438	if (status)
439	return status;
440
441	if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
442	udelay(2);
443	break;
444	}
445	} else {
446	status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
447	MDIO_MMD_PHYXS, &ctrl);
448	if (status)
449	return status;
450
451	if (!(ctrl & MDIO_CTRL1_RESET)) {
452	udelay(2);
453	break;
454	}
455	}
456	}
457
458	if (ctrl & MDIO_CTRL1_RESET) {
459	hw_dbg(hw, "PHY reset polling failed to complete.\n");
460	return IXGBE_ERR_RESET_FAILED;
461	}
462
463	return 0;
464	}
465
466	/**
467	* ixgbe_read_phy_reg_mdi - read PHY register
468	* @hw: pointer to hardware structure
469	* @reg_addr: 32 bit address of PHY register to read
470	* @device_type: 5 bit device type
471	* @phy_data: Pointer to read data from PHY register
472	*
473	* Reads a value from a specified PHY register without the SWFW lock
474	**/
475	s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
476	u16 *phy_data)
477	{
478	u32 i, data, command;
479
480	/* Setup and write the address cycle command */
481	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
482	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
483	(hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
484	(IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
485
486	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
487
488	/* Check every 10 usec to see if the address cycle completed.
489	* The MDI Command bit will clear when the operation is
490	* complete
491	*/
492	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
493	udelay(10);
494
495	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
496	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
497	break;
498	}
499
500
501	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
502	hw_dbg(hw, "PHY address command did not complete.\n");
503	return IXGBE_ERR_PHY;
504	}
505
506	/* Address cycle complete, setup and write the read
507	* command
508	*/
509	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
510	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
511	(hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
512	(IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
513
514	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
515
516	/* Check every 10 usec to see if the address cycle
517	* completed. The MDI Command bit will clear when the
518	* operation is complete
519	*/
520	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
521	udelay(10);
522
523	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
524	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
525	break;
526	}
527
528	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
529	hw_dbg(hw, "PHY read command didn't complete\n");
530	return IXGBE_ERR_PHY;
531	}
532
533	/* Read operation is complete. Get the data
534	* from MSRWD
535	*/
536	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
537	data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
538	*phy_data = (u16)(data);
539
540	return 0;
541	}
542
543	/**
544	* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
545	* using the SWFW lock - this function is needed in most cases
546	* @hw: pointer to hardware structure
547	* @reg_addr: 32 bit address of PHY register to read
548	* @device_type: 5 bit device type
549	* @phy_data: Pointer to read data from PHY register
550	**/
551	s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
552	u32 device_type, u16 *phy_data)
553	{
554	s32 status;
555	u32 gssr = hw->phy.phy_semaphore_mask;
556
557	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
558	status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
559	phy_data);
560	hw->mac.ops.release_swfw_sync(hw, gssr);
561	} else {
562	return IXGBE_ERR_SWFW_SYNC;
563	}
564
565	return status;
566	}
567
568	/**
569	* ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
570	* without SWFW lock
571	* @hw: pointer to hardware structure
572	* @reg_addr: 32 bit PHY register to write
573	* @device_type: 5 bit device type
574	* @phy_data: Data to write to the PHY register
575	**/
576	s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
577	u32 device_type, u16 phy_data)
578	{
579	u32 i, command;
580
581	/* Put the data in the MDI single read and write data register*/
582	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
583
584	/* Setup and write the address cycle command */
585	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
586	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
587	(hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
588	(IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
589
590	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
591
592	/*
593	* Check every 10 usec to see if the address cycle completed.
594	* The MDI Command bit will clear when the operation is
595	* complete
596	*/
597	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
598	udelay(10);
599
600	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
601	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
602	break;
603	}
604
605	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
606	hw_dbg(hw, "PHY address cmd didn't complete\n");
607	return IXGBE_ERR_PHY;
608	}
609
610	/*
611	* Address cycle complete, setup and write the write
612	* command
613	*/
614	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
615	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
616	(hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
617	(IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
618
619	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
620
621	/* Check every 10 usec to see if the address cycle
622	* completed. The MDI Command bit will clear when the
623	* operation is complete
624	*/
625	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
626	udelay(10);
627
628	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
629	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
630	break;
631	}
632
633	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
634	hw_dbg(hw, "PHY write cmd didn't complete\n");
635	return IXGBE_ERR_PHY;
636	}
637
638	return 0;
639	}
640
641	/**
642	* ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
643	* using SWFW lock- this function is needed in most cases
644	* @hw: pointer to hardware structure
645	* @reg_addr: 32 bit PHY register to write
646	* @device_type: 5 bit device type
647	* @phy_data: Data to write to the PHY register
648	**/
649	s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
650	u32 device_type, u16 phy_data)
651	{
652	s32 status;
653	u32 gssr = hw->phy.phy_semaphore_mask;
654
655	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
656	status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
657	phy_data);
658	hw->mac.ops.release_swfw_sync(hw, gssr);
659	} else {
660	return IXGBE_ERR_SWFW_SYNC;
661	}
662
663	return status;
664	}
665
666	#define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
667
668	/**
669	* ixgbe_msca_cmd - Write the command register and poll for completion/timeout
670	* @hw: pointer to hardware structure
671	* @cmd: command register value to write
672	**/
673	static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
674	{
675	IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
676
677	return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
678	!(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
679	10 * IXGBE_MDIO_COMMAND_TIMEOUT);
680	}
681
682	/**
683	* ixgbe_mii_bus_read_generic_c22 - Read a clause 22 register with gssr flags
684	* @hw: pointer to hardware structure
685	* @addr: address
686	* @regnum: register number
687	* @gssr: semaphore flags to acquire
688	**/
689	static s32 ixgbe_mii_bus_read_generic_c22(struct ixgbe_hw *hw, int addr,
690	int regnum, u32 gssr)
691	{
692	u32 hwaddr, cmd;
693	s32 data;
694
695	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
696	return -EBUSY;
697
698	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
699	hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
700	cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
701	IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
702
703	data = ixgbe_msca_cmd(hw, cmd);
704	if (data < 0)
705	goto mii_bus_read_done;
706
707	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
708	data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
709
710	mii_bus_read_done:
711	hw->mac.ops.release_swfw_sync(hw, gssr);
712	return data;
713	}
714
715	/**
716	* ixgbe_mii_bus_read_generic_c45 - Read a clause 45 register with gssr flags
717	* @hw: pointer to hardware structure
718	* @addr: address
719	* @devad: device address to read
720	* @regnum: register number
721	* @gssr: semaphore flags to acquire
722	**/
723	static s32 ixgbe_mii_bus_read_generic_c45(struct ixgbe_hw *hw, int addr,
724	int devad, int regnum, u32 gssr)
725	{
726	u32 hwaddr, cmd;
727	s32 data;
728
729	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
730	return -EBUSY;
731
732	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
733	hwaddr |= devad << 16 | regnum;
734	cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
735
736	data = ixgbe_msca_cmd(hw, cmd);
737	if (data < 0)
738	goto mii_bus_read_done;
739
740	cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
741	data = ixgbe_msca_cmd(hw, cmd);
742	if (data < 0)
743	goto mii_bus_read_done;
744
745	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
746	data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
747
748	mii_bus_read_done:
749	hw->mac.ops.release_swfw_sync(hw, gssr);
750	return data;
751	}
752
753	/**
754	* ixgbe_mii_bus_write_generic_c22 - Write a clause 22 register with gssr flags
755	* @hw: pointer to hardware structure
756	* @addr: address
757	* @regnum: register number
758	* @val: value to write
759	* @gssr: semaphore flags to acquire
760	**/
761	static s32 ixgbe_mii_bus_write_generic_c22(struct ixgbe_hw *hw, int addr,
762	int regnum, u16 val, u32 gssr)
763	{
764	u32 hwaddr, cmd;
765	s32 err;
766
767	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
768	return -EBUSY;
769
770	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
771
772	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
773	hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
774	cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
775	IXGBE_MSCA_MDI_COMMAND;
776
777	err = ixgbe_msca_cmd(hw, cmd);
778
779	hw->mac.ops.release_swfw_sync(hw, gssr);
780	return err;
781	}
782
783	/**
784	* ixgbe_mii_bus_write_generic_c45 - Write a clause 45 register with gssr flags
785	* @hw: pointer to hardware structure
786	* @addr: address
787	* @devad: device address to read
788	* @regnum: register number
789	* @val: value to write
790	* @gssr: semaphore flags to acquire
791	**/
792	static s32 ixgbe_mii_bus_write_generic_c45(struct ixgbe_hw *hw, int addr,
793	int devad, int regnum, u16 val,
794	u32 gssr)
795	{
796	u32 hwaddr, cmd;
797	s32 err;
798
799	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
800	return -EBUSY;
801
802	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
803
804	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
805	hwaddr |= devad << 16 | regnum;
806	cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
807
808	err = ixgbe_msca_cmd(hw, cmd);
809	if (err < 0)
810	goto mii_bus_write_done;
811
812	cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
813	err = ixgbe_msca_cmd(hw, cmd);
814
815	mii_bus_write_done:
816	hw->mac.ops.release_swfw_sync(hw, gssr);
817	return err;
818	}
819
820	/**
821	* ixgbe_mii_bus_read_c22 - Read a clause 22 register
822	* @bus: pointer to mii_bus structure which points to our driver private
823	* @addr: address
824	* @regnum: register number
825	**/
826	static s32 ixgbe_mii_bus_read_c22(struct mii_bus *bus, int addr, int regnum)
827	{
828	struct ixgbe_adapter *adapter = bus->priv;
829	struct ixgbe_hw *hw = &adapter->hw;
830	u32 gssr = hw->phy.phy_semaphore_mask;
831
832	return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
833	}
834
835	/**
836	* ixgbe_mii_bus_read_c45 - Read a clause 45 register
837	* @bus: pointer to mii_bus structure which points to our driver private
838	* @devad: device address to read
839	* @addr: address
840	* @regnum: register number
841	**/
842	static s32 ixgbe_mii_bus_read_c45(struct mii_bus *bus, int devad, int addr,
843	int regnum)
844	{
845	struct ixgbe_adapter *adapter = bus->priv;
846	struct ixgbe_hw *hw = &adapter->hw;
847	u32 gssr = hw->phy.phy_semaphore_mask;
848
849	return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
850	}
851
852	/**
853	* ixgbe_mii_bus_write_c22 - Write a clause 22 register
854	* @bus: pointer to mii_bus structure which points to our driver private
855	* @addr: address
856	* @regnum: register number
857	* @val: value to write
858	**/
859	static s32 ixgbe_mii_bus_write_c22(struct mii_bus *bus, int addr, int regnum,
860	u16 val)
861	{
862	struct ixgbe_adapter *adapter = bus->priv;
863	struct ixgbe_hw *hw = &adapter->hw;
864	u32 gssr = hw->phy.phy_semaphore_mask;
865
866	return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
867	}
868
869	/**
870	* ixgbe_mii_bus_write_c45 - Write a clause 45 register
871	* @bus: pointer to mii_bus structure which points to our driver private
872	* @addr: address
873	* @devad: device address to read
874	* @regnum: register number
875	* @val: value to write
876	**/
877	static s32 ixgbe_mii_bus_write_c45(struct mii_bus *bus, int addr, int devad,
878	int regnum, u16 val)
879	{
880	struct ixgbe_adapter *adapter = bus->priv;
881	struct ixgbe_hw *hw = &adapter->hw;
882	u32 gssr = hw->phy.phy_semaphore_mask;
883
884	return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
885	gssr);
886	}
887
888	/**
889	* ixgbe_x550em_a_mii_bus_read_c22 - Read a clause 22 register on x550em_a
890	* @bus: pointer to mii_bus structure which points to our driver private
891	* @addr: address
892	* @regnum: register number
893	**/
894	static s32 ixgbe_x550em_a_mii_bus_read_c22(struct mii_bus *bus, int addr,
895	int regnum)
896	{
897	struct ixgbe_adapter *adapter = bus->priv;
898	struct ixgbe_hw *hw = &adapter->hw;
899	u32 gssr = hw->phy.phy_semaphore_mask;
900
901	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
902	return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
903	}
904
905	/**
906	* ixgbe_x550em_a_mii_bus_read_c45 - Read a clause 45 register on x550em_a
907	* @bus: pointer to mii_bus structure which points to our driver private
908	* @addr: address
909	* @devad: device address to read
910	* @regnum: register number
911	**/
912	static s32 ixgbe_x550em_a_mii_bus_read_c45(struct mii_bus *bus, int addr,
913	int devad, int regnum)
914	{
915	struct ixgbe_adapter *adapter = bus->priv;
916	struct ixgbe_hw *hw = &adapter->hw;
917	u32 gssr = hw->phy.phy_semaphore_mask;
918
919	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
920	return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
921	}
922
923	/**
924	* ixgbe_x550em_a_mii_bus_write_c22 - Write a clause 22 register on x550em_a
925	* @bus: pointer to mii_bus structure which points to our driver private
926	* @addr: address
927	* @regnum: register number
928	* @val: value to write
929	**/
930	static s32 ixgbe_x550em_a_mii_bus_write_c22(struct mii_bus *bus, int addr,
931	int regnum, u16 val)
932	{
933	struct ixgbe_adapter *adapter = bus->priv;
934	struct ixgbe_hw *hw = &adapter->hw;
935	u32 gssr = hw->phy.phy_semaphore_mask;
936
937	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
938	return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
939	}
940
941	/**
942	* ixgbe_x550em_a_mii_bus_write_c45 - Write a clause 45 register on x550em_a
943	* @bus: pointer to mii_bus structure which points to our driver private
944	* @addr: address
945	* @devad: device address to read
946	* @regnum: register number
947	* @val: value to write
948	**/
949	static s32 ixgbe_x550em_a_mii_bus_write_c45(struct mii_bus *bus, int addr,
950	int devad, int regnum, u16 val)
951	{
952	struct ixgbe_adapter *adapter = bus->priv;
953	struct ixgbe_hw *hw = &adapter->hw;
954	u32 gssr = hw->phy.phy_semaphore_mask;
955
956	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
957	return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
958	gssr);
959	}
960
961	/**
962	* ixgbe_get_first_secondary_devfn - get first device downstream of root port
963	* @devfn: PCI_DEVFN of root port on domain 0, bus 0
964	*
965	* Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
966	* on domain 0, bus 0, devfn = 'devfn'
967	**/
968	static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
969	{
970	struct pci_dev *rp_pdev;
971	int bus;
972
973	rp_pdev = pci_get_domain_bus_and_slot(domain: 0, bus: 0, devfn);
974	if (rp_pdev && rp_pdev->subordinate) {
975	bus = rp_pdev->subordinate->number;
976	pci_dev_put(dev: rp_pdev);
977	return pci_get_domain_bus_and_slot(domain: 0, bus, devfn: 0);
978	}
979
980	pci_dev_put(dev: rp_pdev);
981	return NULL;
982	}
983
984	/**
985	* ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
986	* @hw: pointer to hardware structure
987	*
988	* Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
989	* the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
990	* but we only want to register one MDIO bus.
991	**/
992	static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
993	{
994	struct ixgbe_adapter *adapter = hw->back;
995	struct pci_dev *pdev = adapter->pdev;
996	struct pci_dev *func0_pdev;
997	bool has_mii = false;
998
999	/* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
1000	* are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
1001	* It's not valid for function 0 to be disabled and function 1 is up,
1002	* so the lowest numbered ixgbe dev will be device 0 function 0 on one
1003	* of those two root ports
1004	*/
1005	func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
1006	if (func0_pdev) {
1007	if (func0_pdev == pdev)
1008	has_mii = true;
1009	goto out;
1010	}
1011	func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
1012	if (func0_pdev == pdev)
1013	has_mii = true;
1014
1015	out:
1016	pci_dev_put(dev: func0_pdev);
1017	return has_mii;
1018	}
1019
1020	/**
1021	* ixgbe_mii_bus_init - mii_bus structure setup
1022	* @hw: pointer to hardware structure
1023	*
1024	* Returns 0 on success, negative on failure
1025	*
1026	* ixgbe_mii_bus_init initializes a mii_bus structure in adapter
1027	**/
1028	s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw)
1029	{
1030	s32 (*write_c22)(struct mii_bus *bus, int addr, int regnum, u16 val);
1031	s32 (*read_c22)(struct mii_bus *bus, int addr, int regnum);
1032	s32 (*write_c45)(struct mii_bus *bus, int addr, int devad, int regnum,
1033	u16 val);
1034	s32 (*read_c45)(struct mii_bus *bus, int addr, int devad, int regnum);
1035	struct ixgbe_adapter *adapter = hw->back;
1036	struct pci_dev *pdev = adapter->pdev;
1037	struct device *dev = &adapter->netdev->dev;
1038	struct mii_bus *bus;
1039
1040	switch (hw->device_id) {
1041	/* C3000 SoCs */
1042	case IXGBE_DEV_ID_X550EM_A_KR:
1043	case IXGBE_DEV_ID_X550EM_A_KR_L:
1044	case IXGBE_DEV_ID_X550EM_A_SFP_N:
1045	case IXGBE_DEV_ID_X550EM_A_SGMII:
1046	case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1047	case IXGBE_DEV_ID_X550EM_A_10G_T:
1048	case IXGBE_DEV_ID_X550EM_A_SFP:
1049	case IXGBE_DEV_ID_X550EM_A_1G_T:
1050	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1051	if (!ixgbe_x550em_a_has_mii(hw))
1052	return 0;
1053	read_c22 = ixgbe_x550em_a_mii_bus_read_c22;
1054	write_c22 = ixgbe_x550em_a_mii_bus_write_c22;
1055	read_c45 = ixgbe_x550em_a_mii_bus_read_c45;
1056	write_c45 = ixgbe_x550em_a_mii_bus_write_c45;
1057	break;
1058	default:
1059	read_c22 = ixgbe_mii_bus_read_c22;
1060	write_c22 = ixgbe_mii_bus_write_c22;
1061	read_c45 = ixgbe_mii_bus_read_c45;
1062	write_c45 = ixgbe_mii_bus_write_c45;
1063	break;
1064	}
1065
1066	bus = devm_mdiobus_alloc(dev);
1067	if (!bus)
1068	return -ENOMEM;
1069
1070	bus->read = read_c22;
1071	bus->write = write_c22;
1072	bus->read_c45 = read_c45;
1073	bus->write_c45 = write_c45;
1074
1075	/* Use the position of the device in the PCI hierarchy as the id */
1076	snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "%s-mdio-%s", ixgbe_driver_name,
1077	pci_name(pdev));
1078
1079	bus->name = "ixgbe-mdio";
1080	bus->priv = adapter;
1081	bus->parent = dev;
1082	bus->phy_mask = GENMASK(31, 0);
1083
1084	/* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22
1085	* unfortunately that causes some clause 22 frames to be sent with
1086	* clause 45 addressing. We don't want that.
1087	*/
1088	hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
1089
1090	adapter->mii_bus = bus;
1091	return mdiobus_register(bus);
1092	}
1093
1094	/**
1095	* ixgbe_setup_phy_link_generic - Set and restart autoneg
1096	* @hw: pointer to hardware structure
1097	*
1098	* Restart autonegotiation and PHY and waits for completion.
1099	**/
1100	s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
1101	{
1102	s32 status = 0;
1103	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1104	bool autoneg = false;
1105	ixgbe_link_speed speed;
1106
1107	ixgbe_get_copper_link_capabilities_generic(hw, speed: &speed, autoneg: &autoneg);
1108
1109	/* Set or unset auto-negotiation 10G advertisement */
1110	hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
1111
1112	autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1113	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
1114	(speed & IXGBE_LINK_SPEED_10GB_FULL))
1115	autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1116
1117	hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
1118
1119	hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1120	MDIO_MMD_AN, &autoneg_reg);
1121
1122	if (hw->mac.type == ixgbe_mac_X550) {
1123	/* Set or unset auto-negotiation 5G advertisement */
1124	autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
1125	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
1126	(speed & IXGBE_LINK_SPEED_5GB_FULL))
1127	autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
1128
1129	/* Set or unset auto-negotiation 2.5G advertisement */
1130	autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
1131	if ((hw->phy.autoneg_advertised &
1132	IXGBE_LINK_SPEED_2_5GB_FULL) &&
1133	(speed & IXGBE_LINK_SPEED_2_5GB_FULL))
1134	autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
1135	}
1136
1137	/* Set or unset auto-negotiation 1G advertisement */
1138	autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
1139	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1140	(speed & IXGBE_LINK_SPEED_1GB_FULL))
1141	autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1142
1143	hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1144	MDIO_MMD_AN, autoneg_reg);
1145
1146	/* Set or unset auto-negotiation 100M advertisement */
1147	hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1148
1149	autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1150	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1151	(speed & IXGBE_LINK_SPEED_100_FULL))
1152	autoneg_reg |= ADVERTISE_100FULL;
1153
1154	hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1155
1156	/* Blocked by MNG FW so don't reset PHY */
1157	if (ixgbe_check_reset_blocked(hw))
1158	return 0;
1159
1160	/* Restart PHY autonegotiation and wait for completion */
1161	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1162	MDIO_MMD_AN, &autoneg_reg);
1163
1164	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1165
1166	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1167	MDIO_MMD_AN, autoneg_reg);
1168
1169	return status;
1170	}
1171
1172	/**
1173	* ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1174	* @hw: pointer to hardware structure
1175	* @speed: new link speed
1176	* @autoneg_wait_to_complete: unused
1177	**/
1178	s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1179	ixgbe_link_speed speed,
1180	bool autoneg_wait_to_complete)
1181	{
1182	/* Clear autoneg_advertised and set new values based on input link
1183	* speed.
1184	*/
1185	hw->phy.autoneg_advertised = 0;
1186
1187	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1188	hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1189
1190	if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1191	hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1192
1193	if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1194	hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1195
1196	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1197	hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1198
1199	if (speed & IXGBE_LINK_SPEED_100_FULL)
1200	hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1201
1202	if (speed & IXGBE_LINK_SPEED_10_FULL)
1203	hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1204
1205	/* Setup link based on the new speed settings */
1206	if (hw->phy.ops.setup_link)
1207	hw->phy.ops.setup_link(hw);
1208
1209	return 0;
1210	}
1211
1212	/**
1213	* ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1214	* @hw: pointer to hardware structure
1215	*
1216	* Determines the supported link capabilities by reading the PHY auto
1217	* negotiation register.
1218	*/
1219	static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1220	{
1221	u16 speed_ability;
1222	s32 status;
1223
1224	status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1225	&speed_ability);
1226	if (status)
1227	return status;
1228
1229	if (speed_ability & MDIO_SPEED_10G)
1230	hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1231	if (speed_ability & MDIO_PMA_SPEED_1000)
1232	hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1233	if (speed_ability & MDIO_PMA_SPEED_100)
1234	hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1235
1236	switch (hw->mac.type) {
1237	case ixgbe_mac_X550:
1238	hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1239	hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1240	break;
1241	case ixgbe_mac_X550EM_x:
1242	case ixgbe_mac_x550em_a:
1243	hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1244	break;
1245	default:
1246	break;
1247	}
1248
1249	return 0;
1250	}
1251
1252	/**
1253	* ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1254	* @hw: pointer to hardware structure
1255	* @speed: pointer to link speed
1256	* @autoneg: boolean auto-negotiation value
1257	*/
1258	s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1259	ixgbe_link_speed *speed,
1260	bool *autoneg)
1261	{
1262	s32 status = 0;
1263
1264	*autoneg = true;
1265	if (!hw->phy.speeds_supported)
1266	status = ixgbe_get_copper_speeds_supported(hw);
1267
1268	*speed = hw->phy.speeds_supported;
1269	return status;
1270	}
1271
1272	/**
1273	* ixgbe_check_phy_link_tnx - Determine link and speed status
1274	* @hw: pointer to hardware structure
1275	* @speed: link speed
1276	* @link_up: status of link
1277	*
1278	* Reads the VS1 register to determine if link is up and the current speed for
1279	* the PHY.
1280	**/
1281	s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1282	bool *link_up)
1283	{
1284	s32 status;
1285	u32 time_out;
1286	u32 max_time_out = 10;
1287	u16 phy_link = 0;
1288	u16 phy_speed = 0;
1289	u16 phy_data = 0;
1290
1291	/* Initialize speed and link to default case */
1292	*link_up = false;
1293	*speed = IXGBE_LINK_SPEED_10GB_FULL;
1294
1295	/*
1296	* Check current speed and link status of the PHY register.
1297	* This is a vendor specific register and may have to
1298	* be changed for other copper PHYs.
1299	*/
1300	for (time_out = 0; time_out < max_time_out; time_out++) {
1301	udelay(10);
1302	status = hw->phy.ops.read_reg(hw,
1303	MDIO_STAT1,
1304	MDIO_MMD_VEND1,
1305	&phy_data);
1306	phy_link = phy_data &
1307	IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1308	phy_speed = phy_data &
1309	IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1310	if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1311	*link_up = true;
1312	if (phy_speed ==
1313	IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1314	*speed = IXGBE_LINK_SPEED_1GB_FULL;
1315	break;
1316	}
1317	}
1318
1319	return status;
1320	}
1321
1322	/**
1323	* ixgbe_setup_phy_link_tnx - Set and restart autoneg
1324	* @hw: pointer to hardware structure
1325	*
1326	* Restart autonegotiation and PHY and waits for completion.
1327	* This function always returns success, this is nessary since
1328	* it is called via a function pointer that could call other
1329	* functions that could return an error.
1330	**/
1331	s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1332	{
1333	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1334	bool autoneg = false;
1335	ixgbe_link_speed speed;
1336
1337	ixgbe_get_copper_link_capabilities_generic(hw, speed: &speed, autoneg: &autoneg);
1338
1339	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1340	/* Set or unset auto-negotiation 10G advertisement */
1341	hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1342	MDIO_MMD_AN,
1343	&autoneg_reg);
1344
1345	autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1346	if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1347	autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1348
1349	hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1350	MDIO_MMD_AN,
1351	autoneg_reg);
1352	}
1353
1354	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1355	/* Set or unset auto-negotiation 1G advertisement */
1356	hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1357	MDIO_MMD_AN,
1358	&autoneg_reg);
1359
1360	autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1361	if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1362	autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1363
1364	hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1365	MDIO_MMD_AN,
1366	autoneg_reg);
1367	}
1368
1369	if (speed & IXGBE_LINK_SPEED_100_FULL) {
1370	/* Set or unset auto-negotiation 100M advertisement */
1371	hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1372	MDIO_MMD_AN,
1373	&autoneg_reg);
1374
1375	autoneg_reg &= ~(ADVERTISE_100FULL |
1376	ADVERTISE_100HALF);
1377	if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1378	autoneg_reg |= ADVERTISE_100FULL;
1379
1380	hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1381	MDIO_MMD_AN,
1382	autoneg_reg);
1383	}
1384
1385	/* Blocked by MNG FW so don't reset PHY */
1386	if (ixgbe_check_reset_blocked(hw))
1387	return 0;
1388
1389	/* Restart PHY autonegotiation and wait for completion */
1390	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1391	MDIO_MMD_AN, &autoneg_reg);
1392
1393	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1394
1395	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1396	MDIO_MMD_AN, autoneg_reg);
1397	return 0;
1398	}
1399
1400	/**
1401	* ixgbe_reset_phy_nl - Performs a PHY reset
1402	* @hw: pointer to hardware structure
1403	**/
1404	s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1405	{
1406	u16 phy_offset, control, eword, edata, block_crc;
1407	bool end_data = false;
1408	u16 list_offset, data_offset;
1409	u16 phy_data = 0;
1410	s32 ret_val;
1411	u32 i;
1412
1413	/* Blocked by MNG FW so bail */
1414	if (ixgbe_check_reset_blocked(hw))
1415	return 0;
1416
1417	hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1418
1419	/* reset the PHY and poll for completion */
1420	hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1421	(phy_data | MDIO_CTRL1_RESET));
1422
1423	for (i = 0; i < 100; i++) {
1424	hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1425	&phy_data);
1426	if ((phy_data & MDIO_CTRL1_RESET) == 0)
1427	break;
1428	usleep_range(min: 10000, max: 20000);
1429	}
1430
1431	if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1432	hw_dbg(hw, "PHY reset did not complete.\n");
1433	return IXGBE_ERR_PHY;
1434	}
1435
1436	/* Get init offsets */
1437	ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, list_offset: &list_offset,
1438	data_offset: &data_offset);
1439	if (ret_val)
1440	return ret_val;
1441
1442	ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1443	data_offset++;
1444	while (!end_data) {
1445	/*
1446	* Read control word from PHY init contents offset
1447	*/
1448	ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1449	if (ret_val)
1450	goto err_eeprom;
1451	control = (eword & IXGBE_CONTROL_MASK_NL) >>
1452	IXGBE_CONTROL_SHIFT_NL;
1453	edata = eword & IXGBE_DATA_MASK_NL;
1454	switch (control) {
1455	case IXGBE_DELAY_NL:
1456	data_offset++;
1457	hw_dbg(hw, "DELAY: %d MS\n", edata);
1458	usleep_range(min: edata * 1000, max: edata * 2000);
1459	break;
1460	case IXGBE_DATA_NL:
1461	hw_dbg(hw, "DATA:\n");
1462	data_offset++;
1463	ret_val = hw->eeprom.ops.read(hw, data_offset++,
1464	&phy_offset);
1465	if (ret_val)
1466	goto err_eeprom;
1467	for (i = 0; i < edata; i++) {
1468	ret_val = hw->eeprom.ops.read(hw, data_offset,
1469	&eword);
1470	if (ret_val)
1471	goto err_eeprom;
1472	hw->phy.ops.write_reg(hw, phy_offset,
1473	MDIO_MMD_PMAPMD, eword);
1474	hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1475	phy_offset);
1476	data_offset++;
1477	phy_offset++;
1478	}
1479	break;
1480	case IXGBE_CONTROL_NL:
1481	data_offset++;
1482	hw_dbg(hw, "CONTROL:\n");
1483	if (edata == IXGBE_CONTROL_EOL_NL) {
1484	hw_dbg(hw, "EOL\n");
1485	end_data = true;
1486	} else if (edata == IXGBE_CONTROL_SOL_NL) {
1487	hw_dbg(hw, "SOL\n");
1488	} else {
1489	hw_dbg(hw, "Bad control value\n");
1490	return IXGBE_ERR_PHY;
1491	}
1492	break;
1493	default:
1494	hw_dbg(hw, "Bad control type\n");
1495	return IXGBE_ERR_PHY;
1496	}
1497	}
1498
1499	return ret_val;
1500
1501	err_eeprom:
1502	hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1503	return IXGBE_ERR_PHY;
1504	}
1505
1506	/**
1507	* ixgbe_identify_module_generic - Identifies module type
1508	* @hw: pointer to hardware structure
1509	*
1510	* Determines HW type and calls appropriate function.
1511	**/
1512	s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1513	{
1514	switch (hw->mac.ops.get_media_type(hw)) {
1515	case ixgbe_media_type_fiber:
1516	return ixgbe_identify_sfp_module_generic(hw);
1517	case ixgbe_media_type_fiber_qsfp:
1518	return ixgbe_identify_qsfp_module_generic(hw);
1519	default:
1520	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1521	return IXGBE_ERR_SFP_NOT_PRESENT;
1522	}
1523
1524	return IXGBE_ERR_SFP_NOT_PRESENT;
1525	}
1526
1527	/**
1528	* ixgbe_identify_sfp_module_generic - Identifies SFP modules
1529	* @hw: pointer to hardware structure
1530	*
1531	* Searches for and identifies the SFP module and assigns appropriate PHY type.
1532	**/
1533	s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1534	{
1535	struct ixgbe_adapter *adapter = hw->back;
1536	s32 status;
1537	u32 vendor_oui = 0;
1538	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1539	u8 identifier = 0;
1540	u8 comp_codes_1g = 0;
1541	u8 comp_codes_10g = 0;
1542	u8 oui_bytes[3] = {0, 0, 0};
1543	u8 cable_tech = 0;
1544	u8 cable_spec = 0;
1545	u16 enforce_sfp = 0;
1546
1547	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1548	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1549	return IXGBE_ERR_SFP_NOT_PRESENT;
1550	}
1551
1552	/* LAN ID is needed for sfp_type determination */
1553	hw->mac.ops.set_lan_id(hw);
1554
1555	status = hw->phy.ops.read_i2c_eeprom(hw,
1556	IXGBE_SFF_IDENTIFIER,
1557	&identifier);
1558
1559	if (status)
1560	goto err_read_i2c_eeprom;
1561
1562	if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1563	hw->phy.type = ixgbe_phy_sfp_unsupported;
1564	return IXGBE_ERR_SFP_NOT_SUPPORTED;
1565	}
1566	status = hw->phy.ops.read_i2c_eeprom(hw,
1567	IXGBE_SFF_1GBE_COMP_CODES,
1568	&comp_codes_1g);
1569
1570	if (status)
1571	goto err_read_i2c_eeprom;
1572
1573	status = hw->phy.ops.read_i2c_eeprom(hw,
1574	IXGBE_SFF_10GBE_COMP_CODES,
1575	&comp_codes_10g);
1576
1577	if (status)
1578	goto err_read_i2c_eeprom;
1579	status = hw->phy.ops.read_i2c_eeprom(hw,
1580	IXGBE_SFF_CABLE_TECHNOLOGY,
1581	&cable_tech);
1582
1583	if (status)
1584	goto err_read_i2c_eeprom;
1585
1586	/* ID Module
1587	* =========
1588	* 0 SFP_DA_CU
1589	* 1 SFP_SR
1590	* 2 SFP_LR
1591	* 3 SFP_DA_CORE0 - 82599-specific
1592	* 4 SFP_DA_CORE1 - 82599-specific
1593	* 5 SFP_SR/LR_CORE0 - 82599-specific
1594	* 6 SFP_SR/LR_CORE1 - 82599-specific
1595	* 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1596	* 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1597	* 9 SFP_1g_cu_CORE0 - 82599-specific
1598	* 10 SFP_1g_cu_CORE1 - 82599-specific
1599	* 11 SFP_1g_sx_CORE0 - 82599-specific
1600	* 12 SFP_1g_sx_CORE1 - 82599-specific
1601	*/
1602	if (hw->mac.type == ixgbe_mac_82598EB) {
1603	if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1604	hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1605	else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1606	hw->phy.sfp_type = ixgbe_sfp_type_sr;
1607	else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1608	hw->phy.sfp_type = ixgbe_sfp_type_lr;
1609	else
1610	hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1611	} else {
1612	if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1613	if (hw->bus.lan_id == 0)
1614	hw->phy.sfp_type =
1615	ixgbe_sfp_type_da_cu_core0;
1616	else
1617	hw->phy.sfp_type =
1618	ixgbe_sfp_type_da_cu_core1;
1619	} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1620	hw->phy.ops.read_i2c_eeprom(
1621	hw, IXGBE_SFF_CABLE_SPEC_COMP,
1622	&cable_spec);
1623	if (cable_spec &
1624	IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1625	if (hw->bus.lan_id == 0)
1626	hw->phy.sfp_type =
1627	ixgbe_sfp_type_da_act_lmt_core0;
1628	else
1629	hw->phy.sfp_type =
1630	ixgbe_sfp_type_da_act_lmt_core1;
1631	} else {
1632	hw->phy.sfp_type =
1633	ixgbe_sfp_type_unknown;
1634	}
1635	} else if (comp_codes_10g &
1636	(IXGBE_SFF_10GBASESR_CAPABLE |
1637	IXGBE_SFF_10GBASELR_CAPABLE)) {
1638	if (hw->bus.lan_id == 0)
1639	hw->phy.sfp_type =
1640	ixgbe_sfp_type_srlr_core0;
1641	else
1642	hw->phy.sfp_type =
1643	ixgbe_sfp_type_srlr_core1;
1644	} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1645	if (hw->bus.lan_id == 0)
1646	hw->phy.sfp_type =
1647	ixgbe_sfp_type_1g_cu_core0;
1648	else
1649	hw->phy.sfp_type =
1650	ixgbe_sfp_type_1g_cu_core1;
1651	} else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1652	if (hw->bus.lan_id == 0)
1653	hw->phy.sfp_type =
1654	ixgbe_sfp_type_1g_sx_core0;
1655	else
1656	hw->phy.sfp_type =
1657	ixgbe_sfp_type_1g_sx_core1;
1658	} else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1659	if (hw->bus.lan_id == 0)
1660	hw->phy.sfp_type =
1661	ixgbe_sfp_type_1g_lx_core0;
1662	else
1663	hw->phy.sfp_type =
1664	ixgbe_sfp_type_1g_lx_core1;
1665	} else {
1666	hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1667	}
1668	}
1669
1670	if (hw->phy.sfp_type != stored_sfp_type)
1671	hw->phy.sfp_setup_needed = true;
1672
1673	/* Determine if the SFP+ PHY is dual speed or not. */
1674	hw->phy.multispeed_fiber = false;
1675	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1676	(comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1677	((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1678	(comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1679	hw->phy.multispeed_fiber = true;
1680
1681	/* Determine PHY vendor */
1682	if (hw->phy.type != ixgbe_phy_nl) {
1683	hw->phy.id = identifier;
1684	status = hw->phy.ops.read_i2c_eeprom(hw,
1685	IXGBE_SFF_VENDOR_OUI_BYTE0,
1686	&oui_bytes[0]);
1687
1688	if (status != 0)
1689	goto err_read_i2c_eeprom;
1690
1691	status = hw->phy.ops.read_i2c_eeprom(hw,
1692	IXGBE_SFF_VENDOR_OUI_BYTE1,
1693	&oui_bytes[1]);
1694
1695	if (status != 0)
1696	goto err_read_i2c_eeprom;
1697
1698	status = hw->phy.ops.read_i2c_eeprom(hw,
1699	IXGBE_SFF_VENDOR_OUI_BYTE2,
1700	&oui_bytes[2]);
1701
1702	if (status != 0)
1703	goto err_read_i2c_eeprom;
1704
1705	vendor_oui =
1706	((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1707	(oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1708	(oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1709
1710	switch (vendor_oui) {
1711	case IXGBE_SFF_VENDOR_OUI_TYCO:
1712	if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1713	hw->phy.type =
1714	ixgbe_phy_sfp_passive_tyco;
1715	break;
1716	case IXGBE_SFF_VENDOR_OUI_FTL:
1717	if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1718	hw->phy.type = ixgbe_phy_sfp_ftl_active;
1719	else
1720	hw->phy.type = ixgbe_phy_sfp_ftl;
1721	break;
1722	case IXGBE_SFF_VENDOR_OUI_AVAGO:
1723	hw->phy.type = ixgbe_phy_sfp_avago;
1724	break;
1725	case IXGBE_SFF_VENDOR_OUI_INTEL:
1726	hw->phy.type = ixgbe_phy_sfp_intel;
1727	break;
1728	default:
1729	if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1730	hw->phy.type =
1731	ixgbe_phy_sfp_passive_unknown;
1732	else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1733	hw->phy.type =
1734	ixgbe_phy_sfp_active_unknown;
1735	else
1736	hw->phy.type = ixgbe_phy_sfp_unknown;
1737	break;
1738	}
1739	}
1740
1741	/* Allow any DA cable vendor */
1742	if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1743	IXGBE_SFF_DA_ACTIVE_CABLE))
1744	return 0;
1745
1746	/* Verify supported 1G SFP modules */
1747	if (comp_codes_10g == 0 &&
1748	!(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1749	hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1750	hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1751	hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1752	hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1753	hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1754	hw->phy.type = ixgbe_phy_sfp_unsupported;
1755	return IXGBE_ERR_SFP_NOT_SUPPORTED;
1756	}
1757
1758	/* Anything else 82598-based is supported */
1759	if (hw->mac.type == ixgbe_mac_82598EB)
1760	return 0;
1761
1762	hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1763	if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1764	!(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1765	hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1766	hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1767	hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1768	hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1769	hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1770	/* Make sure we're a supported PHY type */
1771	if (hw->phy.type == ixgbe_phy_sfp_intel)
1772	return 0;
1773	if (hw->allow_unsupported_sfp) {
1774	e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1775	return 0;
1776	}
1777	hw_dbg(hw, "SFP+ module not supported\n");
1778	hw->phy.type = ixgbe_phy_sfp_unsupported;
1779	return IXGBE_ERR_SFP_NOT_SUPPORTED;
1780	}
1781	return 0;
1782
1783	err_read_i2c_eeprom:
1784	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1785	if (hw->phy.type != ixgbe_phy_nl) {
1786	hw->phy.id = 0;
1787	hw->phy.type = ixgbe_phy_unknown;
1788	}
1789	return IXGBE_ERR_SFP_NOT_PRESENT;
1790	}
1791
1792	/**
1793	* ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1794	* @hw: pointer to hardware structure
1795	*
1796	* Searches for and identifies the QSFP module and assigns appropriate PHY type
1797	**/
1798	static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1799	{
1800	struct ixgbe_adapter *adapter = hw->back;
1801	s32 status;
1802	u32 vendor_oui = 0;
1803	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1804	u8 identifier = 0;
1805	u8 comp_codes_1g = 0;
1806	u8 comp_codes_10g = 0;
1807	u8 oui_bytes[3] = {0, 0, 0};
1808	u16 enforce_sfp = 0;
1809	u8 connector = 0;
1810	u8 cable_length = 0;
1811	u8 device_tech = 0;
1812	bool active_cable = false;
1813
1814	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1815	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1816	return IXGBE_ERR_SFP_NOT_PRESENT;
1817	}
1818
1819	/* LAN ID is needed for sfp_type determination */
1820	hw->mac.ops.set_lan_id(hw);
1821
1822	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1823	&identifier);
1824
1825	if (status != 0)
1826	goto err_read_i2c_eeprom;
1827
1828	if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1829	hw->phy.type = ixgbe_phy_sfp_unsupported;
1830	return IXGBE_ERR_SFP_NOT_SUPPORTED;
1831	}
1832
1833	hw->phy.id = identifier;
1834
1835	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1836	&comp_codes_10g);
1837
1838	if (status != 0)
1839	goto err_read_i2c_eeprom;
1840
1841	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1842	&comp_codes_1g);
1843
1844	if (status != 0)
1845	goto err_read_i2c_eeprom;
1846
1847	if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1848	hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1849	if (hw->bus.lan_id == 0)
1850	hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1851	else
1852	hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1853	} else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1854	IXGBE_SFF_10GBASELR_CAPABLE)) {
1855	if (hw->bus.lan_id == 0)
1856	hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1857	else
1858	hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1859	} else {
1860	if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1861	active_cable = true;
1862
1863	if (!active_cable) {
1864	/* check for active DA cables that pre-date
1865	* SFF-8436 v3.6
1866	*/
1867	hw->phy.ops.read_i2c_eeprom(hw,
1868	IXGBE_SFF_QSFP_CONNECTOR,
1869	&connector);
1870
1871	hw->phy.ops.read_i2c_eeprom(hw,
1872	IXGBE_SFF_QSFP_CABLE_LENGTH,
1873	&cable_length);
1874
1875	hw->phy.ops.read_i2c_eeprom(hw,
1876	IXGBE_SFF_QSFP_DEVICE_TECH,
1877	&device_tech);
1878
1879	if ((connector ==
1880	IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1881	(cable_length > 0) &&
1882	((device_tech >> 4) ==
1883	IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1884	active_cable = true;
1885	}
1886
1887	if (active_cable) {
1888	hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1889	if (hw->bus.lan_id == 0)
1890	hw->phy.sfp_type =
1891	ixgbe_sfp_type_da_act_lmt_core0;
1892	else
1893	hw->phy.sfp_type =
1894	ixgbe_sfp_type_da_act_lmt_core1;
1895	} else {
1896	/* unsupported module type */
1897	hw->phy.type = ixgbe_phy_sfp_unsupported;
1898	return IXGBE_ERR_SFP_NOT_SUPPORTED;
1899	}
1900	}
1901
1902	if (hw->phy.sfp_type != stored_sfp_type)
1903	hw->phy.sfp_setup_needed = true;
1904
1905	/* Determine if the QSFP+ PHY is dual speed or not. */
1906	hw->phy.multispeed_fiber = false;
1907	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1908	(comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1909	((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1910	(comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1911	hw->phy.multispeed_fiber = true;
1912
1913	/* Determine PHY vendor for optical modules */
1914	if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1915	IXGBE_SFF_10GBASELR_CAPABLE)) {
1916	status = hw->phy.ops.read_i2c_eeprom(hw,
1917	IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1918	&oui_bytes[0]);
1919
1920	if (status != 0)
1921	goto err_read_i2c_eeprom;
1922
1923	status = hw->phy.ops.read_i2c_eeprom(hw,
1924	IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1925	&oui_bytes[1]);
1926
1927	if (status != 0)
1928	goto err_read_i2c_eeprom;
1929
1930	status = hw->phy.ops.read_i2c_eeprom(hw,
1931	IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1932	&oui_bytes[2]);
1933
1934	if (status != 0)
1935	goto err_read_i2c_eeprom;
1936
1937	vendor_oui =
1938	((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1939	(oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1940	(oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1941
1942	if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1943	hw->phy.type = ixgbe_phy_qsfp_intel;
1944	else
1945	hw->phy.type = ixgbe_phy_qsfp_unknown;
1946
1947	hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1948	if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1949	/* Make sure we're a supported PHY type */
1950	if (hw->phy.type == ixgbe_phy_qsfp_intel)
1951	return 0;
1952	if (hw->allow_unsupported_sfp) {
1953	e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1954	return 0;
1955	}
1956	hw_dbg(hw, "QSFP module not supported\n");
1957	hw->phy.type = ixgbe_phy_sfp_unsupported;
1958	return IXGBE_ERR_SFP_NOT_SUPPORTED;
1959	}
1960	return 0;
1961	}
1962	return 0;
1963
1964	err_read_i2c_eeprom:
1965	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1966	hw->phy.id = 0;
1967	hw->phy.type = ixgbe_phy_unknown;
1968
1969	return IXGBE_ERR_SFP_NOT_PRESENT;
1970	}
1971
1972	/**
1973	* ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1974	* @hw: pointer to hardware structure
1975	* @list_offset: offset to the SFP ID list
1976	* @data_offset: offset to the SFP data block
1977	*
1978	* Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1979	* so it returns the offsets to the phy init sequence block.
1980	**/
1981	s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1982	u16 *list_offset,
1983	u16 *data_offset)
1984	{
1985	u16 sfp_id;
1986	u16 sfp_type = hw->phy.sfp_type;
1987
1988	if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1989	return IXGBE_ERR_SFP_NOT_SUPPORTED;
1990
1991	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1992	return IXGBE_ERR_SFP_NOT_PRESENT;
1993
1994	if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1995	(hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1996	return IXGBE_ERR_SFP_NOT_SUPPORTED;
1997
1998	/*
1999	* Limiting active cables and 1G Phys must be initialized as
2000	* SR modules
2001	*/
2002	if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
2003	sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2004	sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
2005	sfp_type == ixgbe_sfp_type_1g_sx_core0)
2006	sfp_type = ixgbe_sfp_type_srlr_core0;
2007	else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
2008	sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
2009	sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
2010	sfp_type == ixgbe_sfp_type_1g_sx_core1)
2011	sfp_type = ixgbe_sfp_type_srlr_core1;
2012
2013	/* Read offset to PHY init contents */
2014	if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
2015	hw_err(hw, "eeprom read at %d failed\n",
2016	IXGBE_PHY_INIT_OFFSET_NL);
2017	return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
2018	}
2019
2020	if ((!*list_offset) || (*list_offset == 0xFFFF))
2021	return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
2022
2023	/* Shift offset to first ID word */
2024	(*list_offset)++;
2025
2026	/*
2027	* Find the matching SFP ID in the EEPROM
2028	* and program the init sequence
2029	*/
2030	if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2031	goto err_phy;
2032
2033	while (sfp_id != IXGBE_PHY_INIT_END_NL) {
2034	if (sfp_id == sfp_type) {
2035	(*list_offset)++;
2036	if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
2037	goto err_phy;
2038	if ((!*data_offset) || (*data_offset == 0xFFFF)) {
2039	hw_dbg(hw, "SFP+ module not supported\n");
2040	return IXGBE_ERR_SFP_NOT_SUPPORTED;
2041	} else {
2042	break;
2043	}
2044	} else {
2045	(*list_offset) += 2;
2046	if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2047	goto err_phy;
2048	}
2049	}
2050
2051	if (sfp_id == IXGBE_PHY_INIT_END_NL) {
2052	hw_dbg(hw, "No matching SFP+ module found\n");
2053	return IXGBE_ERR_SFP_NOT_SUPPORTED;
2054	}
2055
2056	return 0;
2057
2058	err_phy:
2059	hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
2060	return IXGBE_ERR_PHY;
2061	}
2062
2063	/**
2064	* ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
2065	* @hw: pointer to hardware structure
2066	* @byte_offset: EEPROM byte offset to read
2067	* @eeprom_data: value read
2068	*
2069	* Performs byte read operation to SFP module's EEPROM over I2C interface.
2070	**/
2071	s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2072	u8 *eeprom_data)
2073	{
2074	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2075	IXGBE_I2C_EEPROM_DEV_ADDR,
2076	eeprom_data);
2077	}
2078
2079	/**
2080	* ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
2081	* @hw: pointer to hardware structure
2082	* @byte_offset: byte offset at address 0xA2
2083	* @sff8472_data: value read
2084	*
2085	* Performs byte read operation to SFP module's SFF-8472 data over I2C
2086	**/
2087	s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
2088	u8 *sff8472_data)
2089	{
2090	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2091	IXGBE_I2C_EEPROM_DEV_ADDR2,
2092	sff8472_data);
2093	}
2094
2095	/**
2096	* ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
2097	* @hw: pointer to hardware structure
2098	* @byte_offset: EEPROM byte offset to write
2099	* @eeprom_data: value to write
2100	*
2101	* Performs byte write operation to SFP module's EEPROM over I2C interface.
2102	**/
2103	s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2104	u8 eeprom_data)
2105	{
2106	return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2107	IXGBE_I2C_EEPROM_DEV_ADDR,
2108	eeprom_data);
2109	}
2110
2111	/**
2112	* ixgbe_is_sfp_probe - Returns true if SFP is being detected
2113	* @hw: pointer to hardware structure
2114	* @offset: eeprom offset to be read
2115	* @addr: I2C address to be read
2116	*/
2117	static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2118	{
2119	if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2120	offset == IXGBE_SFF_IDENTIFIER &&
2121	hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2122	return true;
2123	return false;
2124	}
2125
2126	/**
2127	* ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2128	* @hw: pointer to hardware structure
2129	* @byte_offset: byte offset to read
2130	* @dev_addr: device address
2131	* @data: value read
2132	* @lock: true if to take and release semaphore
2133	*
2134	* Performs byte read operation to SFP module's EEPROM over I2C interface at
2135	* a specified device address.
2136	*/
2137	static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2138	u8 dev_addr, u8 *data, bool lock)
2139	{
2140	s32 status;
2141	u32 max_retry = 10;
2142	u32 retry = 0;
2143	u32 swfw_mask = hw->phy.phy_semaphore_mask;
2144	bool nack = true;
2145
2146	if (hw->mac.type >= ixgbe_mac_X550)
2147	max_retry = 3;
2148	if (ixgbe_is_sfp_probe(hw, offset: byte_offset, addr: dev_addr))
2149	max_retry = IXGBE_SFP_DETECT_RETRIES;
2150
2151	*data = 0;
2152
2153	do {
2154	if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2155	return IXGBE_ERR_SWFW_SYNC;
2156
2157	ixgbe_i2c_start(hw);
2158
2159	/* Device Address and write indication */
2160	status = ixgbe_clock_out_i2c_byte(hw, data: dev_addr);
2161	if (status != 0)
2162	goto fail;
2163
2164	status = ixgbe_get_i2c_ack(hw);
2165	if (status != 0)
2166	goto fail;
2167
2168	status = ixgbe_clock_out_i2c_byte(hw, data: byte_offset);
2169	if (status != 0)
2170	goto fail;
2171
2172	status = ixgbe_get_i2c_ack(hw);
2173	if (status != 0)
2174	goto fail;
2175
2176	ixgbe_i2c_start(hw);
2177
2178	/* Device Address and read indication */
2179	status = ixgbe_clock_out_i2c_byte(hw, data: (dev_addr | 0x1));
2180	if (status != 0)
2181	goto fail;
2182
2183	status = ixgbe_get_i2c_ack(hw);
2184	if (status != 0)
2185	goto fail;
2186
2187	status = ixgbe_clock_in_i2c_byte(hw, data);
2188	if (status != 0)
2189	goto fail;
2190
2191	status = ixgbe_clock_out_i2c_bit(hw, data: nack);
2192	if (status != 0)
2193	goto fail;
2194
2195	ixgbe_i2c_stop(hw);
2196	if (lock)
2197	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2198	return 0;
2199
2200	fail:
2201	ixgbe_i2c_bus_clear(hw);
2202	if (lock) {
2203	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2204	msleep(msecs: 100);
2205	}
2206	retry++;
2207	if (retry < max_retry)
2208	hw_dbg(hw, "I2C byte read error - Retrying.\n");
2209	else
2210	hw_dbg(hw, "I2C byte read error.\n");
2211
2212	} while (retry < max_retry);
2213
2214	return status;
2215	}
2216
2217	/**
2218	* ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2219	* @hw: pointer to hardware structure
2220	* @byte_offset: byte offset to read
2221	* @dev_addr: device address
2222	* @data: value read
2223	*
2224	* Performs byte read operation to SFP module's EEPROM over I2C interface at
2225	* a specified device address.
2226	*/
2227	s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2228	u8 dev_addr, u8 *data)
2229	{
2230	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2231	data, lock: true);
2232	}
2233
2234	/**
2235	* ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2236	* @hw: pointer to hardware structure
2237	* @byte_offset: byte offset to read
2238	* @dev_addr: device address
2239	* @data: value read
2240	*
2241	* Performs byte read operation to SFP module's EEPROM over I2C interface at
2242	* a specified device address.
2243	*/
2244	s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2245	u8 dev_addr, u8 *data)
2246	{
2247	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2248	data, lock: false);
2249	}
2250
2251	/**
2252	* ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2253	* @hw: pointer to hardware structure
2254	* @byte_offset: byte offset to write
2255	* @dev_addr: device address
2256	* @data: value to write
2257	* @lock: true if to take and release semaphore
2258	*
2259	* Performs byte write operation to SFP module's EEPROM over I2C interface at
2260	* a specified device address.
2261	*/
2262	static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2263	u8 dev_addr, u8 data, bool lock)
2264	{
2265	s32 status;
2266	u32 max_retry = 1;
2267	u32 retry = 0;
2268	u32 swfw_mask = hw->phy.phy_semaphore_mask;
2269
2270	if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2271	return IXGBE_ERR_SWFW_SYNC;
2272
2273	do {
2274	ixgbe_i2c_start(hw);
2275
2276	status = ixgbe_clock_out_i2c_byte(hw, data: dev_addr);
2277	if (status != 0)
2278	goto fail;
2279
2280	status = ixgbe_get_i2c_ack(hw);
2281	if (status != 0)
2282	goto fail;
2283
2284	status = ixgbe_clock_out_i2c_byte(hw, data: byte_offset);
2285	if (status != 0)
2286	goto fail;
2287
2288	status = ixgbe_get_i2c_ack(hw);
2289	if (status != 0)
2290	goto fail;
2291
2292	status = ixgbe_clock_out_i2c_byte(hw, data);
2293	if (status != 0)
2294	goto fail;
2295
2296	status = ixgbe_get_i2c_ack(hw);
2297	if (status != 0)
2298	goto fail;
2299
2300	ixgbe_i2c_stop(hw);
2301	if (lock)
2302	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2303	return 0;
2304
2305	fail:
2306	ixgbe_i2c_bus_clear(hw);
2307	retry++;
2308	if (retry < max_retry)
2309	hw_dbg(hw, "I2C byte write error - Retrying.\n");
2310	else
2311	hw_dbg(hw, "I2C byte write error.\n");
2312	} while (retry < max_retry);
2313
2314	if (lock)
2315	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2316
2317	return status;
2318	}
2319
2320	/**
2321	* ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2322	* @hw: pointer to hardware structure
2323	* @byte_offset: byte offset to write
2324	* @dev_addr: device address
2325	* @data: value to write
2326	*
2327	* Performs byte write operation to SFP module's EEPROM over I2C interface at
2328	* a specified device address.
2329	*/
2330	s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2331	u8 dev_addr, u8 data)
2332	{
2333	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2334	data, lock: true);
2335	}
2336
2337	/**
2338	* ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2339	* @hw: pointer to hardware structure
2340	* @byte_offset: byte offset to write
2341	* @dev_addr: device address
2342	* @data: value to write
2343	*
2344	* Performs byte write operation to SFP module's EEPROM over I2C interface at
2345	* a specified device address.
2346	*/
2347	s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2348	u8 dev_addr, u8 data)
2349	{
2350	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2351	data, lock: false);
2352	}
2353
2354	/**
2355	* ixgbe_i2c_start - Sets I2C start condition
2356	* @hw: pointer to hardware structure
2357	*
2358	* Sets I2C start condition (High -> Low on SDA while SCL is High)
2359	* Set bit-bang mode on X550 hardware.
2360	**/
2361	static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2362	{
2363	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2364
2365	i2cctl |= IXGBE_I2C_BB_EN(hw);
2366
2367	/* Start condition must begin with data and clock high */
2368	ixgbe_set_i2c_data(hw, i2cctl: &i2cctl, data: 1);
2369	ixgbe_raise_i2c_clk(hw, i2cctl: &i2cctl);
2370
2371	/* Setup time for start condition (4.7us) */
2372	udelay(IXGBE_I2C_T_SU_STA);
2373
2374	ixgbe_set_i2c_data(hw, i2cctl: &i2cctl, data: 0);
2375
2376	/* Hold time for start condition (4us) */
2377	udelay(IXGBE_I2C_T_HD_STA);
2378
2379	ixgbe_lower_i2c_clk(hw, i2cctl: &i2cctl);
2380
2381	/* Minimum low period of clock is 4.7 us */
2382	udelay(IXGBE_I2C_T_LOW);
2383
2384	}
2385
2386	/**
2387	* ixgbe_i2c_stop - Sets I2C stop condition
2388	* @hw: pointer to hardware structure
2389	*
2390	* Sets I2C stop condition (Low -> High on SDA while SCL is High)
2391	* Disables bit-bang mode and negates data output enable on X550
2392	* hardware.
2393	**/
2394	static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2395	{
2396	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2397	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2398	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2399	u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2400
2401	/* Stop condition must begin with data low and clock high */
2402	ixgbe_set_i2c_data(hw, i2cctl: &i2cctl, data: 0);
2403	ixgbe_raise_i2c_clk(hw, i2cctl: &i2cctl);
2404
2405	/* Setup time for stop condition (4us) */
2406	udelay(IXGBE_I2C_T_SU_STO);
2407
2408	ixgbe_set_i2c_data(hw, i2cctl: &i2cctl, data: 1);
2409
2410	/* bus free time between stop and start (4.7us)*/
2411	udelay(IXGBE_I2C_T_BUF);
2412
2413	if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2414	i2cctl &= ~bb_en_bit;
2415	i2cctl |= data_oe_bit | clk_oe_bit;
2416	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2417	IXGBE_WRITE_FLUSH(hw);
2418	}
2419	}
2420
2421	/**
2422	* ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2423	* @hw: pointer to hardware structure
2424	* @data: data byte to clock in
2425	*
2426	* Clocks in one byte data via I2C data/clock
2427	**/
2428	static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2429	{
2430	s32 i;
2431	bool bit = false;
2432
2433	*data = 0;
2434	for (i = 7; i >= 0; i--) {
2435	ixgbe_clock_in_i2c_bit(hw, data: &bit);
2436	*data |= bit << i;
2437	}
2438
2439	return 0;
2440	}
2441
2442	/**
2443	* ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2444	* @hw: pointer to hardware structure
2445	* @data: data byte clocked out
2446	*
2447	* Clocks out one byte data via I2C data/clock
2448	**/
2449	static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2450	{
2451	s32 status;
2452	s32 i;
2453	u32 i2cctl;
2454	bool bit = false;
2455
2456	for (i = 7; i >= 0; i--) {
2457	bit = (data >> i) & 0x1;
2458	status = ixgbe_clock_out_i2c_bit(hw, data: bit);
2459
2460	if (status != 0)
2461	break;
2462	}
2463
2464	/* Release SDA line (set high) */
2465	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2466	i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2467	i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2468	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2469	IXGBE_WRITE_FLUSH(hw);
2470
2471	return status;
2472	}
2473
2474	/**
2475	* ixgbe_get_i2c_ack - Polls for I2C ACK
2476	* @hw: pointer to hardware structure
2477	*
2478	* Clocks in/out one bit via I2C data/clock
2479	**/
2480	static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2481	{
2482	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2483	s32 status = 0;
2484	u32 i = 0;
2485	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2486	u32 timeout = 10;
2487	bool ack = true;
2488
2489	if (data_oe_bit) {
2490	i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2491	i2cctl |= data_oe_bit;
2492	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2493	IXGBE_WRITE_FLUSH(hw);
2494	}
2495	ixgbe_raise_i2c_clk(hw, i2cctl: &i2cctl);
2496
2497	/* Minimum high period of clock is 4us */
2498	udelay(IXGBE_I2C_T_HIGH);
2499
2500	/* Poll for ACK. Note that ACK in I2C spec is
2501	* transition from 1 to 0 */
2502	for (i = 0; i < timeout; i++) {
2503	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2504	ack = ixgbe_get_i2c_data(hw, i2cctl: &i2cctl);
2505
2506	udelay(1);
2507	if (ack == 0)
2508	break;
2509	}
2510
2511	if (ack == 1) {
2512	hw_dbg(hw, "I2C ack was not received.\n");
2513	status = IXGBE_ERR_I2C;
2514	}
2515
2516	ixgbe_lower_i2c_clk(hw, i2cctl: &i2cctl);
2517
2518	/* Minimum low period of clock is 4.7 us */
2519	udelay(IXGBE_I2C_T_LOW);
2520
2521	return status;
2522	}
2523
2524	/**
2525	* ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2526	* @hw: pointer to hardware structure
2527	* @data: read data value
2528	*
2529	* Clocks in one bit via I2C data/clock
2530	**/
2531	static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2532	{
2533	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2534	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2535
2536	if (data_oe_bit) {
2537	i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2538	i2cctl |= data_oe_bit;
2539	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2540	IXGBE_WRITE_FLUSH(hw);
2541	}
2542	ixgbe_raise_i2c_clk(hw, i2cctl: &i2cctl);
2543
2544	/* Minimum high period of clock is 4us */
2545	udelay(IXGBE_I2C_T_HIGH);
2546
2547	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2548	*data = ixgbe_get_i2c_data(hw, i2cctl: &i2cctl);
2549
2550	ixgbe_lower_i2c_clk(hw, i2cctl: &i2cctl);
2551
2552	/* Minimum low period of clock is 4.7 us */
2553	udelay(IXGBE_I2C_T_LOW);
2554
2555	return 0;
2556	}
2557
2558	/**
2559	* ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2560	* @hw: pointer to hardware structure
2561	* @data: data value to write
2562	*
2563	* Clocks out one bit via I2C data/clock
2564	**/
2565	static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2566	{
2567	s32 status;
2568	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2569
2570	status = ixgbe_set_i2c_data(hw, i2cctl: &i2cctl, data);
2571	if (status == 0) {
2572	ixgbe_raise_i2c_clk(hw, i2cctl: &i2cctl);
2573
2574	/* Minimum high period of clock is 4us */
2575	udelay(IXGBE_I2C_T_HIGH);
2576
2577	ixgbe_lower_i2c_clk(hw, i2cctl: &i2cctl);
2578
2579	/* Minimum low period of clock is 4.7 us.
2580	* This also takes care of the data hold time.
2581	*/
2582	udelay(IXGBE_I2C_T_LOW);
2583	} else {
2584	hw_dbg(hw, "I2C data was not set to %X\n", data);
2585	return IXGBE_ERR_I2C;
2586	}
2587
2588	return 0;
2589	}
2590	/**
2591	* ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2592	* @hw: pointer to hardware structure
2593	* @i2cctl: Current value of I2CCTL register
2594	*
2595	* Raises the I2C clock line '0'->'1'
2596	* Negates the I2C clock output enable on X550 hardware.
2597	**/
2598	static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2599	{
2600	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2601	u32 i = 0;
2602	u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2603	u32 i2cctl_r = 0;
2604
2605	if (clk_oe_bit) {
2606	*i2cctl |= clk_oe_bit;
2607	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2608	}
2609
2610	for (i = 0; i < timeout; i++) {
2611	*i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2612	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2613	IXGBE_WRITE_FLUSH(hw);
2614	/* SCL rise time (1000ns) */
2615	udelay(IXGBE_I2C_T_RISE);
2616
2617	i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2618	if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2619	break;
2620	}
2621	}
2622
2623	/**
2624	* ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2625	* @hw: pointer to hardware structure
2626	* @i2cctl: Current value of I2CCTL register
2627	*
2628	* Lowers the I2C clock line '1'->'0'
2629	* Asserts the I2C clock output enable on X550 hardware.
2630	**/
2631	static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2632	{
2633
2634	*i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2635	*i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2636
2637	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2638	IXGBE_WRITE_FLUSH(hw);
2639
2640	/* SCL fall time (300ns) */
2641	udelay(IXGBE_I2C_T_FALL);
2642	}
2643
2644	/**
2645	* ixgbe_set_i2c_data - Sets the I2C data bit
2646	* @hw: pointer to hardware structure
2647	* @i2cctl: Current value of I2CCTL register
2648	* @data: I2C data value (0 or 1) to set
2649	*
2650	* Sets the I2C data bit
2651	* Asserts the I2C data output enable on X550 hardware.
2652	**/
2653	static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2654	{
2655	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2656
2657	if (data)
2658	*i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2659	else
2660	*i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2661	*i2cctl &= ~data_oe_bit;
2662
2663	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2664	IXGBE_WRITE_FLUSH(hw);
2665
2666	/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2667	udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2668
2669	if (!data) /* Can't verify data in this case */
2670	return 0;
2671	if (data_oe_bit) {
2672	*i2cctl |= data_oe_bit;
2673	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2674	IXGBE_WRITE_FLUSH(hw);
2675	}
2676
2677	/* Verify data was set correctly */
2678	*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2679	if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2680	hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2681	return IXGBE_ERR_I2C;
2682	}
2683
2684	return 0;
2685	}
2686
2687	/**
2688	* ixgbe_get_i2c_data - Reads the I2C SDA data bit
2689	* @hw: pointer to hardware structure
2690	* @i2cctl: Current value of I2CCTL register
2691	*
2692	* Returns the I2C data bit value
2693	* Negates the I2C data output enable on X550 hardware.
2694	**/
2695	static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2696	{
2697	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2698
2699	if (data_oe_bit) {
2700	*i2cctl |= data_oe_bit;
2701	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2702	IXGBE_WRITE_FLUSH(hw);
2703	udelay(IXGBE_I2C_T_FALL);
2704	}
2705
2706	if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2707	return true;
2708	return false;
2709	}
2710
2711	/**
2712	* ixgbe_i2c_bus_clear - Clears the I2C bus
2713	* @hw: pointer to hardware structure
2714	*
2715	* Clears the I2C bus by sending nine clock pulses.
2716	* Used when data line is stuck low.
2717	**/
2718	static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2719	{
2720	u32 i2cctl;
2721	u32 i;
2722
2723	ixgbe_i2c_start(hw);
2724	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2725
2726	ixgbe_set_i2c_data(hw, i2cctl: &i2cctl, data: 1);
2727
2728	for (i = 0; i < 9; i++) {
2729	ixgbe_raise_i2c_clk(hw, i2cctl: &i2cctl);
2730
2731	/* Min high period of clock is 4us */
2732	udelay(IXGBE_I2C_T_HIGH);
2733
2734	ixgbe_lower_i2c_clk(hw, i2cctl: &i2cctl);
2735
2736	/* Min low period of clock is 4.7us*/
2737	udelay(IXGBE_I2C_T_LOW);
2738	}
2739
2740	ixgbe_i2c_start(hw);
2741
2742	/* Put the i2c bus back to default state */
2743	ixgbe_i2c_stop(hw);
2744	}
2745
2746	/**
2747	* ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2748	* @hw: pointer to hardware structure
2749	*
2750	* Checks if the LASI temp alarm status was triggered due to overtemp
2751	**/
2752	s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2753	{
2754	u16 phy_data = 0;
2755
2756	if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2757	return 0;
2758
2759	/* Check that the LASI temp alarm status was triggered */
2760	hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2761	MDIO_MMD_PMAPMD, &phy_data);
2762
2763	if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2764	return 0;
2765
2766	return IXGBE_ERR_OVERTEMP;
2767	}
2768
2769	/** ixgbe_set_copper_phy_power - Control power for copper phy
2770	* @hw: pointer to hardware structure
2771	* @on: true for on, false for off
2772	**/
2773	s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2774	{
2775	u32 status;
2776	u16 reg;
2777
2778	/* Bail if we don't have copper phy */
2779	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2780	return 0;
2781
2782	if (!on && ixgbe_mng_present(hw))
2783	return 0;
2784
2785	status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg);
2786	if (status)
2787	return status;
2788
2789	if (on) {
2790	reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2791	} else {
2792	if (ixgbe_check_reset_blocked(hw))
2793	return 0;
2794	reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2795	}
2796
2797	status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2798	return status;
2799	}
2800