1 | /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ |
2 | /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ |
3 | |
4 | #ifndef _MLXSW_TXHEADER_H |
5 | #define |
6 | |
7 | #define MLXSW_TXHDR_LEN 0x10 |
8 | #define MLXSW_TXHDR_VERSION_0 0 |
9 | #define MLXSW_TXHDR_VERSION_1 1 |
10 | |
11 | enum { |
12 | MLXSW_TXHDR_ETH_CTL, |
13 | MLXSW_TXHDR_ETH_DATA, |
14 | }; |
15 | |
16 | #define MLXSW_TXHDR_PROTO_ETH 1 |
17 | |
18 | enum { |
19 | MLXSW_TXHDR_ETCLASS_0, |
20 | MLXSW_TXHDR_ETCLASS_1, |
21 | MLXSW_TXHDR_ETCLASS_2, |
22 | MLXSW_TXHDR_ETCLASS_3, |
23 | MLXSW_TXHDR_ETCLASS_4, |
24 | MLXSW_TXHDR_ETCLASS_5, |
25 | MLXSW_TXHDR_ETCLASS_6, |
26 | MLXSW_TXHDR_ETCLASS_7, |
27 | }; |
28 | |
29 | enum { |
30 | MLXSW_TXHDR_RDQ_OTHER, |
31 | MLXSW_TXHDR_RDQ_EMAD = 0x1f, |
32 | }; |
33 | |
34 | #define MLXSW_TXHDR_CTCLASS3 0 |
35 | #define MLXSW_TXHDR_CPU_SIG 0 |
36 | #define MLXSW_TXHDR_SIG 0xE0E0 |
37 | #define MLXSW_TXHDR_STCLASS_NONE 0 |
38 | |
39 | enum { |
40 | MLXSW_TXHDR_NOT_EMAD, |
41 | MLXSW_TXHDR_EMAD, |
42 | }; |
43 | |
44 | enum { |
45 | MLXSW_TXHDR_TYPE_DATA, |
46 | MLXSW_TXHDR_TYPE_CONTROL = 6, |
47 | }; |
48 | |
49 | #endif |
50 | |