1 | #ifndef TLAN_H |
2 | #define TLAN_H |
3 | /******************************************************************** |
4 | * |
5 | * Linux ThunderLAN Driver |
6 | * |
7 | * tlan.h |
8 | * by James Banks |
9 | * |
10 | * (C) 1997-1998 Caldera, Inc. |
11 | * (C) 1999-2001 Torben Mathiasen |
12 | * |
13 | * This software may be used and distributed according to the terms |
14 | * of the GNU General Public License, incorporated herein by reference. |
15 | * |
16 | * |
17 | * Dec 10, 1999 Torben Mathiasen <torben.mathiasen@compaq.com> |
18 | * New Maintainer |
19 | * |
20 | ********************************************************************/ |
21 | |
22 | |
23 | #include <linux/io.h> |
24 | #include <linux/types.h> |
25 | #include <linux/netdevice.h> |
26 | |
27 | |
28 | |
29 | /***************************************************************** |
30 | * TLan Definitions |
31 | * |
32 | ****************************************************************/ |
33 | |
34 | #define TLAN_MIN_FRAME_SIZE 64 |
35 | #define TLAN_MAX_FRAME_SIZE 1600 |
36 | |
37 | #define TLAN_NUM_RX_LISTS 32 |
38 | #define TLAN_NUM_TX_LISTS 64 |
39 | |
40 | #define TLAN_IGNORE 0 |
41 | #define TLAN_RECORD 1 |
42 | |
43 | #define TLAN_DBG(lvl, format, args...) \ |
44 | do { \ |
45 | if (debug&lvl) \ |
46 | printk(KERN_DEBUG "TLAN: " format, ##args); \ |
47 | } while (0) |
48 | |
49 | #define TLAN_DEBUG_GNRL 0x0001 |
50 | #define TLAN_DEBUG_TX 0x0002 |
51 | #define TLAN_DEBUG_RX 0x0004 |
52 | #define TLAN_DEBUG_LIST 0x0008 |
53 | #define TLAN_DEBUG_PROBE 0x0010 |
54 | |
55 | #define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */ |
56 | #define MAX_TLAN_BOARDS 8 /* Max number of boards installed |
57 | at a time */ |
58 | |
59 | |
60 | /***************************************************************** |
61 | * Device Identification Definitions |
62 | * |
63 | ****************************************************************/ |
64 | |
65 | #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012 |
66 | #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030 |
67 | #ifndef PCI_DEVICE_ID_OLICOM_OC2183 |
68 | #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 |
69 | #endif |
70 | #ifndef PCI_DEVICE_ID_OLICOM_OC2325 |
71 | #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 |
72 | #endif |
73 | #ifndef PCI_DEVICE_ID_OLICOM_OC2326 |
74 | #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 |
75 | #endif |
76 | |
77 | struct tlan_adapter_entry { |
78 | u16 vendor_id; |
79 | u16 device_id; |
80 | char *device_label; |
81 | u32 flags; |
82 | u16 addr_ofs; |
83 | }; |
84 | |
85 | #define TLAN_ADAPTER_NONE 0x00000000 |
86 | #define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001 |
87 | #define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002 |
88 | #define TLAN_ADAPTER_USE_INTERN_10 0x00000004 |
89 | #define TLAN_ADAPTER_ACTIVITY_LED 0x00000008 |
90 | |
91 | #define TLAN_SPEED_DEFAULT 0 |
92 | #define TLAN_SPEED_10 10 |
93 | #define TLAN_SPEED_100 100 |
94 | |
95 | #define TLAN_DUPLEX_DEFAULT 0 |
96 | #define TLAN_DUPLEX_HALF 1 |
97 | #define TLAN_DUPLEX_FULL 2 |
98 | |
99 | |
100 | |
101 | /***************************************************************** |
102 | * EISA Definitions |
103 | * |
104 | ****************************************************************/ |
105 | |
106 | #define EISA_ID 0xc80 /* EISA ID Registers */ |
107 | #define EISA_ID0 0xc80 /* EISA ID Register 0 */ |
108 | #define EISA_ID1 0xc81 /* EISA ID Register 1 */ |
109 | #define EISA_ID2 0xc82 /* EISA ID Register 2 */ |
110 | #define EISA_ID3 0xc83 /* EISA ID Register 3 */ |
111 | #define EISA_CR 0xc84 /* EISA Control Register */ |
112 | #define EISA_REG0 0xc88 /* EISA Configuration Register 0 */ |
113 | #define EISA_REG1 0xc89 /* EISA Configuration Register 1 */ |
114 | #define EISA_REG2 0xc8a /* EISA Configuration Register 2 */ |
115 | #define EISA_REG3 0xc8f /* EISA Configuration Register 3 */ |
116 | #define EISA_APROM 0xc90 /* Ethernet Address PROM */ |
117 | |
118 | |
119 | |
120 | /***************************************************************** |
121 | * Rx/Tx List Definitions |
122 | * |
123 | ****************************************************************/ |
124 | |
125 | #define TLAN_BUFFERS_PER_LIST 10 |
126 | #define TLAN_LAST_BUFFER 0x80000000 |
127 | #define TLAN_CSTAT_UNUSED 0x8000 |
128 | #define TLAN_CSTAT_FRM_CMP 0x4000 |
129 | #define TLAN_CSTAT_READY 0x3000 |
130 | #define TLAN_CSTAT_EOC 0x0800 |
131 | #define TLAN_CSTAT_RX_ERROR 0x0400 |
132 | #define TLAN_CSTAT_PASS_CRC 0x0200 |
133 | #define TLAN_CSTAT_DP_PR 0x0100 |
134 | |
135 | |
136 | struct tlan_buffer { |
137 | u32 count; |
138 | u32 address; |
139 | }; |
140 | |
141 | |
142 | struct tlan_list { |
143 | u32 forward; |
144 | u16 c_stat; |
145 | u16 frame_size; |
146 | struct tlan_buffer buffer[TLAN_BUFFERS_PER_LIST]; |
147 | }; |
148 | |
149 | |
150 | typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE]; |
151 | |
152 | |
153 | |
154 | |
155 | /***************************************************************** |
156 | * PHY definitions |
157 | * |
158 | ****************************************************************/ |
159 | |
160 | #define TLAN_PHY_MAX_ADDR 0x1F |
161 | #define TLAN_PHY_NONE 0x20 |
162 | |
163 | |
164 | |
165 | |
166 | /***************************************************************** |
167 | * TLAN Private Information Structure |
168 | * |
169 | ****************************************************************/ |
170 | |
171 | struct tlan_priv { |
172 | struct net_device *next_device; |
173 | struct pci_dev *pci_dev; |
174 | struct net_device *dev; |
175 | void *dma_storage; |
176 | dma_addr_t dma_storage_dma; |
177 | unsigned int dma_size; |
178 | u8 *pad_buffer; |
179 | struct tlan_list *rx_list; |
180 | dma_addr_t rx_list_dma; |
181 | u8 *rx_buffer; |
182 | dma_addr_t rx_buffer_dma; |
183 | u32 rx_head; |
184 | u32 rx_tail; |
185 | u32 rx_eoc_count; |
186 | struct tlan_list *tx_list; |
187 | dma_addr_t tx_list_dma; |
188 | u8 *tx_buffer; |
189 | dma_addr_t tx_buffer_dma; |
190 | u32 tx_head; |
191 | u32 tx_in_progress; |
192 | u32 tx_tail; |
193 | u32 tx_busy_count; |
194 | u32 phy_online; |
195 | u32 timer_set_at; |
196 | u32 timer_type; |
197 | struct timer_list timer; |
198 | struct timer_list media_timer; |
199 | struct board *adapter; |
200 | u32 adapter_rev; |
201 | u32 aui; |
202 | u32 debug; |
203 | u32 duplex; |
204 | u32 phy[2]; |
205 | u32 phy_num; |
206 | u32 speed; |
207 | u8 tlan_rev; |
208 | u8 tlan_full_duplex; |
209 | spinlock_t lock; |
210 | struct work_struct tlan_tqueue; |
211 | }; |
212 | |
213 | |
214 | |
215 | |
216 | /***************************************************************** |
217 | * TLan Driver Timer Definitions |
218 | * |
219 | ****************************************************************/ |
220 | |
221 | #define TLAN_TIMER_ACTIVITY 2 |
222 | #define TLAN_TIMER_PHY_PDOWN 3 |
223 | #define TLAN_TIMER_PHY_PUP 4 |
224 | #define TLAN_TIMER_PHY_RESET 5 |
225 | #define TLAN_TIMER_PHY_START_LINK 6 |
226 | #define TLAN_TIMER_PHY_FINISH_AN 7 |
227 | #define TLAN_TIMER_FINISH_RESET 8 |
228 | |
229 | #define TLAN_TIMER_ACT_DELAY (HZ/10) |
230 | |
231 | |
232 | |
233 | |
234 | /***************************************************************** |
235 | * TLan Driver Eeprom Definitions |
236 | * |
237 | ****************************************************************/ |
238 | |
239 | #define TLAN_EEPROM_ACK 0 |
240 | #define TLAN_EEPROM_STOP 1 |
241 | |
242 | #define TLAN_EEPROM_SIZE 256 |
243 | |
244 | |
245 | |
246 | /***************************************************************** |
247 | * Host Register Offsets and Contents |
248 | * |
249 | ****************************************************************/ |
250 | |
251 | #define TLAN_HOST_CMD 0x00 |
252 | #define TLAN_HC_GO 0x80000000 |
253 | #define TLAN_HC_STOP 0x40000000 |
254 | #define TLAN_HC_ACK 0x20000000 |
255 | #define TLAN_HC_CS_MASK 0x1FE00000 |
256 | #define TLAN_HC_EOC 0x00100000 |
257 | #define TLAN_HC_RT 0x00080000 |
258 | #define TLAN_HC_NES 0x00040000 |
259 | #define TLAN_HC_AD_RST 0x00008000 |
260 | #define TLAN_HC_LD_TMR 0x00004000 |
261 | #define TLAN_HC_LD_THR 0x00002000 |
262 | #define TLAN_HC_REQ_INT 0x00001000 |
263 | #define TLAN_HC_INT_OFF 0x00000800 |
264 | #define TLAN_HC_INT_ON 0x00000400 |
265 | #define TLAN_HC_AC_MASK 0x000000FF |
266 | #define TLAN_CH_PARM 0x04 |
267 | #define TLAN_DIO_ADR 0x08 |
268 | #define TLAN_DA_ADR_INC 0x8000 |
269 | #define TLAN_DA_RAM_ADR 0x4000 |
270 | #define TLAN_HOST_INT 0x0A |
271 | #define TLAN_HI_IV_MASK 0x1FE0 |
272 | #define TLAN_HI_IT_MASK 0x001C |
273 | #define TLAN_DIO_DATA 0x0C |
274 | |
275 | |
276 | /* ThunderLAN Internal Register DIO Offsets */ |
277 | |
278 | #define TLAN_NET_CMD 0x00 |
279 | #define TLAN_NET_CMD_NRESET 0x80 |
280 | #define TLAN_NET_CMD_NWRAP 0x40 |
281 | #define TLAN_NET_CMD_CSF 0x20 |
282 | #define TLAN_NET_CMD_CAF 0x10 |
283 | #define TLAN_NET_CMD_NOBRX 0x08 |
284 | #define TLAN_NET_CMD_DUPLEX 0x04 |
285 | #define TLAN_NET_CMD_TRFRAM 0x02 |
286 | #define TLAN_NET_CMD_TXPACE 0x01 |
287 | #define TLAN_NET_SIO 0x01 |
288 | #define TLAN_NET_SIO_MINTEN 0x80 |
289 | #define TLAN_NET_SIO_ECLOK 0x40 |
290 | #define TLAN_NET_SIO_ETXEN 0x20 |
291 | #define TLAN_NET_SIO_EDATA 0x10 |
292 | #define TLAN_NET_SIO_NMRST 0x08 |
293 | #define TLAN_NET_SIO_MCLK 0x04 |
294 | #define TLAN_NET_SIO_MTXEN 0x02 |
295 | #define TLAN_NET_SIO_MDATA 0x01 |
296 | #define TLAN_NET_STS 0x02 |
297 | #define TLAN_NET_STS_MIRQ 0x80 |
298 | #define TLAN_NET_STS_HBEAT 0x40 |
299 | #define TLAN_NET_STS_TXSTOP 0x20 |
300 | #define TLAN_NET_STS_RXSTOP 0x10 |
301 | #define TLAN_NET_STS_RSRVD 0x0F |
302 | #define TLAN_NET_MASK 0x03 |
303 | #define TLAN_NET_MASK_MASK7 0x80 |
304 | #define TLAN_NET_MASK_MASK6 0x40 |
305 | #define TLAN_NET_MASK_MASK5 0x20 |
306 | #define TLAN_NET_MASK_MASK4 0x10 |
307 | #define TLAN_NET_MASK_RSRVD 0x0F |
308 | #define TLAN_NET_CONFIG 0x04 |
309 | #define TLAN_NET_CFG_RCLK 0x8000 |
310 | #define TLAN_NET_CFG_TCLK 0x4000 |
311 | #define TLAN_NET_CFG_BIT 0x2000 |
312 | #define TLAN_NET_CFG_RXCRC 0x1000 |
313 | #define TLAN_NET_CFG_PEF 0x0800 |
314 | #define TLAN_NET_CFG_1FRAG 0x0400 |
315 | #define TLAN_NET_CFG_1CHAN 0x0200 |
316 | #define TLAN_NET_CFG_MTEST 0x0100 |
317 | #define TLAN_NET_CFG_PHY_EN 0x0080 |
318 | #define TLAN_NET_CFG_MSMASK 0x007F |
319 | #define TLAN_MAN_TEST 0x06 |
320 | #define TLAN_DEF_VENDOR_ID 0x08 |
321 | #define TLAN_DEF_DEVICE_ID 0x0A |
322 | #define TLAN_DEF_REVISION 0x0C |
323 | #define TLAN_DEF_SUBCLASS 0x0D |
324 | #define TLAN_DEF_MIN_LAT 0x0E |
325 | #define TLAN_DEF_MAX_LAT 0x0F |
326 | #define TLAN_AREG_0 0x10 |
327 | #define TLAN_AREG_1 0x16 |
328 | #define TLAN_AREG_2 0x1C |
329 | #define TLAN_AREG_3 0x22 |
330 | #define TLAN_HASH_1 0x28 |
331 | #define TLAN_HASH_2 0x2C |
332 | #define TLAN_GOOD_TX_FRMS 0x30 |
333 | #define TLAN_TX_UNDERUNS 0x33 |
334 | #define TLAN_GOOD_RX_FRMS 0x34 |
335 | #define TLAN_RX_OVERRUNS 0x37 |
336 | #define TLAN_DEFERRED_TX 0x38 |
337 | #define TLAN_CRC_ERRORS 0x3A |
338 | #define TLAN_CODE_ERRORS 0x3B |
339 | #define TLAN_MULTICOL_FRMS 0x3C |
340 | #define TLAN_SINGLECOL_FRMS 0x3E |
341 | #define TLAN_EXCESSCOL_FRMS 0x40 |
342 | #define TLAN_LATE_COLS 0x41 |
343 | #define TLAN_CARRIER_LOSS 0x42 |
344 | #define TLAN_ACOMMIT 0x43 |
345 | #define TLAN_LED_REG 0x44 |
346 | #define TLAN_LED_ACT 0x10 |
347 | #define TLAN_LED_LINK 0x01 |
348 | #define TLAN_BSIZE_REG 0x45 |
349 | #define TLAN_MAX_RX 0x46 |
350 | #define TLAN_INT_DIS 0x48 |
351 | #define TLAN_ID_TX_EOC 0x04 |
352 | #define TLAN_ID_RX_EOF 0x02 |
353 | #define TLAN_ID_RX_EOC 0x01 |
354 | |
355 | |
356 | |
357 | /* ThunderLAN Interrupt Codes */ |
358 | |
359 | #define TLAN_INT_NUMBER_OF_INTS 8 |
360 | |
361 | #define TLAN_INT_NONE 0x0000 |
362 | #define TLAN_INT_TX_EOF 0x0001 |
363 | #define TLAN_INT_STAT_OVERFLOW 0x0002 |
364 | #define TLAN_INT_RX_EOF 0x0003 |
365 | #define TLAN_INT_DUMMY 0x0004 |
366 | #define TLAN_INT_TX_EOC 0x0005 |
367 | #define TLAN_INT_STATUS_CHECK 0x0006 |
368 | #define TLAN_INT_RX_EOC 0x0007 |
369 | |
370 | |
371 | |
372 | /* ThunderLAN MII Registers */ |
373 | |
374 | /* Generic MII/PHY Registers */ |
375 | |
376 | #define MII_GEN_CTL 0x00 |
377 | #define MII_GC_RESET 0x8000 |
378 | #define MII_GC_LOOPBK 0x4000 |
379 | #define MII_GC_SPEEDSEL 0x2000 |
380 | #define MII_GC_AUTOENB 0x1000 |
381 | #define MII_GC_PDOWN 0x0800 |
382 | #define MII_GC_ISOLATE 0x0400 |
383 | #define MII_GC_AUTORSRT 0x0200 |
384 | #define MII_GC_DUPLEX 0x0100 |
385 | #define MII_GC_COLTEST 0x0080 |
386 | #define MII_GC_RESERVED 0x007F |
387 | #define MII_GEN_STS 0x01 |
388 | #define MII_GS_100BT4 0x8000 |
389 | #define MII_GS_100BTXFD 0x4000 |
390 | #define MII_GS_100BTXHD 0x2000 |
391 | #define MII_GS_10BTFD 0x1000 |
392 | #define MII_GS_10BTHD 0x0800 |
393 | #define MII_GS_RESERVED 0x07C0 |
394 | #define MII_GS_AUTOCMPLT 0x0020 |
395 | #define MII_GS_RFLT 0x0010 |
396 | #define MII_GS_AUTONEG 0x0008 |
397 | #define MII_GS_LINK 0x0004 |
398 | #define MII_GS_JABBER 0x0002 |
399 | #define MII_GS_EXTCAP 0x0001 |
400 | #define MII_GEN_ID_HI 0x02 |
401 | #define MII_GEN_ID_LO 0x03 |
402 | #define MII_GIL_OUI 0xFC00 |
403 | #define MII_GIL_MODEL 0x03F0 |
404 | #define MII_GIL_REVISION 0x000F |
405 | #define MII_AN_ADV 0x04 |
406 | #define MII_AN_LPA 0x05 |
407 | #define MII_AN_EXP 0x06 |
408 | |
409 | /* ThunderLAN Specific MII/PHY Registers */ |
410 | |
411 | #define TLAN_TLPHY_ID 0x10 |
412 | #define TLAN_TLPHY_CTL 0x11 |
413 | #define TLAN_TC_IGLINK 0x8000 |
414 | #define TLAN_TC_SWAPOL 0x4000 |
415 | #define TLAN_TC_AUISEL 0x2000 |
416 | #define TLAN_TC_SQEEN 0x1000 |
417 | #define TLAN_TC_MTEST 0x0800 |
418 | #define TLAN_TC_RESERVED 0x07F8 |
419 | #define TLAN_TC_NFEW 0x0004 |
420 | #define TLAN_TC_INTEN 0x0002 |
421 | #define TLAN_TC_TINT 0x0001 |
422 | #define TLAN_TLPHY_STS 0x12 |
423 | #define TLAN_TS_MINT 0x8000 |
424 | #define TLAN_TS_PHOK 0x4000 |
425 | #define TLAN_TS_POLOK 0x2000 |
426 | #define TLAN_TS_TPENERGY 0x1000 |
427 | #define TLAN_TS_RESERVED 0x0FFF |
428 | #define TLAN_TLPHY_PAR 0x19 |
429 | #define TLAN_PHY_CIM_STAT 0x0020 |
430 | #define TLAN_PHY_SPEED_100 0x0040 |
431 | #define TLAN_PHY_DUPLEX_FULL 0x0080 |
432 | #define TLAN_PHY_AN_EN_STAT 0x0400 |
433 | |
434 | /* National Sem. & Level1 PHY id's */ |
435 | #define NAT_SEM_ID1 0x2000 |
436 | #define NAT_SEM_ID2 0x5C01 |
437 | #define LEVEL1_ID1 0x7810 |
438 | #define LEVEL1_ID2 0x0000 |
439 | |
440 | #define CIRC_INC(a, b) if (++a >= b) a = 0 |
441 | |
442 | /* Routines to access internal registers. */ |
443 | |
444 | static inline u8 tlan_dio_read8(u16 base_addr, u16 internal_addr) |
445 | { |
446 | outw(value: internal_addr, port: base_addr + TLAN_DIO_ADR); |
447 | return inb(port: (base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)); |
448 | |
449 | } |
450 | |
451 | |
452 | |
453 | |
454 | static inline u16 tlan_dio_read16(u16 base_addr, u16 internal_addr) |
455 | { |
456 | outw(value: internal_addr, port: base_addr + TLAN_DIO_ADR); |
457 | return inw(port: (base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)); |
458 | |
459 | } |
460 | |
461 | |
462 | |
463 | |
464 | static inline u32 tlan_dio_read32(u16 base_addr, u16 internal_addr) |
465 | { |
466 | outw(value: internal_addr, port: base_addr + TLAN_DIO_ADR); |
467 | return inl(port: base_addr + TLAN_DIO_DATA); |
468 | |
469 | } |
470 | |
471 | |
472 | |
473 | |
474 | static inline void tlan_dio_write8(u16 base_addr, u16 internal_addr, u8 data) |
475 | { |
476 | outw(value: internal_addr, port: base_addr + TLAN_DIO_ADR); |
477 | outb(value: data, port: base_addr + TLAN_DIO_DATA + (internal_addr & 0x3)); |
478 | |
479 | } |
480 | |
481 | |
482 | |
483 | |
484 | static inline void tlan_dio_write16(u16 base_addr, u16 internal_addr, u16 data) |
485 | { |
486 | outw(value: internal_addr, port: base_addr + TLAN_DIO_ADR); |
487 | outw(value: data, port: base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); |
488 | |
489 | } |
490 | |
491 | |
492 | |
493 | |
494 | static inline void tlan_dio_write32(u16 base_addr, u16 internal_addr, u32 data) |
495 | { |
496 | outw(value: internal_addr, port: base_addr + TLAN_DIO_ADR); |
497 | outl(value: data, port: base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); |
498 | |
499 | } |
500 | |
501 | #define tlan_clear_bit(bit, port) outb_p(inb_p(port) & ~bit, port) |
502 | #define tlan_get_bit(bit, port) ((int) (inb_p(port) & bit)) |
503 | #define tlan_set_bit(bit, port) outb_p(inb_p(port) | bit, port) |
504 | |
505 | /* |
506 | * given 6 bytes, view them as 8 6-bit numbers and return the XOR of those |
507 | * the code below is about seven times as fast as the original code |
508 | * |
509 | * The original code was: |
510 | * |
511 | * u32 xor(u32 a, u32 b) { return ((a && !b ) || (! a && b )); } |
512 | * |
513 | * #define XOR8(a, b, c, d, e, f, g, h) \ |
514 | * xor(a, xor(b, xor(c, xor(d, xor(e, xor(f, xor(g, h)) ) ) ) ) ) |
515 | * #define DA(a, bit) (( (u8) a[bit/8] ) & ( (u8) (1 << bit%8)) ) |
516 | * |
517 | * hash = XOR8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), |
518 | * DA(a,30), DA(a,36), DA(a,42)); |
519 | * hash |= XOR8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), |
520 | * DA(a,31), DA(a,37), DA(a,43)) << 1; |
521 | * hash |= XOR8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), |
522 | * DA(a,32), DA(a,38), DA(a,44)) << 2; |
523 | * hash |= XOR8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), |
524 | * DA(a,33), DA(a,39), DA(a,45)) << 3; |
525 | * hash |= XOR8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), |
526 | * DA(a,34), DA(a,40), DA(a,46)) << 4; |
527 | * hash |= XOR8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), |
528 | * DA(a,35), DA(a,41), DA(a,47)) << 5; |
529 | * |
530 | */ |
531 | static inline u32 tlan_hash_func(const u8 *a) |
532 | { |
533 | u8 hash; |
534 | |
535 | hash = (a[0]^a[3]); /* & 077 */ |
536 | hash ^= ((a[0]^a[3])>>6); /* & 003 */ |
537 | hash ^= ((a[1]^a[4])<<2); /* & 074 */ |
538 | hash ^= ((a[1]^a[4])>>4); /* & 017 */ |
539 | hash ^= ((a[2]^a[5])<<4); /* & 060 */ |
540 | hash ^= ((a[2]^a[5])>>2); /* & 077 */ |
541 | |
542 | return hash & 077; |
543 | } |
544 | #endif |
545 | |