1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd..
4 * All rights reserved.
5 *
6 * ESWIN Reset Driver
7 *
8 * Authors:
9 * Yifeng Huang <huangyifeng@eswincomputing.com>
10 * Xuyang Dong <dongxuyang@eswincomputing.com>
11 */
12
13#include <linux/err.h>
14#include <linux/init.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/regmap.h>
18#include <linux/reset-controller.h>
19#include <linux/slab.h>
20#include <linux/types.h>
21
22#include <dt-bindings/reset/eswin,eic7700-reset.h>
23
24#define SYSCRG_CLEAR_BOOT_INFO_OFFSET 0xC
25#define CLEAR_BOOT_FLAG_BIT BIT(0)
26#define SYSCRG_RESET_OFFSET 0x100
27
28/**
29 * struct eic7700_reset_data - reset controller information structure
30 * @rcdev: reset controller entity
31 * @regmap: regmap handle containing the memory-mapped reset registers
32 */
33struct eic7700_reset_data {
34 struct reset_controller_dev rcdev;
35 struct regmap *regmap;
36};
37
38static const struct regmap_config eic7700_regmap_config = {
39 .reg_bits = 32,
40 .val_bits = 32,
41 .reg_stride = 4,
42 .max_register = 0x1fc,
43};
44
45struct eic7700_reg {
46 u32 reg;
47 u32 bit;
48};
49
50static inline struct eic7700_reset_data *
51to_eic7700_reset_data(struct reset_controller_dev *rcdev)
52{
53 return container_of(rcdev, struct eic7700_reset_data, rcdev);
54}
55
56#define EIC7700_RESET(id, reg, bit)[id] = \
57 { SYSCRG_RESET_OFFSET + (reg) * sizeof(u32), BIT(bit) }
58
59/* mapping table for reset ID to register offset and reset bit */
60static const struct eic7700_reg eic7700_reset[] = {
61 EIC7700_RESET(EIC7700_RESET_NOC_NSP, 0, 0),
62 EIC7700_RESET(EIC7700_RESET_NOC_CFG, 0, 1),
63 EIC7700_RESET(EIC7700_RESET_RNOC_NSP, 0, 2),
64 EIC7700_RESET(EIC7700_RESET_SNOC_TCU, 0, 3),
65 EIC7700_RESET(EIC7700_RESET_SNOC_U84, 0, 4),
66 EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_XSR, 0, 5),
67 EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_XMR, 0, 6),
68 EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_PR, 0, 7),
69 EIC7700_RESET(EIC7700_RESET_SNOC_NPU, 0, 8),
70 EIC7700_RESET(EIC7700_RESET_SNOC_JTAG, 0, 9),
71 EIC7700_RESET(EIC7700_RESET_SNOC_DSP, 0, 10),
72 EIC7700_RESET(EIC7700_RESET_SNOC_DDRC1_P2, 0, 11),
73 EIC7700_RESET(EIC7700_RESET_SNOC_DDRC1_P1, 0, 12),
74 EIC7700_RESET(EIC7700_RESET_SNOC_DDRC0_P2, 0, 13),
75 EIC7700_RESET(EIC7700_RESET_SNOC_DDRC0_P1, 0, 14),
76 EIC7700_RESET(EIC7700_RESET_SNOC_D2D, 0, 15),
77 EIC7700_RESET(EIC7700_RESET_SNOC_AON, 0, 16),
78 EIC7700_RESET(EIC7700_RESET_GPU_AXI, 1, 0),
79 EIC7700_RESET(EIC7700_RESET_GPU_CFG, 1, 1),
80 EIC7700_RESET(EIC7700_RESET_GPU_GRAY, 1, 2),
81 EIC7700_RESET(EIC7700_RESET_GPU_JONES, 1, 3),
82 EIC7700_RESET(EIC7700_RESET_GPU_SPU, 1, 4),
83 EIC7700_RESET(EIC7700_RESET_DSP_AXI, 2, 0),
84 EIC7700_RESET(EIC7700_RESET_DSP_CFG, 2, 1),
85 EIC7700_RESET(EIC7700_RESET_DSP_DIV4, 2, 2),
86 EIC7700_RESET(EIC7700_RESET_DSP_DIV0, 2, 4),
87 EIC7700_RESET(EIC7700_RESET_DSP_DIV1, 2, 5),
88 EIC7700_RESET(EIC7700_RESET_DSP_DIV2, 2, 6),
89 EIC7700_RESET(EIC7700_RESET_DSP_DIV3, 2, 7),
90 EIC7700_RESET(EIC7700_RESET_D2D_AXI, 3, 0),
91 EIC7700_RESET(EIC7700_RESET_D2D_CFG, 3, 1),
92 EIC7700_RESET(EIC7700_RESET_D2D_PRST, 3, 2),
93 EIC7700_RESET(EIC7700_RESET_D2D_RAW_PCS, 3, 4),
94 EIC7700_RESET(EIC7700_RESET_D2D_RX, 3, 5),
95 EIC7700_RESET(EIC7700_RESET_D2D_TX, 3, 6),
96 EIC7700_RESET(EIC7700_RESET_D2D_CORE, 3, 7),
97 EIC7700_RESET(EIC7700_RESET_DDR1_ARST, 4, 0),
98 EIC7700_RESET(EIC7700_RESET_DDR1_TRACE, 4, 6),
99 EIC7700_RESET(EIC7700_RESET_DDR0_ARST, 4, 16),
100 EIC7700_RESET(EIC7700_RESET_DDR_CFG, 4, 21),
101 EIC7700_RESET(EIC7700_RESET_DDR0_TRACE, 4, 22),
102 EIC7700_RESET(EIC7700_RESET_DDR_CORE, 4, 23),
103 EIC7700_RESET(EIC7700_RESET_DDR_PRST, 4, 26),
104 EIC7700_RESET(EIC7700_RESET_TCU_AXI, 5, 0),
105 EIC7700_RESET(EIC7700_RESET_TCU_CFG, 5, 1),
106 EIC7700_RESET(EIC7700_RESET_TCU_TBU0, 5, 4),
107 EIC7700_RESET(EIC7700_RESET_TCU_TBU1, 5, 5),
108 EIC7700_RESET(EIC7700_RESET_TCU_TBU2, 5, 6),
109 EIC7700_RESET(EIC7700_RESET_TCU_TBU3, 5, 7),
110 EIC7700_RESET(EIC7700_RESET_TCU_TBU4, 5, 8),
111 EIC7700_RESET(EIC7700_RESET_TCU_TBU5, 5, 9),
112 EIC7700_RESET(EIC7700_RESET_TCU_TBU6, 5, 10),
113 EIC7700_RESET(EIC7700_RESET_TCU_TBU7, 5, 11),
114 EIC7700_RESET(EIC7700_RESET_TCU_TBU8, 5, 12),
115 EIC7700_RESET(EIC7700_RESET_TCU_TBU9, 5, 13),
116 EIC7700_RESET(EIC7700_RESET_TCU_TBU10, 5, 14),
117 EIC7700_RESET(EIC7700_RESET_TCU_TBU11, 5, 15),
118 EIC7700_RESET(EIC7700_RESET_TCU_TBU12, 5, 16),
119 EIC7700_RESET(EIC7700_RESET_TCU_TBU13, 5, 17),
120 EIC7700_RESET(EIC7700_RESET_TCU_TBU14, 5, 18),
121 EIC7700_RESET(EIC7700_RESET_TCU_TBU15, 5, 19),
122 EIC7700_RESET(EIC7700_RESET_TCU_TBU16, 5, 20),
123 EIC7700_RESET(EIC7700_RESET_NPU_AXI, 6, 0),
124 EIC7700_RESET(EIC7700_RESET_NPU_CFG, 6, 1),
125 EIC7700_RESET(EIC7700_RESET_NPU_CORE, 6, 2),
126 EIC7700_RESET(EIC7700_RESET_NPU_E31CORE, 6, 3),
127 EIC7700_RESET(EIC7700_RESET_NPU_E31BUS, 6, 4),
128 EIC7700_RESET(EIC7700_RESET_NPU_E31DBG, 6, 5),
129 EIC7700_RESET(EIC7700_RESET_NPU_LLC, 6, 6),
130 EIC7700_RESET(EIC7700_RESET_HSP_AXI, 7, 0),
131 EIC7700_RESET(EIC7700_RESET_HSP_CFG, 7, 1),
132 EIC7700_RESET(EIC7700_RESET_HSP_POR, 7, 2),
133 EIC7700_RESET(EIC7700_RESET_MSHC0_PHY, 7, 3),
134 EIC7700_RESET(EIC7700_RESET_MSHC1_PHY, 7, 4),
135 EIC7700_RESET(EIC7700_RESET_MSHC2_PHY, 7, 5),
136 EIC7700_RESET(EIC7700_RESET_MSHC0_TXRX, 7, 6),
137 EIC7700_RESET(EIC7700_RESET_MSHC1_TXRX, 7, 7),
138 EIC7700_RESET(EIC7700_RESET_MSHC2_TXRX, 7, 8),
139 EIC7700_RESET(EIC7700_RESET_SATA_ASIC0, 7, 9),
140 EIC7700_RESET(EIC7700_RESET_SATA_OOB, 7, 10),
141 EIC7700_RESET(EIC7700_RESET_SATA_PMALIVE, 7, 11),
142 EIC7700_RESET(EIC7700_RESET_SATA_RBC, 7, 12),
143 EIC7700_RESET(EIC7700_RESET_DMA0, 7, 13),
144 EIC7700_RESET(EIC7700_RESET_HSP_DMA, 7, 14),
145 EIC7700_RESET(EIC7700_RESET_USB0_VAUX, 7, 15),
146 EIC7700_RESET(EIC7700_RESET_USB1_VAUX, 7, 16),
147 EIC7700_RESET(EIC7700_RESET_HSP_SD1_PRST, 7, 17),
148 EIC7700_RESET(EIC7700_RESET_HSP_SD0_PRST, 7, 18),
149 EIC7700_RESET(EIC7700_RESET_HSP_EMMC_PRST, 7, 19),
150 EIC7700_RESET(EIC7700_RESET_HSP_DMA_PRST, 7, 20),
151 EIC7700_RESET(EIC7700_RESET_HSP_SD1_ARST, 7, 21),
152 EIC7700_RESET(EIC7700_RESET_HSP_SD0_ARST, 7, 22),
153 EIC7700_RESET(EIC7700_RESET_HSP_EMMC_ARST, 7, 23),
154 EIC7700_RESET(EIC7700_RESET_HSP_DMA_ARST, 7, 24),
155 EIC7700_RESET(EIC7700_RESET_HSP_ETH1_ARST, 7, 25),
156 EIC7700_RESET(EIC7700_RESET_HSP_ETH0_ARST, 7, 26),
157 EIC7700_RESET(EIC7700_RESET_SATA_ARST, 7, 27),
158 EIC7700_RESET(EIC7700_RESET_PCIE_CFG, 8, 0),
159 EIC7700_RESET(EIC7700_RESET_PCIE_POWEUP, 8, 1),
160 EIC7700_RESET(EIC7700_RESET_PCIE_PERST, 8, 2),
161 EIC7700_RESET(EIC7700_RESET_I2C0, 9, 0),
162 EIC7700_RESET(EIC7700_RESET_I2C1, 9, 1),
163 EIC7700_RESET(EIC7700_RESET_I2C2, 9, 2),
164 EIC7700_RESET(EIC7700_RESET_I2C3, 9, 3),
165 EIC7700_RESET(EIC7700_RESET_I2C4, 9, 4),
166 EIC7700_RESET(EIC7700_RESET_I2C5, 9, 5),
167 EIC7700_RESET(EIC7700_RESET_I2C6, 9, 6),
168 EIC7700_RESET(EIC7700_RESET_I2C7, 9, 7),
169 EIC7700_RESET(EIC7700_RESET_I2C8, 9, 8),
170 EIC7700_RESET(EIC7700_RESET_I2C9, 9, 9),
171 EIC7700_RESET(EIC7700_RESET_FAN, 10, 0),
172 EIC7700_RESET(EIC7700_RESET_PVT0, 11, 0),
173 EIC7700_RESET(EIC7700_RESET_PVT1, 11, 1),
174 EIC7700_RESET(EIC7700_RESET_MBOX0, 12, 0),
175 EIC7700_RESET(EIC7700_RESET_MBOX1, 12, 1),
176 EIC7700_RESET(EIC7700_RESET_MBOX2, 12, 2),
177 EIC7700_RESET(EIC7700_RESET_MBOX3, 12, 3),
178 EIC7700_RESET(EIC7700_RESET_MBOX4, 12, 4),
179 EIC7700_RESET(EIC7700_RESET_MBOX5, 12, 5),
180 EIC7700_RESET(EIC7700_RESET_MBOX6, 12, 6),
181 EIC7700_RESET(EIC7700_RESET_MBOX7, 12, 7),
182 EIC7700_RESET(EIC7700_RESET_MBOX8, 12, 8),
183 EIC7700_RESET(EIC7700_RESET_MBOX9, 12, 9),
184 EIC7700_RESET(EIC7700_RESET_MBOX10, 12, 10),
185 EIC7700_RESET(EIC7700_RESET_MBOX11, 12, 11),
186 EIC7700_RESET(EIC7700_RESET_MBOX12, 12, 12),
187 EIC7700_RESET(EIC7700_RESET_MBOX13, 12, 13),
188 EIC7700_RESET(EIC7700_RESET_MBOX14, 12, 14),
189 EIC7700_RESET(EIC7700_RESET_MBOX15, 12, 15),
190 EIC7700_RESET(EIC7700_RESET_UART0, 13, 0),
191 EIC7700_RESET(EIC7700_RESET_UART1, 13, 1),
192 EIC7700_RESET(EIC7700_RESET_UART2, 13, 2),
193 EIC7700_RESET(EIC7700_RESET_UART3, 13, 3),
194 EIC7700_RESET(EIC7700_RESET_UART4, 13, 4),
195 EIC7700_RESET(EIC7700_RESET_GPIO0, 14, 0),
196 EIC7700_RESET(EIC7700_RESET_GPIO1, 14, 1),
197 EIC7700_RESET(EIC7700_RESET_TIMER, 15, 0),
198 EIC7700_RESET(EIC7700_RESET_SSI0, 16, 0),
199 EIC7700_RESET(EIC7700_RESET_SSI1, 16, 1),
200 EIC7700_RESET(EIC7700_RESET_WDT0, 17, 0),
201 EIC7700_RESET(EIC7700_RESET_WDT1, 17, 1),
202 EIC7700_RESET(EIC7700_RESET_WDT2, 17, 2),
203 EIC7700_RESET(EIC7700_RESET_WDT3, 17, 3),
204 EIC7700_RESET(EIC7700_RESET_LSP_CFG, 18, 0),
205 EIC7700_RESET(EIC7700_RESET_U84_CORE0, 19, 0),
206 EIC7700_RESET(EIC7700_RESET_U84_CORE1, 19, 1),
207 EIC7700_RESET(EIC7700_RESET_U84_CORE2, 19, 2),
208 EIC7700_RESET(EIC7700_RESET_U84_CORE3, 19, 3),
209 EIC7700_RESET(EIC7700_RESET_U84_BUS, 19, 4),
210 EIC7700_RESET(EIC7700_RESET_U84_DBG, 19, 5),
211 EIC7700_RESET(EIC7700_RESET_U84_TRACECOM, 19, 6),
212 EIC7700_RESET(EIC7700_RESET_U84_TRACE0, 19, 8),
213 EIC7700_RESET(EIC7700_RESET_U84_TRACE1, 19, 9),
214 EIC7700_RESET(EIC7700_RESET_U84_TRACE2, 19, 10),
215 EIC7700_RESET(EIC7700_RESET_U84_TRACE3, 19, 11),
216 EIC7700_RESET(EIC7700_RESET_SCPU_CORE, 20, 0),
217 EIC7700_RESET(EIC7700_RESET_SCPU_BUS, 20, 1),
218 EIC7700_RESET(EIC7700_RESET_SCPU_DBG, 20, 2),
219 EIC7700_RESET(EIC7700_RESET_LPCPU_CORE, 21, 0),
220 EIC7700_RESET(EIC7700_RESET_LPCPU_BUS, 21, 1),
221 EIC7700_RESET(EIC7700_RESET_LPCPU_DBG, 21, 2),
222 EIC7700_RESET(EIC7700_RESET_VC_CFG, 22, 0),
223 EIC7700_RESET(EIC7700_RESET_VC_AXI, 22, 1),
224 EIC7700_RESET(EIC7700_RESET_VC_MONCFG, 22, 2),
225 EIC7700_RESET(EIC7700_RESET_JD_CFG, 23, 0),
226 EIC7700_RESET(EIC7700_RESET_JD_AXI, 23, 1),
227 EIC7700_RESET(EIC7700_RESET_JE_CFG, 24, 0),
228 EIC7700_RESET(EIC7700_RESET_JE_AXI, 24, 1),
229 EIC7700_RESET(EIC7700_RESET_VD_CFG, 25, 0),
230 EIC7700_RESET(EIC7700_RESET_VD_AXI, 25, 1),
231 EIC7700_RESET(EIC7700_RESET_VE_AXI, 26, 0),
232 EIC7700_RESET(EIC7700_RESET_VE_CFG, 26, 1),
233 EIC7700_RESET(EIC7700_RESET_G2D_CORE, 27, 0),
234 EIC7700_RESET(EIC7700_RESET_G2D_CFG, 27, 1),
235 EIC7700_RESET(EIC7700_RESET_G2D_AXI, 27, 2),
236 EIC7700_RESET(EIC7700_RESET_VI_AXI, 28, 0),
237 EIC7700_RESET(EIC7700_RESET_VI_CFG, 28, 1),
238 EIC7700_RESET(EIC7700_RESET_VI_DWE, 28, 2),
239 EIC7700_RESET(EIC7700_RESET_DVP, 29, 0),
240 EIC7700_RESET(EIC7700_RESET_ISP0, 30, 0),
241 EIC7700_RESET(EIC7700_RESET_ISP1, 31, 0),
242 EIC7700_RESET(EIC7700_RESET_SHUTTR0, 32, 0),
243 EIC7700_RESET(EIC7700_RESET_SHUTTR1, 32, 1),
244 EIC7700_RESET(EIC7700_RESET_SHUTTR2, 32, 2),
245 EIC7700_RESET(EIC7700_RESET_SHUTTR3, 32, 3),
246 EIC7700_RESET(EIC7700_RESET_SHUTTR4, 32, 4),
247 EIC7700_RESET(EIC7700_RESET_SHUTTR5, 32, 5),
248 EIC7700_RESET(EIC7700_RESET_VO_MIPI, 33, 0),
249 EIC7700_RESET(EIC7700_RESET_VO_PRST, 33, 1),
250 EIC7700_RESET(EIC7700_RESET_VO_HDMI_PRST, 33, 3),
251 EIC7700_RESET(EIC7700_RESET_VO_HDMI_PHY, 33, 4),
252 EIC7700_RESET(EIC7700_RESET_VO_HDMI, 33, 5),
253 EIC7700_RESET(EIC7700_RESET_VO_I2S, 34, 0),
254 EIC7700_RESET(EIC7700_RESET_VO_I2S_PRST, 34, 1),
255 EIC7700_RESET(EIC7700_RESET_VO_AXI, 35, 0),
256 EIC7700_RESET(EIC7700_RESET_VO_CFG, 35, 1),
257 EIC7700_RESET(EIC7700_RESET_VO_DC, 35, 2),
258 EIC7700_RESET(EIC7700_RESET_VO_DC_PRST, 35, 3),
259 EIC7700_RESET(EIC7700_RESET_BOOTSPI_HRST, 36, 0),
260 EIC7700_RESET(EIC7700_RESET_BOOTSPI, 36, 1),
261 EIC7700_RESET(EIC7700_RESET_ANO1, 37, 0),
262 EIC7700_RESET(EIC7700_RESET_ANO0, 38, 0),
263 EIC7700_RESET(EIC7700_RESET_DMA1_ARST, 39, 0),
264 EIC7700_RESET(EIC7700_RESET_DMA1_HRST, 39, 1),
265 EIC7700_RESET(EIC7700_RESET_FPRT, 40, 0),
266 EIC7700_RESET(EIC7700_RESET_HBLOCK, 41, 0),
267 EIC7700_RESET(EIC7700_RESET_SECSR, 42, 0),
268 EIC7700_RESET(EIC7700_RESET_OTP, 43, 0),
269 EIC7700_RESET(EIC7700_RESET_PKA, 44, 0),
270 EIC7700_RESET(EIC7700_RESET_SPACC, 45, 0),
271 EIC7700_RESET(EIC7700_RESET_TRNG, 46, 0),
272 EIC7700_RESET(EIC7700_RESET_TIMER0_0, 48, 0),
273 EIC7700_RESET(EIC7700_RESET_TIMER0_1, 48, 1),
274 EIC7700_RESET(EIC7700_RESET_TIMER0_2, 48, 2),
275 EIC7700_RESET(EIC7700_RESET_TIMER0_3, 48, 3),
276 EIC7700_RESET(EIC7700_RESET_TIMER0_4, 48, 4),
277 EIC7700_RESET(EIC7700_RESET_TIMER0_5, 48, 5),
278 EIC7700_RESET(EIC7700_RESET_TIMER0_6, 48, 6),
279 EIC7700_RESET(EIC7700_RESET_TIMER0_7, 48, 7),
280 EIC7700_RESET(EIC7700_RESET_TIMER0_N, 48, 8),
281 EIC7700_RESET(EIC7700_RESET_TIMER1_0, 49, 0),
282 EIC7700_RESET(EIC7700_RESET_TIMER1_1, 49, 1),
283 EIC7700_RESET(EIC7700_RESET_TIMER1_2, 49, 2),
284 EIC7700_RESET(EIC7700_RESET_TIMER1_3, 49, 3),
285 EIC7700_RESET(EIC7700_RESET_TIMER1_4, 49, 4),
286 EIC7700_RESET(EIC7700_RESET_TIMER1_5, 49, 5),
287 EIC7700_RESET(EIC7700_RESET_TIMER1_6, 49, 6),
288 EIC7700_RESET(EIC7700_RESET_TIMER1_7, 49, 7),
289 EIC7700_RESET(EIC7700_RESET_TIMER1_N, 49, 8),
290 EIC7700_RESET(EIC7700_RESET_TIMER2_0, 50, 0),
291 EIC7700_RESET(EIC7700_RESET_TIMER2_1, 50, 1),
292 EIC7700_RESET(EIC7700_RESET_TIMER2_2, 50, 2),
293 EIC7700_RESET(EIC7700_RESET_TIMER2_3, 50, 3),
294 EIC7700_RESET(EIC7700_RESET_TIMER2_4, 50, 4),
295 EIC7700_RESET(EIC7700_RESET_TIMER2_5, 50, 5),
296 EIC7700_RESET(EIC7700_RESET_TIMER2_6, 50, 6),
297 EIC7700_RESET(EIC7700_RESET_TIMER2_7, 50, 7),
298 EIC7700_RESET(EIC7700_RESET_TIMER2_N, 50, 8),
299 EIC7700_RESET(EIC7700_RESET_TIMER3_0, 51, 0),
300 EIC7700_RESET(EIC7700_RESET_TIMER3_1, 51, 1),
301 EIC7700_RESET(EIC7700_RESET_TIMER3_2, 51, 2),
302 EIC7700_RESET(EIC7700_RESET_TIMER3_3, 51, 3),
303 EIC7700_RESET(EIC7700_RESET_TIMER3_4, 51, 4),
304 EIC7700_RESET(EIC7700_RESET_TIMER3_5, 51, 5),
305 EIC7700_RESET(EIC7700_RESET_TIMER3_6, 51, 6),
306 EIC7700_RESET(EIC7700_RESET_TIMER3_7, 51, 7),
307 EIC7700_RESET(EIC7700_RESET_TIMER3_N, 51, 8),
308 EIC7700_RESET(EIC7700_RESET_RTC, 52, 0),
309 EIC7700_RESET(EIC7700_RESET_MNOC_SNOC_NSP, 53, 0),
310 EIC7700_RESET(EIC7700_RESET_MNOC_VC, 53, 1),
311 EIC7700_RESET(EIC7700_RESET_MNOC_CFG, 53, 2),
312 EIC7700_RESET(EIC7700_RESET_MNOC_HSP, 53, 3),
313 EIC7700_RESET(EIC7700_RESET_MNOC_GPU, 53, 4),
314 EIC7700_RESET(EIC7700_RESET_MNOC_DDRC1_P3, 53, 5),
315 EIC7700_RESET(EIC7700_RESET_MNOC_DDRC0_P3, 53, 6),
316 EIC7700_RESET(EIC7700_RESET_RNOC_VO, 54, 0),
317 EIC7700_RESET(EIC7700_RESET_RNOC_VI, 54, 1),
318 EIC7700_RESET(EIC7700_RESET_RNOC_SNOC_NSP, 54, 2),
319 EIC7700_RESET(EIC7700_RESET_RNOC_CFG, 54, 3),
320 EIC7700_RESET(EIC7700_RESET_MNOC_DDRC1_P4, 54, 4),
321 EIC7700_RESET(EIC7700_RESET_MNOC_DDRC0_P4, 54, 5),
322 EIC7700_RESET(EIC7700_RESET_CNOC_VO_CFG, 55, 0),
323 EIC7700_RESET(EIC7700_RESET_CNOC_VI_CFG, 55, 1),
324 EIC7700_RESET(EIC7700_RESET_CNOC_VC_CFG, 55, 2),
325 EIC7700_RESET(EIC7700_RESET_CNOC_TCU_CFG, 55, 3),
326 EIC7700_RESET(EIC7700_RESET_CNOC_PCIE_CFG, 55, 4),
327 EIC7700_RESET(EIC7700_RESET_CNOC_NPU_CFG, 55, 5),
328 EIC7700_RESET(EIC7700_RESET_CNOC_LSP_CFG, 55, 6),
329 EIC7700_RESET(EIC7700_RESET_CNOC_HSP_CFG, 55, 7),
330 EIC7700_RESET(EIC7700_RESET_CNOC_GPU_CFG, 55, 8),
331 EIC7700_RESET(EIC7700_RESET_CNOC_DSPT_CFG, 55, 9),
332 EIC7700_RESET(EIC7700_RESET_CNOC_DDRT1_CFG, 55, 10),
333 EIC7700_RESET(EIC7700_RESET_CNOC_DDRT0_CFG, 55, 11),
334 EIC7700_RESET(EIC7700_RESET_CNOC_D2D_CFG, 55, 12),
335 EIC7700_RESET(EIC7700_RESET_CNOC_CFG, 55, 13),
336 EIC7700_RESET(EIC7700_RESET_CNOC_CLMM_CFG, 55, 14),
337 EIC7700_RESET(EIC7700_RESET_CNOC_AON_CFG, 55, 15),
338 EIC7700_RESET(EIC7700_RESET_LNOC_CFG, 56, 0),
339 EIC7700_RESET(EIC7700_RESET_LNOC_NPU_LLC, 56, 1),
340 EIC7700_RESET(EIC7700_RESET_LNOC_DDRC1_P0, 56, 2),
341 EIC7700_RESET(EIC7700_RESET_LNOC_DDRC0_P0, 56, 3),
342};
343
344static int eic7700_reset_assert(struct reset_controller_dev *rcdev,
345 unsigned long id)
346{
347 struct eic7700_reset_data *data = to_eic7700_reset_data(rcdev);
348
349 return regmap_clear_bits(map: data->regmap, reg: eic7700_reset[id].reg,
350 bits: eic7700_reset[id].bit);
351}
352
353static int eic7700_reset_deassert(struct reset_controller_dev *rcdev,
354 unsigned long id)
355{
356 struct eic7700_reset_data *data = to_eic7700_reset_data(rcdev);
357
358 return regmap_set_bits(map: data->regmap, reg: eic7700_reset[id].reg,
359 bits: eic7700_reset[id].bit);
360}
361
362static int eic7700_reset_reset(struct reset_controller_dev *rcdev,
363 unsigned long id)
364{
365 int ret;
366
367 ret = eic7700_reset_assert(rcdev, id);
368 if (ret)
369 return ret;
370
371 usleep_range(min: 10, max: 15);
372
373 return eic7700_reset_deassert(rcdev, id);
374}
375
376static const struct reset_control_ops eic7700_reset_ops = {
377 .reset = eic7700_reset_reset,
378 .assert = eic7700_reset_assert,
379 .deassert = eic7700_reset_deassert,
380};
381
382static const struct of_device_id eic7700_reset_dt_ids[] = {
383 { .compatible = "eswin,eic7700-reset", },
384 { /* sentinel */ }
385};
386
387static int eic7700_reset_probe(struct platform_device *pdev)
388{
389 struct eic7700_reset_data *data;
390 struct device *dev = &pdev->dev;
391 void __iomem *base;
392
393 data = devm_kzalloc(dev, size: sizeof(*data), GFP_KERNEL);
394 if (!data)
395 return -ENOMEM;
396
397 base = devm_platform_ioremap_resource(pdev, index: 0);
398 if (IS_ERR(ptr: base))
399 return PTR_ERR(ptr: base);
400
401 data->regmap = devm_regmap_init_mmio(dev, base, &eic7700_regmap_config);
402 if (IS_ERR(ptr: data->regmap))
403 return dev_err_probe(dev, err: PTR_ERR(ptr: data->regmap),
404 fmt: "failed to get regmap!\n");
405
406 data->rcdev.owner = THIS_MODULE;
407 data->rcdev.ops = &eic7700_reset_ops;
408 data->rcdev.of_node = dev->of_node;
409 data->rcdev.of_reset_n_cells = 1;
410 data->rcdev.dev = dev;
411 data->rcdev.nr_resets = ARRAY_SIZE(eic7700_reset);
412
413 /* clear boot flag so u84 and scpu could be reseted by software */
414 regmap_set_bits(map: data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET,
415 CLEAR_BOOT_FLAG_BIT);
416 msleep(msecs: 50);
417
418 return devm_reset_controller_register(dev, rcdev: &data->rcdev);
419}
420
421static struct platform_driver eic7700_reset_driver = {
422 .probe = eic7700_reset_probe,
423 .driver = {
424 .name = "eic7700-reset",
425 .of_match_table = eic7700_reset_dt_ids,
426 },
427};
428
429builtin_platform_driver(eic7700_reset_driver);
430

source code of linux/drivers/reset/reset-eic7700.c