1// SPDX-License-Identifier: GPL-2.0-only
2
3/* SpacemiT reset controller driver */
4
5#include <linux/auxiliary_bus.h>
6#include <linux/container_of.h>
7#include <linux/device.h>
8#include <linux/module.h>
9#include <linux/regmap.h>
10#include <linux/reset-controller.h>
11#include <linux/types.h>
12
13#include <soc/spacemit/k1-syscon.h>
14#include <dt-bindings/clock/spacemit,k1-syscon.h>
15
16struct ccu_reset_data {
17 u32 offset;
18 u32 assert_mask;
19 u32 deassert_mask;
20};
21
22struct ccu_reset_controller_data {
23 const struct ccu_reset_data *reset_data; /* array */
24 size_t count;
25};
26
27struct ccu_reset_controller {
28 struct reset_controller_dev rcdev;
29 const struct ccu_reset_controller_data *data;
30 struct regmap *regmap;
31};
32
33#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \
34 { \
35 .offset = (_offset), \
36 .assert_mask = (_assert_mask), \
37 .deassert_mask = (_deassert_mask), \
38 }
39
40static const struct ccu_reset_data k1_mpmu_resets[] = {
41 [RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0),
42};
43
44static const struct ccu_reset_controller_data k1_mpmu_reset_data = {
45 .reset_data = k1_mpmu_resets,
46 .count = ARRAY_SIZE(k1_mpmu_resets),
47};
48
49static const struct ccu_reset_data k1_apbc_resets[] = {
50 [RESET_UART0] = RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0),
51 [RESET_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0),
52 [RESET_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0),
53 [RESET_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)),
54 [RESET_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)),
55 [RESET_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)),
56 [RESET_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)),
57 [RESET_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)),
58 [RESET_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)),
59 [RESET_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)),
60 [RESET_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)),
61 [RESET_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)),
62 [RESET_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)),
63 [RESET_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)),
64 [RESET_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)),
65 [RESET_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)),
66 [RESET_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)),
67 [RESET_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)),
68 [RESET_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)),
69 [RESET_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)),
70 [RESET_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)),
71 [RESET_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)),
72 [RESET_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)),
73 [RESET_SSP3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0),
74 [RESET_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0),
75 [RESET_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0),
76 [RESET_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0),
77 [RESET_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0),
78 [RESET_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0),
79 [RESET_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0),
80 [RESET_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0),
81 [RESET_SSPA0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0),
82 [RESET_SSPA1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0),
83 [RESET_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0),
84 [RESET_IR] = RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0),
85 [RESET_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0),
86 [RESET_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0),
87 [RESET_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0),
88 [RESET_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0),
89 [RESET_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0),
90 [RESET_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0),
91 [RESET_TWSI7] = RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0),
92 [RESET_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0),
93 [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0),
94 [RESET_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0),
95 [RESET_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0),
96 [RESET_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0),
97 [RESET_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0),
98 [RESET_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0),
99 [RESET_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0),
100 [RESET_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0),
101};
102
103static const struct ccu_reset_controller_data k1_apbc_reset_data = {
104 .reset_data = k1_apbc_resets,
105 .count = ARRAY_SIZE(k1_apbc_resets),
106};
107
108static const struct ccu_reset_data k1_apmu_resets[] = {
109 [RESET_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)),
110 [RESET_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)),
111 [RESET_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)),
112 [RESET_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
113 [RESET_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
114 [RESET_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
115 [RESET_USBP1_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)),
116 [RESET_USB_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)),
117 [RESET_USB30_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)),
118 [RESET_USB30_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)),
119 [RESET_USB30_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)),
120 [RESET_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
121 [RESET_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
122 [RESET_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
123 [RESET_AES] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)),
124 [RESET_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)),
125 [RESET_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)),
126 [RESET_EMMC] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)),
127 [RESET_EMMC_X] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)),
128 [RESET_AUDIO_SYS] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(0)),
129 [RESET_AUDIO_MCU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(2)),
130 [RESET_AUDIO_APMU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(3)),
131 [RESET_HDMI] = RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)),
132 [RESET_PCIE0_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(3)),
133 [RESET_PCIE0_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(4)),
134 [RESET_PCIE0_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(5)),
135 [RESET_PCIE0_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), 0),
136 [RESET_PCIE1_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(3)),
137 [RESET_PCIE1_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(4)),
138 [RESET_PCIE1_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(5)),
139 [RESET_PCIE1_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), 0),
140 [RESET_PCIE2_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(3)),
141 [RESET_PCIE2_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(4)),
142 [RESET_PCIE2_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(5)),
143 [RESET_PCIE2_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), 0),
144 [RESET_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
145 [RESET_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
146 [RESET_JPG] = RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)),
147 [RESET_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)),
148 [RESET_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)),
149 [RESET_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)),
150 [RESET_ISP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)),
151 [RESET_ISP_CPP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)),
152 [RESET_ISP_BUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)),
153 [RESET_ISP_CI] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)),
154 [RESET_DPU_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)),
155 [RESET_DPU_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)),
156 [RESET_DPU_HCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)),
157 [RESET_DPU_SPIBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)),
158 [RESET_DPU_SPI_HBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)),
159 [RESET_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)),
160 [RESET_MIPI] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)),
161 [RESET_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)),
162};
163
164static const struct ccu_reset_controller_data k1_apmu_reset_data = {
165 .reset_data = k1_apmu_resets,
166 .count = ARRAY_SIZE(k1_apmu_resets),
167};
168
169static const struct ccu_reset_data k1_rcpu_resets[] = {
170 [RESET_RCPU_SSP0] = RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)),
171 [RESET_RCPU_I2C0] = RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)),
172 [RESET_RCPU_UART1] = RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)),
173 [RESET_RCPU_IR] = RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)),
174 [RESET_RCPU_CAN] = RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)),
175 [RESET_RCPU_UART0] = RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)),
176 [RESET_RCPU_HDMI_AUDIO] = RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)),
177};
178
179static const struct ccu_reset_controller_data k1_rcpu_reset_data = {
180 .reset_data = k1_rcpu_resets,
181 .count = ARRAY_SIZE(k1_rcpu_resets),
182};
183
184static const struct ccu_reset_data k1_rcpu2_resets[] = {
185 [RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
186 [RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
187 [RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
188 [RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
189 [RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
190 [RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
191 [RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
192 [RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
193 [RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
194 [RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
195};
196
197static const struct ccu_reset_controller_data k1_rcpu2_reset_data = {
198 .reset_data = k1_rcpu2_resets,
199 .count = ARRAY_SIZE(k1_rcpu2_resets),
200};
201
202static const struct ccu_reset_data k1_apbc2_resets[] = {
203 [RESET_APBC2_UART1] = RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0),
204 [RESET_APBC2_SSP2] = RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0),
205 [RESET_APBC2_TWSI3] = RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0),
206 [RESET_APBC2_RTC] = RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0),
207 [RESET_APBC2_TIMERS0] = RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), 0),
208 [RESET_APBC2_KPC] = RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), 0),
209 [RESET_APBC2_GPIO] = RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0),
210};
211
212static const struct ccu_reset_controller_data k1_apbc2_reset_data = {
213 .reset_data = k1_apbc2_resets,
214 .count = ARRAY_SIZE(k1_apbc2_resets),
215};
216
217static int spacemit_reset_update(struct reset_controller_dev *rcdev,
218 unsigned long id, bool assert)
219{
220 struct ccu_reset_controller *controller;
221 const struct ccu_reset_data *data;
222 u32 mask;
223 u32 val;
224
225 controller = container_of(rcdev, struct ccu_reset_controller, rcdev);
226 data = &controller->data->reset_data[id];
227 mask = data->assert_mask | data->deassert_mask;
228 val = assert ? data->assert_mask : data->deassert_mask;
229
230 return regmap_update_bits(map: controller->regmap, reg: data->offset, mask, val);
231}
232
233static int spacemit_reset_assert(struct reset_controller_dev *rcdev,
234 unsigned long id)
235{
236 return spacemit_reset_update(rcdev, id, assert: true);
237}
238
239static int spacemit_reset_deassert(struct reset_controller_dev *rcdev,
240 unsigned long id)
241{
242 return spacemit_reset_update(rcdev, id, assert: false);
243}
244
245static const struct reset_control_ops spacemit_reset_control_ops = {
246 .assert = spacemit_reset_assert,
247 .deassert = spacemit_reset_deassert,
248};
249
250static int spacemit_reset_controller_register(struct device *dev,
251 struct ccu_reset_controller *controller)
252{
253 struct reset_controller_dev *rcdev = &controller->rcdev;
254
255 rcdev->ops = &spacemit_reset_control_ops;
256 rcdev->owner = THIS_MODULE;
257 rcdev->of_node = dev->of_node;
258 rcdev->nr_resets = controller->data->count;
259
260 return devm_reset_controller_register(dev, rcdev: &controller->rcdev);
261}
262
263static int spacemit_reset_probe(struct auxiliary_device *adev,
264 const struct auxiliary_device_id *id)
265{
266 struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev);
267 struct ccu_reset_controller *controller;
268 struct device *dev = &adev->dev;
269
270 controller = devm_kzalloc(dev, size: sizeof(*controller), GFP_KERNEL);
271 if (!controller)
272 return -ENOMEM;
273 controller->data = (const struct ccu_reset_controller_data *)id->driver_data;
274 controller->regmap = rdev->regmap;
275
276 return spacemit_reset_controller_register(dev, controller);
277}
278
279#define K1_AUX_DEV_ID(_unit) \
280 { \
281 .name = "spacemit_ccu_k1." #_unit "-reset", \
282 .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \
283 }
284
285static const struct auxiliary_device_id spacemit_reset_ids[] = {
286 K1_AUX_DEV_ID(mpmu),
287 K1_AUX_DEV_ID(apbc),
288 K1_AUX_DEV_ID(apmu),
289 K1_AUX_DEV_ID(rcpu),
290 K1_AUX_DEV_ID(rcpu2),
291 K1_AUX_DEV_ID(apbc2),
292 { },
293};
294MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids);
295
296static struct auxiliary_driver spacemit_k1_reset_driver = {
297 .probe = spacemit_reset_probe,
298 .id_table = spacemit_reset_ids,
299};
300module_auxiliary_driver(spacemit_k1_reset_driver);
301
302MODULE_AUTHOR("Alex Elder <elder@kernel.org>");
303MODULE_DESCRIPTION("SpacemiT reset controller driver");
304MODULE_LICENSE("GPL");
305

source code of linux/drivers/reset/reset-spacemit.c