1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * ci.h - common structures, functions, and macros of the ChipIdea driver |
4 | * |
5 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. |
6 | * |
7 | * Author: David Lopo |
8 | */ |
9 | |
10 | #ifndef __DRIVERS_USB_CHIPIDEA_CI_H |
11 | #define __DRIVERS_USB_CHIPIDEA_CI_H |
12 | |
13 | #include <linux/list.h> |
14 | #include <linux/irqreturn.h> |
15 | #include <linux/usb.h> |
16 | #include <linux/usb/gadget.h> |
17 | #include <linux/usb/otg-fsm.h> |
18 | #include <linux/usb/otg.h> |
19 | #include <linux/usb/role.h> |
20 | #include <linux/ulpi/interface.h> |
21 | |
22 | /****************************************************************************** |
23 | * DEFINE |
24 | *****************************************************************************/ |
25 | #define TD_PAGE_COUNT 5 |
26 | #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */ |
27 | #define ENDPT_MAX 32 |
28 | #define CI_MAX_REQ_SIZE (4 * CI_HDRC_PAGE_SIZE) |
29 | #define CI_MAX_BUF_SIZE (TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE) |
30 | |
31 | /****************************************************************************** |
32 | * REGISTERS |
33 | *****************************************************************************/ |
34 | /* Identification Registers */ |
35 | #define ID_ID 0x0 |
36 | #define ID_HWGENERAL 0x4 |
37 | #define ID_HWHOST 0x8 |
38 | #define ID_HWDEVICE 0xc |
39 | #define ID_HWTXBUF 0x10 |
40 | #define ID_HWRXBUF 0x14 |
41 | #define ID_SBUSCFG 0x90 |
42 | |
43 | /* register indices */ |
44 | enum ci_hw_regs { |
45 | CAP_CAPLENGTH, |
46 | CAP_HCCPARAMS, |
47 | CAP_DCCPARAMS, |
48 | CAP_TESTMODE, |
49 | CAP_LAST = CAP_TESTMODE, |
50 | OP_USBCMD, |
51 | OP_USBSTS, |
52 | OP_USBINTR, |
53 | OP_FRINDEX, |
54 | OP_DEVICEADDR, |
55 | OP_ENDPTLISTADDR, |
56 | OP_TTCTRL, |
57 | OP_BURSTSIZE, |
58 | OP_ULPI_VIEWPORT, |
59 | OP_PORTSC, |
60 | OP_DEVLC, |
61 | OP_OTGSC, |
62 | OP_USBMODE, |
63 | OP_ENDPTSETUPSTAT, |
64 | OP_ENDPTPRIME, |
65 | OP_ENDPTFLUSH, |
66 | OP_ENDPTSTAT, |
67 | OP_ENDPTCOMPLETE, |
68 | OP_ENDPTCTRL, |
69 | /* endptctrl1..15 follow */ |
70 | OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2, |
71 | }; |
72 | |
73 | /****************************************************************************** |
74 | * STRUCTURES |
75 | *****************************************************************************/ |
76 | /** |
77 | * struct ci_hw_ep - endpoint representation |
78 | * @ep: endpoint structure for gadget drivers |
79 | * @dir: endpoint direction (TX/RX) |
80 | * @num: endpoint number |
81 | * @type: endpoint type |
82 | * @name: string description of the endpoint |
83 | * @qh: queue head for this endpoint |
84 | * @wedge: is the endpoint wedged |
85 | * @ci: pointer to the controller |
86 | * @lock: pointer to controller's spinlock |
87 | * @td_pool: pointer to controller's TD pool |
88 | */ |
89 | struct ci_hw_ep { |
90 | struct usb_ep ep; |
91 | u8 dir; |
92 | u8 num; |
93 | u8 type; |
94 | char name[16]; |
95 | struct { |
96 | struct list_head queue; |
97 | struct ci_hw_qh *ptr; |
98 | dma_addr_t dma; |
99 | } qh; |
100 | int wedge; |
101 | |
102 | /* global resources */ |
103 | struct ci_hdrc *ci; |
104 | spinlock_t *lock; |
105 | struct dma_pool *td_pool; |
106 | struct td_node *pending_td; |
107 | }; |
108 | |
109 | enum ci_role { |
110 | CI_ROLE_HOST = 0, |
111 | CI_ROLE_GADGET, |
112 | CI_ROLE_END, |
113 | }; |
114 | |
115 | enum ci_revision { |
116 | CI_REVISION_1X = 10, /* Revision 1.x */ |
117 | CI_REVISION_20 = 20, /* Revision 2.0 */ |
118 | CI_REVISION_21, /* Revision 2.1 */ |
119 | CI_REVISION_22, /* Revision 2.2 */ |
120 | CI_REVISION_23, /* Revision 2.3 */ |
121 | CI_REVISION_24, /* Revision 2.4 */ |
122 | CI_REVISION_25, /* Revision 2.5 */ |
123 | CI_REVISION_25_PLUS, /* Revision above than 2.5 */ |
124 | CI_REVISION_UNKNOWN = 99, /* Unknown Revision */ |
125 | }; |
126 | |
127 | /** |
128 | * struct ci_role_driver - host/gadget role driver |
129 | * @start: start this role |
130 | * @stop: stop this role |
131 | * @suspend: system suspend handler for this role |
132 | * @resume: system resume handler for this role |
133 | * @irq: irq handler for this role |
134 | * @name: role name string (host/gadget) |
135 | */ |
136 | struct ci_role_driver { |
137 | int (*start)(struct ci_hdrc *); |
138 | void (*stop)(struct ci_hdrc *); |
139 | void (*suspend)(struct ci_hdrc *ci); |
140 | void (*resume)(struct ci_hdrc *ci, bool power_lost); |
141 | irqreturn_t (*irq)(struct ci_hdrc *); |
142 | const char *name; |
143 | }; |
144 | |
145 | /** |
146 | * struct hw_bank - hardware register mapping representation |
147 | * @lpm: set if the device is LPM capable |
148 | * @phys: physical address of the controller's registers |
149 | * @abs: absolute address of the beginning of register window |
150 | * @cap: capability registers |
151 | * @op: operational registers |
152 | * @size: size of the register window |
153 | * @regmap: register lookup table |
154 | */ |
155 | struct hw_bank { |
156 | unsigned lpm; |
157 | resource_size_t phys; |
158 | void __iomem *abs; |
159 | void __iomem *cap; |
160 | void __iomem *op; |
161 | size_t size; |
162 | void __iomem *regmap[OP_LAST + 1]; |
163 | }; |
164 | |
165 | /** |
166 | * struct ci_hdrc - chipidea device representation |
167 | * @dev: pointer to parent device |
168 | * @lock: access synchronization |
169 | * @hw_bank: hardware register mapping |
170 | * @irq: IRQ number |
171 | * @roles: array of supported roles for this controller |
172 | * @role: current role |
173 | * @is_otg: if the device is otg-capable |
174 | * @fsm: otg finite state machine |
175 | * @otg_fsm_hrtimer: hrtimer for otg fsm timers |
176 | * @hr_timeouts: time out list for active otg fsm timers |
177 | * @enabled_otg_timer_bits: bits of enabled otg timers |
178 | * @next_otg_timer: next nearest enabled timer to be expired |
179 | * @work: work for role changing |
180 | * @power_lost_work: work for power lost handling |
181 | * @wq: workqueue thread |
182 | * @qh_pool: allocation pool for queue heads |
183 | * @td_pool: allocation pool for transfer descriptors |
184 | * @gadget: device side representation for peripheral controller |
185 | * @driver: gadget driver |
186 | * @resume_state: save the state of gadget suspend from |
187 | * @hw_ep_max: total number of endpoints supported by hardware |
188 | * @ci_hw_ep: array of endpoints |
189 | * @ep0_dir: ep0 direction |
190 | * @ep0out: pointer to ep0 OUT endpoint |
191 | * @ep0in: pointer to ep0 IN endpoint |
192 | * @status: ep0 status request |
193 | * @setaddr: if we should set the address on status completion |
194 | * @address: usb address received from the host |
195 | * @remote_wakeup: host-enabled remote wakeup |
196 | * @suspended: suspended by host |
197 | * @test_mode: the selected test mode |
198 | * @platdata: platform specific information supplied by parent device |
199 | * @vbus_active: is VBUS active |
200 | * @ulpi: pointer to ULPI device, if any |
201 | * @ulpi_ops: ULPI read/write ops for this device |
202 | * @phy: pointer to PHY, if any |
203 | * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework |
204 | * @hcd: pointer to usb_hcd for ehci host driver |
205 | * @id_event: indicates there is an id event, and handled at ci_otg_work |
206 | * @b_sess_valid_event: indicates there is a vbus event, and handled |
207 | * at ci_otg_work |
208 | * @imx28_write_fix: Freescale imx28 needs swp instruction for writing |
209 | * @supports_runtime_pm: if runtime pm is supported |
210 | * @in_lpm: if the core in low power mode |
211 | * @wakeup_int: if wakeup interrupt occur |
212 | * @rev: The revision number for controller |
213 | * @mutex: protect code from concorrent running when doing role switch |
214 | */ |
215 | struct ci_hdrc { |
216 | struct device *dev; |
217 | spinlock_t lock; |
218 | struct hw_bank hw_bank; |
219 | int irq; |
220 | struct ci_role_driver *roles[CI_ROLE_END]; |
221 | enum ci_role role; |
222 | bool is_otg; |
223 | struct usb_otg otg; |
224 | struct otg_fsm fsm; |
225 | struct hrtimer otg_fsm_hrtimer; |
226 | ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS]; |
227 | unsigned enabled_otg_timer_bits; |
228 | enum otg_fsm_timer next_otg_timer; |
229 | struct usb_role_switch *role_switch; |
230 | struct work_struct work; |
231 | struct work_struct power_lost_work; |
232 | struct workqueue_struct *wq; |
233 | |
234 | struct dma_pool *qh_pool; |
235 | struct dma_pool *td_pool; |
236 | |
237 | struct usb_gadget gadget; |
238 | struct usb_gadget_driver *driver; |
239 | enum usb_device_state resume_state; |
240 | unsigned hw_ep_max; |
241 | struct ci_hw_ep ci_hw_ep[ENDPT_MAX]; |
242 | u32 ep0_dir; |
243 | struct ci_hw_ep *ep0out, *ep0in; |
244 | |
245 | struct usb_request *status; |
246 | bool setaddr; |
247 | u8 address; |
248 | u8 remote_wakeup; |
249 | u8 suspended; |
250 | u8 test_mode; |
251 | |
252 | struct ci_hdrc_platform_data *platdata; |
253 | int vbus_active; |
254 | struct ulpi *ulpi; |
255 | struct ulpi_ops ulpi_ops; |
256 | struct phy *phy; |
257 | /* old usb_phy interface */ |
258 | struct usb_phy *usb_phy; |
259 | struct usb_hcd *hcd; |
260 | bool id_event; |
261 | bool b_sess_valid_event; |
262 | bool imx28_write_fix; |
263 | bool has_portsc_pec_bug; |
264 | bool has_short_pkt_limit; |
265 | bool supports_runtime_pm; |
266 | bool in_lpm; |
267 | bool wakeup_int; |
268 | enum ci_revision rev; |
269 | struct mutex mutex; |
270 | }; |
271 | |
272 | static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) |
273 | { |
274 | BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]); |
275 | return ci->roles[ci->role]; |
276 | } |
277 | |
278 | static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role) |
279 | { |
280 | int ret; |
281 | |
282 | if (role >= CI_ROLE_END) |
283 | return -EINVAL; |
284 | |
285 | if (!ci->roles[role]) |
286 | return -ENXIO; |
287 | |
288 | ret = ci->roles[role]->start(ci); |
289 | if (ret) |
290 | return ret; |
291 | |
292 | ci->role = role; |
293 | |
294 | if (ci->usb_phy) { |
295 | if (role == CI_ROLE_HOST) |
296 | usb_phy_set_event(x: ci->usb_phy, event: USB_EVENT_ID); |
297 | else |
298 | /* in device mode but vbus is invalid*/ |
299 | usb_phy_set_event(x: ci->usb_phy, event: USB_EVENT_NONE); |
300 | } |
301 | |
302 | return ret; |
303 | } |
304 | |
305 | static inline void ci_role_stop(struct ci_hdrc *ci) |
306 | { |
307 | enum ci_role role = ci->role; |
308 | |
309 | if (role == CI_ROLE_END) |
310 | return; |
311 | |
312 | ci->role = CI_ROLE_END; |
313 | |
314 | ci->roles[role]->stop(ci); |
315 | |
316 | if (ci->usb_phy) |
317 | usb_phy_set_event(x: ci->usb_phy, event: USB_EVENT_NONE); |
318 | } |
319 | |
320 | static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci) |
321 | { |
322 | if (ci->role == CI_ROLE_HOST) |
323 | return USB_ROLE_HOST; |
324 | else if (ci->role == CI_ROLE_GADGET && ci->vbus_active) |
325 | return USB_ROLE_DEVICE; |
326 | else |
327 | return USB_ROLE_NONE; |
328 | } |
329 | |
330 | static inline enum ci_role usb_role_to_ci_role(enum usb_role role) |
331 | { |
332 | if (role == USB_ROLE_HOST) |
333 | return CI_ROLE_HOST; |
334 | else if (role == USB_ROLE_DEVICE) |
335 | return CI_ROLE_GADGET; |
336 | else |
337 | return CI_ROLE_END; |
338 | } |
339 | |
340 | /** |
341 | * hw_read_id_reg: reads from a identification register |
342 | * @ci: the controller |
343 | * @offset: offset from the beginning of identification registers region |
344 | * @mask: bitfield mask |
345 | * |
346 | * This function returns register contents |
347 | */ |
348 | static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask) |
349 | { |
350 | return ioread32(ci->hw_bank.abs + offset) & mask; |
351 | } |
352 | |
353 | /** |
354 | * hw_write_id_reg: writes to a identification register |
355 | * @ci: the controller |
356 | * @offset: offset from the beginning of identification registers region |
357 | * @mask: bitfield mask |
358 | * @data: new value |
359 | */ |
360 | static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset, |
361 | u32 mask, u32 data) |
362 | { |
363 | if (~mask) |
364 | data = (ioread32(ci->hw_bank.abs + offset) & ~mask) |
365 | | (data & mask); |
366 | |
367 | iowrite32(data, ci->hw_bank.abs + offset); |
368 | } |
369 | |
370 | /** |
371 | * hw_read: reads from a hw register |
372 | * @ci: the controller |
373 | * @reg: register index |
374 | * @mask: bitfield mask |
375 | * |
376 | * This function returns register contents |
377 | */ |
378 | static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) |
379 | { |
380 | return ioread32(ci->hw_bank.regmap[reg]) & mask; |
381 | } |
382 | |
383 | #ifdef CONFIG_SOC_IMX28 |
384 | static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) |
385 | { |
386 | __asm__ ("swp %0, %0, [%1]" : : "r" (val), "r" (addr)); |
387 | } |
388 | #else |
389 | static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) |
390 | { |
391 | } |
392 | #endif |
393 | |
394 | static inline void __hw_write(struct ci_hdrc *ci, u32 val, |
395 | void __iomem *addr) |
396 | { |
397 | if (ci->imx28_write_fix) |
398 | imx28_ci_writel(val, addr); |
399 | else |
400 | iowrite32(val, addr); |
401 | } |
402 | |
403 | /** |
404 | * hw_write: writes to a hw register |
405 | * @ci: the controller |
406 | * @reg: register index |
407 | * @mask: bitfield mask |
408 | * @data: new value |
409 | */ |
410 | static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, |
411 | u32 mask, u32 data) |
412 | { |
413 | if (~mask) |
414 | data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) |
415 | | (data & mask); |
416 | |
417 | __hw_write(ci, val: data, addr: ci->hw_bank.regmap[reg]); |
418 | } |
419 | |
420 | /** |
421 | * hw_test_and_clear: tests & clears a hw register |
422 | * @ci: the controller |
423 | * @reg: register index |
424 | * @mask: bitfield mask |
425 | * |
426 | * This function returns register contents |
427 | */ |
428 | static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, |
429 | u32 mask) |
430 | { |
431 | u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; |
432 | |
433 | __hw_write(ci, val, addr: ci->hw_bank.regmap[reg]); |
434 | return val; |
435 | } |
436 | |
437 | /** |
438 | * hw_test_and_write: tests & writes a hw register |
439 | * @ci: the controller |
440 | * @reg: register index |
441 | * @mask: bitfield mask |
442 | * @data: new value |
443 | * |
444 | * This function returns register contents |
445 | */ |
446 | static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, |
447 | u32 mask, u32 data) |
448 | { |
449 | u32 val = hw_read(ci, reg, mask: ~0); |
450 | |
451 | hw_write(ci, reg, mask, data); |
452 | return (val & mask) >> __ffs(mask); |
453 | } |
454 | |
455 | /** |
456 | * ci_otg_is_fsm_mode: runtime check if otg controller |
457 | * is in otg fsm mode. |
458 | * |
459 | * @ci: chipidea device |
460 | */ |
461 | static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci) |
462 | { |
463 | #ifdef CONFIG_USB_OTG_FSM |
464 | struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps; |
465 | |
466 | return ci->is_otg && ci->roles[CI_ROLE_HOST] && |
467 | ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support || |
468 | otg_caps->hnp_support || otg_caps->adp_support); |
469 | #else |
470 | return false; |
471 | #endif |
472 | } |
473 | |
474 | int ci_ulpi_init(struct ci_hdrc *ci); |
475 | void ci_ulpi_exit(struct ci_hdrc *ci); |
476 | int ci_ulpi_resume(struct ci_hdrc *ci); |
477 | |
478 | u32 hw_read_intr_enable(struct ci_hdrc *ci); |
479 | |
480 | u32 hw_read_intr_status(struct ci_hdrc *ci); |
481 | |
482 | int hw_device_reset(struct ci_hdrc *ci); |
483 | |
484 | int hw_port_test_set(struct ci_hdrc *ci, u8 mode); |
485 | |
486 | u8 hw_port_test_get(struct ci_hdrc *ci); |
487 | |
488 | void hw_phymode_configure(struct ci_hdrc *ci); |
489 | |
490 | void ci_platform_configure(struct ci_hdrc *ci); |
491 | |
492 | void dbg_create_files(struct ci_hdrc *ci); |
493 | |
494 | void dbg_remove_files(struct ci_hdrc *ci); |
495 | #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */ |
496 | |