1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* |
3 | * Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de> |
4 | * |
5 | * Driver for Alcor Micro AU6601 and AU6621 controllers |
6 | */ |
7 | |
8 | #ifndef __ALCOR_PCI_H |
9 | #define __ALCOR_PCI_H |
10 | |
11 | #define ALCOR_SD_CARD 0 |
12 | #define ALCOR_MS_CARD 1 |
13 | |
14 | #define DRV_NAME_ALCOR_PCI_SDMMC "alcor_sdmmc" |
15 | #define DRV_NAME_ALCOR_PCI_MS "alcor_ms" |
16 | |
17 | #define PCI_ID_ALCOR_MICRO 0x1AEA |
18 | #define PCI_ID_AU6601 0x6601 |
19 | #define PCI_ID_AU6621 0x6621 |
20 | #define PCI_ID_AU6625 0x6625 |
21 | |
22 | #define MHZ_TO_HZ(freq) ((freq) * 1000 * 1000) |
23 | |
24 | #define AU6601_BASE_CLOCK 31000000 |
25 | #define AU6601_MIN_CLOCK 150000 |
26 | #define AU6601_MAX_CLOCK 208000000 |
27 | #define AU6601_MAX_DMA_SEGMENTS 64 |
28 | #define AU6601_MAX_PIO_SEGMENTS 1 |
29 | #define AU6601_MAX_DMA_BLOCK_SIZE 0x1000 |
30 | #define AU6601_MAX_PIO_BLOCK_SIZE 0x200 |
31 | #define AU6601_MAX_DMA_BLOCKS 1 |
32 | #define AU6601_DMA_LOCAL_SEGMENTS 1 |
33 | |
34 | /* registers spotter by reverse engineering but still |
35 | * with unknown functionality: |
36 | * 0x10 - ADMA phy address. AU6621 only? |
37 | * 0x51 - LED ctrl? |
38 | * 0x52 - unknown |
39 | * 0x61 - LED related? Always toggled BIT0 |
40 | * 0x63 - Same as 0x61? |
41 | * 0x77 - unknown |
42 | */ |
43 | |
44 | /* SDMA phy address. Higher then 0x0800.0000? |
45 | * The au6601 and au6621 have different DMA engines with different issues. One |
46 | * For example au6621 engine is triggered by addr change. No other interaction |
47 | * is needed. This means, if we get two buffers with same address, then engine |
48 | * will stall. |
49 | */ |
50 | #define AU6601_REG_SDMA_ADDR 0x00 |
51 | #define AU6601_SDMA_MASK 0xffffffff |
52 | |
53 | #define AU6601_DMA_BOUNDARY 0x05 |
54 | #define AU6621_DMA_PAGE_CNT 0x05 |
55 | /* PIO */ |
56 | #define AU6601_REG_BUFFER 0x08 |
57 | /* ADMA ctrl? AU6621 only. */ |
58 | #define AU6621_DMA_CTRL 0x0c |
59 | #define AU6621_DMA_ENABLE BIT(0) |
60 | /* CMD index */ |
61 | #define AU6601_REG_CMD_OPCODE 0x23 |
62 | /* CMD parametr */ |
63 | #define AU6601_REG_CMD_ARG 0x24 |
64 | /* CMD response 4x4 Bytes */ |
65 | #define AU6601_REG_CMD_RSP0 0x30 |
66 | #define AU6601_REG_CMD_RSP1 0x34 |
67 | #define AU6601_REG_CMD_RSP2 0x38 |
68 | #define AU6601_REG_CMD_RSP3 0x3C |
69 | /* default timeout set to 125: 125 * 40ms = 5 sec |
70 | * how exactly it is calculated? |
71 | */ |
72 | #define AU6601_TIME_OUT_CTRL 0x69 |
73 | /* Block size for SDMA or PIO */ |
74 | #define AU6601_REG_BLOCK_SIZE 0x6c |
75 | /* Some power related reg, used together with AU6601_OUTPUT_ENABLE */ |
76 | #define AU6601_POWER_CONTROL 0x70 |
77 | |
78 | /* PLL ctrl */ |
79 | #define AU6601_CLK_SELECT 0x72 |
80 | #define AU6601_CLK_OVER_CLK 0x80 |
81 | #define AU6601_CLK_384_MHZ 0x30 |
82 | #define AU6601_CLK_125_MHZ 0x20 |
83 | #define AU6601_CLK_48_MHZ 0x10 |
84 | #define AU6601_CLK_EXT_PLL 0x04 |
85 | #define AU6601_CLK_X2_MODE 0x02 |
86 | #define AU6601_CLK_ENABLE 0x01 |
87 | #define AU6601_CLK_31_25_MHZ 0x00 |
88 | |
89 | #define AU6601_CLK_DIVIDER 0x73 |
90 | |
91 | #define AU6601_INTERFACE_MODE_CTRL 0x74 |
92 | #define AU6601_DLINK_MODE 0x80 |
93 | #define AU6601_INTERRUPT_DELAY_TIME 0x40 |
94 | #define AU6601_SIGNAL_REQ_CTRL 0x30 |
95 | #define AU6601_MS_CARD_WP BIT(3) |
96 | #define AU6601_SD_CARD_WP BIT(0) |
97 | |
98 | /* same register values are used for: |
99 | * - AU6601_OUTPUT_ENABLE |
100 | * - AU6601_POWER_CONTROL |
101 | */ |
102 | #define AU6601_ACTIVE_CTRL 0x75 |
103 | #define AU6601_XD_CARD BIT(4) |
104 | /* AU6601_MS_CARD_ACTIVE - will cativate MS card section? */ |
105 | #define AU6601_MS_CARD BIT(3) |
106 | #define AU6601_SD_CARD BIT(0) |
107 | |
108 | /* card slot state. It should automatically detect type of |
109 | * the card |
110 | */ |
111 | #define AU6601_DETECT_STATUS 0x76 |
112 | #define AU6601_DETECT_EN BIT(7) |
113 | #define AU6601_MS_DETECTED BIT(3) |
114 | #define AU6601_SD_DETECTED BIT(0) |
115 | #define AU6601_DETECT_STATUS_M 0xf |
116 | |
117 | #define AU6601_REG_SW_RESET 0x79 |
118 | #define AU6601_BUF_CTRL_RESET BIT(7) |
119 | #define AU6601_RESET_DATA BIT(3) |
120 | #define AU6601_RESET_CMD BIT(0) |
121 | |
122 | #define AU6601_OUTPUT_ENABLE 0x7a |
123 | |
124 | #define AU6601_PAD_DRIVE0 0x7b |
125 | #define AU6601_PAD_DRIVE1 0x7c |
126 | #define AU6601_PAD_DRIVE2 0x7d |
127 | /* read EEPROM? */ |
128 | #define AU6601_FUNCTION 0x7f |
129 | |
130 | #define AU6601_CMD_XFER_CTRL 0x81 |
131 | #define AU6601_CMD_17_BYTE_CRC 0xc0 |
132 | #define AU6601_CMD_6_BYTE_WO_CRC 0x80 |
133 | #define AU6601_CMD_6_BYTE_CRC 0x40 |
134 | #define AU6601_CMD_START_XFER 0x20 |
135 | #define AU6601_CMD_STOP_WAIT_RDY 0x10 |
136 | #define AU6601_CMD_NO_RESP 0x00 |
137 | |
138 | #define AU6601_REG_BUS_CTRL 0x82 |
139 | #define AU6601_BUS_WIDTH_4BIT 0x20 |
140 | #define AU6601_BUS_WIDTH_8BIT 0x10 |
141 | #define AU6601_BUS_WIDTH_1BIT 0x00 |
142 | |
143 | #define AU6601_DATA_XFER_CTRL 0x83 |
144 | #define AU6601_DATA_WRITE BIT(7) |
145 | #define AU6601_DATA_DMA_MODE BIT(6) |
146 | #define AU6601_DATA_START_XFER BIT(0) |
147 | |
148 | #define AU6601_DATA_PIN_STATE 0x84 |
149 | #define AU6601_BUS_STAT_CMD BIT(15) |
150 | /* BIT(4) - BIT(7) are permanently 1. |
151 | * May be reserved or not attached DAT4-DAT7 |
152 | */ |
153 | #define AU6601_BUS_STAT_DAT3 BIT(3) |
154 | #define AU6601_BUS_STAT_DAT2 BIT(2) |
155 | #define AU6601_BUS_STAT_DAT1 BIT(1) |
156 | #define AU6601_BUS_STAT_DAT0 BIT(0) |
157 | #define AU6601_BUS_STAT_DAT_MASK 0xf |
158 | |
159 | #define AU6601_OPT 0x85 |
160 | #define AU6601_OPT_CMD_LINE_LEVEL 0x80 |
161 | #define AU6601_OPT_NCRC_16_CLK BIT(4) |
162 | #define AU6601_OPT_CMD_NWT BIT(3) |
163 | #define AU6601_OPT_STOP_CLK BIT(2) |
164 | #define AU6601_OPT_DDR_MODE BIT(1) |
165 | #define AU6601_OPT_SD_18V BIT(0) |
166 | |
167 | #define AU6601_CLK_DELAY 0x86 |
168 | #define AU6601_CLK_DATA_POSITIVE_EDGE 0x80 |
169 | #define AU6601_CLK_CMD_POSITIVE_EDGE 0x40 |
170 | #define AU6601_CLK_POSITIVE_EDGE_ALL (AU6601_CLK_CMD_POSITIVE_EDGE \ |
171 | | AU6601_CLK_DATA_POSITIVE_EDGE) |
172 | |
173 | |
174 | #define AU6601_REG_INT_STATUS 0x90 |
175 | #define AU6601_REG_INT_ENABLE 0x94 |
176 | #define AU6601_INT_DATA_END_BIT_ERR BIT(22) |
177 | #define AU6601_INT_DATA_CRC_ERR BIT(21) |
178 | #define AU6601_INT_DATA_TIMEOUT_ERR BIT(20) |
179 | #define AU6601_INT_CMD_INDEX_ERR BIT(19) |
180 | #define AU6601_INT_CMD_END_BIT_ERR BIT(18) |
181 | #define AU6601_INT_CMD_CRC_ERR BIT(17) |
182 | #define AU6601_INT_CMD_TIMEOUT_ERR BIT(16) |
183 | #define AU6601_INT_ERROR BIT(15) |
184 | #define AU6601_INT_OVER_CURRENT_ERR BIT(8) |
185 | #define AU6601_INT_CARD_INSERT BIT(7) |
186 | #define AU6601_INT_CARD_REMOVE BIT(6) |
187 | #define AU6601_INT_READ_BUF_RDY BIT(5) |
188 | #define AU6601_INT_WRITE_BUF_RDY BIT(4) |
189 | #define AU6601_INT_DMA_END BIT(3) |
190 | #define AU6601_INT_DATA_END BIT(1) |
191 | #define AU6601_INT_CMD_END BIT(0) |
192 | |
193 | #define AU6601_INT_NORMAL_MASK 0x00007FFF |
194 | #define AU6601_INT_ERROR_MASK 0xFFFF8000 |
195 | |
196 | #define AU6601_INT_CMD_MASK (AU6601_INT_CMD_END | \ |
197 | AU6601_INT_CMD_TIMEOUT_ERR | AU6601_INT_CMD_CRC_ERR | \ |
198 | AU6601_INT_CMD_END_BIT_ERR | AU6601_INT_CMD_INDEX_ERR) |
199 | #define AU6601_INT_DATA_MASK (AU6601_INT_DATA_END | AU6601_INT_DMA_END | \ |
200 | AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY | \ |
201 | AU6601_INT_DATA_TIMEOUT_ERR | AU6601_INT_DATA_CRC_ERR | \ |
202 | AU6601_INT_DATA_END_BIT_ERR) |
203 | #define AU6601_INT_ALL_MASK ((u32)-1) |
204 | |
205 | /* MS_CARD mode registers */ |
206 | |
207 | #define AU6601_MS_STATUS 0xa0 |
208 | |
209 | #define AU6601_MS_BUS_MODE_CTRL 0xa1 |
210 | #define AU6601_MS_BUS_8BIT_MODE 0x03 |
211 | #define AU6601_MS_BUS_4BIT_MODE 0x01 |
212 | #define AU6601_MS_BUS_1BIT_MODE 0x00 |
213 | |
214 | #define AU6601_MS_TPC_CMD 0xa2 |
215 | #define AU6601_MS_TPC_READ_PAGE_DATA 0x02 |
216 | #define AU6601_MS_TPC_READ_REG 0x04 |
217 | #define AU6601_MS_TPC_GET_INT 0x07 |
218 | #define AU6601_MS_TPC_WRITE_PAGE_DATA 0x0D |
219 | #define AU6601_MS_TPC_WRITE_REG 0x0B |
220 | #define AU6601_MS_TPC_SET_RW_REG_ADRS 0x08 |
221 | #define AU6601_MS_TPC_SET_CMD 0x0E |
222 | #define AU6601_MS_TPC_EX_SET_CMD 0x09 |
223 | #define AU6601_MS_TPC_READ_SHORT_DATA 0x03 |
224 | #define AU6601_MS_TPC_WRITE_SHORT_DATA 0x0C |
225 | |
226 | #define AU6601_MS_TRANSFER_MODE 0xa3 |
227 | #define AU6601_MS_XFER_INT_TIMEOUT_CHK BIT(2) |
228 | #define AU6601_MS_XFER_DMA_ENABLE BIT(1) |
229 | #define AU6601_MS_XFER_START BIT(0) |
230 | |
231 | #define AU6601_MS_DATA_PIN_STATE 0xa4 |
232 | |
233 | #define AU6601_MS_INT_STATUS 0xb0 |
234 | #define AU6601_MS_INT_ENABLE 0xb4 |
235 | #define AU6601_MS_INT_OVER_CURRENT_ERROR BIT(23) |
236 | #define AU6601_MS_INT_DATA_CRC_ERROR BIT(21) |
237 | #define AU6601_MS_INT_INT_TIMEOUT BIT(20) |
238 | #define AU6601_MS_INT_INT_RESP_ERROR BIT(19) |
239 | #define AU6601_MS_INT_CED_ERROR BIT(18) |
240 | #define AU6601_MS_INT_TPC_TIMEOUT BIT(16) |
241 | #define AU6601_MS_INT_ERROR BIT(15) |
242 | #define AU6601_MS_INT_CARD_INSERT BIT(7) |
243 | #define AU6601_MS_INT_CARD_REMOVE BIT(6) |
244 | #define AU6601_MS_INT_BUF_READ_RDY BIT(5) |
245 | #define AU6601_MS_INT_BUF_WRITE_RDY BIT(4) |
246 | #define AU6601_MS_INT_DMA_END BIT(3) |
247 | #define AU6601_MS_INT_TPC_END BIT(1) |
248 | |
249 | #define AU6601_MS_INT_DATA_MASK 0x00000038 |
250 | #define AU6601_MS_INT_TPC_MASK 0x003d8002 |
251 | #define AU6601_MS_INT_TPC_ERROR 0x003d0000 |
252 | |
253 | #define ALCOR_PCIE_LINK_CTRL_OFFSET 0x10 |
254 | #define ALCOR_PCIE_LINK_CAP_OFFSET 0x0c |
255 | #define ALCOR_CAP_START_OFFSET 0x34 |
256 | |
257 | struct alcor_dev_cfg { |
258 | u8 dma; |
259 | }; |
260 | |
261 | struct alcor_pci_priv { |
262 | struct pci_dev *pdev; |
263 | struct pci_dev *parent_pdev; |
264 | struct device *dev; |
265 | void __iomem *iobase; |
266 | unsigned int irq; |
267 | |
268 | unsigned long id; /* idr id */ |
269 | |
270 | struct alcor_dev_cfg *cfg; |
271 | }; |
272 | |
273 | void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr); |
274 | void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr); |
275 | void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr); |
276 | void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr); |
277 | u8 alcor_read8(struct alcor_pci_priv *priv, unsigned int addr); |
278 | u32 alcor_read32(struct alcor_pci_priv *priv, unsigned int addr); |
279 | u32 alcor_read32be(struct alcor_pci_priv *priv, unsigned int addr); |
280 | #endif |
281 | |